2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/pci.h>
38 #include <linux/libata.h>
39 #include <linux/highmem.h>
43 const struct ata_port_operations ata_sff_port_ops = {
44 .inherits = &ata_base_port_ops,
46 .qc_prep = ata_sff_qc_prep,
47 .qc_issue = ata_sff_qc_issue,
48 .qc_fill_rtf = ata_sff_qc_fill_rtf,
50 .freeze = ata_sff_freeze,
52 .prereset = ata_sff_prereset,
53 .softreset = ata_sff_softreset,
54 .hardreset = sata_sff_hardreset,
55 .postreset = ata_sff_postreset,
56 .drain_fifo = ata_sff_drain_fifo,
57 .error_handler = ata_sff_error_handler,
58 .post_internal_cmd = ata_sff_post_internal_cmd,
60 .sff_dev_select = ata_sff_dev_select,
61 .sff_check_status = ata_sff_check_status,
62 .sff_tf_load = ata_sff_tf_load,
63 .sff_tf_read = ata_sff_tf_read,
64 .sff_exec_command = ata_sff_exec_command,
65 .sff_data_xfer = ata_sff_data_xfer,
66 .sff_irq_clear = ata_sff_irq_clear,
68 .lost_interrupt = ata_sff_lost_interrupt,
70 .port_start = ata_sff_port_start,
72 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
74 const struct ata_port_operations ata_bmdma_port_ops = {
75 .inherits = &ata_sff_port_ops,
77 .mode_filter = ata_bmdma_mode_filter,
79 .bmdma_setup = ata_bmdma_setup,
80 .bmdma_start = ata_bmdma_start,
81 .bmdma_stop = ata_bmdma_stop,
82 .bmdma_status = ata_bmdma_status,
84 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
86 const struct ata_port_operations ata_bmdma32_port_ops = {
87 .inherits = &ata_bmdma_port_ops,
89 .sff_data_xfer = ata_sff_data_xfer32,
90 .port_start = ata_sff_port_start32,
92 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
95 * ata_fill_sg - Fill PCI IDE PRD table
96 * @qc: Metadata associated with taskfile to be transferred
98 * Fill PCI IDE PRD (scatter-gather) table with segments
99 * associated with the current disk command.
102 * spin_lock_irqsave(host lock)
105 static void ata_fill_sg(struct ata_queued_cmd *qc)
107 struct ata_port *ap = qc->ap;
108 struct scatterlist *sg;
112 for_each_sg(qc->sg, sg, qc->n_elem, si) {
116 /* determine if physical DMA addr spans 64K boundary.
117 * Note h/w doesn't support 64-bit, so we unconditionally
118 * truncate dma_addr_t to u32.
120 addr = (u32) sg_dma_address(sg);
121 sg_len = sg_dma_len(sg);
124 offset = addr & 0xffff;
126 if ((offset + sg_len) > 0x10000)
127 len = 0x10000 - offset;
129 ap->prd[pi].addr = cpu_to_le32(addr);
130 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
131 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
139 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
143 * ata_fill_sg_dumb - Fill PCI IDE PRD table
144 * @qc: Metadata associated with taskfile to be transferred
146 * Fill PCI IDE PRD (scatter-gather) table with segments
147 * associated with the current disk command. Perform the fill
148 * so that we avoid writing any length 64K records for
149 * controllers that don't follow the spec.
152 * spin_lock_irqsave(host lock)
155 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
157 struct ata_port *ap = qc->ap;
158 struct scatterlist *sg;
162 for_each_sg(qc->sg, sg, qc->n_elem, si) {
164 u32 sg_len, len, blen;
166 /* determine if physical DMA addr spans 64K boundary.
167 * Note h/w doesn't support 64-bit, so we unconditionally
168 * truncate dma_addr_t to u32.
170 addr = (u32) sg_dma_address(sg);
171 sg_len = sg_dma_len(sg);
174 offset = addr & 0xffff;
176 if ((offset + sg_len) > 0x10000)
177 len = 0x10000 - offset;
180 ap->prd[pi].addr = cpu_to_le32(addr);
182 /* Some PATA chipsets like the CS5530 can't
183 cope with 0x0000 meaning 64K as the spec
185 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
187 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
189 ap->prd[pi].flags_len = cpu_to_le32(blen);
190 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
198 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
202 * ata_sff_qc_prep - Prepare taskfile for submission
203 * @qc: Metadata associated with taskfile to be prepared
205 * Prepare ATA taskfile for submission.
208 * spin_lock_irqsave(host lock)
210 void ata_sff_qc_prep(struct ata_queued_cmd *qc)
212 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
217 EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
220 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
221 * @qc: Metadata associated with taskfile to be prepared
223 * Prepare ATA taskfile for submission.
226 * spin_lock_irqsave(host lock)
228 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
230 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
233 ata_fill_sg_dumb(qc);
235 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
238 * ata_sff_check_status - Read device status reg & clear interrupt
239 * @ap: port where the device is
241 * Reads ATA taskfile status register for currently-selected device
242 * and return its value. This also clears pending interrupts
246 * Inherited from caller.
248 u8 ata_sff_check_status(struct ata_port *ap)
250 return ioread8(ap->ioaddr.status_addr);
252 EXPORT_SYMBOL_GPL(ata_sff_check_status);
255 * ata_sff_altstatus - Read device alternate status reg
256 * @ap: port where the device is
258 * Reads ATA taskfile alternate status register for
259 * currently-selected device and return its value.
261 * Note: may NOT be used as the check_altstatus() entry in
262 * ata_port_operations.
265 * Inherited from caller.
267 static u8 ata_sff_altstatus(struct ata_port *ap)
269 if (ap->ops->sff_check_altstatus)
270 return ap->ops->sff_check_altstatus(ap);
272 return ioread8(ap->ioaddr.altstatus_addr);
276 * ata_sff_irq_status - Check if the device is busy
277 * @ap: port where the device is
279 * Determine if the port is currently busy. Uses altstatus
280 * if available in order to avoid clearing shared IRQ status
281 * when finding an IRQ source. Non ctl capable devices don't
282 * share interrupt lines fortunately for us.
285 * Inherited from caller.
287 static u8 ata_sff_irq_status(struct ata_port *ap)
291 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
292 status = ata_sff_altstatus(ap);
293 /* Not us: We are busy */
294 if (status & ATA_BUSY)
297 /* Clear INTRQ latch */
298 status = ap->ops->sff_check_status(ap);
303 * ata_sff_sync - Flush writes
304 * @ap: Port to wait for.
307 * If we have an mmio device with no ctl and no altstatus
308 * method this will fail. No such devices are known to exist.
311 * Inherited from caller.
314 static void ata_sff_sync(struct ata_port *ap)
316 if (ap->ops->sff_check_altstatus)
317 ap->ops->sff_check_altstatus(ap);
318 else if (ap->ioaddr.altstatus_addr)
319 ioread8(ap->ioaddr.altstatus_addr);
323 * ata_sff_pause - Flush writes and wait 400nS
324 * @ap: Port to pause for.
327 * If we have an mmio device with no ctl and no altstatus
328 * method this will fail. No such devices are known to exist.
331 * Inherited from caller.
334 void ata_sff_pause(struct ata_port *ap)
339 EXPORT_SYMBOL_GPL(ata_sff_pause);
342 * ata_sff_dma_pause - Pause before commencing DMA
343 * @ap: Port to pause for.
345 * Perform I/O fencing and ensure sufficient cycle delays occur
346 * for the HDMA1:0 transition
349 void ata_sff_dma_pause(struct ata_port *ap)
351 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
352 /* An altstatus read will cause the needed delay without
353 messing up the IRQ status */
354 ata_sff_altstatus(ap);
357 /* There are no DMA controllers without ctl. BUG here to ensure
358 we never violate the HDMA1:0 transition timing and risk
362 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
365 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
366 * @ap: port containing status register to be polled
367 * @tmout_pat: impatience timeout in msecs
368 * @tmout: overall timeout in msecs
370 * Sleep until ATA Status register bit BSY clears,
371 * or a timeout occurs.
374 * Kernel thread context (may sleep).
377 * 0 on success, -errno otherwise.
379 int ata_sff_busy_sleep(struct ata_port *ap,
380 unsigned long tmout_pat, unsigned long tmout)
382 unsigned long timer_start, timeout;
385 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
386 timer_start = jiffies;
387 timeout = ata_deadline(timer_start, tmout_pat);
388 while (status != 0xff && (status & ATA_BUSY) &&
389 time_before(jiffies, timeout)) {
391 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
394 if (status != 0xff && (status & ATA_BUSY))
395 ata_port_printk(ap, KERN_WARNING,
396 "port is slow to respond, please be patient "
397 "(Status 0x%x)\n", status);
399 timeout = ata_deadline(timer_start, tmout);
400 while (status != 0xff && (status & ATA_BUSY) &&
401 time_before(jiffies, timeout)) {
403 status = ap->ops->sff_check_status(ap);
409 if (status & ATA_BUSY) {
410 ata_port_printk(ap, KERN_ERR, "port failed to respond "
411 "(%lu secs, Status 0x%x)\n",
412 DIV_ROUND_UP(tmout, 1000), status);
418 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
420 static int ata_sff_check_ready(struct ata_link *link)
422 u8 status = link->ap->ops->sff_check_status(link->ap);
424 return ata_check_ready(status);
428 * ata_sff_wait_ready - sleep until BSY clears, or timeout
429 * @link: SFF link to wait ready status for
430 * @deadline: deadline jiffies for the operation
432 * Sleep until ATA Status register bit BSY clears, or timeout
436 * Kernel thread context (may sleep).
439 * 0 on success, -errno otherwise.
441 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
443 return ata_wait_ready(link, deadline, ata_sff_check_ready);
445 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
448 * ata_sff_set_devctl - Write device control reg
449 * @ap: port where the device is
450 * @ctl: value to write
452 * Writes ATA taskfile device control register.
454 * Note: may NOT be used as the sff_set_devctl() entry in
455 * ata_port_operations.
458 * Inherited from caller.
460 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
462 if (ap->ops->sff_set_devctl)
463 ap->ops->sff_set_devctl(ap, ctl);
465 iowrite8(ctl, ap->ioaddr.ctl_addr);
469 * ata_sff_dev_select - Select device 0/1 on ATA bus
470 * @ap: ATA channel to manipulate
471 * @device: ATA device (numbered from zero) to select
473 * Use the method defined in the ATA specification to
474 * make either device 0, or device 1, active on the
475 * ATA channel. Works with both PIO and MMIO.
477 * May be used as the dev_select() entry in ata_port_operations.
482 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
487 tmp = ATA_DEVICE_OBS;
489 tmp = ATA_DEVICE_OBS | ATA_DEV1;
491 iowrite8(tmp, ap->ioaddr.device_addr);
492 ata_sff_pause(ap); /* needed; also flushes, for mmio */
494 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
497 * ata_dev_select - Select device 0/1 on ATA bus
498 * @ap: ATA channel to manipulate
499 * @device: ATA device (numbered from zero) to select
500 * @wait: non-zero to wait for Status register BSY bit to clear
501 * @can_sleep: non-zero if context allows sleeping
503 * Use the method defined in the ATA specification to
504 * make either device 0, or device 1, active on the
507 * This is a high-level version of ata_sff_dev_select(), which
508 * additionally provides the services of inserting the proper
509 * pauses and status polling, where needed.
514 void ata_dev_select(struct ata_port *ap, unsigned int device,
515 unsigned int wait, unsigned int can_sleep)
517 if (ata_msg_probe(ap))
518 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
519 "device %u, wait %u\n", device, wait);
524 ap->ops->sff_dev_select(ap, device);
527 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
534 * ata_sff_irq_on - Enable interrupts on a port.
535 * @ap: Port on which interrupts are enabled.
537 * Enable interrupts on a legacy IDE device using MMIO or PIO,
538 * wait for idle, clear any pending interrupts.
540 * Note: may NOT be used as the sff_irq_on() entry in
541 * ata_port_operations.
544 * Inherited from caller.
546 void ata_sff_irq_on(struct ata_port *ap)
548 struct ata_ioports *ioaddr = &ap->ioaddr;
550 if (ap->ops->sff_irq_on) {
551 ap->ops->sff_irq_on(ap);
555 ap->ctl &= ~ATA_NIEN;
556 ap->last_ctl = ap->ctl;
558 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
559 ata_sff_set_devctl(ap, ap->ctl);
562 ap->ops->sff_irq_clear(ap);
564 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
567 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
568 * @ap: Port associated with this ATA transaction.
570 * Clear interrupt and error flags in DMA status register.
572 * May be used as the irq_clear() entry in ata_port_operations.
575 * spin_lock_irqsave(host lock)
577 void ata_sff_irq_clear(struct ata_port *ap)
579 void __iomem *mmio = ap->ioaddr.bmdma_addr;
584 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
586 EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
589 * ata_sff_tf_load - send taskfile registers to host controller
590 * @ap: Port to which output is sent
591 * @tf: ATA taskfile register set
593 * Outputs ATA taskfile to standard ATA host controller.
596 * Inherited from caller.
598 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
600 struct ata_ioports *ioaddr = &ap->ioaddr;
601 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
603 if (tf->ctl != ap->last_ctl) {
604 if (ioaddr->ctl_addr)
605 iowrite8(tf->ctl, ioaddr->ctl_addr);
606 ap->last_ctl = tf->ctl;
610 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
611 WARN_ON_ONCE(!ioaddr->ctl_addr);
612 iowrite8(tf->hob_feature, ioaddr->feature_addr);
613 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
614 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
615 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
616 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
617 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
626 iowrite8(tf->feature, ioaddr->feature_addr);
627 iowrite8(tf->nsect, ioaddr->nsect_addr);
628 iowrite8(tf->lbal, ioaddr->lbal_addr);
629 iowrite8(tf->lbam, ioaddr->lbam_addr);
630 iowrite8(tf->lbah, ioaddr->lbah_addr);
631 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
639 if (tf->flags & ATA_TFLAG_DEVICE) {
640 iowrite8(tf->device, ioaddr->device_addr);
641 VPRINTK("device 0x%X\n", tf->device);
646 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
649 * ata_sff_tf_read - input device's ATA taskfile shadow registers
650 * @ap: Port from which input is read
651 * @tf: ATA taskfile register set for storing input
653 * Reads ATA taskfile registers for currently-selected device
654 * into @tf. Assumes the device has a fully SFF compliant task file
655 * layout and behaviour. If you device does not (eg has a different
656 * status method) then you will need to provide a replacement tf_read
659 * Inherited from caller.
661 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
663 struct ata_ioports *ioaddr = &ap->ioaddr;
665 tf->command = ata_sff_check_status(ap);
666 tf->feature = ioread8(ioaddr->error_addr);
667 tf->nsect = ioread8(ioaddr->nsect_addr);
668 tf->lbal = ioread8(ioaddr->lbal_addr);
669 tf->lbam = ioread8(ioaddr->lbam_addr);
670 tf->lbah = ioread8(ioaddr->lbah_addr);
671 tf->device = ioread8(ioaddr->device_addr);
673 if (tf->flags & ATA_TFLAG_LBA48) {
674 if (likely(ioaddr->ctl_addr)) {
675 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
676 tf->hob_feature = ioread8(ioaddr->error_addr);
677 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
678 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
679 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
680 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
681 iowrite8(tf->ctl, ioaddr->ctl_addr);
682 ap->last_ctl = tf->ctl;
687 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
690 * ata_sff_exec_command - issue ATA command to host controller
691 * @ap: port to which command is being issued
692 * @tf: ATA taskfile register set
694 * Issues ATA command, with proper synchronization with interrupt
695 * handler / other threads.
698 * spin_lock_irqsave(host lock)
700 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
702 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
704 iowrite8(tf->command, ap->ioaddr.command_addr);
707 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
710 * ata_tf_to_host - issue ATA taskfile to host controller
711 * @ap: port to which command is being issued
712 * @tf: ATA taskfile register set
714 * Issues ATA taskfile register set to ATA host controller,
715 * with proper synchronization with interrupt handler and
719 * spin_lock_irqsave(host lock)
721 static inline void ata_tf_to_host(struct ata_port *ap,
722 const struct ata_taskfile *tf)
724 ap->ops->sff_tf_load(ap, tf);
725 ap->ops->sff_exec_command(ap, tf);
729 * ata_sff_data_xfer - Transfer data by PIO
730 * @dev: device to target
732 * @buflen: buffer length
735 * Transfer data from/to the device data register by PIO.
738 * Inherited from caller.
743 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
744 unsigned int buflen, int rw)
746 struct ata_port *ap = dev->link->ap;
747 void __iomem *data_addr = ap->ioaddr.data_addr;
748 unsigned int words = buflen >> 1;
750 /* Transfer multiple of 2 bytes */
752 ioread16_rep(data_addr, buf, words);
754 iowrite16_rep(data_addr, buf, words);
756 /* Transfer trailing byte, if any. */
757 if (unlikely(buflen & 0x01)) {
758 unsigned char pad[2];
760 /* Point buf to the tail of buffer */
764 * Use io*16_rep() accessors here as well to avoid pointlessly
765 * swapping bytes to and from on the big endian machines...
768 ioread16_rep(data_addr, pad, 1);
772 iowrite16_rep(data_addr, pad, 1);
779 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
782 * ata_sff_data_xfer32 - Transfer data by PIO
783 * @dev: device to target
785 * @buflen: buffer length
788 * Transfer data from/to the device data register by PIO using 32bit
792 * Inherited from caller.
798 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
799 unsigned int buflen, int rw)
801 struct ata_port *ap = dev->link->ap;
802 void __iomem *data_addr = ap->ioaddr.data_addr;
803 unsigned int words = buflen >> 2;
804 int slop = buflen & 3;
806 if (!(ap->pflags & ATA_PFLAG_PIO32))
807 return ata_sff_data_xfer(dev, buf, buflen, rw);
809 /* Transfer multiple of 4 bytes */
811 ioread32_rep(data_addr, buf, words);
813 iowrite32_rep(data_addr, buf, words);
815 /* Transfer trailing bytes, if any */
816 if (unlikely(slop)) {
817 unsigned char pad[4];
819 /* Point buf to the tail of buffer */
820 buf += buflen - slop;
823 * Use io*_rep() accessors here as well to avoid pointlessly
824 * swapping bytes to and from on the big endian machines...
828 ioread16_rep(data_addr, pad, 1);
830 ioread32_rep(data_addr, pad, 1);
831 memcpy(buf, pad, slop);
833 memcpy(pad, buf, slop);
835 iowrite16_rep(data_addr, pad, 1);
837 iowrite32_rep(data_addr, pad, 1);
840 return (buflen + 1) & ~1;
842 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
845 * ata_sff_data_xfer_noirq - Transfer data by PIO
846 * @dev: device to target
848 * @buflen: buffer length
851 * Transfer data from/to the device data register by PIO. Do the
852 * transfer with interrupts disabled.
855 * Inherited from caller.
860 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
861 unsigned int buflen, int rw)
864 unsigned int consumed;
866 local_irq_save(flags);
867 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
868 local_irq_restore(flags);
872 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
875 * ata_pio_sector - Transfer a sector of data.
876 * @qc: Command on going
878 * Transfer qc->sect_size bytes of data from/to the ATA device.
881 * Inherited from caller.
883 static void ata_pio_sector(struct ata_queued_cmd *qc)
885 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
886 struct ata_port *ap = qc->ap;
891 if (qc->curbytes == qc->nbytes - qc->sect_size)
892 ap->hsm_task_state = HSM_ST_LAST;
894 page = sg_page(qc->cursg);
895 offset = qc->cursg->offset + qc->cursg_ofs;
897 /* get the current page and offset */
898 page = nth_page(page, (offset >> PAGE_SHIFT));
901 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
903 if (PageHighMem(page)) {
906 /* FIXME: use a bounce buffer */
907 local_irq_save(flags);
908 buf = kmap_atomic(page, KM_IRQ0);
910 /* do the actual data transfer */
911 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
914 kunmap_atomic(buf, KM_IRQ0);
915 local_irq_restore(flags);
917 buf = page_address(page);
918 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
923 flush_dcache_page(page);
925 qc->curbytes += qc->sect_size;
926 qc->cursg_ofs += qc->sect_size;
928 if (qc->cursg_ofs == qc->cursg->length) {
929 qc->cursg = sg_next(qc->cursg);
935 * ata_pio_sectors - Transfer one or many sectors.
936 * @qc: Command on going
938 * Transfer one or many sectors of data from/to the
939 * ATA device for the DRQ request.
942 * Inherited from caller.
944 static void ata_pio_sectors(struct ata_queued_cmd *qc)
946 if (is_multi_taskfile(&qc->tf)) {
947 /* READ/WRITE MULTIPLE */
950 WARN_ON_ONCE(qc->dev->multi_count == 0);
952 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
953 qc->dev->multi_count);
959 ata_sff_sync(qc->ap); /* flush */
963 * atapi_send_cdb - Write CDB bytes to hardware
964 * @ap: Port to which ATAPI device is attached.
965 * @qc: Taskfile currently active
967 * When device has indicated its readiness to accept
968 * a CDB, this function is called. Send the CDB.
973 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
976 DPRINTK("send cdb\n");
977 WARN_ON_ONCE(qc->dev->cdb_len < 12);
979 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
981 /* FIXME: If the CDB is for DMA do we need to do the transition delay
982 or is bmdma_start guaranteed to do it ? */
983 switch (qc->tf.protocol) {
985 ap->hsm_task_state = HSM_ST;
987 case ATAPI_PROT_NODATA:
988 ap->hsm_task_state = HSM_ST_LAST;
991 ap->hsm_task_state = HSM_ST_LAST;
993 ap->ops->bmdma_start(qc);
999 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
1000 * @qc: Command on going
1001 * @bytes: number of bytes
1003 * Transfer Transfer data from/to the ATAPI device.
1006 * Inherited from caller.
1009 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
1011 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
1012 struct ata_port *ap = qc->ap;
1013 struct ata_device *dev = qc->dev;
1014 struct ata_eh_info *ehi = &dev->link->eh_info;
1015 struct scatterlist *sg;
1018 unsigned int offset, count, consumed;
1022 if (unlikely(!sg)) {
1023 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
1024 "buf=%u cur=%u bytes=%u",
1025 qc->nbytes, qc->curbytes, bytes);
1030 offset = sg->offset + qc->cursg_ofs;
1032 /* get the current page and offset */
1033 page = nth_page(page, (offset >> PAGE_SHIFT));
1034 offset %= PAGE_SIZE;
1036 /* don't overrun current sg */
1037 count = min(sg->length - qc->cursg_ofs, bytes);
1039 /* don't cross page boundaries */
1040 count = min(count, (unsigned int)PAGE_SIZE - offset);
1042 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
1044 if (PageHighMem(page)) {
1045 unsigned long flags;
1047 /* FIXME: use bounce buffer */
1048 local_irq_save(flags);
1049 buf = kmap_atomic(page, KM_IRQ0);
1051 /* do the actual data transfer */
1052 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
1055 kunmap_atomic(buf, KM_IRQ0);
1056 local_irq_restore(flags);
1058 buf = page_address(page);
1059 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
1063 bytes -= min(bytes, consumed);
1064 qc->curbytes += count;
1065 qc->cursg_ofs += count;
1067 if (qc->cursg_ofs == sg->length) {
1068 qc->cursg = sg_next(qc->cursg);
1073 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
1074 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
1075 * check correctly as it doesn't know if it is the last request being
1076 * made. Somebody should implement a proper sanity check.
1084 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
1085 * @qc: Command on going
1087 * Transfer Transfer data from/to the ATAPI device.
1090 * Inherited from caller.
1092 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
1094 struct ata_port *ap = qc->ap;
1095 struct ata_device *dev = qc->dev;
1096 struct ata_eh_info *ehi = &dev->link->eh_info;
1097 unsigned int ireason, bc_lo, bc_hi, bytes;
1098 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
1100 /* Abuse qc->result_tf for temp storage of intermediate TF
1101 * here to save some kernel stack usage.
1102 * For normal completion, qc->result_tf is not relevant. For
1103 * error, qc->result_tf is later overwritten by ata_qc_complete().
1104 * So, the correctness of qc->result_tf is not affected.
1106 ap->ops->sff_tf_read(ap, &qc->result_tf);
1107 ireason = qc->result_tf.nsect;
1108 bc_lo = qc->result_tf.lbam;
1109 bc_hi = qc->result_tf.lbah;
1110 bytes = (bc_hi << 8) | bc_lo;
1112 /* shall be cleared to zero, indicating xfer of data */
1113 if (unlikely(ireason & (1 << 0)))
1116 /* make sure transfer direction matches expected */
1117 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
1118 if (unlikely(do_write != i_write))
1121 if (unlikely(!bytes))
1124 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
1126 if (unlikely(__atapi_pio_bytes(qc, bytes)))
1128 ata_sff_sync(ap); /* flush */
1133 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
1136 qc->err_mask |= AC_ERR_HSM;
1137 ap->hsm_task_state = HSM_ST_ERR;
1141 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
1142 * @ap: the target ata_port
1146 * 1 if ok in workqueue, 0 otherwise.
1148 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
1149 struct ata_queued_cmd *qc)
1151 if (qc->tf.flags & ATA_TFLAG_POLLING)
1154 if (ap->hsm_task_state == HSM_ST_FIRST) {
1155 if (qc->tf.protocol == ATA_PROT_PIO &&
1156 (qc->tf.flags & ATA_TFLAG_WRITE))
1159 if (ata_is_atapi(qc->tf.protocol) &&
1160 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1168 * ata_hsm_qc_complete - finish a qc running on standard HSM
1169 * @qc: Command to complete
1170 * @in_wq: 1 if called from workqueue, 0 otherwise
1172 * Finish @qc which is running on standard HSM.
1175 * If @in_wq is zero, spin_lock_irqsave(host lock).
1176 * Otherwise, none on entry and grabs host lock.
1178 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1180 struct ata_port *ap = qc->ap;
1181 unsigned long flags;
1183 if (ap->ops->error_handler) {
1185 spin_lock_irqsave(ap->lock, flags);
1187 /* EH might have kicked in while host lock is
1190 qc = ata_qc_from_tag(ap, qc->tag);
1192 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1194 ata_qc_complete(qc);
1196 ata_port_freeze(ap);
1199 spin_unlock_irqrestore(ap->lock, flags);
1201 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1202 ata_qc_complete(qc);
1204 ata_port_freeze(ap);
1208 spin_lock_irqsave(ap->lock, flags);
1210 ata_qc_complete(qc);
1211 spin_unlock_irqrestore(ap->lock, flags);
1213 ata_qc_complete(qc);
1218 * ata_sff_hsm_move - move the HSM to the next state.
1219 * @ap: the target ata_port
1221 * @status: current device status
1222 * @in_wq: 1 if called from workqueue, 0 otherwise
1225 * 1 when poll next status needed, 0 otherwise.
1227 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1228 u8 status, int in_wq)
1230 struct ata_eh_info *ehi = &ap->link.eh_info;
1231 unsigned long flags = 0;
1234 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1236 /* Make sure ata_sff_qc_issue() does not throw things
1237 * like DMA polling into the workqueue. Notice that
1238 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1240 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1243 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1244 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1246 switch (ap->hsm_task_state) {
1248 /* Send first data block or PACKET CDB */
1250 /* If polling, we will stay in the work queue after
1251 * sending the data. Otherwise, interrupt handler
1252 * takes over after sending the data.
1254 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1256 /* check device status */
1257 if (unlikely((status & ATA_DRQ) == 0)) {
1258 /* handle BSY=0, DRQ=0 as error */
1259 if (likely(status & (ATA_ERR | ATA_DF)))
1260 /* device stops HSM for abort/error */
1261 qc->err_mask |= AC_ERR_DEV;
1263 /* HSM violation. Let EH handle this */
1264 ata_ehi_push_desc(ehi,
1265 "ST_FIRST: !(DRQ|ERR|DF)");
1266 qc->err_mask |= AC_ERR_HSM;
1269 ap->hsm_task_state = HSM_ST_ERR;
1273 /* Device should not ask for data transfer (DRQ=1)
1274 * when it finds something wrong.
1275 * We ignore DRQ here and stop the HSM by
1276 * changing hsm_task_state to HSM_ST_ERR and
1277 * let the EH abort the command or reset the device.
1279 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1280 /* Some ATAPI tape drives forget to clear the ERR bit
1281 * when doing the next command (mostly request sense).
1282 * We ignore ERR here to workaround and proceed sending
1285 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1286 ata_ehi_push_desc(ehi, "ST_FIRST: "
1287 "DRQ=1 with device error, "
1288 "dev_stat 0x%X", status);
1289 qc->err_mask |= AC_ERR_HSM;
1290 ap->hsm_task_state = HSM_ST_ERR;
1295 /* Send the CDB (atapi) or the first data block (ata pio out).
1296 * During the state transition, interrupt handler shouldn't
1297 * be invoked before the data transfer is complete and
1298 * hsm_task_state is changed. Hence, the following locking.
1301 spin_lock_irqsave(ap->lock, flags);
1303 if (qc->tf.protocol == ATA_PROT_PIO) {
1304 /* PIO data out protocol.
1305 * send first data block.
1308 /* ata_pio_sectors() might change the state
1309 * to HSM_ST_LAST. so, the state is changed here
1310 * before ata_pio_sectors().
1312 ap->hsm_task_state = HSM_ST;
1313 ata_pio_sectors(qc);
1316 atapi_send_cdb(ap, qc);
1319 spin_unlock_irqrestore(ap->lock, flags);
1321 /* if polling, ata_pio_task() handles the rest.
1322 * otherwise, interrupt handler takes over from here.
1327 /* complete command or read/write the data register */
1328 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1329 /* ATAPI PIO protocol */
1330 if ((status & ATA_DRQ) == 0) {
1331 /* No more data to transfer or device error.
1332 * Device error will be tagged in HSM_ST_LAST.
1334 ap->hsm_task_state = HSM_ST_LAST;
1338 /* Device should not ask for data transfer (DRQ=1)
1339 * when it finds something wrong.
1340 * We ignore DRQ here and stop the HSM by
1341 * changing hsm_task_state to HSM_ST_ERR and
1342 * let the EH abort the command or reset the device.
1344 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1345 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1346 "DRQ=1 with device error, "
1347 "dev_stat 0x%X", status);
1348 qc->err_mask |= AC_ERR_HSM;
1349 ap->hsm_task_state = HSM_ST_ERR;
1353 atapi_pio_bytes(qc);
1355 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1356 /* bad ireason reported by device */
1360 /* ATA PIO protocol */
1361 if (unlikely((status & ATA_DRQ) == 0)) {
1362 /* handle BSY=0, DRQ=0 as error */
1363 if (likely(status & (ATA_ERR | ATA_DF))) {
1364 /* device stops HSM for abort/error */
1365 qc->err_mask |= AC_ERR_DEV;
1367 /* If diagnostic failed and this is
1368 * IDENTIFY, it's likely a phantom
1369 * device. Mark hint.
1371 if (qc->dev->horkage &
1372 ATA_HORKAGE_DIAGNOSTIC)
1376 /* HSM violation. Let EH handle this.
1377 * Phantom devices also trigger this
1378 * condition. Mark hint.
1380 ata_ehi_push_desc(ehi, "ST-ATA: "
1381 "DRQ=0 without device error, "
1382 "dev_stat 0x%X", status);
1383 qc->err_mask |= AC_ERR_HSM |
1387 ap->hsm_task_state = HSM_ST_ERR;
1391 /* For PIO reads, some devices may ask for
1392 * data transfer (DRQ=1) alone with ERR=1.
1393 * We respect DRQ here and transfer one
1394 * block of junk data before changing the
1395 * hsm_task_state to HSM_ST_ERR.
1397 * For PIO writes, ERR=1 DRQ=1 doesn't make
1398 * sense since the data block has been
1399 * transferred to the device.
1401 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1402 /* data might be corrputed */
1403 qc->err_mask |= AC_ERR_DEV;
1405 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1406 ata_pio_sectors(qc);
1407 status = ata_wait_idle(ap);
1410 if (status & (ATA_BUSY | ATA_DRQ)) {
1411 ata_ehi_push_desc(ehi, "ST-ATA: "
1412 "BUSY|DRQ persists on ERR|DF, "
1413 "dev_stat 0x%X", status);
1414 qc->err_mask |= AC_ERR_HSM;
1417 /* There are oddball controllers with
1418 * status register stuck at 0x7f and
1419 * lbal/m/h at zero which makes it
1420 * pass all other presence detection
1421 * mechanisms we have. Set NODEV_HINT
1422 * for it. Kernel bz#7241.
1425 qc->err_mask |= AC_ERR_NODEV_HINT;
1427 /* ata_pio_sectors() might change the
1428 * state to HSM_ST_LAST. so, the state
1429 * is changed after ata_pio_sectors().
1431 ap->hsm_task_state = HSM_ST_ERR;
1435 ata_pio_sectors(qc);
1437 if (ap->hsm_task_state == HSM_ST_LAST &&
1438 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1440 status = ata_wait_idle(ap);
1449 if (unlikely(!ata_ok(status))) {
1450 qc->err_mask |= __ac_err_mask(status);
1451 ap->hsm_task_state = HSM_ST_ERR;
1455 /* no more data to transfer */
1456 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1457 ap->print_id, qc->dev->devno, status);
1459 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1461 ap->hsm_task_state = HSM_ST_IDLE;
1463 /* complete taskfile transaction */
1464 ata_hsm_qc_complete(qc, in_wq);
1470 ap->hsm_task_state = HSM_ST_IDLE;
1472 /* complete taskfile transaction */
1473 ata_hsm_qc_complete(qc, in_wq);
1484 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1486 void ata_pio_task(struct work_struct *work)
1488 struct ata_port *ap =
1489 container_of(work, struct ata_port, port_task.work);
1490 struct ata_queued_cmd *qc = ap->port_task_data;
1495 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1498 * This is purely heuristic. This is a fast path.
1499 * Sometimes when we enter, BSY will be cleared in
1500 * a chk-status or two. If not, the drive is probably seeking
1501 * or something. Snooze for a couple msecs, then
1502 * chk-status again. If still busy, queue delayed work.
1504 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1505 if (status & ATA_BUSY) {
1507 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1508 if (status & ATA_BUSY) {
1509 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1515 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1517 /* another command or interrupt handler
1518 * may be running at this point.
1525 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
1526 * @qc: command to issue to device
1528 * Using various libata functions and hooks, this function
1529 * starts an ATA command. ATA commands are grouped into
1530 * classes called "protocols", and issuing each type of protocol
1531 * is slightly different.
1533 * May be used as the qc_issue() entry in ata_port_operations.
1536 * spin_lock_irqsave(host lock)
1539 * Zero on success, AC_ERR_* mask on failure
1541 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1543 struct ata_port *ap = qc->ap;
1545 /* Use polling pio if the LLD doesn't handle
1546 * interrupt driven pio and atapi CDB interrupt.
1548 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1549 switch (qc->tf.protocol) {
1551 case ATA_PROT_NODATA:
1552 case ATAPI_PROT_PIO:
1553 case ATAPI_PROT_NODATA:
1554 qc->tf.flags |= ATA_TFLAG_POLLING;
1556 case ATAPI_PROT_DMA:
1557 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1558 /* see ata_dma_blacklisted() */
1566 /* select the device */
1567 ata_dev_select(ap, qc->dev->devno, 1, 0);
1569 /* start the command */
1570 switch (qc->tf.protocol) {
1571 case ATA_PROT_NODATA:
1572 if (qc->tf.flags & ATA_TFLAG_POLLING)
1573 ata_qc_set_polling(qc);
1575 ata_tf_to_host(ap, &qc->tf);
1576 ap->hsm_task_state = HSM_ST_LAST;
1578 if (qc->tf.flags & ATA_TFLAG_POLLING)
1579 ata_pio_queue_task(ap, qc, 0);
1584 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
1586 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1587 ap->ops->bmdma_setup(qc); /* set up bmdma */
1588 ap->ops->bmdma_start(qc); /* initiate bmdma */
1589 ap->hsm_task_state = HSM_ST_LAST;
1593 if (qc->tf.flags & ATA_TFLAG_POLLING)
1594 ata_qc_set_polling(qc);
1596 ata_tf_to_host(ap, &qc->tf);
1598 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1599 /* PIO data out protocol */
1600 ap->hsm_task_state = HSM_ST_FIRST;
1601 ata_pio_queue_task(ap, qc, 0);
1603 /* always send first data block using
1604 * the ata_pio_task() codepath.
1607 /* PIO data in protocol */
1608 ap->hsm_task_state = HSM_ST;
1610 if (qc->tf.flags & ATA_TFLAG_POLLING)
1611 ata_pio_queue_task(ap, qc, 0);
1613 /* if polling, ata_pio_task() handles the rest.
1614 * otherwise, interrupt handler takes over from here.
1620 case ATAPI_PROT_PIO:
1621 case ATAPI_PROT_NODATA:
1622 if (qc->tf.flags & ATA_TFLAG_POLLING)
1623 ata_qc_set_polling(qc);
1625 ata_tf_to_host(ap, &qc->tf);
1627 ap->hsm_task_state = HSM_ST_FIRST;
1629 /* send cdb by polling if no cdb interrupt */
1630 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1631 (qc->tf.flags & ATA_TFLAG_POLLING))
1632 ata_pio_queue_task(ap, qc, 0);
1635 case ATAPI_PROT_DMA:
1636 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
1638 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1639 ap->ops->bmdma_setup(qc); /* set up bmdma */
1640 ap->hsm_task_state = HSM_ST_FIRST;
1642 /* send cdb by polling if no cdb interrupt */
1643 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1644 ata_pio_queue_task(ap, qc, 0);
1649 return AC_ERR_SYSTEM;
1654 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1657 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1658 * @qc: qc to fill result TF for
1660 * @qc is finished and result TF needs to be filled. Fill it
1661 * using ->sff_tf_read.
1664 * spin_lock_irqsave(host lock)
1667 * true indicating that result TF is successfully filled.
1669 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1671 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1674 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1677 * ata_sff_host_intr - Handle host interrupt for given (port, task)
1678 * @ap: Port on which interrupt arrived (possibly...)
1679 * @qc: Taskfile currently active in engine
1681 * Handle host interrupt for given queued command. Currently,
1682 * only DMA interrupts are handled. All other commands are
1683 * handled via polling with interrupts disabled (nIEN bit).
1686 * spin_lock_irqsave(host lock)
1689 * One if interrupt was handled, zero if not (shared irq).
1691 unsigned int ata_sff_host_intr(struct ata_port *ap,
1692 struct ata_queued_cmd *qc)
1694 struct ata_eh_info *ehi = &ap->link.eh_info;
1695 u8 status, host_stat = 0;
1696 bool bmdma_stopped = false;
1698 VPRINTK("ata%u: protocol %d task_state %d\n",
1699 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1701 /* Check whether we are expecting interrupt in this state */
1702 switch (ap->hsm_task_state) {
1704 /* Some pre-ATAPI-4 devices assert INTRQ
1705 * at this state when ready to receive CDB.
1708 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1709 * The flag was turned on only for atapi devices. No
1710 * need to check ata_is_atapi(qc->tf.protocol) again.
1712 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1716 if (qc->tf.protocol == ATA_PROT_DMA ||
1717 qc->tf.protocol == ATAPI_PROT_DMA) {
1718 /* check status of DMA engine */
1719 host_stat = ap->ops->bmdma_status(ap);
1720 VPRINTK("ata%u: host_stat 0x%X\n",
1721 ap->print_id, host_stat);
1723 /* if it's not our irq... */
1724 if (!(host_stat & ATA_DMA_INTR))
1727 /* before we do anything else, clear DMA-Start bit */
1728 ap->ops->bmdma_stop(qc);
1729 bmdma_stopped = true;
1731 if (unlikely(host_stat & ATA_DMA_ERR)) {
1732 /* error when transfering data to/from memory */
1733 qc->err_mask |= AC_ERR_HOST_BUS;
1734 ap->hsm_task_state = HSM_ST_ERR;
1745 /* check main status, clearing INTRQ if needed */
1746 status = ata_sff_irq_status(ap);
1747 if (status & ATA_BUSY) {
1748 if (bmdma_stopped) {
1749 /* BMDMA engine is already stopped, we're screwed */
1750 qc->err_mask |= AC_ERR_HSM;
1751 ap->hsm_task_state = HSM_ST_ERR;
1756 /* ack bmdma irq events */
1757 ap->ops->sff_irq_clear(ap);
1759 ata_sff_hsm_move(ap, qc, status, 0);
1761 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1762 qc->tf.protocol == ATAPI_PROT_DMA))
1763 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1765 return 1; /* irq handled */
1768 ap->stats.idle_irq++;
1771 if ((ap->stats.idle_irq % 1000) == 0) {
1772 ap->ops->sff_check_status(ap);
1773 ap->ops->sff_irq_clear(ap);
1774 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1778 return 0; /* irq not handled */
1780 EXPORT_SYMBOL_GPL(ata_sff_host_intr);
1783 * ata_sff_interrupt - Default ATA host interrupt handler
1784 * @irq: irq line (unused)
1785 * @dev_instance: pointer to our ata_host information structure
1787 * Default interrupt handler for PCI IDE devices. Calls
1788 * ata_sff_host_intr() for each port that is not disabled.
1791 * Obtains host lock during operation.
1794 * IRQ_NONE or IRQ_HANDLED.
1796 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1798 struct ata_host *host = dev_instance;
1799 bool retried = false;
1801 unsigned int handled, idle, polling;
1802 unsigned long flags;
1804 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1805 spin_lock_irqsave(&host->lock, flags);
1808 handled = idle = polling = 0;
1809 for (i = 0; i < host->n_ports; i++) {
1810 struct ata_port *ap = host->ports[i];
1811 struct ata_queued_cmd *qc;
1813 if (unlikely(ap->flags & ATA_FLAG_DISABLED))
1816 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1818 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1819 handled |= ata_sff_host_intr(ap, qc);
1827 * If no port was expecting IRQ but the controller is actually
1828 * asserting IRQ line, nobody cared will ensue. Check IRQ
1829 * pending status if available and clear spurious IRQ.
1831 if (!handled && !retried) {
1834 for (i = 0; i < host->n_ports; i++) {
1835 struct ata_port *ap = host->ports[i];
1837 if (polling & (1 << i))
1840 if (!ap->ops->sff_irq_check ||
1841 !ap->ops->sff_irq_check(ap))
1844 if (idle & (1 << i)) {
1845 ap->ops->sff_check_status(ap);
1846 ap->ops->sff_irq_clear(ap);
1848 /* clear INTRQ and check if BUSY cleared */
1849 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1852 * With command in flight, we can't do
1853 * sff_irq_clear() w/o racing with completion.
1864 spin_unlock_irqrestore(&host->lock, flags);
1866 return IRQ_RETVAL(handled);
1868 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1871 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1872 * @ap: port that appears to have timed out
1874 * Called from the libata error handlers when the core code suspects
1875 * an interrupt has been lost. If it has complete anything we can and
1876 * then return. Interface must support altstatus for this faster
1877 * recovery to occur.
1880 * Caller holds host lock
1883 void ata_sff_lost_interrupt(struct ata_port *ap)
1886 struct ata_queued_cmd *qc;
1888 /* Only one outstanding command per SFF channel */
1889 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1890 /* Check we have a live one.. */
1891 if (qc == NULL || !(qc->flags & ATA_QCFLAG_ACTIVE))
1893 /* We cannot lose an interrupt on a polled command */
1894 if (qc->tf.flags & ATA_TFLAG_POLLING)
1896 /* See if the controller thinks it is still busy - if so the command
1897 isn't a lost IRQ but is still in progress */
1898 status = ata_sff_altstatus(ap);
1899 if (status & ATA_BUSY)
1902 /* There was a command running, we are no longer busy and we have
1904 ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n",
1906 /* Run the host interrupt logic as if the interrupt had not been
1908 ata_sff_host_intr(ap, qc);
1910 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1913 * ata_sff_freeze - Freeze SFF controller port
1914 * @ap: port to freeze
1916 * Freeze BMDMA controller port.
1919 * Inherited from caller.
1921 void ata_sff_freeze(struct ata_port *ap)
1923 ap->ctl |= ATA_NIEN;
1924 ap->last_ctl = ap->ctl;
1926 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1927 ata_sff_set_devctl(ap, ap->ctl);
1929 /* Under certain circumstances, some controllers raise IRQ on
1930 * ATA_NIEN manipulation. Also, many controllers fail to mask
1931 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1933 ap->ops->sff_check_status(ap);
1935 ap->ops->sff_irq_clear(ap);
1937 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1940 * ata_sff_thaw - Thaw SFF controller port
1943 * Thaw SFF controller port.
1946 * Inherited from caller.
1948 void ata_sff_thaw(struct ata_port *ap)
1950 /* clear & re-enable interrupts */
1951 ap->ops->sff_check_status(ap);
1952 ap->ops->sff_irq_clear(ap);
1955 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1958 * ata_sff_prereset - prepare SFF link for reset
1959 * @link: SFF link to be reset
1960 * @deadline: deadline jiffies for the operation
1962 * SFF link @link is about to be reset. Initialize it. It first
1963 * calls ata_std_prereset() and wait for !BSY if the port is
1967 * Kernel thread context (may sleep)
1970 * 0 on success, -errno otherwise.
1972 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1974 struct ata_eh_context *ehc = &link->eh_context;
1977 rc = ata_std_prereset(link, deadline);
1981 /* if we're about to do hardreset, nothing more to do */
1982 if (ehc->i.action & ATA_EH_HARDRESET)
1985 /* wait for !BSY if we don't know that no device is attached */
1986 if (!ata_link_offline(link)) {
1987 rc = ata_sff_wait_ready(link, deadline);
1988 if (rc && rc != -ENODEV) {
1989 ata_link_printk(link, KERN_WARNING, "device not ready "
1990 "(errno=%d), forcing hardreset\n", rc);
1991 ehc->i.action |= ATA_EH_HARDRESET;
1997 EXPORT_SYMBOL_GPL(ata_sff_prereset);
2000 * ata_devchk - PATA device presence detection
2001 * @ap: ATA channel to examine
2002 * @device: Device to examine (starting at zero)
2004 * This technique was originally described in
2005 * Hale Landis's ATADRVR (www.ata-atapi.com), and
2006 * later found its way into the ATA/ATAPI spec.
2008 * Write a pattern to the ATA shadow registers,
2009 * and if a device is present, it will respond by
2010 * correctly storing and echoing back the
2011 * ATA shadow register contents.
2016 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
2018 struct ata_ioports *ioaddr = &ap->ioaddr;
2021 ap->ops->sff_dev_select(ap, device);
2023 iowrite8(0x55, ioaddr->nsect_addr);
2024 iowrite8(0xaa, ioaddr->lbal_addr);
2026 iowrite8(0xaa, ioaddr->nsect_addr);
2027 iowrite8(0x55, ioaddr->lbal_addr);
2029 iowrite8(0x55, ioaddr->nsect_addr);
2030 iowrite8(0xaa, ioaddr->lbal_addr);
2032 nsect = ioread8(ioaddr->nsect_addr);
2033 lbal = ioread8(ioaddr->lbal_addr);
2035 if ((nsect == 0x55) && (lbal == 0xaa))
2036 return 1; /* we found a device */
2038 return 0; /* nothing found */
2042 * ata_sff_dev_classify - Parse returned ATA device signature
2043 * @dev: ATA device to classify (starting at zero)
2044 * @present: device seems present
2045 * @r_err: Value of error register on completion
2047 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
2048 * an ATA/ATAPI-defined set of values is placed in the ATA
2049 * shadow registers, indicating the results of device detection
2052 * Select the ATA device, and read the values from the ATA shadow
2053 * registers. Then parse according to the Error register value,
2054 * and the spec-defined values examined by ata_dev_classify().
2060 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
2062 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
2065 struct ata_port *ap = dev->link->ap;
2066 struct ata_taskfile tf;
2070 ap->ops->sff_dev_select(ap, dev->devno);
2072 memset(&tf, 0, sizeof(tf));
2074 ap->ops->sff_tf_read(ap, &tf);
2079 /* see if device passed diags: continue and warn later */
2081 /* diagnostic fail : do nothing _YET_ */
2082 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
2085 else if ((dev->devno == 0) && (err == 0x81))
2088 return ATA_DEV_NONE;
2090 /* determine if device is ATA or ATAPI */
2091 class = ata_dev_classify(&tf);
2093 if (class == ATA_DEV_UNKNOWN) {
2094 /* If the device failed diagnostic, it's likely to
2095 * have reported incorrect device signature too.
2096 * Assume ATA device if the device seems present but
2097 * device signature is invalid with diagnostic
2100 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
2101 class = ATA_DEV_ATA;
2103 class = ATA_DEV_NONE;
2104 } else if ((class == ATA_DEV_ATA) &&
2105 (ap->ops->sff_check_status(ap) == 0))
2106 class = ATA_DEV_NONE;
2110 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2113 * ata_sff_wait_after_reset - wait for devices to become ready after reset
2114 * @link: SFF link which is just reset
2115 * @devmask: mask of present devices
2116 * @deadline: deadline jiffies for the operation
2118 * Wait devices attached to SFF @link to become ready after
2119 * reset. It contains preceding 150ms wait to avoid accessing TF
2120 * status register too early.
2123 * Kernel thread context (may sleep).
2126 * 0 on success, -ENODEV if some or all of devices in @devmask
2127 * don't seem to exist. -errno on other errors.
2129 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
2130 unsigned long deadline)
2132 struct ata_port *ap = link->ap;
2133 struct ata_ioports *ioaddr = &ap->ioaddr;
2134 unsigned int dev0 = devmask & (1 << 0);
2135 unsigned int dev1 = devmask & (1 << 1);
2138 msleep(ATA_WAIT_AFTER_RESET);
2140 /* always check readiness of the master device */
2141 rc = ata_sff_wait_ready(link, deadline);
2142 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
2143 * and TF status is 0xff, bail out on it too.
2148 /* if device 1 was found in ata_devchk, wait for register
2149 * access briefly, then wait for BSY to clear.
2154 ap->ops->sff_dev_select(ap, 1);
2156 /* Wait for register access. Some ATAPI devices fail
2157 * to set nsect/lbal after reset, so don't waste too
2158 * much time on it. We're gonna wait for !BSY anyway.
2160 for (i = 0; i < 2; i++) {
2163 nsect = ioread8(ioaddr->nsect_addr);
2164 lbal = ioread8(ioaddr->lbal_addr);
2165 if ((nsect == 1) && (lbal == 1))
2167 msleep(50); /* give drive a breather */
2170 rc = ata_sff_wait_ready(link, deadline);
2178 /* is all this really necessary? */
2179 ap->ops->sff_dev_select(ap, 0);
2181 ap->ops->sff_dev_select(ap, 1);
2183 ap->ops->sff_dev_select(ap, 0);
2187 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2189 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2190 unsigned long deadline)
2192 struct ata_ioports *ioaddr = &ap->ioaddr;
2194 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2196 /* software reset. causes dev0 to be selected */
2197 iowrite8(ap->ctl, ioaddr->ctl_addr);
2198 udelay(20); /* FIXME: flush */
2199 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2200 udelay(20); /* FIXME: flush */
2201 iowrite8(ap->ctl, ioaddr->ctl_addr);
2202 ap->last_ctl = ap->ctl;
2204 /* wait the port to become ready */
2205 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2209 * ata_sff_softreset - reset host port via ATA SRST
2210 * @link: ATA link to reset
2211 * @classes: resulting classes of attached devices
2212 * @deadline: deadline jiffies for the operation
2214 * Reset host port using ATA SRST.
2217 * Kernel thread context (may sleep)
2220 * 0 on success, -errno otherwise.
2222 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2223 unsigned long deadline)
2225 struct ata_port *ap = link->ap;
2226 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2227 unsigned int devmask = 0;
2233 /* determine if device 0/1 are present */
2234 if (ata_devchk(ap, 0))
2235 devmask |= (1 << 0);
2236 if (slave_possible && ata_devchk(ap, 1))
2237 devmask |= (1 << 1);
2239 /* select device 0 again */
2240 ap->ops->sff_dev_select(ap, 0);
2242 /* issue bus reset */
2243 DPRINTK("about to softreset, devmask=%x\n", devmask);
2244 rc = ata_bus_softreset(ap, devmask, deadline);
2245 /* if link is occupied, -ENODEV too is an error */
2246 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2247 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2251 /* determine by signature whether we have ATA or ATAPI devices */
2252 classes[0] = ata_sff_dev_classify(&link->device[0],
2253 devmask & (1 << 0), &err);
2254 if (slave_possible && err != 0x81)
2255 classes[1] = ata_sff_dev_classify(&link->device[1],
2256 devmask & (1 << 1), &err);
2258 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2261 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2264 * sata_sff_hardreset - reset host port via SATA phy reset
2265 * @link: link to reset
2266 * @class: resulting class of attached device
2267 * @deadline: deadline jiffies for the operation
2269 * SATA phy-reset host port using DET bits of SControl register,
2270 * wait for !BSY and classify the attached device.
2273 * Kernel thread context (may sleep)
2276 * 0 on success, -errno otherwise.
2278 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2279 unsigned long deadline)
2281 struct ata_eh_context *ehc = &link->eh_context;
2282 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2286 rc = sata_link_hardreset(link, timing, deadline, &online,
2287 ata_sff_check_ready);
2289 *class = ata_sff_dev_classify(link->device, 1, NULL);
2291 DPRINTK("EXIT, class=%u\n", *class);
2294 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2297 * ata_sff_postreset - SFF postreset callback
2298 * @link: the target SFF ata_link
2299 * @classes: classes of attached devices
2301 * This function is invoked after a successful reset. It first
2302 * calls ata_std_postreset() and performs SFF specific postreset
2306 * Kernel thread context (may sleep)
2308 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2310 struct ata_port *ap = link->ap;
2312 ata_std_postreset(link, classes);
2314 /* is double-select really necessary? */
2315 if (classes[0] != ATA_DEV_NONE)
2316 ap->ops->sff_dev_select(ap, 1);
2317 if (classes[1] != ATA_DEV_NONE)
2318 ap->ops->sff_dev_select(ap, 0);
2320 /* bail out if no device is present */
2321 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2322 DPRINTK("EXIT, no device\n");
2326 /* set up device control */
2327 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2328 ata_sff_set_devctl(ap, ap->ctl);
2329 ap->last_ctl = ap->ctl;
2332 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2335 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2338 * Drain the FIFO and device of any stuck data following a command
2339 * failing to complete. In some cases this is necessary before a
2340 * reset will recover the device.
2344 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2347 struct ata_port *ap;
2349 /* We only need to flush incoming data when a command was running */
2350 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2354 /* Drain up to 64K of data before we give up this recovery method */
2355 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2356 && count < 65536; count += 2)
2357 ioread16(ap->ioaddr.data_addr);
2359 /* Can become DEBUG later */
2361 ata_port_printk(ap, KERN_DEBUG,
2362 "drained %d bytes to clear DRQ.\n", count);
2365 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2368 * ata_sff_error_handler - Stock error handler for BMDMA controller
2369 * @ap: port to handle error for
2371 * Stock error handler for SFF controller. It can handle both
2372 * PATA and SATA controllers. Many controllers should be able to
2373 * use this EH as-is or with some added handling before and
2377 * Kernel thread context (may sleep)
2379 void ata_sff_error_handler(struct ata_port *ap)
2381 ata_reset_fn_t softreset = ap->ops->softreset;
2382 ata_reset_fn_t hardreset = ap->ops->hardreset;
2383 struct ata_queued_cmd *qc;
2384 unsigned long flags;
2387 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2388 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2391 /* reset PIO HSM and stop DMA engine */
2392 spin_lock_irqsave(ap->lock, flags);
2394 ap->hsm_task_state = HSM_ST_IDLE;
2396 if (ap->ioaddr.bmdma_addr &&
2397 qc && (qc->tf.protocol == ATA_PROT_DMA ||
2398 qc->tf.protocol == ATAPI_PROT_DMA)) {
2401 host_stat = ap->ops->bmdma_status(ap);
2403 /* BMDMA controllers indicate host bus error by
2404 * setting DMA_ERR bit and timing out. As it wasn't
2405 * really a timeout event, adjust error mask and
2406 * cancel frozen state.
2408 if (qc->err_mask == AC_ERR_TIMEOUT
2409 && (host_stat & ATA_DMA_ERR)) {
2410 qc->err_mask = AC_ERR_HOST_BUS;
2414 ap->ops->bmdma_stop(qc);
2417 ata_sff_sync(ap); /* FIXME: We don't need this */
2418 ap->ops->sff_check_status(ap);
2419 ap->ops->sff_irq_clear(ap);
2420 /* We *MUST* do FIFO draining before we issue a reset as several
2421 * devices helpfully clear their internal state and will lock solid
2422 * if we touch the data port post reset. Pass qc in case anyone wants
2423 * to do different PIO/DMA recovery or has per command fixups
2425 if (ap->ops->drain_fifo)
2426 ap->ops->drain_fifo(qc);
2428 spin_unlock_irqrestore(ap->lock, flags);
2431 ata_eh_thaw_port(ap);
2433 /* PIO and DMA engines have been stopped, perform recovery */
2435 /* Ignore ata_sff_softreset if ctl isn't accessible and
2436 * built-in hardresets if SCR access isn't available.
2438 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2440 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
2443 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2444 ap->ops->postreset);
2446 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2449 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
2450 * @qc: internal command to clean up
2453 * Kernel thread context (may sleep)
2455 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
2457 struct ata_port *ap = qc->ap;
2458 unsigned long flags;
2460 spin_lock_irqsave(ap->lock, flags);
2462 ap->hsm_task_state = HSM_ST_IDLE;
2464 if (ap->ioaddr.bmdma_addr)
2465 ap->ops->bmdma_stop(qc);
2467 spin_unlock_irqrestore(ap->lock, flags);
2469 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2472 * ata_sff_port_start - Set port up for dma.
2473 * @ap: Port to initialize
2475 * Called just after data structures for each port are
2476 * initialized. Allocates space for PRD table if the device
2477 * is DMA capable SFF.
2479 * May be used as the port_start() entry in ata_port_operations.
2482 * Inherited from caller.
2484 int ata_sff_port_start(struct ata_port *ap)
2486 if (ap->ioaddr.bmdma_addr)
2487 return ata_port_start(ap);
2490 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2493 * ata_sff_port_start32 - Set port up for dma.
2494 * @ap: Port to initialize
2496 * Called just after data structures for each port are
2497 * initialized. Allocates space for PRD table if the device
2498 * is DMA capable SFF.
2500 * May be used as the port_start() entry in ata_port_operations for
2501 * devices that are capable of 32bit PIO.
2504 * Inherited from caller.
2506 int ata_sff_port_start32(struct ata_port *ap)
2508 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
2509 if (ap->ioaddr.bmdma_addr)
2510 return ata_port_start(ap);
2513 EXPORT_SYMBOL_GPL(ata_sff_port_start32);
2516 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2517 * @ioaddr: IO address structure to be initialized
2519 * Utility function which initializes data_addr, error_addr,
2520 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2521 * device_addr, status_addr, and command_addr to standard offsets
2522 * relative to cmd_addr.
2524 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2526 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2528 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2529 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2530 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2531 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2532 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2533 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2534 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2535 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2536 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2537 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2539 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2541 unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2542 unsigned long xfer_mask)
2544 /* Filter out DMA modes if the device has been configured by
2545 the BIOS as PIO only */
2547 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2548 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2551 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2554 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2555 * @qc: Info associated with this ATA transaction.
2558 * spin_lock_irqsave(host lock)
2560 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2562 struct ata_port *ap = qc->ap;
2563 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2566 /* load PRD table addr. */
2567 mb(); /* make sure PRD table writes are visible to controller */
2568 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2570 /* specify data direction, triple-check start bit is clear */
2571 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2572 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2574 dmactl |= ATA_DMA_WR;
2575 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2577 /* issue r/w command */
2578 ap->ops->sff_exec_command(ap, &qc->tf);
2580 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2583 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2584 * @qc: Info associated with this ATA transaction.
2587 * spin_lock_irqsave(host lock)
2589 void ata_bmdma_start(struct ata_queued_cmd *qc)
2591 struct ata_port *ap = qc->ap;
2594 /* start host DMA transaction */
2595 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2596 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2598 /* Strictly, one may wish to issue an ioread8() here, to
2599 * flush the mmio write. However, control also passes
2600 * to the hardware at this point, and it will interrupt
2601 * us when we are to resume control. So, in effect,
2602 * we don't care when the mmio write flushes.
2603 * Further, a read of the DMA status register _immediately_
2604 * following the write may not be what certain flaky hardware
2605 * is expected, so I think it is best to not add a readb()
2606 * without first all the MMIO ATA cards/mobos.
2607 * Or maybe I'm just being paranoid.
2609 * FIXME: The posting of this write means I/O starts are
2610 * unneccessarily delayed for MMIO
2613 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2616 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2617 * @qc: Command we are ending DMA for
2619 * Clears the ATA_DMA_START flag in the dma control register
2621 * May be used as the bmdma_stop() entry in ata_port_operations.
2624 * spin_lock_irqsave(host lock)
2626 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2628 struct ata_port *ap = qc->ap;
2629 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2631 /* clear start/stop bit */
2632 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2633 mmio + ATA_DMA_CMD);
2635 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2636 ata_sff_dma_pause(ap);
2638 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2641 * ata_bmdma_status - Read PCI IDE BMDMA status
2642 * @ap: Port associated with this ATA transaction.
2644 * Read and return BMDMA status register.
2646 * May be used as the bmdma_status() entry in ata_port_operations.
2649 * spin_lock_irqsave(host lock)
2651 u8 ata_bmdma_status(struct ata_port *ap)
2653 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2655 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2660 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
2663 * Some PCI ATA devices report simplex mode but in fact can be told to
2664 * enter non simplex mode. This implements the necessary logic to
2665 * perform the task on such devices. Calling it on other devices will
2666 * have -undefined- behaviour.
2668 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2670 unsigned long bmdma = pci_resource_start(pdev, 4);
2676 simplex = inb(bmdma + 0x02);
2677 outb(simplex & 0x60, bmdma + 0x02);
2678 simplex = inb(bmdma + 0x02);
2683 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2686 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
2687 * @host: target ATA host
2689 * Acquire PCI BMDMA resources and initialize @host accordingly.
2692 * Inherited from calling layer (may sleep).
2695 * 0 on success, -errno otherwise.
2697 int ata_pci_bmdma_init(struct ata_host *host)
2699 struct device *gdev = host->dev;
2700 struct pci_dev *pdev = to_pci_dev(gdev);
2703 /* No BAR4 allocation: No DMA */
2704 if (pci_resource_start(pdev, 4) == 0)
2707 /* TODO: If we get no DMA mask we should fall back to PIO */
2708 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2711 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2715 /* request and iomap DMA region */
2716 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2718 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2721 host->iomap = pcim_iomap_table(pdev);
2723 for (i = 0; i < 2; i++) {
2724 struct ata_port *ap = host->ports[i];
2725 void __iomem *bmdma = host->iomap[4] + 8 * i;
2727 if (ata_port_is_dummy(ap))
2730 ap->ioaddr.bmdma_addr = bmdma;
2731 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2732 (ioread8(bmdma + 2) & 0x80))
2733 host->flags |= ATA_HOST_SIMPLEX;
2735 ata_port_desc(ap, "bmdma 0x%llx",
2736 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2741 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2743 static int ata_resources_present(struct pci_dev *pdev, int port)
2747 /* Check the PCI resources for this channel are enabled */
2749 for (i = 0; i < 2; i++) {
2750 if (pci_resource_start(pdev, port + i) == 0 ||
2751 pci_resource_len(pdev, port + i) == 0)
2758 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2759 * @host: target ATA host
2761 * Acquire native PCI ATA resources for @host and initialize the
2762 * first two ports of @host accordingly. Ports marked dummy are
2763 * skipped and allocation failure makes the port dummy.
2765 * Note that native PCI resources are valid even for legacy hosts
2766 * as we fix up pdev resources array early in boot, so this
2767 * function can be used for both native and legacy SFF hosts.
2770 * Inherited from calling layer (may sleep).
2773 * 0 if at least one port is initialized, -ENODEV if no port is
2776 int ata_pci_sff_init_host(struct ata_host *host)
2778 struct device *gdev = host->dev;
2779 struct pci_dev *pdev = to_pci_dev(gdev);
2780 unsigned int mask = 0;
2783 /* request, iomap BARs and init port addresses accordingly */
2784 for (i = 0; i < 2; i++) {
2785 struct ata_port *ap = host->ports[i];
2787 void __iomem * const *iomap;
2789 if (ata_port_is_dummy(ap))
2792 /* Discard disabled ports. Some controllers show
2793 * their unused channels this way. Disabled ports are
2796 if (!ata_resources_present(pdev, i)) {
2797 ap->ops = &ata_dummy_port_ops;
2801 rc = pcim_iomap_regions(pdev, 0x3 << base,
2802 dev_driver_string(gdev));
2804 dev_printk(KERN_WARNING, gdev,
2805 "failed to request/iomap BARs for port %d "
2806 "(errno=%d)\n", i, rc);
2808 pcim_pin_device(pdev);
2809 ap->ops = &ata_dummy_port_ops;
2812 host->iomap = iomap = pcim_iomap_table(pdev);
2814 ap->ioaddr.cmd_addr = iomap[base];
2815 ap->ioaddr.altstatus_addr =
2816 ap->ioaddr.ctl_addr = (void __iomem *)
2817 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2818 ata_sff_std_ports(&ap->ioaddr);
2820 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2821 (unsigned long long)pci_resource_start(pdev, base),
2822 (unsigned long long)pci_resource_start(pdev, base + 1));
2828 dev_printk(KERN_ERR, gdev, "no available native port\n");
2834 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2837 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
2838 * @pdev: target PCI device
2839 * @ppi: array of port_info, must be enough for two ports
2840 * @r_host: out argument for the initialized ATA host
2842 * Helper to allocate ATA host for @pdev, acquire all native PCI
2843 * resources and initialize it accordingly in one go.
2846 * Inherited from calling layer (may sleep).
2849 * 0 on success, -errno otherwise.
2851 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2852 const struct ata_port_info * const *ppi,
2853 struct ata_host **r_host)
2855 struct ata_host *host;
2858 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2861 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2863 dev_printk(KERN_ERR, &pdev->dev,
2864 "failed to allocate ATA host\n");
2869 rc = ata_pci_sff_init_host(host);
2873 /* init DMA related stuff */
2874 rc = ata_pci_bmdma_init(host);
2878 devres_remove_group(&pdev->dev, NULL);
2883 /* This is necessary because PCI and iomap resources are
2884 * merged and releasing the top group won't release the
2885 * acquired resources if some of those have been acquired
2886 * before entering this function.
2888 pcim_iounmap_regions(pdev, 0xf);
2890 devres_release_group(&pdev->dev, NULL);
2893 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2896 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2897 * @host: target SFF ATA host
2898 * @irq_handler: irq_handler used when requesting IRQ(s)
2899 * @sht: scsi_host_template to use when registering the host
2901 * This is the counterpart of ata_host_activate() for SFF ATA
2902 * hosts. This separate helper is necessary because SFF hosts
2903 * use two separate interrupts in legacy mode.
2906 * Inherited from calling layer (may sleep).
2909 * 0 on success, -errno otherwise.
2911 int ata_pci_sff_activate_host(struct ata_host *host,
2912 irq_handler_t irq_handler,
2913 struct scsi_host_template *sht)
2915 struct device *dev = host->dev;
2916 struct pci_dev *pdev = to_pci_dev(dev);
2917 const char *drv_name = dev_driver_string(host->dev);
2918 int legacy_mode = 0, rc;
2920 rc = ata_host_start(host);
2924 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2927 /* TODO: What if one channel is in native mode ... */
2928 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2929 mask = (1 << 2) | (1 << 0);
2930 if ((tmp8 & mask) != mask)
2932 #if defined(CONFIG_NO_ATA_LEGACY)
2933 /* Some platforms with PCI limits cannot address compat
2934 port space. In that case we punt if their firmware has
2935 left a device in compatibility mode */
2937 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2943 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2946 if (!legacy_mode && pdev->irq) {
2947 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2948 IRQF_SHARED, drv_name, host);
2952 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2953 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2954 } else if (legacy_mode) {
2955 if (!ata_port_is_dummy(host->ports[0])) {
2956 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2957 irq_handler, IRQF_SHARED,
2962 ata_port_desc(host->ports[0], "irq %d",
2963 ATA_PRIMARY_IRQ(pdev));
2966 if (!ata_port_is_dummy(host->ports[1])) {
2967 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2968 irq_handler, IRQF_SHARED,
2973 ata_port_desc(host->ports[1], "irq %d",
2974 ATA_SECONDARY_IRQ(pdev));
2978 rc = ata_host_register(host, sht);
2981 devres_remove_group(dev, NULL);
2983 devres_release_group(dev, NULL);
2987 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2990 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
2991 * @pdev: Controller to be initialized
2992 * @ppi: array of port_info, must be enough for two ports
2993 * @sht: scsi_host_template to use when registering the host
2994 * @host_priv: host private_data
2995 * @hflag: host flags
2997 * This is a helper function which can be called from a driver's
2998 * xxx_init_one() probe function if the hardware uses traditional
2999 * IDE taskfile registers.
3001 * This function calls pci_enable_device(), reserves its register
3002 * regions, sets the dma mask, enables bus master mode, and calls
3006 * Nobody makes a single channel controller that appears solely as
3007 * the secondary legacy port on PCI.
3010 * Inherited from PCI layer (may sleep).
3013 * Zero on success, negative on errno-based value on error.
3015 int ata_pci_sff_init_one(struct pci_dev *pdev,
3016 const struct ata_port_info * const *ppi,
3017 struct scsi_host_template *sht, void *host_priv, int hflag)
3019 struct device *dev = &pdev->dev;
3020 const struct ata_port_info *pi = NULL;
3021 struct ata_host *host = NULL;
3026 /* look up the first valid port_info */
3027 for (i = 0; i < 2 && ppi[i]; i++) {
3028 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
3035 dev_printk(KERN_ERR, &pdev->dev,
3036 "no valid port_info specified\n");
3040 if (!devres_open_group(dev, NULL, GFP_KERNEL))
3043 rc = pcim_enable_device(pdev);
3047 /* prepare and activate SFF host */
3048 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
3051 host->private_data = host_priv;
3052 host->flags |= hflag;
3054 pci_set_master(pdev);
3055 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
3058 devres_remove_group(&pdev->dev, NULL);
3060 devres_release_group(&pdev->dev, NULL);
3064 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
3066 #endif /* CONFIG_PCI */