2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.3"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
102 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
103 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
105 /* registers for each SATA port */
106 PORT_LST_ADDR = 0x00, /* command list DMA addr */
107 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
108 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
109 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
110 PORT_IRQ_STAT = 0x10, /* interrupt status */
111 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
112 PORT_CMD = 0x18, /* port command */
113 PORT_TFDATA = 0x20, /* taskfile data */
114 PORT_SIG = 0x24, /* device TF signature */
115 PORT_CMD_ISSUE = 0x38, /* command issue */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
122 /* PORT_IRQ_{STAT,MASK} bits */
123 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
124 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
125 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
126 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
127 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
128 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
129 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
130 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
133 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
134 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
135 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
136 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
137 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
138 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
139 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
140 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
147 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
149 PORT_IRQ_HBUS_DATA_ERR,
150 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
151 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
152 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
155 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
156 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
157 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
158 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
159 PORT_CMD_CLO = (1 << 3), /* Command list override */
160 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
161 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
162 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
164 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
165 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
166 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
167 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
173 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
174 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
175 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
176 AHCI_FLAG_NO_HOTPLUG = (1 << 31), /* ignore PxSERR.DIAG.N */
178 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
181 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
184 struct ahci_cmd_hdr {
199 struct ahci_host_priv {
200 u32 cap; /* cap to use */
201 u32 port_map; /* port map to use */
202 u32 saved_cap; /* saved initial cap */
203 u32 saved_port_map; /* saved initial port_map */
206 struct ahci_port_priv {
207 struct ahci_cmd_hdr *cmd_slot;
208 dma_addr_t cmd_slot_dma;
210 dma_addr_t cmd_tbl_dma;
212 dma_addr_t rx_fis_dma;
213 /* for NCQ spurious interrupt analysis */
214 unsigned int ncq_saw_d2h:1;
215 unsigned int ncq_saw_dmas:1;
216 unsigned int ncq_saw_sdb:1;
217 u32 intr_mask; /* interrupts to enable */
220 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
221 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
222 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
223 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
224 static void ahci_irq_clear(struct ata_port *ap);
225 static int ahci_port_start(struct ata_port *ap);
226 static void ahci_port_stop(struct ata_port *ap);
227 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
228 static void ahci_qc_prep(struct ata_queued_cmd *qc);
229 static u8 ahci_check_status(struct ata_port *ap);
230 static void ahci_freeze(struct ata_port *ap);
231 static void ahci_thaw(struct ata_port *ap);
232 static void ahci_error_handler(struct ata_port *ap);
233 static void ahci_vt8251_error_handler(struct ata_port *ap);
234 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
235 static int ahci_port_resume(struct ata_port *ap);
236 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
237 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
240 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
241 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
242 static int ahci_pci_device_resume(struct pci_dev *pdev);
245 static struct scsi_host_template ahci_sht = {
246 .module = THIS_MODULE,
248 .ioctl = ata_scsi_ioctl,
249 .queuecommand = ata_scsi_queuecmd,
250 .change_queue_depth = ata_scsi_change_queue_depth,
251 .can_queue = AHCI_MAX_CMDS - 1,
252 .this_id = ATA_SHT_THIS_ID,
253 .sg_tablesize = AHCI_MAX_SG,
254 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
255 .emulated = ATA_SHT_EMULATED,
256 .use_clustering = AHCI_USE_CLUSTERING,
257 .proc_name = DRV_NAME,
258 .dma_boundary = AHCI_DMA_BOUNDARY,
259 .slave_configure = ata_scsi_slave_config,
260 .slave_destroy = ata_scsi_slave_destroy,
261 .bios_param = ata_std_bios_param,
264 static const struct ata_port_operations ahci_ops = {
265 .check_status = ahci_check_status,
266 .check_altstatus = ahci_check_status,
267 .dev_select = ata_noop_dev_select,
269 .tf_read = ahci_tf_read,
271 .qc_prep = ahci_qc_prep,
272 .qc_issue = ahci_qc_issue,
274 .irq_clear = ahci_irq_clear,
276 .scr_read = ahci_scr_read,
277 .scr_write = ahci_scr_write,
279 .freeze = ahci_freeze,
282 .error_handler = ahci_error_handler,
283 .post_internal_cmd = ahci_post_internal_cmd,
286 .port_suspend = ahci_port_suspend,
287 .port_resume = ahci_port_resume,
290 .port_start = ahci_port_start,
291 .port_stop = ahci_port_stop,
294 static const struct ata_port_operations ahci_vt8251_ops = {
295 .check_status = ahci_check_status,
296 .check_altstatus = ahci_check_status,
297 .dev_select = ata_noop_dev_select,
299 .tf_read = ahci_tf_read,
301 .qc_prep = ahci_qc_prep,
302 .qc_issue = ahci_qc_issue,
304 .irq_clear = ahci_irq_clear,
306 .scr_read = ahci_scr_read,
307 .scr_write = ahci_scr_write,
309 .freeze = ahci_freeze,
312 .error_handler = ahci_vt8251_error_handler,
313 .post_internal_cmd = ahci_post_internal_cmd,
316 .port_suspend = ahci_port_suspend,
317 .port_resume = ahci_port_resume,
320 .port_start = ahci_port_start,
321 .port_stop = ahci_port_stop,
324 static const struct ata_port_info ahci_port_info[] = {
327 .flags = AHCI_FLAG_COMMON,
328 .link_flags = AHCI_LFLAG_COMMON,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = ATA_UDMA6,
331 .port_ops = &ahci_ops,
333 /* board_ahci_vt8251 */
335 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_NO_NCQ,
336 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
337 .pio_mask = 0x1f, /* pio0-4 */
338 .udma_mask = ATA_UDMA6,
339 .port_ops = &ahci_vt8251_ops,
341 /* board_ahci_ign_iferr */
343 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
344 .link_flags = AHCI_LFLAG_COMMON,
345 .pio_mask = 0x1f, /* pio0-4 */
346 .udma_mask = ATA_UDMA6,
347 .port_ops = &ahci_ops,
349 /* board_ahci_sb600 */
351 .flags = AHCI_FLAG_COMMON |
352 AHCI_FLAG_IGN_SERR_INTERNAL |
353 AHCI_FLAG_32BIT_ONLY,
354 .link_flags = AHCI_LFLAG_COMMON,
355 .pio_mask = 0x1f, /* pio0-4 */
356 .udma_mask = ATA_UDMA6,
357 .port_ops = &ahci_ops,
362 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
363 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
364 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
366 .link_flags = AHCI_LFLAG_COMMON,
367 .pio_mask = 0x1f, /* pio0-4 */
368 .udma_mask = ATA_UDMA6,
369 .port_ops = &ahci_ops,
373 static const struct pci_device_id ahci_pci_tbl[] = {
375 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
376 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
377 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
378 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
379 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
380 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
381 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
382 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
383 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
384 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
385 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
386 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
387 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
388 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
389 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
390 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
391 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
392 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
393 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
395 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
396 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
397 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
398 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
399 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
400 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
401 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
403 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
404 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
405 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
408 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
409 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
410 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
411 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
412 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
413 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
414 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
417 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
418 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
421 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
442 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
443 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
444 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
445 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
446 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
447 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
454 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
455 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
456 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
457 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
458 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
468 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
469 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
472 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
474 /* Generic, PCI class code for AHCI */
475 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
476 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
478 { } /* terminate list */
482 static struct pci_driver ahci_pci_driver = {
484 .id_table = ahci_pci_tbl,
485 .probe = ahci_init_one,
486 .remove = ata_pci_remove_one,
488 .suspend = ahci_pci_device_suspend,
489 .resume = ahci_pci_device_resume,
494 static inline int ahci_nr_ports(u32 cap)
496 return (cap & 0x1f) + 1;
499 static inline void __iomem *__ahci_port_base(struct ata_host *host,
500 unsigned int port_no)
502 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
504 return mmio + 0x100 + (port_no * 0x80);
507 static inline void __iomem *ahci_port_base(struct ata_port *ap)
509 return __ahci_port_base(ap->host, ap->port_no);
513 * ahci_save_initial_config - Save and fixup initial config values
514 * @pdev: target PCI device
515 * @pi: associated ATA port info
516 * @hpriv: host private area to store config values
518 * Some registers containing configuration info might be setup by
519 * BIOS and might be cleared on reset. This function saves the
520 * initial values of those registers into @hpriv such that they
521 * can be restored after controller reset.
523 * If inconsistent, config values are fixed up by this function.
528 static void ahci_save_initial_config(struct pci_dev *pdev,
529 const struct ata_port_info *pi,
530 struct ahci_host_priv *hpriv)
532 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
536 /* Values prefixed with saved_ are written back to host after
537 * reset. Values without are used for driver operation.
539 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
540 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
542 /* some chips have errata preventing 64bit use */
543 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
544 dev_printk(KERN_INFO, &pdev->dev,
545 "controller can't do 64bit DMA, forcing 32bit\n");
549 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
550 dev_printk(KERN_INFO, &pdev->dev,
551 "controller can't do NCQ, turning off CAP_NCQ\n");
552 cap &= ~HOST_CAP_NCQ;
556 * Temporary Marvell 6145 hack: PATA port presence
557 * is asserted through the standard AHCI port
558 * presence register, as bit 4 (counting from 0)
560 if (pi->flags & AHCI_FLAG_MV_PATA) {
561 dev_printk(KERN_ERR, &pdev->dev,
562 "MV_AHCI HACK: port_map %x -> %x\n",
564 hpriv->port_map & 0xf);
569 /* cross check port_map and cap.n_ports */
571 u32 tmp_port_map = port_map;
572 int n_ports = ahci_nr_ports(cap);
574 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
575 if (tmp_port_map & (1 << i)) {
577 tmp_port_map &= ~(1 << i);
581 /* If n_ports and port_map are inconsistent, whine and
582 * clear port_map and let it be generated from n_ports.
584 if (n_ports || tmp_port_map) {
585 dev_printk(KERN_WARNING, &pdev->dev,
586 "nr_ports (%u) and implemented port map "
587 "(0x%x) don't match, using nr_ports\n",
588 ahci_nr_ports(cap), port_map);
593 /* fabricate port_map from cap.nr_ports */
595 port_map = (1 << ahci_nr_ports(cap)) - 1;
596 dev_printk(KERN_WARNING, &pdev->dev,
597 "forcing PORTS_IMPL to 0x%x\n", port_map);
599 /* write the fixed up value to the PI register */
600 hpriv->saved_port_map = port_map;
603 /* record values to use during operation */
605 hpriv->port_map = port_map;
609 * ahci_restore_initial_config - Restore initial config
610 * @host: target ATA host
612 * Restore initial config stored by ahci_save_initial_config().
617 static void ahci_restore_initial_config(struct ata_host *host)
619 struct ahci_host_priv *hpriv = host->private_data;
620 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
622 writel(hpriv->saved_cap, mmio + HOST_CAP);
623 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
624 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
627 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
629 static const int offset[] = {
630 [SCR_STATUS] = PORT_SCR_STAT,
631 [SCR_CONTROL] = PORT_SCR_CTL,
632 [SCR_ERROR] = PORT_SCR_ERR,
633 [SCR_ACTIVE] = PORT_SCR_ACT,
634 [SCR_NOTIFICATION] = PORT_SCR_NTF,
636 struct ahci_host_priv *hpriv = ap->host->private_data;
638 if (sc_reg < ARRAY_SIZE(offset) &&
639 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
640 return offset[sc_reg];
644 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
646 void __iomem *port_mmio = ahci_port_base(ap);
647 int offset = ahci_scr_offset(ap, sc_reg);
650 *val = readl(port_mmio + offset);
656 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
658 void __iomem *port_mmio = ahci_port_base(ap);
659 int offset = ahci_scr_offset(ap, sc_reg);
662 writel(val, port_mmio + offset);
668 static void ahci_start_engine(struct ata_port *ap)
670 void __iomem *port_mmio = ahci_port_base(ap);
674 tmp = readl(port_mmio + PORT_CMD);
675 tmp |= PORT_CMD_START;
676 writel(tmp, port_mmio + PORT_CMD);
677 readl(port_mmio + PORT_CMD); /* flush */
680 static int ahci_stop_engine(struct ata_port *ap)
682 void __iomem *port_mmio = ahci_port_base(ap);
685 tmp = readl(port_mmio + PORT_CMD);
687 /* check if the HBA is idle */
688 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
691 /* setting HBA to idle */
692 tmp &= ~PORT_CMD_START;
693 writel(tmp, port_mmio + PORT_CMD);
695 /* wait for engine to stop. This could be as long as 500 msec */
696 tmp = ata_wait_register(port_mmio + PORT_CMD,
697 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
698 if (tmp & PORT_CMD_LIST_ON)
704 static void ahci_start_fis_rx(struct ata_port *ap)
706 void __iomem *port_mmio = ahci_port_base(ap);
707 struct ahci_host_priv *hpriv = ap->host->private_data;
708 struct ahci_port_priv *pp = ap->private_data;
711 /* set FIS registers */
712 if (hpriv->cap & HOST_CAP_64)
713 writel((pp->cmd_slot_dma >> 16) >> 16,
714 port_mmio + PORT_LST_ADDR_HI);
715 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
717 if (hpriv->cap & HOST_CAP_64)
718 writel((pp->rx_fis_dma >> 16) >> 16,
719 port_mmio + PORT_FIS_ADDR_HI);
720 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
722 /* enable FIS reception */
723 tmp = readl(port_mmio + PORT_CMD);
724 tmp |= PORT_CMD_FIS_RX;
725 writel(tmp, port_mmio + PORT_CMD);
728 readl(port_mmio + PORT_CMD);
731 static int ahci_stop_fis_rx(struct ata_port *ap)
733 void __iomem *port_mmio = ahci_port_base(ap);
736 /* disable FIS reception */
737 tmp = readl(port_mmio + PORT_CMD);
738 tmp &= ~PORT_CMD_FIS_RX;
739 writel(tmp, port_mmio + PORT_CMD);
741 /* wait for completion, spec says 500ms, give it 1000 */
742 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
743 PORT_CMD_FIS_ON, 10, 1000);
744 if (tmp & PORT_CMD_FIS_ON)
750 static void ahci_power_up(struct ata_port *ap)
752 struct ahci_host_priv *hpriv = ap->host->private_data;
753 void __iomem *port_mmio = ahci_port_base(ap);
756 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
759 if (hpriv->cap & HOST_CAP_SSS) {
760 cmd |= PORT_CMD_SPIN_UP;
761 writel(cmd, port_mmio + PORT_CMD);
765 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
769 static void ahci_power_down(struct ata_port *ap)
771 struct ahci_host_priv *hpriv = ap->host->private_data;
772 void __iomem *port_mmio = ahci_port_base(ap);
775 if (!(hpriv->cap & HOST_CAP_SSS))
778 /* put device into listen mode, first set PxSCTL.DET to 0 */
779 scontrol = readl(port_mmio + PORT_SCR_CTL);
781 writel(scontrol, port_mmio + PORT_SCR_CTL);
783 /* then set PxCMD.SUD to 0 */
784 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
785 cmd &= ~PORT_CMD_SPIN_UP;
786 writel(cmd, port_mmio + PORT_CMD);
790 static void ahci_start_port(struct ata_port *ap)
792 /* enable FIS reception */
793 ahci_start_fis_rx(ap);
796 ahci_start_engine(ap);
799 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
804 rc = ahci_stop_engine(ap);
806 *emsg = "failed to stop engine";
810 /* disable FIS reception */
811 rc = ahci_stop_fis_rx(ap);
813 *emsg = "failed stop FIS RX";
820 static int ahci_reset_controller(struct ata_host *host)
822 struct pci_dev *pdev = to_pci_dev(host->dev);
823 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
826 /* global controller reset */
827 tmp = readl(mmio + HOST_CTL);
828 if ((tmp & HOST_RESET) == 0) {
829 writel(tmp | HOST_RESET, mmio + HOST_CTL);
830 readl(mmio + HOST_CTL); /* flush */
833 /* reset must complete within 1 second, or
834 * the hardware should be considered fried.
838 tmp = readl(mmio + HOST_CTL);
839 if (tmp & HOST_RESET) {
840 dev_printk(KERN_ERR, host->dev,
841 "controller reset failed (0x%x)\n", tmp);
845 /* turn on AHCI mode */
846 writel(HOST_AHCI_EN, mmio + HOST_CTL);
847 (void) readl(mmio + HOST_CTL); /* flush */
849 /* some registers might be cleared on reset. restore initial values */
850 ahci_restore_initial_config(host);
852 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
856 pci_read_config_word(pdev, 0x92, &tmp16);
858 pci_write_config_word(pdev, 0x92, tmp16);
864 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
865 int port_no, void __iomem *mmio,
866 void __iomem *port_mmio)
868 const char *emsg = NULL;
872 /* make sure port is not active */
873 rc = ahci_deinit_port(ap, &emsg);
875 dev_printk(KERN_WARNING, &pdev->dev,
876 "%s (%d)\n", emsg, rc);
879 tmp = readl(port_mmio + PORT_SCR_ERR);
880 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
881 writel(tmp, port_mmio + PORT_SCR_ERR);
884 tmp = readl(port_mmio + PORT_IRQ_STAT);
885 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
887 writel(tmp, port_mmio + PORT_IRQ_STAT);
889 writel(1 << port_no, mmio + HOST_IRQ_STAT);
892 static void ahci_init_controller(struct ata_host *host)
894 struct pci_dev *pdev = to_pci_dev(host->dev);
895 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
897 void __iomem *port_mmio;
900 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
901 port_mmio = __ahci_port_base(host, 4);
903 writel(0, port_mmio + PORT_IRQ_MASK);
906 tmp = readl(port_mmio + PORT_IRQ_STAT);
907 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
909 writel(tmp, port_mmio + PORT_IRQ_STAT);
912 for (i = 0; i < host->n_ports; i++) {
913 struct ata_port *ap = host->ports[i];
915 port_mmio = ahci_port_base(ap);
916 if (ata_port_is_dummy(ap))
919 ahci_port_init(pdev, ap, i, mmio, port_mmio);
922 tmp = readl(mmio + HOST_CTL);
923 VPRINTK("HOST_CTL 0x%x\n", tmp);
924 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
925 tmp = readl(mmio + HOST_CTL);
926 VPRINTK("HOST_CTL 0x%x\n", tmp);
929 static unsigned int ahci_dev_classify(struct ata_port *ap)
931 void __iomem *port_mmio = ahci_port_base(ap);
932 struct ata_taskfile tf;
935 tmp = readl(port_mmio + PORT_SIG);
936 tf.lbah = (tmp >> 24) & 0xff;
937 tf.lbam = (tmp >> 16) & 0xff;
938 tf.lbal = (tmp >> 8) & 0xff;
939 tf.nsect = (tmp) & 0xff;
941 return ata_dev_classify(&tf);
944 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
947 dma_addr_t cmd_tbl_dma;
949 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
951 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
952 pp->cmd_slot[tag].status = 0;
953 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
954 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
957 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
959 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
960 struct ahci_host_priv *hpriv = ap->host->private_data;
964 /* do we need to kick the port? */
965 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
966 if (!busy && !force_restart)
970 rc = ahci_stop_engine(ap);
974 /* need to do CLO? */
980 if (!(hpriv->cap & HOST_CAP_CLO)) {
986 tmp = readl(port_mmio + PORT_CMD);
988 writel(tmp, port_mmio + PORT_CMD);
991 tmp = ata_wait_register(port_mmio + PORT_CMD,
992 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
993 if (tmp & PORT_CMD_CLO)
998 ahci_start_engine(ap);
1002 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1003 struct ata_taskfile *tf, int is_cmd, u16 flags,
1004 unsigned long timeout_msec)
1006 const u32 cmd_fis_len = 5; /* five dwords */
1007 struct ahci_port_priv *pp = ap->private_data;
1008 void __iomem *port_mmio = ahci_port_base(ap);
1009 u8 *fis = pp->cmd_tbl;
1012 /* prep the command */
1013 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1014 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1017 writel(1, port_mmio + PORT_CMD_ISSUE);
1020 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1023 ahci_kick_engine(ap, 1);
1027 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1032 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1033 int pmp, unsigned long deadline)
1035 struct ata_port *ap = link->ap;
1036 const char *reason = NULL;
1037 unsigned long now, msecs;
1038 struct ata_taskfile tf;
1043 if (ata_link_offline(link)) {
1044 DPRINTK("PHY reports no device\n");
1045 *class = ATA_DEV_NONE;
1049 /* prepare for SRST (AHCI-1.1 10.4.1) */
1050 rc = ahci_kick_engine(ap, 1);
1052 ata_link_printk(link, KERN_WARNING,
1053 "failed to reset engine (errno=%d)", rc);
1055 ata_tf_init(link->device, &tf);
1057 /* issue the first D2H Register FIS */
1060 if (time_after(now, deadline))
1061 msecs = jiffies_to_msecs(deadline - now);
1064 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1065 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1067 reason = "1st FIS failed";
1071 /* spec says at least 5us, but be generous and sleep for 1ms */
1074 /* issue the second D2H Register FIS */
1075 tf.ctl &= ~ATA_SRST;
1076 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1078 /* spec mandates ">= 2ms" before checking status.
1079 * We wait 150ms, because that was the magic delay used for
1080 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1081 * between when the ATA command register is written, and then
1082 * status is checked. Because waiting for "a while" before
1083 * checking status is fine, post SRST, we perform this magic
1084 * delay here as well.
1088 rc = ata_wait_ready(ap, deadline);
1089 /* link occupied, -ENODEV too is an error */
1091 reason = "device not ready";
1094 *class = ahci_dev_classify(ap);
1096 DPRINTK("EXIT, class=%u\n", *class);
1100 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1104 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1105 unsigned long deadline)
1107 return ahci_do_softreset(link, class, 0, deadline);
1110 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1111 unsigned long deadline)
1113 struct ata_port *ap = link->ap;
1114 struct ahci_port_priv *pp = ap->private_data;
1115 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1116 struct ata_taskfile tf;
1121 ahci_stop_engine(ap);
1123 /* clear D2H reception area to properly wait for D2H FIS */
1124 ata_tf_init(link->device, &tf);
1126 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1128 rc = sata_std_hardreset(link, class, deadline);
1130 ahci_start_engine(ap);
1132 if (rc == 0 && ata_link_online(link))
1133 *class = ahci_dev_classify(ap);
1134 if (*class == ATA_DEV_UNKNOWN)
1135 *class = ATA_DEV_NONE;
1137 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1141 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1142 unsigned long deadline)
1144 struct ata_port *ap = link->ap;
1150 ahci_stop_engine(ap);
1152 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1155 /* vt8251 needs SError cleared for the port to operate */
1156 ahci_scr_read(ap, SCR_ERROR, &serror);
1157 ahci_scr_write(ap, SCR_ERROR, serror);
1159 ahci_start_engine(ap);
1161 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1163 /* vt8251 doesn't clear BSY on signature FIS reception,
1164 * request follow-up softreset.
1166 return rc ?: -EAGAIN;
1169 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1171 struct ata_port *ap = link->ap;
1172 void __iomem *port_mmio = ahci_port_base(ap);
1175 ata_std_postreset(link, class);
1177 /* Make sure port's ATAPI bit is set appropriately */
1178 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1179 if (*class == ATA_DEV_ATAPI)
1180 new_tmp |= PORT_CMD_ATAPI;
1182 new_tmp &= ~PORT_CMD_ATAPI;
1183 if (new_tmp != tmp) {
1184 writel(new_tmp, port_mmio + PORT_CMD);
1185 readl(port_mmio + PORT_CMD); /* flush */
1189 static u8 ahci_check_status(struct ata_port *ap)
1191 void __iomem *mmio = ap->ioaddr.cmd_addr;
1193 return readl(mmio + PORT_TFDATA) & 0xFF;
1196 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1198 struct ahci_port_priv *pp = ap->private_data;
1199 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1201 ata_tf_from_fis(d2h_fis, tf);
1204 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1206 struct scatterlist *sg;
1207 struct ahci_sg *ahci_sg;
1208 unsigned int n_sg = 0;
1213 * Next, the S/G list.
1215 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1216 ata_for_each_sg(sg, qc) {
1217 dma_addr_t addr = sg_dma_address(sg);
1218 u32 sg_len = sg_dma_len(sg);
1220 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1221 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1222 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1231 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1233 struct ata_port *ap = qc->ap;
1234 struct ahci_port_priv *pp = ap->private_data;
1235 int is_atapi = is_atapi_taskfile(&qc->tf);
1238 const u32 cmd_fis_len = 5; /* five dwords */
1239 unsigned int n_elem;
1242 * Fill in command table information. First, the header,
1243 * a SATA Register - Host to Device command FIS.
1245 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1247 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
1249 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1250 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1254 if (qc->flags & ATA_QCFLAG_DMAMAP)
1255 n_elem = ahci_fill_sg(qc, cmd_tbl);
1258 * Fill in command slot information.
1260 opts = cmd_fis_len | n_elem << 16;
1261 if (qc->tf.flags & ATA_TFLAG_WRITE)
1262 opts |= AHCI_CMD_WRITE;
1264 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1266 ahci_fill_cmd_slot(pp, qc->tag, opts);
1269 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1271 struct ahci_port_priv *pp = ap->private_data;
1272 struct ata_eh_info *ehi = &ap->link.eh_info;
1273 unsigned int err_mask = 0, action = 0;
1274 struct ata_queued_cmd *qc;
1277 ata_ehi_clear_desc(ehi);
1279 /* AHCI needs SError cleared; otherwise, it might lock up */
1280 ahci_scr_read(ap, SCR_ERROR, &serror);
1281 ahci_scr_write(ap, SCR_ERROR, serror);
1283 /* analyze @irq_stat */
1284 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1286 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1287 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1288 irq_stat &= ~PORT_IRQ_IF_ERR;
1290 if (irq_stat & PORT_IRQ_TF_ERR) {
1291 err_mask |= AC_ERR_DEV;
1292 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1293 serror &= ~SERR_INTERNAL;
1296 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1297 err_mask |= AC_ERR_HOST_BUS;
1298 action |= ATA_EH_SOFTRESET;
1301 if (irq_stat & PORT_IRQ_IF_ERR) {
1302 err_mask |= AC_ERR_ATA_BUS;
1303 action |= ATA_EH_SOFTRESET;
1304 ata_ehi_push_desc(ehi, "interface fatal error");
1307 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1308 ata_ehi_hotplugged(ehi);
1309 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
1310 "connection status changed" : "PHY RDY changed");
1313 if (irq_stat & PORT_IRQ_UNK_FIS) {
1314 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1316 err_mask |= AC_ERR_HSM;
1317 action |= ATA_EH_SOFTRESET;
1318 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
1319 unk[0], unk[1], unk[2], unk[3]);
1322 /* okay, let's hand over to EH */
1323 ehi->serror |= serror;
1324 ehi->action |= action;
1326 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1328 qc->err_mask |= err_mask;
1330 ehi->err_mask |= err_mask;
1332 if (irq_stat & PORT_IRQ_FREEZE)
1333 ata_port_freeze(ap);
1338 static void ahci_port_intr(struct ata_port *ap)
1340 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1341 struct ata_eh_info *ehi = &ap->link.eh_info;
1342 struct ahci_port_priv *pp = ap->private_data;
1343 u32 status, qc_active;
1344 int rc, known_irq = 0;
1346 status = readl(port_mmio + PORT_IRQ_STAT);
1347 writel(status, port_mmio + PORT_IRQ_STAT);
1349 if (unlikely(status & PORT_IRQ_ERROR)) {
1350 ahci_error_intr(ap, status);
1354 if (status & PORT_IRQ_SDB_FIS) {
1356 * if this is an ATAPI device with AN turned on,
1357 * then we should interrogate the device to
1358 * determine the cause of the interrupt
1360 * for AN - this we should check the SDB FIS
1361 * and find the I and N bits set
1363 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1364 u32 f0 = le32_to_cpu(f[0]);
1366 /* check the 'N' bit in word 0 of the FIS */
1367 if (f0 & (1 << 15)) {
1368 int port_addr = ((f0 & 0x00000f00) >> 8);
1369 struct ata_device *adev;
1370 if (port_addr < ATA_MAX_DEVICES) {
1371 adev = &ap->link.device[port_addr];
1372 if (adev->flags & ATA_DFLAG_AN)
1373 ata_scsi_media_change_notify(adev);
1378 if (ap->link.sactive)
1379 qc_active = readl(port_mmio + PORT_SCR_ACT);
1381 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1383 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1387 ehi->err_mask |= AC_ERR_HSM;
1388 ehi->action |= ATA_EH_SOFTRESET;
1389 ata_port_freeze(ap);
1393 /* hmmm... a spurious interupt */
1395 /* if !NCQ, ignore. No modern ATA device has broken HSM
1396 * implementation for non-NCQ commands.
1398 if (!ap->link.sactive)
1401 if (status & PORT_IRQ_D2H_REG_FIS) {
1402 if (!pp->ncq_saw_d2h)
1403 ata_port_printk(ap, KERN_INFO,
1404 "D2H reg with I during NCQ, "
1405 "this message won't be printed again\n");
1406 pp->ncq_saw_d2h = 1;
1410 if (status & PORT_IRQ_DMAS_FIS) {
1411 if (!pp->ncq_saw_dmas)
1412 ata_port_printk(ap, KERN_INFO,
1413 "DMAS FIS during NCQ, "
1414 "this message won't be printed again\n");
1415 pp->ncq_saw_dmas = 1;
1419 if (status & PORT_IRQ_SDB_FIS) {
1420 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1422 if (le32_to_cpu(f[1])) {
1423 /* SDB FIS containing spurious completions
1424 * might be dangerous, whine and fail commands
1425 * with HSM violation. EH will turn off NCQ
1426 * after several such failures.
1428 ata_ehi_push_desc(ehi,
1429 "spurious completions during NCQ "
1430 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1431 readl(port_mmio + PORT_CMD_ISSUE),
1432 readl(port_mmio + PORT_SCR_ACT),
1433 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1434 ehi->err_mask |= AC_ERR_HSM;
1435 ehi->action |= ATA_EH_SOFTRESET;
1436 ata_port_freeze(ap);
1438 if (!pp->ncq_saw_sdb)
1439 ata_port_printk(ap, KERN_INFO,
1440 "spurious SDB FIS %08x:%08x during NCQ, "
1441 "this message won't be printed again\n",
1442 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1443 pp->ncq_saw_sdb = 1;
1449 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1450 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1451 status, ap->link.active_tag, ap->link.sactive);
1454 static void ahci_irq_clear(struct ata_port *ap)
1459 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1461 struct ata_host *host = dev_instance;
1462 struct ahci_host_priv *hpriv;
1463 unsigned int i, handled = 0;
1465 u32 irq_stat, irq_ack = 0;
1469 hpriv = host->private_data;
1470 mmio = host->iomap[AHCI_PCI_BAR];
1472 /* sigh. 0xffffffff is a valid return from h/w */
1473 irq_stat = readl(mmio + HOST_IRQ_STAT);
1474 irq_stat &= hpriv->port_map;
1478 spin_lock(&host->lock);
1480 for (i = 0; i < host->n_ports; i++) {
1481 struct ata_port *ap;
1483 if (!(irq_stat & (1 << i)))
1486 ap = host->ports[i];
1489 VPRINTK("port %u\n", i);
1491 VPRINTK("port %u (no irq)\n", i);
1492 if (ata_ratelimit())
1493 dev_printk(KERN_WARNING, host->dev,
1494 "interrupt on disabled port %u\n", i);
1497 irq_ack |= (1 << i);
1501 writel(irq_ack, mmio + HOST_IRQ_STAT);
1505 spin_unlock(&host->lock);
1509 return IRQ_RETVAL(handled);
1512 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1514 struct ata_port *ap = qc->ap;
1515 void __iomem *port_mmio = ahci_port_base(ap);
1517 if (qc->tf.protocol == ATA_PROT_NCQ)
1518 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1519 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1520 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1525 static void ahci_freeze(struct ata_port *ap)
1527 void __iomem *port_mmio = ahci_port_base(ap);
1530 writel(0, port_mmio + PORT_IRQ_MASK);
1533 static void ahci_thaw(struct ata_port *ap)
1535 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1536 void __iomem *port_mmio = ahci_port_base(ap);
1538 struct ahci_port_priv *pp = ap->private_data;
1541 tmp = readl(port_mmio + PORT_IRQ_STAT);
1542 writel(tmp, port_mmio + PORT_IRQ_STAT);
1543 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1545 /* turn IRQ back on */
1546 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1549 static void ahci_error_handler(struct ata_port *ap)
1551 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1552 /* restart engine */
1553 ahci_stop_engine(ap);
1554 ahci_start_engine(ap);
1557 /* perform recovery */
1558 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1562 static void ahci_vt8251_error_handler(struct ata_port *ap)
1564 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1565 /* restart engine */
1566 ahci_stop_engine(ap);
1567 ahci_start_engine(ap);
1570 /* perform recovery */
1571 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1575 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1577 struct ata_port *ap = qc->ap;
1579 /* make DMA engine forget about the failed command */
1580 if (qc->flags & ATA_QCFLAG_FAILED)
1581 ahci_kick_engine(ap, 1);
1584 static int ahci_port_resume(struct ata_port *ap)
1587 ahci_start_port(ap);
1593 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1595 const char *emsg = NULL;
1598 rc = ahci_deinit_port(ap, &emsg);
1600 ahci_power_down(ap);
1602 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1603 ahci_start_port(ap);
1609 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1611 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1612 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1615 if (mesg.event == PM_EVENT_SUSPEND) {
1616 /* AHCI spec rev1.1 section 8.3.3:
1617 * Software must disable interrupts prior to requesting a
1618 * transition of the HBA to D3 state.
1620 ctl = readl(mmio + HOST_CTL);
1621 ctl &= ~HOST_IRQ_EN;
1622 writel(ctl, mmio + HOST_CTL);
1623 readl(mmio + HOST_CTL); /* flush */
1626 return ata_pci_device_suspend(pdev, mesg);
1629 static int ahci_pci_device_resume(struct pci_dev *pdev)
1631 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1634 rc = ata_pci_device_do_resume(pdev);
1638 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1639 rc = ahci_reset_controller(host);
1643 ahci_init_controller(host);
1646 ata_host_resume(host);
1652 static int ahci_port_start(struct ata_port *ap)
1654 struct device *dev = ap->host->dev;
1655 struct ahci_port_priv *pp;
1660 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1664 rc = ata_pad_alloc(ap, dev);
1668 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1672 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1675 * First item in chunk of DMA memory: 32-slot command table,
1676 * 32 bytes each in size
1679 pp->cmd_slot_dma = mem_dma;
1681 mem += AHCI_CMD_SLOT_SZ;
1682 mem_dma += AHCI_CMD_SLOT_SZ;
1685 * Second item: Received-FIS area
1688 pp->rx_fis_dma = mem_dma;
1690 mem += AHCI_RX_FIS_SZ;
1691 mem_dma += AHCI_RX_FIS_SZ;
1694 * Third item: data area for storing a single command
1695 * and its scatter-gather table
1698 pp->cmd_tbl_dma = mem_dma;
1701 * Save off initial list of interrupts to be enabled.
1702 * This could be changed later
1704 pp->intr_mask = DEF_PORT_IRQ;
1706 ap->private_data = pp;
1708 /* engage engines, captain */
1709 return ahci_port_resume(ap);
1712 static void ahci_port_stop(struct ata_port *ap)
1714 const char *emsg = NULL;
1717 /* de-initialize port */
1718 rc = ahci_deinit_port(ap, &emsg);
1720 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1723 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1728 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1729 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1731 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1733 dev_printk(KERN_ERR, &pdev->dev,
1734 "64-bit DMA enable failed\n");
1739 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1741 dev_printk(KERN_ERR, &pdev->dev,
1742 "32-bit DMA enable failed\n");
1745 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1747 dev_printk(KERN_ERR, &pdev->dev,
1748 "32-bit consistent DMA enable failed\n");
1755 static void ahci_print_info(struct ata_host *host)
1757 struct ahci_host_priv *hpriv = host->private_data;
1758 struct pci_dev *pdev = to_pci_dev(host->dev);
1759 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1760 u32 vers, cap, impl, speed;
1761 const char *speed_s;
1765 vers = readl(mmio + HOST_VERSION);
1767 impl = hpriv->port_map;
1769 speed = (cap >> 20) & 0xf;
1772 else if (speed == 2)
1777 pci_read_config_word(pdev, 0x0a, &cc);
1778 if (cc == PCI_CLASS_STORAGE_IDE)
1780 else if (cc == PCI_CLASS_STORAGE_SATA)
1782 else if (cc == PCI_CLASS_STORAGE_RAID)
1787 dev_printk(KERN_INFO, &pdev->dev,
1788 "AHCI %02x%02x.%02x%02x "
1789 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1792 (vers >> 24) & 0xff,
1793 (vers >> 16) & 0xff,
1797 ((cap >> 8) & 0x1f) + 1,
1803 dev_printk(KERN_INFO, &pdev->dev,
1809 cap & (1 << 31) ? "64bit " : "",
1810 cap & (1 << 30) ? "ncq " : "",
1811 cap & (1 << 29) ? "sntf " : "",
1812 cap & (1 << 28) ? "ilck " : "",
1813 cap & (1 << 27) ? "stag " : "",
1814 cap & (1 << 26) ? "pm " : "",
1815 cap & (1 << 25) ? "led " : "",
1817 cap & (1 << 24) ? "clo " : "",
1818 cap & (1 << 19) ? "nz " : "",
1819 cap & (1 << 18) ? "only " : "",
1820 cap & (1 << 17) ? "pmp " : "",
1821 cap & (1 << 15) ? "pio " : "",
1822 cap & (1 << 14) ? "slum " : "",
1823 cap & (1 << 13) ? "part " : ""
1827 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1829 static int printed_version;
1830 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1831 const struct ata_port_info *ppi[] = { &pi, NULL };
1832 struct device *dev = &pdev->dev;
1833 struct ahci_host_priv *hpriv;
1834 struct ata_host *host;
1839 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1841 if (!printed_version++)
1842 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1844 /* acquire resources */
1845 rc = pcim_enable_device(pdev);
1849 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1851 pcim_pin_device(pdev);
1855 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
1858 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1862 /* save initial config */
1863 ahci_save_initial_config(pdev, &pi, hpriv);
1866 if (hpriv->cap & HOST_CAP_NCQ)
1867 pi.flags |= ATA_FLAG_NCQ;
1869 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1872 host->iomap = pcim_iomap_table(pdev);
1873 host->private_data = hpriv;
1875 for (i = 0; i < host->n_ports; i++) {
1876 struct ata_port *ap = host->ports[i];
1877 void __iomem *port_mmio = ahci_port_base(ap);
1879 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1880 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1881 0x100 + ap->port_no * 0x80, "port");
1883 /* standard SATA port setup */
1884 if (hpriv->port_map & (1 << i))
1885 ap->ioaddr.cmd_addr = port_mmio;
1887 /* disabled/not-implemented port */
1889 ap->ops = &ata_dummy_port_ops;
1892 /* initialize adapter */
1893 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1897 rc = ahci_reset_controller(host);
1901 ahci_init_controller(host);
1902 ahci_print_info(host);
1904 pci_set_master(pdev);
1905 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1909 static int __init ahci_init(void)
1911 return pci_register_driver(&ahci_pci_driver);
1914 static void __exit ahci_exit(void)
1916 pci_unregister_driver(&ahci_pci_driver);
1920 MODULE_AUTHOR("Jeff Garzik");
1921 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1922 MODULE_LICENSE("GPL");
1923 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1924 MODULE_VERSION(DRV_VERSION);
1926 module_init(ahci_init);
1927 module_exit(ahci_exit);