2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIP report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 #include <linux/config.h>
38 #include <linux/init.h>
41 #include <linux/kernel_stat.h>
42 #include <linux/smp_lock.h>
43 #include <linux/irq.h>
44 #include <linux/bootmem.h>
45 #include <linux/thread_info.h>
46 #include <linux/module.h>
48 #include <linux/delay.h>
49 #include <linux/mc146818rtc.h>
51 #include <asm/pgalloc.h>
53 #include <asm/kdebug.h>
54 #include <asm/tlbflush.h>
55 #include <asm/proto.h>
57 /* Number of siblings per CPU package */
58 int smp_num_siblings = 1;
59 /* Package ID of each logical CPU */
60 u8 phys_proc_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
61 /* Core ID of each logical CPU */
62 u8 cpu_core_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
63 EXPORT_SYMBOL(phys_proc_id);
64 EXPORT_SYMBOL(cpu_core_id);
66 /* Bitmask of currently online CPUs */
67 cpumask_t cpu_online_map;
69 cpumask_t cpu_callin_map;
70 cpumask_t cpu_callout_map;
71 static cpumask_t smp_commenced_mask;
73 /* Per CPU bogomips and other parameters */
74 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
76 cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
77 cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
80 * Trampoline 80x86 program as an array.
83 extern unsigned char trampoline_data [];
84 extern unsigned char trampoline_end [];
87 * Currently trivial. Write the real->protected mode
88 * bootstrap into the page concerned. The caller
89 * has made sure it's suitably aligned.
92 static unsigned long __init setup_trampoline(void)
94 void *tramp = __va(SMP_TRAMPOLINE_BASE);
95 memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
96 return virt_to_phys(tramp);
100 * The bootstrap kernel entry code has set these up. Save them for
104 static void __init smp_store_cpu_info(int id)
106 struct cpuinfo_x86 *c = cpu_data + id;
113 * TSC synchronization.
115 * We first check whether all CPUs have their TSC's synchronized,
116 * then we print a warning if not, and always resync.
119 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
120 static atomic_t tsc_count_start = ATOMIC_INIT(0);
121 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
122 static unsigned long long tsc_values[NR_CPUS];
126 extern unsigned int fast_gettimeoffset_quotient;
128 static void __init synchronize_tsc_bp (void)
131 unsigned long long t0;
132 unsigned long long sum, avg;
137 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ",num_booting_cpus());
141 atomic_set(&tsc_start_flag, 1);
145 * We loop a few times to get a primed instruction cache,
146 * then the last pass is more or less synchronized and
147 * the BP and APs set their cycle counters to zero all at
148 * once. This reduces the chance of having random offsets
149 * between the processors, and guarantees that the maximum
150 * delay between the cycle counters is never bigger than
151 * the latency of information-passing (cachelines) between
154 for (i = 0; i < NR_LOOPS; i++) {
156 * all APs synchronize but they loop on '== num_cpus'
158 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) mb();
159 atomic_set(&tsc_count_stop, 0);
162 * this lets the APs save their current TSC:
164 atomic_inc(&tsc_count_start);
167 rdtscll(tsc_values[smp_processor_id()]);
169 * We clear the TSC in the last loop:
175 * Wait for all APs to leave the synchronization point:
177 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) mb();
178 atomic_set(&tsc_count_start, 0);
180 atomic_inc(&tsc_count_stop);
184 for (i = 0; i < NR_CPUS; i++) {
185 if (cpu_isset(i, cpu_callout_map)) {
190 avg = sum / num_booting_cpus();
193 for (i = 0; i < NR_CPUS; i++) {
194 if (!cpu_isset(i, cpu_callout_map))
197 delta = tsc_values[i] - avg;
201 * We report bigger than 2 microseconds clock differences.
203 if (delta > 2*one_usec) {
209 realdelta = delta / one_usec;
210 if (tsc_values[i] < avg)
211 realdelta = -realdelta;
213 printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n",
223 static void __init synchronize_tsc_ap (void)
228 * Not every cpu is online at the time
229 * this gets called, so we first wait for the BP to
230 * finish SMP initialization:
232 while (!atomic_read(&tsc_start_flag)) mb();
234 for (i = 0; i < NR_LOOPS; i++) {
235 atomic_inc(&tsc_count_start);
236 while (atomic_read(&tsc_count_start) != num_booting_cpus()) mb();
239 rdtscll(tsc_values[smp_processor_id()]);
243 atomic_inc(&tsc_count_stop);
244 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
249 static atomic_t init_deasserted;
251 static void __init smp_callin(void)
254 unsigned long timeout;
257 * If waken up by an INIT in an 82489DX configuration
258 * we may get here before an INIT-deassert IPI reaches
259 * our local APIC. We have to wait for the IPI or we'll
260 * lock up on an APIC access.
262 while (!atomic_read(&init_deasserted));
265 * (This works even if the APIC is not enabled.)
267 phys_id = GET_APIC_ID(apic_read(APIC_ID));
268 cpuid = smp_processor_id();
269 if (cpu_isset(cpuid, cpu_callin_map)) {
270 panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
273 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
276 * STARTUP IPIs are fragile beasts as they might sometimes
277 * trigger some glue motherboard logic. Complete APIC bus
278 * silence for 1 second, this overestimates the time the
279 * boot CPU is spending to send the up to 2 STARTUP IPIs
280 * by a factor of two. This should be enough.
284 * Waiting 2s total for startup (udelay is not yet working)
286 timeout = jiffies + 2*HZ;
287 while (time_before(jiffies, timeout)) {
289 * Has the boot CPU finished it's STARTUP sequence?
291 if (cpu_isset(cpuid, cpu_callout_map))
296 if (!time_before(jiffies, timeout)) {
297 panic("smp_callin: CPU%d started up but did not get a callout!\n",
302 * the boot CPU has finished the init stage and is spinning
303 * on callin_map until we finish. We are free to set up this
304 * CPU, first the APIC. (this is probably redundant on most
308 Dprintk("CALLIN, before setup_local_APIC().\n");
315 Dprintk("Stack at about %p\n",&cpuid);
317 disable_APIC_timer();
320 * Save our processor parameters
322 smp_store_cpu_info(cpuid);
325 * Allow the master to continue.
327 cpu_set(cpuid, cpu_callin_map);
330 * Synchronize the TSC with the BP
333 synchronize_tsc_ap();
339 * Activate a secondary processor.
341 void __init start_secondary(void)
344 * Dont put anything before smp_callin(), SMP
345 * booting is too fragile that we want to limit the
346 * things done here to the most necessary things.
351 /* otherwise gcc will move up the smp_processor_id before the cpu_init */
354 Dprintk("cpu %d: waiting for commence\n", smp_processor_id());
355 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
358 Dprintk("cpu %d: setting up apic clock\n", smp_processor_id());
359 setup_secondary_APIC_clock();
361 Dprintk("cpu %d: enabling apic timer\n", smp_processor_id());
363 if (nmi_watchdog == NMI_IO_APIC) {
364 disable_8259A_irq(0);
365 enable_NMI_through_LVT0(NULL);
373 * low-memory mappings have been cleared, flush them from
374 * the local TLBs too.
378 Dprintk("cpu %d eSetting cpu_online_map\n", smp_processor_id());
379 cpu_set(smp_processor_id(), cpu_online_map);
385 extern volatile unsigned long init_rsp;
386 extern void (*initial_code)(void);
389 static inline void inquire_remote_apic(int apicid)
391 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
392 char *names[] = { "ID", "VERSION", "SPIV" };
395 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
397 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
398 printk("... APIC #%d %s: ", apicid, names[i]);
403 apic_wait_icr_idle();
405 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
406 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
411 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
412 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
415 case APIC_ICR_RR_VALID:
416 status = apic_read(APIC_RRR);
417 printk("%08x\n", status);
426 static int __init wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
428 unsigned long send_status = 0, accept_status = 0;
429 int maxlvt, timeout, num_starts, j;
431 Dprintk("Asserting INIT.\n");
434 * Turn INIT on target chip
436 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
441 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
444 Dprintk("Waiting for send to finish...\n");
449 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
450 } while (send_status && (timeout++ < 1000));
454 Dprintk("Deasserting INIT.\n");
457 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
460 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
462 Dprintk("Waiting for send to finish...\n");
467 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
468 } while (send_status && (timeout++ < 1000));
470 atomic_set(&init_deasserted, 1);
473 * Should we send STARTUP IPIs ?
475 * Determine this based on the APIC version.
476 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
478 if (APIC_INTEGRATED(apic_version[phys_apicid]))
484 * Run STARTUP IPI loop.
486 Dprintk("#startup loops: %d.\n", num_starts);
488 maxlvt = get_maxlvt();
490 for (j = 1; j <= num_starts; j++) {
491 Dprintk("Sending STARTUP #%d.\n",j);
492 apic_read_around(APIC_SPIV);
493 apic_write(APIC_ESR, 0);
495 Dprintk("After apic_write.\n");
502 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
504 /* Boot on the stack */
505 /* Kick the second */
506 apic_write_around(APIC_ICR, APIC_DM_STARTUP
507 | (start_rip >> 12));
510 * Give the other CPU some time to accept the IPI.
514 Dprintk("Startup point 1.\n");
516 Dprintk("Waiting for send to finish...\n");
521 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
522 } while (send_status && (timeout++ < 1000));
525 * Give the other CPU some time to accept the IPI.
529 * Due to the Pentium erratum 3AP.
532 apic_read_around(APIC_SPIV);
533 apic_write(APIC_ESR, 0);
535 accept_status = (apic_read(APIC_ESR) & 0xEF);
536 if (send_status || accept_status)
539 Dprintk("After Startup.\n");
542 printk(KERN_ERR "APIC never delivered???\n");
544 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
546 return (send_status | accept_status);
549 static void __init do_boot_cpu (int apicid)
551 struct task_struct *idle;
552 unsigned long boot_error;
554 unsigned long start_rip;
558 * We can't use kernel_thread since we must avoid to
559 * reschedule the child.
561 idle = fork_idle(cpu);
563 panic("failed fork for CPU %d", cpu);
564 x86_cpu_to_apicid[cpu] = apicid;
566 cpu_pda[cpu].pcurrent = idle;
568 start_rip = setup_trampoline();
570 init_rsp = idle->thread.rsp;
571 per_cpu(init_tss,cpu).rsp0 = init_rsp;
572 initial_code = start_secondary;
573 clear_ti_thread_flag(idle->thread_info, TIF_FORK);
575 printk(KERN_INFO "Booting processor %d/%d rip %lx rsp %lx\n", cpu, apicid,
576 start_rip, init_rsp);
579 * This grunge runs the startup process for
580 * the targeted processor.
583 atomic_set(&init_deasserted, 0);
585 Dprintk("Setting warm reset code and vector.\n");
587 CMOS_WRITE(0xa, 0xf);
590 *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
592 *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
596 * Be paranoid about clearing APIC errors.
598 if (APIC_INTEGRATED(apic_version[apicid])) {
599 apic_read_around(APIC_SPIV);
600 apic_write(APIC_ESR, 0);
605 * Status is now clean
610 * Starting actual IPI sequence...
612 boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
616 * allow APs to start initializing.
618 Dprintk("Before Callout %d.\n", cpu);
619 cpu_set(cpu, cpu_callout_map);
620 Dprintk("After Callout %d.\n", cpu);
623 * Wait 5s total for a response
625 for (timeout = 0; timeout < 50000; timeout++) {
626 if (cpu_isset(cpu, cpu_callin_map))
627 break; /* It has booted */
631 if (cpu_isset(cpu, cpu_callin_map)) {
632 /* number CPUs logically, starting from 1 (BSP is 0) */
634 print_cpu_info(&cpu_data[cpu]);
635 Dprintk("CPU has booted.\n");
638 if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
640 /* trampoline started but...? */
641 printk("Stuck ??\n");
643 /* trampoline code not run */
644 printk("Not responding.\n");
646 inquire_remote_apic(apicid);
651 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
652 clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
654 x86_cpu_to_apicid[cpu] = BAD_APICID;
655 x86_cpu_to_log_apicid[cpu] = BAD_APICID;
659 static void smp_tune_scheduling (void)
661 int cachesize; /* kB */
662 unsigned long bandwidth = 1000; /* MB/s */
664 * Rough estimation for SMP scheduling, this is the number of
665 * cycles it takes for a fully memory-limited process to flush
666 * the SMP-local cache.
668 * (For a P5 this pretty much means we will choose another idle
669 * CPU almost always at wakeup time (this is due to the small
670 * L1 cache), on PIIs it's around 50-100 usecs, depending on
677 cachesize = boot_cpu_data.x86_cache_size;
678 if (cachesize == -1) {
679 cachesize = 16; /* Pentiums, 2x8kB cache */
686 * Cycle through the processors sending APIC IPIs to boot each.
689 static void __init smp_boot_cpus(unsigned int max_cpus)
691 unsigned apicid, cpu, bit, kicked;
693 nmi_watchdog_default();
696 * Setup boot CPU information
698 smp_store_cpu_info(0); /* Final full version of the data */
699 printk(KERN_INFO "CPU%d: ", 0);
700 print_cpu_info(&cpu_data[0]);
702 current_thread_info()->cpu = 0;
703 smp_tune_scheduling();
705 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
706 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
707 hard_smp_processor_id());
708 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
712 * If we couldn't find an SMP configuration at boot time,
713 * get out of here now!
715 if (!smp_found_config) {
716 printk(KERN_NOTICE "SMP motherboard not detected.\n");
718 cpu_online_map = cpumask_of_cpu(0);
719 cpu_set(0, cpu_sibling_map[0]);
720 cpu_set(0, cpu_core_map[0]);
721 phys_cpu_present_map = physid_mask_of_physid(0);
722 if (APIC_init_uniprocessor())
723 printk(KERN_NOTICE "Local APIC not detected."
724 " Using dummy APIC emulation.\n");
729 * Should not be necessary because the MP table should list the boot
730 * CPU too, but we do it for the sake of robustness anyway.
732 if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
733 printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
735 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
739 * If we couldn't find a local APIC, then get out of here now!
741 if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
742 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
744 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
746 cpu_online_map = cpumask_of_cpu(0);
747 cpu_set(0, cpu_sibling_map[0]);
748 cpu_set(0, cpu_core_map[0]);
749 phys_cpu_present_map = physid_mask_of_physid(0);
757 * If SMP should be disabled, then really disable it!
760 smp_found_config = 0;
761 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
763 cpu_online_map = cpumask_of_cpu(0);
764 cpu_set(0, cpu_sibling_map[0]);
765 cpu_set(0, cpu_core_map[0]);
766 phys_cpu_present_map = physid_mask_of_physid(0);
774 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id)
777 x86_cpu_to_apicid[0] = boot_cpu_id;
780 * Now scan the CPU present map and fire up the other CPUs.
782 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
785 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
786 apicid = cpu_present_to_apicid(bit);
788 * Don't even attempt to start the boot CPU!
790 if (apicid == boot_cpu_id || (apicid == BAD_APICID))
793 if (!physid_isset(apicid, phys_cpu_present_map))
795 if ((max_cpus >= 0) && (max_cpus <= cpucount+1))
803 * Cleanup possible dangling ends...
807 * Install writable page 0 entry to set BIOS data area.
812 * Paranoid: Set warm reset code and vector here back
817 *((volatile int *) phys_to_virt(0x467)) = 0;
821 * Allow the user to impress friends.
824 Dprintk("Before bogomips.\n");
826 printk(KERN_INFO "Only one processor found.\n");
828 unsigned long bogosum = 0;
829 for (cpu = 0; cpu < NR_CPUS; cpu++)
830 if (cpu_isset(cpu, cpu_callout_map))
831 bogosum += cpu_data[cpu].loops_per_jiffy;
832 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
835 (bogosum/(5000/HZ))%100);
836 Dprintk("Before bogocount - setting activated=1.\n");
840 * Construct cpu_sibling_map[], so that we can tell the
841 * sibling CPU efficiently.
843 for (cpu = 0; cpu < NR_CPUS; cpu++) {
844 cpus_clear(cpu_sibling_map[cpu]);
845 cpus_clear(cpu_core_map[cpu]);
848 for (cpu = 0; cpu < NR_CPUS; cpu++) {
849 struct cpuinfo_x86 *c = cpu_data + cpu;
852 if (!cpu_isset(cpu, cpu_callout_map))
855 if (smp_num_siblings > 1) {
856 for (i = 0; i < NR_CPUS; i++) {
857 if (!cpu_isset(i, cpu_callout_map))
859 if (phys_proc_id[cpu] == cpu_core_id[i]) {
861 cpu_set(i, cpu_sibling_map[cpu]);
866 cpu_set(cpu, cpu_sibling_map[cpu]);
869 if (siblings != smp_num_siblings) {
871 "WARNING: %d siblings found for CPU%d, should be %d\n",
872 siblings, cpu, smp_num_siblings);
873 smp_num_siblings = siblings;
875 if (c->x86_num_cores > 1) {
876 for (i = 0; i < NR_CPUS; i++) {
877 if (!cpu_isset(i, cpu_callout_map))
879 if (phys_proc_id[cpu] == phys_proc_id[i]) {
880 cpu_set(i, cpu_core_map[cpu]);
884 cpu_core_map[cpu] = cpu_sibling_map[cpu];
887 Dprintk("Boot done.\n");
890 * Here we can be sure that there is an IO-APIC in the system. Let's
893 if (!skip_ioapic_setup && nr_ioapics)
898 setup_boot_APIC_clock();
901 * Synchronize the TSC with the AP
903 if (cpu_has_tsc && cpucount)
904 synchronize_tsc_bp();
910 /* These are wrappers to interface to the new boot process. Someone
911 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
912 void __init smp_prepare_cpus(unsigned int max_cpus)
914 smp_boot_cpus(max_cpus);
917 void __devinit smp_prepare_boot_cpu(void)
919 cpu_set(smp_processor_id(), cpu_online_map);
920 cpu_set(smp_processor_id(), cpu_callout_map);
923 int __devinit __cpu_up(unsigned int cpu)
925 /* This only works at boot for x86. See "rewrite" above. */
926 if (cpu_isset(cpu, smp_commenced_mask)) {
931 /* In case one didn't come up */
932 if (!cpu_isset(cpu, cpu_callin_map)) {
938 /* Unleash the CPU! */
939 Dprintk("waiting for cpu %d\n", cpu);
941 cpu_set(cpu, smp_commenced_mask);
942 while (!cpu_isset(cpu, cpu_online_map))
947 void __init smp_cpus_done(unsigned int max_cpus)
949 #ifdef CONFIG_X86_IO_APIC