SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33
  34 #include <asm/io.h>
  35 #include <asm/smp.h>
  36 #include <asm/desc.h>
  37 #include <asm/proto.h>
  38 #include <asm/mach_apic.h>
  39 #include <asm/acpi.h>
  40
  41 #define __apicdebuginit  __init
  42
  43 int sis_apic_bug; /* not actually supported, dummy for compile */
  44
  45 static int no_timer_check;
  46
  47 int disable_timer_pin_1 __initdata;
  48
  49 static DEFINE_SPINLOCK(ioapic_lock);
  50
  51 /*
  52  * # of IRQ routing registers
  53  */
  54 int nr_ioapic_registers[MAX_IO_APICS];
  55
  56 /*
  57  * Rough estimation of how many shared IRQs there are, can
  58  * be changed anytime.
  59  */
  60 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  61 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  62
  63 /*
  64  * This is performance-critical, we want to do it O(1)
  65  *
  66  * the indexing order of this array favors 1:1 mappings
  67  * between pins and IRQs.
  68  */
  69
  70 static struct irq_pin_list {
  71         short apic, pin, next;
  72 } irq_2_pin[PIN_MAP_SIZE];
  73
  74 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  75 #ifdef CONFIG_PCI_MSI
  76 #define vector_to_irq(vector)   \
  77         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  78 #else
  79 #define vector_to_irq(vector)   (vector)
  80 #endif
  81
  82 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  83                                                                         \
  84 {                                                                       \
  85         int pin;                                                        \
  86         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  87                                                                         \
  88         for (;;) {                                                      \
  89                 unsigned int reg;                                       \
  90                 pin = entry->pin;                                       \
  91                 if (pin == -1)                                          \
  92                         break;                                          \
  93                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
  94                 reg ACTION;                                             \
  95                 io_apic_modify(entry->apic, reg);                       \
  96                 if (!entry->next)                                       \
  97                         break;                                          \
  98                 entry = irq_2_pin + entry->next;                        \
  99         }                                                               \
 100         FINAL;                                                          \
 101 }
 102
 103 #ifdef CONFIG_SMP
 104 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 105 {
 106         unsigned long flags;
 107         unsigned int dest;
 108         cpumask_t tmp;
 109
 110         cpus_and(tmp, mask, cpu_online_map);
 111         if (cpus_empty(tmp))
 112                 tmp = TARGET_CPUS;
 113
 114         cpus_and(mask, tmp, CPU_MASK_ALL);
 115
 116         dest = cpu_mask_to_apicid(mask);
 117
 118         /*
 119          * Only the high 8 bits are valid.
 120          */
 121         dest = SET_APIC_LOGICAL_ID(dest);
 122
 123         spin_lock_irqsave(&ioapic_lock, flags);
 124         __DO_ACTION(1, = dest, )
 125         set_irq_info(irq, mask);
 126         spin_unlock_irqrestore(&ioapic_lock, flags);
 127 }
 128 #endif
 129
 130 /*
 131  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 132  * shared ISA-space IRQs, so we have to support them. We are super
 133  * fast in the common case, and fast for shared ISA-space IRQs.
 134  */
 135 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 136 {
 137         static int first_free_entry = NR_IRQS;
 138         struct irq_pin_list *entry = irq_2_pin + irq;
 139
 140         while (entry->next)
 141                 entry = irq_2_pin + entry->next;
 142
 143         if (entry->pin != -1) {
 144                 entry->next = first_free_entry;
 145                 entry = irq_2_pin + entry->next;
 146                 if (++first_free_entry >= PIN_MAP_SIZE)
 147                         panic("io_apic.c: whoops");
 148         }
 149         entry->apic = apic;
 150         entry->pin = pin;
 151 }
 152
 153
 154 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 155                                                                         \
 156         static void name##_IO_APIC_irq (unsigned int irq)               \
 157         __DO_ACTION(R, ACTION, FINAL)
 158
 159 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 160                                                 /* mask = 1 */
 161 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 162                                                 /* mask = 0 */
 163
 164 static void mask_IO_APIC_irq (unsigned int irq)
 165 {
 166         unsigned long flags;
 167
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         __mask_IO_APIC_irq(irq);
 170         spin_unlock_irqrestore(&ioapic_lock, flags);
 171 }
 172
 173 static void unmask_IO_APIC_irq (unsigned int irq)
 174 {
 175         unsigned long flags;
 176
 177         spin_lock_irqsave(&ioapic_lock, flags);
 178         __unmask_IO_APIC_irq(irq);
 179         spin_unlock_irqrestore(&ioapic_lock, flags);
 180 }
 181
 182 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 183 {
 184         struct IO_APIC_route_entry entry;
 185         unsigned long flags;
 186
 187         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 188         spin_lock_irqsave(&ioapic_lock, flags);
 189         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 190         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 191         spin_unlock_irqrestore(&ioapic_lock, flags);
 192         if (entry.delivery_mode == dest_SMI)
 193                 return;
 194         /*
 195          * Disable it in the IO-APIC irq-routing table:
 196          */
 197         memset(&entry, 0, sizeof(entry));
 198         entry.mask = 1;
 199         spin_lock_irqsave(&ioapic_lock, flags);
 200         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 201         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 202         spin_unlock_irqrestore(&ioapic_lock, flags);
 203 }
 204
 205 static void clear_IO_APIC (void)
 206 {
 207         int apic, pin;
 208
 209         for (apic = 0; apic < nr_ioapics; apic++)
 210                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 211                         clear_IO_APIC_pin(apic, pin);
 212 }
 213
 214 /*
 215  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 216  * specific CPU-side IRQs.
 217  */
 218
 219 #define MAX_PIRQS 8
 220 static int pirq_entries [MAX_PIRQS];
 221 static int pirqs_enabled;
 222 int skip_ioapic_setup;
 223 int ioapic_force;
 224
 225 /* dummy parsing: see setup.c */
 226
 227 static int __init disable_ioapic_setup(char *str)
 228 {
 229         skip_ioapic_setup = 1;
 230         return 1;
 231 }
 232
 233 static int __init enable_ioapic_setup(char *str)
 234 {
 235         ioapic_force = 1;
 236         skip_ioapic_setup = 0;
 237         return 1;
 238 }
 239
 240 __setup("noapic", disable_ioapic_setup);
 241 __setup("apic", enable_ioapic_setup);
 242
 243 #include <asm/pci-direct.h>
 244 #include <linux/pci_ids.h>
 245 #include <linux/pci.h>
 246
 247 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 248    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 249    Use pci direct infrastructure because this runs before the PCI subsystem.
 250
 251    Can be overwritten with "apic"
 252
 253    And another hack to disable the IOMMU on VIA chipsets.
 254
 255    Kludge-O-Rama. */
 256 void __init check_ioapic(void)
 257 {
 258         int num,slot,func;
 259         if (ioapic_force)
 260                 return;
 261
 262         /* Poor man's PCI discovery */
 263         for (num = 0; num < 32; num++) {
 264                 for (slot = 0; slot < 32; slot++) {
 265                         for (func = 0; func < 8; func++) {
 266                                 u32 class;
 267                                 u32 vendor;
 268                                 u8 type;
 269                                 class = read_pci_config(num,slot,func,
 270                                                         PCI_CLASS_REVISION);
 271                                 if (class == 0xffffffff)
 272                                         break;
 273
 274                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 275                                         continue;
 276
 277                                 vendor = read_pci_config(num, slot, func,
 278                                                          PCI_VENDOR_ID);
 279                                 vendor &= 0xffff;
 280                                 switch (vendor) {
 281                                 case PCI_VENDOR_ID_VIA:
 282 #ifdef CONFIG_GART_IOMMU
 283                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 284                                              force_iommu) &&
 285                                             !iommu_aperture_allowed) {
 286                                                 printk(KERN_INFO
 287     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 288                                                 iommu_aperture_disabled = 1;
 289                                         }
 290 #endif
 291                                         return;
 292                                 case PCI_VENDOR_ID_NVIDIA:
 293 #ifdef CONFIG_ACPI
 294                                         /* All timer overrides on Nvidia
 295                                            seem to be wrong. Skip them. */
 296                                         acpi_skip_timer_override = 1;
 297                                         printk(KERN_INFO
 298              "Nvidia board detected. Ignoring ACPI timer override.\n");
 299 #endif
 300                                         /* RED-PEN skip them on mptables too? */
 301                                         return;
 302                                 }
 303
 304                                 /* No multi-function device? */
 305                                 type = read_pci_config_byte(num,slot,func,
 306                                                             PCI_HEADER_TYPE);
 307                                 if (!(type & 0x80))
 308                                         break;
 309                         }
 310                 }
 311         }
 312 }
 313
 314 static int __init ioapic_pirq_setup(char *str)
 315 {
 316         int i, max;
 317         int ints[MAX_PIRQS+1];
 318
 319         get_options(str, ARRAY_SIZE(ints), ints);
 320
 321         for (i = 0; i < MAX_PIRQS; i++)
 322                 pirq_entries[i] = -1;
 323
 324         pirqs_enabled = 1;
 325         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 326         max = MAX_PIRQS;
 327         if (ints[0] < MAX_PIRQS)
 328                 max = ints[0];
 329
 330         for (i = 0; i < max; i++) {
 331                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 332                 /*
 333                  * PIRQs are mapped upside down, usually.
 334                  */
 335                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 336         }
 337         return 1;
 338 }
 339
 340 __setup("pirq=", ioapic_pirq_setup);
 341
 342 /*
 343  * Find the IRQ entry number of a certain pin.
 344  */
 345 static int find_irq_entry(int apic, int pin, int type)
 346 {
 347         int i;
 348
 349         for (i = 0; i < mp_irq_entries; i++)
 350                 if (mp_irqs[i].mpc_irqtype == type &&
 351                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 352                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 353                     mp_irqs[i].mpc_dstirq == pin)
 354                         return i;
 355
 356         return -1;
 357 }
 358
 359 /*
 360  * Find the pin to which IRQ[irq] (ISA) is connected
 361  */
 362 static int find_isa_irq_pin(int irq, int type)
 363 {
 364         int i;
 365
 366         for (i = 0; i < mp_irq_entries; i++) {
 367                 int lbus = mp_irqs[i].mpc_srcbus;
 368
 369                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 370                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 371                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 372                     (mp_irqs[i].mpc_irqtype == type) &&
 373                     (mp_irqs[i].mpc_srcbusirq == irq))
 374
 375                         return mp_irqs[i].mpc_dstirq;
 376         }
 377         return -1;
 378 }
 379
 380 /*
 381  * Find a specific PCI IRQ entry.
 382  * Not an __init, possibly needed by modules
 383  */
 384 static int pin_2_irq(int idx, int apic, int pin);
 385
 386 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 387 {
 388         int apic, i, best_guess = -1;
 389
 390         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 391                 bus, slot, pin);
 392         if (mp_bus_id_to_pci_bus[bus] == -1) {
 393                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 394                 return -1;
 395         }
 396         for (i = 0; i < mp_irq_entries; i++) {
 397                 int lbus = mp_irqs[i].mpc_srcbus;
 398
 399                 for (apic = 0; apic < nr_ioapics; apic++)
 400                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 401                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 402                                 break;
 403
 404                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 405                     !mp_irqs[i].mpc_irqtype &&
 406                     (bus == lbus) &&
 407                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 408                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 409
 410                         if (!(apic || IO_APIC_IRQ(irq)))
 411                                 continue;
 412
 413                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 414                                 return irq;
 415                         /*
 416                          * Use the first all-but-pin matching entry as a
 417                          * best-guess fuzzy result for broken mptables.
 418                          */
 419                         if (best_guess < 0)
 420                                 best_guess = irq;
 421                 }
 422         }
 423         return best_guess;
 424 }
 425
 426 /*
 427  * EISA Edge/Level control register, ELCR
 428  */
 429 static int EISA_ELCR(unsigned int irq)
 430 {
 431         if (irq < 16) {
 432                 unsigned int port = 0x4d0 + (irq >> 3);
 433                 return (inb(port) >> (irq & 7)) & 1;
 434         }
 435         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 436         return 0;
 437 }
 438
 439 /* EISA interrupts are always polarity zero and can be edge or level
 440  * trigger depending on the ELCR value.  If an interrupt is listed as
 441  * EISA conforming in the MP table, that means its trigger type must
 442  * be read in from the ELCR */
 443
 444 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 445 #define default_EISA_polarity(idx)      (0)
 446
 447 /* ISA interrupts are always polarity zero edge triggered,
 448  * when listed as conforming in the MP table. */
 449
 450 #define default_ISA_trigger(idx)        (0)
 451 #define default_ISA_polarity(idx)       (0)
 452
 453 /* PCI interrupts are always polarity one level triggered,
 454  * when listed as conforming in the MP table. */
 455
 456 #define default_PCI_trigger(idx)        (1)
 457 #define default_PCI_polarity(idx)       (1)
 458
 459 /* MCA interrupts are always polarity zero level triggered,
 460  * when listed as conforming in the MP table. */
 461
 462 #define default_MCA_trigger(idx)        (1)
 463 #define default_MCA_polarity(idx)       (0)
 464
 465 static int __init MPBIOS_polarity(int idx)
 466 {
 467         int bus = mp_irqs[idx].mpc_srcbus;
 468         int polarity;
 469
 470         /*
 471          * Determine IRQ line polarity (high active or low active):
 472          */
 473         switch (mp_irqs[idx].mpc_irqflag & 3)
 474         {
 475                 case 0: /* conforms, ie. bus-type dependent polarity */
 476                 {
 477                         switch (mp_bus_id_to_type[bus])
 478                         {
 479                                 case MP_BUS_ISA: /* ISA pin */
 480                                 {
 481                                         polarity = default_ISA_polarity(idx);
 482                                         break;
 483                                 }
 484                                 case MP_BUS_EISA: /* EISA pin */
 485                                 {
 486                                         polarity = default_EISA_polarity(idx);
 487                                         break;
 488                                 }
 489                                 case MP_BUS_PCI: /* PCI pin */
 490                                 {
 491                                         polarity = default_PCI_polarity(idx);
 492                                         break;
 493                                 }
 494                                 case MP_BUS_MCA: /* MCA pin */
 495                                 {
 496                                         polarity = default_MCA_polarity(idx);
 497                                         break;
 498                                 }
 499                                 default:
 500                                 {
 501                                         printk(KERN_WARNING "broken BIOS!!\n");
 502                                         polarity = 1;
 503                                         break;
 504                                 }
 505                         }
 506                         break;
 507                 }
 508                 case 1: /* high active */
 509                 {
 510                         polarity = 0;
 511                         break;
 512                 }
 513                 case 2: /* reserved */
 514                 {
 515                         printk(KERN_WARNING "broken BIOS!!\n");
 516                         polarity = 1;
 517                         break;
 518                 }
 519                 case 3: /* low active */
 520                 {
 521                         polarity = 1;
 522                         break;
 523                 }
 524                 default: /* invalid */
 525                 {
 526                         printk(KERN_WARNING "broken BIOS!!\n");
 527                         polarity = 1;
 528                         break;
 529                 }
 530         }
 531         return polarity;
 532 }
 533
 534 static int MPBIOS_trigger(int idx)
 535 {
 536         int bus = mp_irqs[idx].mpc_srcbus;
 537         int trigger;
 538
 539         /*
 540          * Determine IRQ trigger mode (edge or level sensitive):
 541          */
 542         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 543         {
 544                 case 0: /* conforms, ie. bus-type dependent */
 545                 {
 546                         switch (mp_bus_id_to_type[bus])
 547                         {
 548                                 case MP_BUS_ISA: /* ISA pin */
 549                                 {
 550                                         trigger = default_ISA_trigger(idx);
 551                                         break;
 552                                 }
 553                                 case MP_BUS_EISA: /* EISA pin */
 554                                 {
 555                                         trigger = default_EISA_trigger(idx);
 556                                         break;
 557                                 }
 558                                 case MP_BUS_PCI: /* PCI pin */
 559                                 {
 560                                         trigger = default_PCI_trigger(idx);
 561                                         break;
 562                                 }
 563                                 case MP_BUS_MCA: /* MCA pin */
 564                                 {
 565                                         trigger = default_MCA_trigger(idx);
 566                                         break;
 567                                 }
 568                                 default:
 569                                 {
 570                                         printk(KERN_WARNING "broken BIOS!!\n");
 571                                         trigger = 1;
 572                                         break;
 573                                 }
 574                         }
 575                         break;
 576                 }
 577                 case 1: /* edge */
 578                 {
 579                         trigger = 0;
 580                         break;
 581                 }
 582                 case 2: /* reserved */
 583                 {
 584                         printk(KERN_WARNING "broken BIOS!!\n");
 585                         trigger = 1;
 586                         break;
 587                 }
 588                 case 3: /* level */
 589                 {
 590                         trigger = 1;
 591                         break;
 592                 }
 593                 default: /* invalid */
 594                 {
 595                         printk(KERN_WARNING "broken BIOS!!\n");
 596                         trigger = 0;
 597                         break;
 598                 }
 599         }
 600         return trigger;
 601 }
 602
 603 static inline int irq_polarity(int idx)
 604 {
 605         return MPBIOS_polarity(idx);
 606 }
 607
 608 static inline int irq_trigger(int idx)
 609 {
 610         return MPBIOS_trigger(idx);
 611 }
 612
 613 static int pin_2_irq(int idx, int apic, int pin)
 614 {
 615         int irq, i;
 616         int bus = mp_irqs[idx].mpc_srcbus;
 617
 618         /*
 619          * Debugging check, we are in big trouble if this message pops up!
 620          */
 621         if (mp_irqs[idx].mpc_dstirq != pin)
 622                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 623
 624         switch (mp_bus_id_to_type[bus])
 625         {
 626                 case MP_BUS_ISA: /* ISA pin */
 627                 case MP_BUS_EISA:
 628                 case MP_BUS_MCA:
 629                 {
 630                         irq = mp_irqs[idx].mpc_srcbusirq;
 631                         break;
 632                 }
 633                 case MP_BUS_PCI: /* PCI pin */
 634                 {
 635                         /*
 636                          * PCI IRQs are mapped in order
 637                          */
 638                         i = irq = 0;
 639                         while (i < apic)
 640                                 irq += nr_ioapic_registers[i++];
 641                         irq += pin;
 642                         break;
 643                 }
 644                 default:
 645                 {
 646                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 647                         irq = 0;
 648                         break;
 649                 }
 650         }
 651
 652         /*
 653          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 654          */
 655         if ((pin >= 16) && (pin <= 23)) {
 656                 if (pirq_entries[pin-16] != -1) {
 657                         if (!pirq_entries[pin-16]) {
 658                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 659                         } else {
 660                                 irq = pirq_entries[pin-16];
 661                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 662                                                 pin-16, irq);
 663                         }
 664                 }
 665         }
 666         return irq;
 667 }
 668
 669 static inline int IO_APIC_irq_trigger(int irq)
 670 {
 671         int apic, idx, pin;
 672
 673         for (apic = 0; apic < nr_ioapics; apic++) {
 674                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 675                         idx = find_irq_entry(apic,pin,mp_INT);
 676                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 677                                 return irq_trigger(idx);
 678                 }
 679         }
 680         /*
 681          * nonexistent IRQs are edge default
 682          */
 683         return 0;
 684 }
 685
 686 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 687 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 688
 689 int assign_irq_vector(int irq)
 690 {
 691         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 692
 693         BUG_ON(irq >= NR_IRQ_VECTORS);
 694         if (IO_APIC_VECTOR(irq) > 0)
 695                 return IO_APIC_VECTOR(irq);
 696 next:
 697         current_vector += 8;
 698         if (current_vector == IA32_SYSCALL_VECTOR)
 699                 goto next;
 700
 701         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 702                 offset++;
 703                 if (!(offset%8))
 704                         return -ENOSPC;
 705                 current_vector = FIRST_DEVICE_VECTOR + offset;
 706         }
 707
 708         vector_irq[current_vector] = irq;
 709         if (irq != AUTO_ASSIGN)
 710                 IO_APIC_VECTOR(irq) = current_vector;
 711
 712         return current_vector;
 713 }
 714
 715 extern void (*interrupt[NR_IRQS])(void);
 716 static struct hw_interrupt_type ioapic_level_type;
 717 static struct hw_interrupt_type ioapic_edge_type;
 718
 719 #define IOAPIC_AUTO     -1
 720 #define IOAPIC_EDGE     0
 721 #define IOAPIC_LEVEL    1
 722
 723 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 724 {
 725         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 726                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 727                                 trigger == IOAPIC_LEVEL)
 728                         irq_desc[vector].handler = &ioapic_level_type;
 729                 else
 730                         irq_desc[vector].handler = &ioapic_edge_type;
 731                 set_intr_gate(vector, interrupt[vector]);
 732         } else  {
 733                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 734                                 trigger == IOAPIC_LEVEL)
 735                         irq_desc[irq].handler = &ioapic_level_type;
 736                 else
 737                         irq_desc[irq].handler = &ioapic_edge_type;
 738                 set_intr_gate(vector, interrupt[irq]);
 739         }
 740 }
 741
 742 static void __init setup_IO_APIC_irqs(void)
 743 {
 744         struct IO_APIC_route_entry entry;
 745         int apic, pin, idx, irq, first_notcon = 1, vector;
 746         unsigned long flags;
 747
 748         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 749
 750         for (apic = 0; apic < nr_ioapics; apic++) {
 751         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 752
 753                 /*
 754                  * add it to the IO-APIC irq-routing table:
 755                  */
 756                 memset(&entry,0,sizeof(entry));
 757
 758                 entry.delivery_mode = INT_DELIVERY_MODE;
 759                 entry.dest_mode = INT_DEST_MODE;
 760                 entry.mask = 0;                         /* enable IRQ */
 761                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 762
 763                 idx = find_irq_entry(apic,pin,mp_INT);
 764                 if (idx == -1) {
 765                         if (first_notcon) {
 766                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 767                                 first_notcon = 0;
 768                         } else
 769                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 770                         continue;
 771                 }
 772
 773                 entry.trigger = irq_trigger(idx);
 774                 entry.polarity = irq_polarity(idx);
 775
 776                 if (irq_trigger(idx)) {
 777                         entry.trigger = 1;
 778                         entry.mask = 1;
 779                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 780                 }
 781
 782                 irq = pin_2_irq(idx, apic, pin);
 783                 add_pin_to_irq(irq, apic, pin);
 784
 785                 if (!apic && !IO_APIC_IRQ(irq))
 786                         continue;
 787
 788                 if (IO_APIC_IRQ(irq)) {
 789                         vector = assign_irq_vector(irq);
 790                         entry.vector = vector;
 791
 792                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 793                         if (!apic && (irq < 16))
 794                                 disable_8259A_irq(irq);
 795                 }
 796                 spin_lock_irqsave(&ioapic_lock, flags);
 797                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 798                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 799                 set_native_irq_info(irq, TARGET_CPUS);
 800                 spin_unlock_irqrestore(&ioapic_lock, flags);
 801         }
 802         }
 803
 804         if (!first_notcon)
 805                 apic_printk(APIC_VERBOSE," not connected.\n");
 806 }
 807
 808 /*
 809  * Set up the 8259A-master output pin as broadcast to all
 810  * CPUs.
 811  */
 812 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 813 {
 814         struct IO_APIC_route_entry entry;
 815         unsigned long flags;
 816
 817         memset(&entry,0,sizeof(entry));
 818
 819         disable_8259A_irq(0);
 820
 821         /* mask LVT0 */
 822         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 823
 824         /*
 825          * We use logical delivery to get the timer IRQ
 826          * to the first CPU.
 827          */
 828         entry.dest_mode = INT_DEST_MODE;
 829         entry.mask = 0;                                 /* unmask IRQ now */
 830         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 831         entry.delivery_mode = INT_DELIVERY_MODE;
 832         entry.polarity = 0;
 833         entry.trigger = 0;
 834         entry.vector = vector;
 835
 836         /*
 837          * The timer IRQ doesn't have to know that behind the
 838          * scene we have a 8259A-master in AEOI mode ...
 839          */
 840         irq_desc[0].handler = &ioapic_edge_type;
 841
 842         /*
 843          * Add it to the IO-APIC irq-routing table:
 844          */
 845         spin_lock_irqsave(&ioapic_lock, flags);
 846         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 847         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 848         spin_unlock_irqrestore(&ioapic_lock, flags);
 849
 850         enable_8259A_irq(0);
 851 }
 852
 853 void __init UNEXPECTED_IO_APIC(void)
 854 {
 855 }
 856
 857 void __apicdebuginit print_IO_APIC(void)
 858 {
 859         int apic, i;
 860         union IO_APIC_reg_00 reg_00;
 861         union IO_APIC_reg_01 reg_01;
 862         union IO_APIC_reg_02 reg_02;
 863         unsigned long flags;
 864
 865         if (apic_verbosity == APIC_QUIET)
 866                 return;
 867
 868         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 869         for (i = 0; i < nr_ioapics; i++)
 870                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 871                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 872
 873         /*
 874          * We are a bit conservative about what we expect.  We have to
 875          * know about every hardware change ASAP.
 876          */
 877         printk(KERN_INFO "testing the IO APIC.......................\n");
 878
 879         for (apic = 0; apic < nr_ioapics; apic++) {
 880
 881         spin_lock_irqsave(&ioapic_lock, flags);
 882         reg_00.raw = io_apic_read(apic, 0);
 883         reg_01.raw = io_apic_read(apic, 1);
 884         if (reg_01.bits.version >= 0x10)
 885                 reg_02.raw = io_apic_read(apic, 2);
 886         spin_unlock_irqrestore(&ioapic_lock, flags);
 887
 888         printk("\n");
 889         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 890         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 891         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 892         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 893                 UNEXPECTED_IO_APIC();
 894
 895         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 896         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 897         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 898                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 899                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 900                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 901                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 902                 (reg_01.bits.entries != 0x2E) &&
 903                 (reg_01.bits.entries != 0x3F) &&
 904                 (reg_01.bits.entries != 0x03)
 905         )
 906                 UNEXPECTED_IO_APIC();
 907
 908         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 909         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 910         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 911                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 912                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 913                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 914                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 915                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 916         )
 917                 UNEXPECTED_IO_APIC();
 918         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 919                 UNEXPECTED_IO_APIC();
 920
 921         if (reg_01.bits.version >= 0x10) {
 922                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 923                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 924                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 925                         UNEXPECTED_IO_APIC();
 926         }
 927
 928         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 929
 930         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 931                           " Stat Dest Deli Vect:   \n");
 932
 933         for (i = 0; i <= reg_01.bits.entries; i++) {
 934                 struct IO_APIC_route_entry entry;
 935
 936                 spin_lock_irqsave(&ioapic_lock, flags);
 937                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 938                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 939                 spin_unlock_irqrestore(&ioapic_lock, flags);
 940
 941                 printk(KERN_DEBUG " %02x %03X %02X  ",
 942                         i,
 943                         entry.dest.logical.logical_dest,
 944                         entry.dest.physical.physical_dest
 945                 );
 946
 947                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 948                         entry.mask,
 949                         entry.trigger,
 950                         entry.irr,
 951                         entry.polarity,
 952                         entry.delivery_status,
 953                         entry.dest_mode,
 954                         entry.delivery_mode,
 955                         entry.vector
 956                 );
 957         }
 958         }
 959         if (use_pci_vector())
 960                 printk(KERN_INFO "Using vector-based indexing\n");
 961         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 962         for (i = 0; i < NR_IRQS; i++) {
 963                 struct irq_pin_list *entry = irq_2_pin + i;
 964                 if (entry->pin < 0)
 965                         continue;
 966                 if (use_pci_vector() && !platform_legacy_irq(i))
 967                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 968                 else
 969                         printk(KERN_DEBUG "IRQ%d ", i);
 970                 for (;;) {
 971                         printk("-> %d:%d", entry->apic, entry->pin);
 972                         if (!entry->next)
 973                                 break;
 974                         entry = irq_2_pin + entry->next;
 975                 }
 976                 printk("\n");
 977         }
 978
 979         printk(KERN_INFO ".................................... done.\n");
 980
 981         return;
 982 }
 983
 984 #if 0
 985
 986 static __apicdebuginit void print_APIC_bitfield (int base)
 987 {
 988         unsigned int v;
 989         int i, j;
 990
 991         if (apic_verbosity == APIC_QUIET)
 992                 return;
 993
 994         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 995         for (i = 0; i < 8; i++) {
 996                 v = apic_read(base + i*0x10);
 997                 for (j = 0; j < 32; j++) {
 998                         if (v & (1<<j))
 999                                 printk("1");
1000                         else
1001                                 printk("0");
1002                 }
1003                 printk("\n");
1004         }
1005 }
1006
1007 void __apicdebuginit print_local_APIC(void * dummy)
1008 {
1009         unsigned int v, ver, maxlvt;
1010
1011         if (apic_verbosity == APIC_QUIET)
1012                 return;
1013
1014         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1015                 smp_processor_id(), hard_smp_processor_id());
1016         v = apic_read(APIC_ID);
1017         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1018         v = apic_read(APIC_LVR);
1019         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1020         ver = GET_APIC_VERSION(v);
1021         maxlvt = get_maxlvt();
1022
1023         v = apic_read(APIC_TASKPRI);
1024         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1025
1026         v = apic_read(APIC_ARBPRI);
1027         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1028                 v & APIC_ARBPRI_MASK);
1029         v = apic_read(APIC_PROCPRI);
1030         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1031
1032         v = apic_read(APIC_EOI);
1033         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1034         v = apic_read(APIC_RRR);
1035         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1036         v = apic_read(APIC_LDR);
1037         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1038         v = apic_read(APIC_DFR);
1039         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1040         v = apic_read(APIC_SPIV);
1041         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1042
1043         printk(KERN_DEBUG "... APIC ISR field:\n");
1044         print_APIC_bitfield(APIC_ISR);
1045         printk(KERN_DEBUG "... APIC TMR field:\n");
1046         print_APIC_bitfield(APIC_TMR);
1047         printk(KERN_DEBUG "... APIC IRR field:\n");
1048         print_APIC_bitfield(APIC_IRR);
1049
1050         v = apic_read(APIC_ESR);
1051         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1052
1053         v = apic_read(APIC_ICR);
1054         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1055         v = apic_read(APIC_ICR2);
1056         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1057
1058         v = apic_read(APIC_LVTT);
1059         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1060
1061         if (maxlvt > 3) {                       /* PC is LVT#4. */
1062                 v = apic_read(APIC_LVTPC);
1063                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1064         }
1065         v = apic_read(APIC_LVT0);
1066         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1067         v = apic_read(APIC_LVT1);
1068         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1069
1070         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1071                 v = apic_read(APIC_LVTERR);
1072                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1073         }
1074
1075         v = apic_read(APIC_TMICT);
1076         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1077         v = apic_read(APIC_TMCCT);
1078         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1079         v = apic_read(APIC_TDCR);
1080         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1081         printk("\n");
1082 }
1083
1084 void print_all_local_APICs (void)
1085 {
1086         on_each_cpu(print_local_APIC, NULL, 1, 1);
1087 }
1088
1089 void __apicdebuginit print_PIC(void)
1090 {
1091         unsigned int v;
1092         unsigned long flags;
1093
1094         if (apic_verbosity == APIC_QUIET)
1095                 return;
1096
1097         printk(KERN_DEBUG "\nprinting PIC contents\n");
1098
1099         spin_lock_irqsave(&i8259A_lock, flags);
1100
1101         v = inb(0xa1) << 8 | inb(0x21);
1102         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1103
1104         v = inb(0xa0) << 8 | inb(0x20);
1105         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1106
1107         outb(0x0b,0xa0);
1108         outb(0x0b,0x20);
1109         v = inb(0xa0) << 8 | inb(0x20);
1110         outb(0x0a,0xa0);
1111         outb(0x0a,0x20);
1112
1113         spin_unlock_irqrestore(&i8259A_lock, flags);
1114
1115         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1116
1117         v = inb(0x4d1) << 8 | inb(0x4d0);
1118         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1119 }
1120
1121 #endif  /*  0  */
1122
1123 static void __init enable_IO_APIC(void)
1124 {
1125         union IO_APIC_reg_01 reg_01;
1126         int i;
1127         unsigned long flags;
1128
1129         for (i = 0; i < PIN_MAP_SIZE; i++) {
1130                 irq_2_pin[i].pin = -1;
1131                 irq_2_pin[i].next = 0;
1132         }
1133         if (!pirqs_enabled)
1134                 for (i = 0; i < MAX_PIRQS; i++)
1135                         pirq_entries[i] = -1;
1136
1137         /*
1138          * The number of IO-APIC IRQ registers (== #pins):
1139          */
1140         for (i = 0; i < nr_ioapics; i++) {
1141                 spin_lock_irqsave(&ioapic_lock, flags);
1142                 reg_01.raw = io_apic_read(i, 1);
1143                 spin_unlock_irqrestore(&ioapic_lock, flags);
1144                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1145         }
1146
1147         /*
1148          * Do not trust the IO-APIC being empty at bootup
1149          */
1150         clear_IO_APIC();
1151 }
1152
1153 /*
1154  * Not an __init, needed by the reboot code
1155  */
1156 void disable_IO_APIC(void)
1157 {
1158         int pin;
1159         /*
1160          * Clear the IO-APIC before rebooting:
1161          */
1162         clear_IO_APIC();
1163
1164         /*
1165          * If the i8259 is routed through an IOAPIC
1166          * Put that IOAPIC in virtual wire mode
1167          * so legacy interrupts can be delivered.
1168          */
1169         pin = find_isa_irq_pin(0, mp_ExtINT);
1170         if (pin != -1) {
1171                 struct IO_APIC_route_entry entry;
1172                 unsigned long flags;
1173
1174                 memset(&entry, 0, sizeof(entry));
1175                 entry.mask            = 0; /* Enabled */
1176                 entry.trigger         = 0; /* Edge */
1177                 entry.irr             = 0;
1178                 entry.polarity        = 0; /* High */
1179                 entry.delivery_status = 0;
1180                 entry.dest_mode       = 0; /* Physical */
1181                 entry.delivery_mode   = 7; /* ExtInt */
1182                 entry.vector          = 0;
1183                 entry.dest.physical.physical_dest = 0;
1184
1185
1186                 /*
1187                  * Add it to the IO-APIC irq-routing table:
1188                  */
1189                 spin_lock_irqsave(&ioapic_lock, flags);
1190                 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1191                 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1192                 spin_unlock_irqrestore(&ioapic_lock, flags);
1193         }
1194
1195         disconnect_bsp_APIC(pin != -1);
1196 }
1197
1198 /*
1199  * function to set the IO-APIC physical IDs based on the
1200  * values stored in the MPC table.
1201  *
1202  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1203  */
1204
1205 static void __init setup_ioapic_ids_from_mpc (void)
1206 {
1207         union IO_APIC_reg_00 reg_00;
1208         int apic;
1209         int i;
1210         unsigned char old_id;
1211         unsigned long flags;
1212
1213         /*
1214          * Set the IOAPIC ID to the value stored in the MPC table.
1215          */
1216         for (apic = 0; apic < nr_ioapics; apic++) {
1217
1218                 /* Read the register 0 value */
1219                 spin_lock_irqsave(&ioapic_lock, flags);
1220                 reg_00.raw = io_apic_read(apic, 0);
1221                 spin_unlock_irqrestore(&ioapic_lock, flags);
1222
1223                 old_id = mp_ioapics[apic].mpc_apicid;
1224
1225
1226                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1227
1228
1229                 /*
1230                  * We need to adjust the IRQ routing table
1231                  * if the ID changed.
1232                  */
1233                 if (old_id != mp_ioapics[apic].mpc_apicid)
1234                         for (i = 0; i < mp_irq_entries; i++)
1235                                 if (mp_irqs[i].mpc_dstapic == old_id)
1236                                         mp_irqs[i].mpc_dstapic
1237                                                 = mp_ioapics[apic].mpc_apicid;
1238
1239                 /*
1240                  * Read the right value from the MPC table and
1241                  * write it into the ID register.
1242                  */
1243                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1244                                 mp_ioapics[apic].mpc_apicid);
1245
1246                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1247                 spin_lock_irqsave(&ioapic_lock, flags);
1248                 io_apic_write(apic, 0, reg_00.raw);
1249                 spin_unlock_irqrestore(&ioapic_lock, flags);
1250
1251                 /*
1252                  * Sanity check
1253                  */
1254                 spin_lock_irqsave(&ioapic_lock, flags);
1255                 reg_00.raw = io_apic_read(apic, 0);
1256                 spin_unlock_irqrestore(&ioapic_lock, flags);
1257                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1258                         printk("could not set ID!\n");
1259                 else
1260                         apic_printk(APIC_VERBOSE," ok.\n");
1261         }
1262 }
1263
1264 /*
1265  * There is a nasty bug in some older SMP boards, their mptable lies
1266  * about the timer IRQ. We do the following to work around the situation:
1267  *
1268  *      - timer IRQ defaults to IO-APIC IRQ
1269  *      - if this function detects that timer IRQs are defunct, then we fall
1270  *        back to ISA timer IRQs
1271  */
1272 static int __init timer_irq_works(void)
1273 {
1274         unsigned long t1 = jiffies;
1275
1276         local_irq_enable();
1277         /* Let ten ticks pass... */
1278         mdelay((10 * 1000) / HZ);
1279
1280         /*
1281          * Expect a few ticks at least, to be sure some possible
1282          * glue logic does not lock up after one or two first
1283          * ticks in a non-ExtINT mode.  Also the local APIC
1284          * might have cached one ExtINT interrupt.  Finally, at
1285          * least one tick may be lost due to delays.
1286          */
1287
1288         /* jiffies wrap? */
1289         if (jiffies - t1 > 4)
1290                 return 1;
1291         return 0;
1292 }
1293
1294 /*
1295  * In the SMP+IOAPIC case it might happen that there are an unspecified
1296  * number of pending IRQ events unhandled. These cases are very rare,
1297  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1298  * better to do it this way as thus we do not have to be aware of
1299  * 'pending' interrupts in the IRQ path, except at this point.
1300  */
1301 /*
1302  * Edge triggered needs to resend any interrupt
1303  * that was delayed but this is now handled in the device
1304  * independent code.
1305  */
1306
1307 /*
1308  * Starting up a edge-triggered IO-APIC interrupt is
1309  * nasty - we need to make sure that we get the edge.
1310  * If it is already asserted for some reason, we need
1311  * return 1 to indicate that is was pending.
1312  *
1313  * This is not complete - we should be able to fake
1314  * an edge even if it isn't on the 8259A...
1315  */
1316
1317 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1318 {
1319         int was_pending = 0;
1320         unsigned long flags;
1321
1322         spin_lock_irqsave(&ioapic_lock, flags);
1323         if (irq < 16) {
1324                 disable_8259A_irq(irq);
1325                 if (i8259A_irq_pending(irq))
1326                         was_pending = 1;
1327         }
1328         __unmask_IO_APIC_irq(irq);
1329         spin_unlock_irqrestore(&ioapic_lock, flags);
1330
1331         return was_pending;
1332 }
1333
1334 /*
1335  * Once we have recorded IRQ_PENDING already, we can mask the
1336  * interrupt for real. This prevents IRQ storms from unhandled
1337  * devices.
1338  */
1339 static void ack_edge_ioapic_irq(unsigned int irq)
1340 {
1341         move_irq(irq);
1342         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1343                                         == (IRQ_PENDING | IRQ_DISABLED))
1344                 mask_IO_APIC_irq(irq);
1345         ack_APIC_irq();
1346 }
1347
1348 /*
1349  * Level triggered interrupts can just be masked,
1350  * and shutting down and starting up the interrupt
1351  * is the same as enabling and disabling them -- except
1352  * with a startup need to return a "was pending" value.
1353  *
1354  * Level triggered interrupts are special because we
1355  * do not touch any IO-APIC register while handling
1356  * them. We ack the APIC in the end-IRQ handler, not
1357  * in the start-IRQ-handler. Protection against reentrance
1358  * from the same interrupt is still provided, both by the
1359  * generic IRQ layer and by the fact that an unacked local
1360  * APIC does not accept IRQs.
1361  */
1362 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1363 {
1364         unmask_IO_APIC_irq(irq);
1365
1366         return 0; /* don't check for pending */
1367 }
1368
1369 static void end_level_ioapic_irq (unsigned int irq)
1370 {
1371         move_irq(irq);
1372         ack_APIC_irq();
1373 }
1374
1375 #ifdef CONFIG_PCI_MSI
1376 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1377 {
1378         int irq = vector_to_irq(vector);
1379
1380         return startup_edge_ioapic_irq(irq);
1381 }
1382
1383 static void ack_edge_ioapic_vector(unsigned int vector)
1384 {
1385         int irq = vector_to_irq(vector);
1386
1387         move_native_irq(vector);
1388         ack_edge_ioapic_irq(irq);
1389 }
1390
1391 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1392 {
1393         int irq = vector_to_irq(vector);
1394
1395         return startup_level_ioapic_irq (irq);
1396 }
1397
1398 static void end_level_ioapic_vector (unsigned int vector)
1399 {
1400         int irq = vector_to_irq(vector);
1401
1402         move_native_irq(vector);
1403         end_level_ioapic_irq(irq);
1404 }
1405
1406 static void mask_IO_APIC_vector (unsigned int vector)
1407 {
1408         int irq = vector_to_irq(vector);
1409
1410         mask_IO_APIC_irq(irq);
1411 }
1412
1413 static void unmask_IO_APIC_vector (unsigned int vector)
1414 {
1415         int irq = vector_to_irq(vector);
1416
1417         unmask_IO_APIC_irq(irq);
1418 }
1419
1420 #ifdef CONFIG_SMP
1421 static void set_ioapic_affinity_vector (unsigned int vector,
1422                                         cpumask_t cpu_mask)
1423 {
1424         int irq = vector_to_irq(vector);
1425
1426         set_native_irq_info(vector, cpu_mask);
1427         set_ioapic_affinity_irq(irq, cpu_mask);
1428 }
1429 #endif // CONFIG_SMP
1430 #endif // CONFIG_PCI_MSI
1431
1432 /*
1433  * Level and edge triggered IO-APIC interrupts need different handling,
1434  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1435  * handled with the level-triggered descriptor, but that one has slightly
1436  * more overhead. Level-triggered interrupts cannot be handled with the
1437  * edge-triggered handler, without risking IRQ storms and other ugly
1438  * races.
1439  */
1440
1441 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1442         .typename = "IO-APIC-edge",
1443         .startup        = startup_edge_ioapic,
1444         .shutdown       = shutdown_edge_ioapic,
1445         .enable         = enable_edge_ioapic,
1446         .disable        = disable_edge_ioapic,
1447         .ack            = ack_edge_ioapic,
1448         .end            = end_edge_ioapic,
1449 #ifdef CONFIG_SMP
1450         .set_affinity = set_ioapic_affinity,
1451 #endif
1452 };
1453
1454 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1455         .typename = "IO-APIC-level",
1456         .startup        = startup_level_ioapic,
1457         .shutdown       = shutdown_level_ioapic,
1458         .enable         = enable_level_ioapic,
1459         .disable        = disable_level_ioapic,
1460         .ack            = mask_and_ack_level_ioapic,
1461         .end            = end_level_ioapic,
1462 #ifdef CONFIG_SMP
1463         .set_affinity = set_ioapic_affinity,
1464 #endif
1465 };
1466
1467 static inline void init_IO_APIC_traps(void)
1468 {
1469         int irq;
1470
1471         /*
1472          * NOTE! The local APIC isn't very good at handling
1473          * multiple interrupts at the same interrupt level.
1474          * As the interrupt level is determined by taking the
1475          * vector number and shifting that right by 4, we
1476          * want to spread these out a bit so that they don't
1477          * all fall in the same interrupt level.
1478          *
1479          * Also, we've got to be careful not to trash gate
1480          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1481          */
1482         for (irq = 0; irq < NR_IRQS ; irq++) {
1483                 int tmp = irq;
1484                 if (use_pci_vector()) {
1485                         if (!platform_legacy_irq(tmp))
1486                                 if ((tmp = vector_to_irq(tmp)) == -1)
1487                                         continue;
1488                 }
1489                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1490                         /*
1491                          * Hmm.. We don't have an entry for this,
1492                          * so default to an old-fashioned 8259
1493                          * interrupt if we can..
1494                          */
1495                         if (irq < 16)
1496                                 make_8259A_irq(irq);
1497                         else
1498                                 /* Strange. Oh, well.. */
1499                                 irq_desc[irq].handler = &no_irq_type;
1500                 }
1501         }
1502 }
1503
1504 static void enable_lapic_irq (unsigned int irq)
1505 {
1506         unsigned long v;
1507
1508         v = apic_read(APIC_LVT0);
1509         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1510 }
1511
1512 static void disable_lapic_irq (unsigned int irq)
1513 {
1514         unsigned long v;
1515
1516         v = apic_read(APIC_LVT0);
1517         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1518 }
1519
1520 static void ack_lapic_irq (unsigned int irq)
1521 {
1522         ack_APIC_irq();
1523 }
1524
1525 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1526
1527 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1528         .typename = "local-APIC-edge",
1529         .startup = NULL, /* startup_irq() not used for IRQ0 */
1530         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1531         .enable = enable_lapic_irq,
1532         .disable = disable_lapic_irq,
1533         .ack = ack_lapic_irq,
1534         .end = end_lapic_irq,
1535 };
1536
1537 static void setup_nmi (void)
1538 {
1539         /*
1540          * Dirty trick to enable the NMI watchdog ...
1541          * We put the 8259A master into AEOI mode and
1542          * unmask on all local APICs LVT0 as NMI.
1543          *
1544          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1545          * is from Maciej W. Rozycki - so we do not have to EOI from
1546          * the NMI handler or the timer interrupt.
1547          */
1548         printk(KERN_INFO "activating NMI Watchdog ...");
1549
1550         enable_NMI_through_LVT0(NULL);
1551
1552         printk(" done.\n");
1553 }
1554
1555 /*
1556  * This looks a bit hackish but it's about the only one way of sending
1557  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1558  * not support the ExtINT mode, unfortunately.  We need to send these
1559  * cycles as some i82489DX-based boards have glue logic that keeps the
1560  * 8259A interrupt line asserted until INTA.  --macro
1561  */
1562 static inline void unlock_ExtINT_logic(void)
1563 {
1564         int pin, i;
1565         struct IO_APIC_route_entry entry0, entry1;
1566         unsigned char save_control, save_freq_select;
1567         unsigned long flags;
1568
1569         pin = find_isa_irq_pin(8, mp_INT);
1570         if (pin == -1)
1571                 return;
1572
1573         spin_lock_irqsave(&ioapic_lock, flags);
1574         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1575         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1576         spin_unlock_irqrestore(&ioapic_lock, flags);
1577         clear_IO_APIC_pin(0, pin);
1578
1579         memset(&entry1, 0, sizeof(entry1));
1580
1581         entry1.dest_mode = 0;                   /* physical delivery */
1582         entry1.mask = 0;                        /* unmask IRQ now */
1583         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1584         entry1.delivery_mode = dest_ExtINT;
1585         entry1.polarity = entry0.polarity;
1586         entry1.trigger = 0;
1587         entry1.vector = 0;
1588
1589         spin_lock_irqsave(&ioapic_lock, flags);
1590         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1591         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1592         spin_unlock_irqrestore(&ioapic_lock, flags);
1593
1594         save_control = CMOS_READ(RTC_CONTROL);
1595         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1596         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1597                    RTC_FREQ_SELECT);
1598         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1599
1600         i = 100;
1601         while (i-- > 0) {
1602                 mdelay(10);
1603                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1604                         i -= 10;
1605         }
1606
1607         CMOS_WRITE(save_control, RTC_CONTROL);
1608         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1609         clear_IO_APIC_pin(0, pin);
1610
1611         spin_lock_irqsave(&ioapic_lock, flags);
1612         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1613         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1614         spin_unlock_irqrestore(&ioapic_lock, flags);
1615 }
1616
1617 /*
1618  * This code may look a bit paranoid, but it's supposed to cooperate with
1619  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1620  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1621  * fanatically on his truly buggy board.
1622  */
1623 static inline void check_timer(void)
1624 {
1625         int pin1, pin2;
1626         int vector;
1627
1628         /*
1629          * get/set the timer IRQ vector:
1630          */
1631         disable_8259A_irq(0);
1632         vector = assign_irq_vector(0);
1633         set_intr_gate(vector, interrupt[0]);
1634
1635         /*
1636          * Subtle, code in do_timer_interrupt() expects an AEOI
1637          * mode for the 8259A whenever interrupts are routed
1638          * through I/O APICs.  Also IRQ0 has to be enabled in
1639          * the 8259A which implies the virtual wire has to be
1640          * disabled in the local APIC.
1641          */
1642         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1643         init_8259A(1);
1644         enable_8259A_irq(0);
1645
1646         pin1 = find_isa_irq_pin(0, mp_INT);
1647         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1648
1649         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1650
1651         if (pin1 != -1) {
1652                 /*
1653                  * Ok, does IRQ0 through the IOAPIC work?
1654                  */
1655                 unmask_IO_APIC_irq(0);
1656                 if (!no_timer_check && timer_irq_works()) {
1657                         nmi_watchdog_default();
1658                         if (nmi_watchdog == NMI_IO_APIC) {
1659                                 disable_8259A_irq(0);
1660                                 setup_nmi();
1661                                 enable_8259A_irq(0);
1662                         }
1663                         if (disable_timer_pin_1 > 0)
1664                                 clear_IO_APIC_pin(0, pin1);
1665                         return;
1666                 }
1667                 clear_IO_APIC_pin(0, pin1);
1668                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1669         }
1670
1671         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1672         if (pin2 != -1) {
1673                 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1674                 /*
1675                  * legacy devices should be connected to IO APIC #0
1676                  */
1677                 setup_ExtINT_IRQ0_pin(pin2, vector);
1678                 if (timer_irq_works()) {
1679                         printk("works.\n");
1680                         nmi_watchdog_default();
1681                         if (nmi_watchdog == NMI_IO_APIC) {
1682                                 setup_nmi();
1683                         }
1684                         return;
1685                 }
1686                 /*
1687                  * Cleanup, just in case ...
1688                  */
1689                 clear_IO_APIC_pin(0, pin2);
1690         }
1691         printk(" failed.\n");
1692
1693         if (nmi_watchdog) {
1694                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1695                 nmi_watchdog = 0;
1696         }
1697
1698         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1699
1700         disable_8259A_irq(0);
1701         irq_desc[0].handler = &lapic_irq_type;
1702         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1703         enable_8259A_irq(0);
1704
1705         if (timer_irq_works()) {
1706                 apic_printk(APIC_QUIET, " works.\n");
1707                 return;
1708         }
1709         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1710         apic_printk(APIC_VERBOSE," failed.\n");
1711
1712         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1713
1714         init_8259A(0);
1715         make_8259A_irq(0);
1716         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1717
1718         unlock_ExtINT_logic();
1719
1720         if (timer_irq_works()) {
1721                 apic_printk(APIC_VERBOSE," works.\n");
1722                 return;
1723         }
1724         apic_printk(APIC_VERBOSE," failed :(.\n");
1725         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1726 }
1727
1728 static int __init notimercheck(char *s)
1729 {
1730         no_timer_check = 1;
1731         return 1;
1732 }
1733 __setup("no_timer_check", notimercheck);
1734
1735 /*
1736  *
1737  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1738  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1739  *   Linux doesn't really care, as it's not actually used
1740  *   for any interrupt handling anyway.
1741  */
1742 #define PIC_IRQS        (1<<2)
1743
1744 void __init setup_IO_APIC(void)
1745 {
1746         enable_IO_APIC();
1747
1748         if (acpi_ioapic)
1749                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1750         else
1751                 io_apic_irqs = ~PIC_IRQS;
1752
1753         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1754
1755         /*
1756          * Set up the IO-APIC IRQ routing table.
1757          */
1758         if (!acpi_ioapic)
1759                 setup_ioapic_ids_from_mpc();
1760         sync_Arb_IDs();
1761         setup_IO_APIC_irqs();
1762         init_IO_APIC_traps();
1763         check_timer();
1764         if (!acpi_ioapic)
1765                 print_IO_APIC();
1766 }
1767
1768 struct sysfs_ioapic_data {
1769         struct sys_device dev;
1770         struct IO_APIC_route_entry entry[0];
1771 };
1772 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1773
1774 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1775 {
1776         struct IO_APIC_route_entry *entry;
1777         struct sysfs_ioapic_data *data;
1778         unsigned long flags;
1779         int i;
1780
1781         data = container_of(dev, struct sysfs_ioapic_data, dev);
1782         entry = data->entry;
1783         spin_lock_irqsave(&ioapic_lock, flags);
1784         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1785                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1786                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1787         }
1788         spin_unlock_irqrestore(&ioapic_lock, flags);
1789
1790         return 0;
1791 }
1792
1793 static int ioapic_resume(struct sys_device *dev)
1794 {
1795         struct IO_APIC_route_entry *entry;
1796         struct sysfs_ioapic_data *data;
1797         unsigned long flags;
1798         union IO_APIC_reg_00 reg_00;
1799         int i;
1800
1801         data = container_of(dev, struct sysfs_ioapic_data, dev);
1802         entry = data->entry;
1803
1804         spin_lock_irqsave(&ioapic_lock, flags);
1805         reg_00.raw = io_apic_read(dev->id, 0);
1806         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1807                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1808                 io_apic_write(dev->id, 0, reg_00.raw);
1809         }
1810         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1811                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1812                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1813         }
1814         spin_unlock_irqrestore(&ioapic_lock, flags);
1815
1816         return 0;
1817 }
1818
1819 static struct sysdev_class ioapic_sysdev_class = {
1820         set_kset_name("ioapic"),
1821         .suspend = ioapic_suspend,
1822         .resume = ioapic_resume,
1823 };
1824
1825 static int __init ioapic_init_sysfs(void)
1826 {
1827         struct sys_device * dev;
1828         int i, size, error = 0;
1829
1830         error = sysdev_class_register(&ioapic_sysdev_class);
1831         if (error)
1832                 return error;
1833
1834         for (i = 0; i < nr_ioapics; i++ ) {
1835                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1836                         * sizeof(struct IO_APIC_route_entry);
1837                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1838                 if (!mp_ioapic_data[i]) {
1839                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1840                         continue;
1841                 }
1842                 memset(mp_ioapic_data[i], 0, size);
1843                 dev = &mp_ioapic_data[i]->dev;
1844                 dev->id = i;
1845                 dev->cls = &ioapic_sysdev_class;
1846                 error = sysdev_register(dev);
1847                 if (error) {
1848                         kfree(mp_ioapic_data[i]);
1849                         mp_ioapic_data[i] = NULL;
1850                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1851                         continue;
1852                 }
1853         }
1854
1855         return 0;
1856 }
1857
1858 device_initcall(ioapic_init_sysfs);
1859
1860 /* --------------------------------------------------------------------------
1861                           ACPI-based IOAPIC Configuration
1862    -------------------------------------------------------------------------- */
1863
1864 #ifdef CONFIG_ACPI
1865
1866 #define IO_APIC_MAX_ID          0xFE
1867
1868 int __init io_apic_get_version (int ioapic)
1869 {
1870         union IO_APIC_reg_01    reg_01;
1871         unsigned long flags;
1872
1873         spin_lock_irqsave(&ioapic_lock, flags);
1874         reg_01.raw = io_apic_read(ioapic, 1);
1875         spin_unlock_irqrestore(&ioapic_lock, flags);
1876
1877         return reg_01.bits.version;
1878 }
1879
1880
1881 int __init io_apic_get_redir_entries (int ioapic)
1882 {
1883         union IO_APIC_reg_01    reg_01;
1884         unsigned long flags;
1885
1886         spin_lock_irqsave(&ioapic_lock, flags);
1887         reg_01.raw = io_apic_read(ioapic, 1);
1888         spin_unlock_irqrestore(&ioapic_lock, flags);
1889
1890         return reg_01.bits.entries;
1891 }
1892
1893
1894 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1895 {
1896         struct IO_APIC_route_entry entry;
1897         unsigned long flags;
1898
1899         if (!IO_APIC_IRQ(irq)) {
1900                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1901                         ioapic);
1902                 return -EINVAL;
1903         }
1904
1905         /*
1906          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1907          * Note that we mask (disable) IRQs now -- these get enabled when the
1908          * corresponding device driver registers for this IRQ.
1909          */
1910
1911         memset(&entry,0,sizeof(entry));
1912
1913         entry.delivery_mode = INT_DELIVERY_MODE;
1914         entry.dest_mode = INT_DEST_MODE;
1915         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1916         entry.trigger = edge_level;
1917         entry.polarity = active_high_low;
1918         entry.mask = 1;                                  /* Disabled (masked) */
1919
1920         /*
1921          * IRQs < 16 are already in the irq_2_pin[] map
1922          */
1923         if (irq >= 16)
1924                 add_pin_to_irq(irq, ioapic, pin);
1925
1926         entry.vector = assign_irq_vector(irq);
1927
1928         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1929                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1930                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1931                edge_level, active_high_low);
1932
1933         ioapic_register_intr(irq, entry.vector, edge_level);
1934
1935         if (!ioapic && (irq < 16))
1936                 disable_8259A_irq(irq);
1937
1938         spin_lock_irqsave(&ioapic_lock, flags);
1939         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1940         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1941         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
1942         spin_unlock_irqrestore(&ioapic_lock, flags);
1943
1944         return 0;
1945 }
1946
1947 #endif /* CONFIG_ACPI */
1948
1949
1950 /*
1951  * This function currently is only a helper for the i386 smp boot process where
1952  * we need to reprogram the ioredtbls to cater for the cpus which have come online
1953  * so mask in all cases should simply be TARGET_CPUS
1954  */
1955 #ifdef CONFIG_SMP
1956 void __init setup_ioapic_dest(void)
1957 {
1958         int pin, ioapic, irq, irq_entry;
1959
1960         if (skip_ioapic_setup == 1)
1961                 return;
1962
1963         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1964                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1965                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1966                         if (irq_entry == -1)
1967                                 continue;
1968                         irq = pin_2_irq(irq_entry, ioapic, pin);
1969                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
1970                 }
1971
1972         }
1973 }
1974 #endif