2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
34 #include <acpi/acpi_bus.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
45 #include <asm/msidef.h>
47 static int assign_irq_vector(int irq);
49 #define __apicdebuginit __init
51 int sis_apic_bug; /* not actually supported, dummy for compile */
53 static int no_timer_check;
55 static int disable_timer_pin_1 __initdata;
57 int timer_over_8254 __initdata = 0;
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
62 static DEFINE_SPINLOCK(ioapic_lock);
63 static DEFINE_SPINLOCK(vector_lock);
66 * # of IRQ routing registers
68 int nr_ioapic_registers[MAX_IO_APICS];
71 * Rough estimation of how many shared IRQs there are, can
74 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
75 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
78 * This is performance-critical, we want to do it O(1)
80 * the indexing order of this array favors 1:1 mappings
81 * between pins and IRQs.
84 static struct irq_pin_list {
85 short apic, pin, next;
86 } irq_2_pin[PIN_MAP_SIZE];
88 #define __DO_ACTION(R, ACTION, FINAL) \
92 struct irq_pin_list *entry = irq_2_pin + irq; \
94 BUG_ON(irq >= NR_IRQS); \
100 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
102 io_apic_modify(entry->apic, reg); \
105 entry = irq_2_pin + entry->next; \
111 struct { u32 w1, w2; };
112 struct IO_APIC_route_entry entry;
115 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
117 union entry_union eu;
119 spin_lock_irqsave(&ioapic_lock, flags);
120 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
121 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
122 spin_unlock_irqrestore(&ioapic_lock, flags);
126 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
129 union entry_union eu;
131 spin_lock_irqsave(&ioapic_lock, flags);
132 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
133 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
134 spin_unlock_irqrestore(&ioapic_lock, flags);
138 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
144 cpus_and(tmp, mask, cpu_online_map);
148 cpus_and(mask, tmp, CPU_MASK_ALL);
150 dest = cpu_mask_to_apicid(mask);
153 * Only the high 8 bits are valid.
155 dest = SET_APIC_LOGICAL_ID(dest);
157 spin_lock_irqsave(&ioapic_lock, flags);
158 __DO_ACTION(1, = dest, )
159 set_native_irq_info(irq, mask);
160 spin_unlock_irqrestore(&ioapic_lock, flags);
164 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
167 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
168 * shared ISA-space IRQs, so we have to support them. We are super
169 * fast in the common case, and fast for shared ISA-space IRQs.
171 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
173 static int first_free_entry = NR_IRQS;
174 struct irq_pin_list *entry = irq_2_pin + irq;
176 BUG_ON(irq >= NR_IRQS);
178 entry = irq_2_pin + entry->next;
180 if (entry->pin != -1) {
181 entry->next = first_free_entry;
182 entry = irq_2_pin + entry->next;
183 if (++first_free_entry >= PIN_MAP_SIZE)
184 panic("io_apic.c: ran out of irq_2_pin entries!");
191 #define DO_ACTION(name,R,ACTION, FINAL) \
193 static void name##_IO_APIC_irq (unsigned int irq) \
194 __DO_ACTION(R, ACTION, FINAL)
196 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
198 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
201 static void mask_IO_APIC_irq (unsigned int irq)
205 spin_lock_irqsave(&ioapic_lock, flags);
206 __mask_IO_APIC_irq(irq);
207 spin_unlock_irqrestore(&ioapic_lock, flags);
210 static void unmask_IO_APIC_irq (unsigned int irq)
214 spin_lock_irqsave(&ioapic_lock, flags);
215 __unmask_IO_APIC_irq(irq);
216 spin_unlock_irqrestore(&ioapic_lock, flags);
219 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
221 struct IO_APIC_route_entry entry;
223 /* Check delivery_mode to be sure we're not clearing an SMI pin */
224 entry = ioapic_read_entry(apic, pin);
225 if (entry.delivery_mode == dest_SMI)
228 * Disable it in the IO-APIC irq-routing table:
230 memset(&entry, 0, sizeof(entry));
232 ioapic_write_entry(apic, pin, entry);
235 static void clear_IO_APIC (void)
239 for (apic = 0; apic < nr_ioapics; apic++)
240 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
241 clear_IO_APIC_pin(apic, pin);
244 int skip_ioapic_setup;
247 /* dummy parsing: see setup.c */
249 static int __init disable_ioapic_setup(char *str)
251 skip_ioapic_setup = 1;
254 early_param("noapic", disable_ioapic_setup);
256 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
257 static int __init disable_timer_pin_setup(char *arg)
259 disable_timer_pin_1 = 1;
262 __setup("disable_timer_pin_1", disable_timer_pin_setup);
264 static int __init setup_disable_8254_timer(char *s)
266 timer_over_8254 = -1;
269 static int __init setup_enable_8254_timer(char *s)
275 __setup("disable_8254_timer", setup_disable_8254_timer);
276 __setup("enable_8254_timer", setup_enable_8254_timer);
280 * Find the IRQ entry number of a certain pin.
282 static int find_irq_entry(int apic, int pin, int type)
286 for (i = 0; i < mp_irq_entries; i++)
287 if (mp_irqs[i].mpc_irqtype == type &&
288 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
289 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
290 mp_irqs[i].mpc_dstirq == pin)
297 * Find the pin to which IRQ[irq] (ISA) is connected
299 static int __init find_isa_irq_pin(int irq, int type)
303 for (i = 0; i < mp_irq_entries; i++) {
304 int lbus = mp_irqs[i].mpc_srcbus;
306 if (test_bit(lbus, mp_bus_not_pci) &&
307 (mp_irqs[i].mpc_irqtype == type) &&
308 (mp_irqs[i].mpc_srcbusirq == irq))
310 return mp_irqs[i].mpc_dstirq;
315 static int __init find_isa_irq_apic(int irq, int type)
319 for (i = 0; i < mp_irq_entries; i++) {
320 int lbus = mp_irqs[i].mpc_srcbus;
322 if (test_bit(lbus, mp_bus_not_pci) &&
323 (mp_irqs[i].mpc_irqtype == type) &&
324 (mp_irqs[i].mpc_srcbusirq == irq))
327 if (i < mp_irq_entries) {
329 for(apic = 0; apic < nr_ioapics; apic++) {
330 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
339 * Find a specific PCI IRQ entry.
340 * Not an __init, possibly needed by modules
342 static int pin_2_irq(int idx, int apic, int pin);
344 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
346 int apic, i, best_guess = -1;
348 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
350 if (mp_bus_id_to_pci_bus[bus] == -1) {
351 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
354 for (i = 0; i < mp_irq_entries; i++) {
355 int lbus = mp_irqs[i].mpc_srcbus;
357 for (apic = 0; apic < nr_ioapics; apic++)
358 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
359 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
362 if (!test_bit(lbus, mp_bus_not_pci) &&
363 !mp_irqs[i].mpc_irqtype &&
365 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
366 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
368 if (!(apic || IO_APIC_IRQ(irq)))
371 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
374 * Use the first all-but-pin matching entry as a
375 * best-guess fuzzy result for broken mptables.
381 BUG_ON(best_guess >= NR_IRQS);
385 /* ISA interrupts are always polarity zero edge triggered,
386 * when listed as conforming in the MP table. */
388 #define default_ISA_trigger(idx) (0)
389 #define default_ISA_polarity(idx) (0)
391 /* PCI interrupts are always polarity one level triggered,
392 * when listed as conforming in the MP table. */
394 #define default_PCI_trigger(idx) (1)
395 #define default_PCI_polarity(idx) (1)
397 static int __init MPBIOS_polarity(int idx)
399 int bus = mp_irqs[idx].mpc_srcbus;
403 * Determine IRQ line polarity (high active or low active):
405 switch (mp_irqs[idx].mpc_irqflag & 3)
407 case 0: /* conforms, ie. bus-type dependent polarity */
408 if (test_bit(bus, mp_bus_not_pci))
409 polarity = default_ISA_polarity(idx);
411 polarity = default_PCI_polarity(idx);
413 case 1: /* high active */
418 case 2: /* reserved */
420 printk(KERN_WARNING "broken BIOS!!\n");
424 case 3: /* low active */
429 default: /* invalid */
431 printk(KERN_WARNING "broken BIOS!!\n");
439 static int MPBIOS_trigger(int idx)
441 int bus = mp_irqs[idx].mpc_srcbus;
445 * Determine IRQ trigger mode (edge or level sensitive):
447 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
449 case 0: /* conforms, ie. bus-type dependent */
450 if (test_bit(bus, mp_bus_not_pci))
451 trigger = default_ISA_trigger(idx);
453 trigger = default_PCI_trigger(idx);
460 case 2: /* reserved */
462 printk(KERN_WARNING "broken BIOS!!\n");
471 default: /* invalid */
473 printk(KERN_WARNING "broken BIOS!!\n");
481 static inline int irq_polarity(int idx)
483 return MPBIOS_polarity(idx);
486 static inline int irq_trigger(int idx)
488 return MPBIOS_trigger(idx);
491 static int next_irq = 16;
494 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
495 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
496 * from ACPI, which can reach 800 in large boxen.
498 * Compact the sparse GSI space into a sequential IRQ series and reuse
499 * vectors if possible.
501 int gsi_irq_sharing(int gsi)
503 int i, tries, vector;
505 BUG_ON(gsi >= NR_IRQ_VECTORS);
507 if (platform_legacy_irq(gsi))
510 if (gsi_2_irq[gsi] != 0xFF)
511 return (int)gsi_2_irq[gsi];
515 vector = assign_irq_vector(gsi);
518 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
519 * use of vector and if found, return that IRQ. However, we never want
520 * to share legacy IRQs, which usually have a different trigger mode
523 for (i = 0; i < NR_IRQS; i++)
524 if (IO_APIC_VECTOR(i) == vector)
526 if (platform_legacy_irq(i)) {
528 IO_APIC_VECTOR(i) = 0;
531 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
535 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
541 BUG_ON(i >= NR_IRQS);
543 IO_APIC_VECTOR(i) = vector;
544 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
549 static int pin_2_irq(int idx, int apic, int pin)
552 int bus = mp_irqs[idx].mpc_srcbus;
555 * Debugging check, we are in big trouble if this message pops up!
557 if (mp_irqs[idx].mpc_dstirq != pin)
558 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
560 if (test_bit(bus, mp_bus_not_pci)) {
561 irq = mp_irqs[idx].mpc_srcbusirq;
564 * PCI IRQs are mapped in order
568 irq += nr_ioapic_registers[i++];
570 irq = gsi_irq_sharing(irq);
572 BUG_ON(irq >= NR_IRQS);
576 static inline int IO_APIC_irq_trigger(int irq)
580 for (apic = 0; apic < nr_ioapics; apic++) {
581 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
582 idx = find_irq_entry(apic,pin,mp_INT);
583 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
584 return irq_trigger(idx);
588 * nonexistent IRQs are edge default
593 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
594 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
596 static int __assign_irq_vector(int irq)
598 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
601 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
603 if (IO_APIC_VECTOR(irq) > 0) {
604 return IO_APIC_VECTOR(irq);
608 if (current_vector == IA32_SYSCALL_VECTOR)
611 if (current_vector >= FIRST_SYSTEM_VECTOR) {
612 /* If we run out of vectors on large boxen, must share them. */
613 offset = (offset + 1) % 8;
614 current_vector = FIRST_DEVICE_VECTOR + offset;
617 vector = current_vector;
618 IO_APIC_VECTOR(irq) = vector;
623 static int assign_irq_vector(int irq)
628 spin_lock_irqsave(&vector_lock, flags);
629 vector = __assign_irq_vector(irq);
630 spin_unlock_irqrestore(&vector_lock, flags);
635 extern void (*interrupt[NR_IRQS])(void);
637 static struct irq_chip ioapic_chip;
639 #define IOAPIC_AUTO -1
640 #define IOAPIC_EDGE 0
641 #define IOAPIC_LEVEL 1
643 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
645 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
646 trigger == IOAPIC_LEVEL)
647 set_irq_chip_and_handler(irq, &ioapic_chip,
650 set_irq_chip_and_handler(irq, &ioapic_chip,
652 set_intr_gate(vector, interrupt[irq]);
655 static void __init setup_IO_APIC_irqs(void)
657 struct IO_APIC_route_entry entry;
658 int apic, pin, idx, irq, first_notcon = 1, vector;
661 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
663 for (apic = 0; apic < nr_ioapics; apic++) {
664 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
667 * add it to the IO-APIC irq-routing table:
669 memset(&entry,0,sizeof(entry));
671 entry.delivery_mode = INT_DELIVERY_MODE;
672 entry.dest_mode = INT_DEST_MODE;
673 entry.mask = 0; /* enable IRQ */
674 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
676 idx = find_irq_entry(apic,pin,mp_INT);
679 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
682 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
686 entry.trigger = irq_trigger(idx);
687 entry.polarity = irq_polarity(idx);
689 if (irq_trigger(idx)) {
692 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
695 irq = pin_2_irq(idx, apic, pin);
696 add_pin_to_irq(irq, apic, pin);
698 if (!apic && !IO_APIC_IRQ(irq))
701 if (IO_APIC_IRQ(irq)) {
702 vector = assign_irq_vector(irq);
703 entry.vector = vector;
705 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
706 if (!apic && (irq < 16))
707 disable_8259A_irq(irq);
709 ioapic_write_entry(apic, pin, entry);
711 spin_lock_irqsave(&ioapic_lock, flags);
712 set_native_irq_info(irq, TARGET_CPUS);
713 spin_unlock_irqrestore(&ioapic_lock, flags);
718 apic_printk(APIC_VERBOSE," not connected.\n");
722 * Set up the 8259A-master output pin as broadcast to all
725 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
727 struct IO_APIC_route_entry entry;
730 memset(&entry,0,sizeof(entry));
732 disable_8259A_irq(0);
735 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
738 * We use logical delivery to get the timer IRQ
741 entry.dest_mode = INT_DEST_MODE;
742 entry.mask = 0; /* unmask IRQ now */
743 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
744 entry.delivery_mode = INT_DELIVERY_MODE;
747 entry.vector = vector;
750 * The timer IRQ doesn't have to know that behind the
751 * scene we have a 8259A-master in AEOI mode ...
753 set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
756 * Add it to the IO-APIC irq-routing table:
758 spin_lock_irqsave(&ioapic_lock, flags);
759 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
760 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
761 spin_unlock_irqrestore(&ioapic_lock, flags);
766 void __init UNEXPECTED_IO_APIC(void)
770 void __apicdebuginit print_IO_APIC(void)
773 union IO_APIC_reg_00 reg_00;
774 union IO_APIC_reg_01 reg_01;
775 union IO_APIC_reg_02 reg_02;
778 if (apic_verbosity == APIC_QUIET)
781 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
782 for (i = 0; i < nr_ioapics; i++)
783 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
784 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
787 * We are a bit conservative about what we expect. We have to
788 * know about every hardware change ASAP.
790 printk(KERN_INFO "testing the IO APIC.......................\n");
792 for (apic = 0; apic < nr_ioapics; apic++) {
794 spin_lock_irqsave(&ioapic_lock, flags);
795 reg_00.raw = io_apic_read(apic, 0);
796 reg_01.raw = io_apic_read(apic, 1);
797 if (reg_01.bits.version >= 0x10)
798 reg_02.raw = io_apic_read(apic, 2);
799 spin_unlock_irqrestore(&ioapic_lock, flags);
802 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
803 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
804 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
805 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
806 UNEXPECTED_IO_APIC();
808 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
809 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
810 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
811 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
812 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
813 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
814 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
815 (reg_01.bits.entries != 0x2E) &&
816 (reg_01.bits.entries != 0x3F) &&
817 (reg_01.bits.entries != 0x03)
819 UNEXPECTED_IO_APIC();
821 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
822 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
823 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
824 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
825 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
826 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
827 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
828 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
830 UNEXPECTED_IO_APIC();
831 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
832 UNEXPECTED_IO_APIC();
834 if (reg_01.bits.version >= 0x10) {
835 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
836 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
837 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
838 UNEXPECTED_IO_APIC();
841 printk(KERN_DEBUG ".... IRQ redirection table:\n");
843 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
844 " Stat Dest Deli Vect: \n");
846 for (i = 0; i <= reg_01.bits.entries; i++) {
847 struct IO_APIC_route_entry entry;
849 entry = ioapic_read_entry(apic, i);
851 printk(KERN_DEBUG " %02x %03X %02X ",
853 entry.dest.logical.logical_dest,
854 entry.dest.physical.physical_dest
857 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
862 entry.delivery_status,
869 printk(KERN_DEBUG "IRQ to pin mappings:\n");
870 for (i = 0; i < NR_IRQS; i++) {
871 struct irq_pin_list *entry = irq_2_pin + i;
874 printk(KERN_DEBUG "IRQ%d ", i);
876 printk("-> %d:%d", entry->apic, entry->pin);
879 entry = irq_2_pin + entry->next;
884 printk(KERN_INFO ".................................... done.\n");
891 static __apicdebuginit void print_APIC_bitfield (int base)
896 if (apic_verbosity == APIC_QUIET)
899 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
900 for (i = 0; i < 8; i++) {
901 v = apic_read(base + i*0x10);
902 for (j = 0; j < 32; j++) {
912 void __apicdebuginit print_local_APIC(void * dummy)
914 unsigned int v, ver, maxlvt;
916 if (apic_verbosity == APIC_QUIET)
919 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
920 smp_processor_id(), hard_smp_processor_id());
921 v = apic_read(APIC_ID);
922 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
923 v = apic_read(APIC_LVR);
924 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
925 ver = GET_APIC_VERSION(v);
926 maxlvt = get_maxlvt();
928 v = apic_read(APIC_TASKPRI);
929 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
931 v = apic_read(APIC_ARBPRI);
932 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
933 v & APIC_ARBPRI_MASK);
934 v = apic_read(APIC_PROCPRI);
935 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
937 v = apic_read(APIC_EOI);
938 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
939 v = apic_read(APIC_RRR);
940 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
941 v = apic_read(APIC_LDR);
942 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
943 v = apic_read(APIC_DFR);
944 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
945 v = apic_read(APIC_SPIV);
946 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
948 printk(KERN_DEBUG "... APIC ISR field:\n");
949 print_APIC_bitfield(APIC_ISR);
950 printk(KERN_DEBUG "... APIC TMR field:\n");
951 print_APIC_bitfield(APIC_TMR);
952 printk(KERN_DEBUG "... APIC IRR field:\n");
953 print_APIC_bitfield(APIC_IRR);
955 v = apic_read(APIC_ESR);
956 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
958 v = apic_read(APIC_ICR);
959 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
960 v = apic_read(APIC_ICR2);
961 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
963 v = apic_read(APIC_LVTT);
964 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
966 if (maxlvt > 3) { /* PC is LVT#4. */
967 v = apic_read(APIC_LVTPC);
968 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
970 v = apic_read(APIC_LVT0);
971 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
972 v = apic_read(APIC_LVT1);
973 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
975 if (maxlvt > 2) { /* ERR is LVT#3. */
976 v = apic_read(APIC_LVTERR);
977 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
980 v = apic_read(APIC_TMICT);
981 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
982 v = apic_read(APIC_TMCCT);
983 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
984 v = apic_read(APIC_TDCR);
985 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
989 void print_all_local_APICs (void)
991 on_each_cpu(print_local_APIC, NULL, 1, 1);
994 void __apicdebuginit print_PIC(void)
999 if (apic_verbosity == APIC_QUIET)
1002 printk(KERN_DEBUG "\nprinting PIC contents\n");
1004 spin_lock_irqsave(&i8259A_lock, flags);
1006 v = inb(0xa1) << 8 | inb(0x21);
1007 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1009 v = inb(0xa0) << 8 | inb(0x20);
1010 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1014 v = inb(0xa0) << 8 | inb(0x20);
1018 spin_unlock_irqrestore(&i8259A_lock, flags);
1020 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1022 v = inb(0x4d1) << 8 | inb(0x4d0);
1023 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1028 static void __init enable_IO_APIC(void)
1030 union IO_APIC_reg_01 reg_01;
1031 int i8259_apic, i8259_pin;
1033 unsigned long flags;
1035 for (i = 0; i < PIN_MAP_SIZE; i++) {
1036 irq_2_pin[i].pin = -1;
1037 irq_2_pin[i].next = 0;
1041 * The number of IO-APIC IRQ registers (== #pins):
1043 for (apic = 0; apic < nr_ioapics; apic++) {
1044 spin_lock_irqsave(&ioapic_lock, flags);
1045 reg_01.raw = io_apic_read(apic, 1);
1046 spin_unlock_irqrestore(&ioapic_lock, flags);
1047 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1049 for(apic = 0; apic < nr_ioapics; apic++) {
1051 /* See if any of the pins is in ExtINT mode */
1052 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1053 struct IO_APIC_route_entry entry;
1054 entry = ioapic_read_entry(apic, pin);
1056 /* If the interrupt line is enabled and in ExtInt mode
1057 * I have found the pin where the i8259 is connected.
1059 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1060 ioapic_i8259.apic = apic;
1061 ioapic_i8259.pin = pin;
1067 /* Look to see what if the MP table has reported the ExtINT */
1068 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1069 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1070 /* Trust the MP table if nothing is setup in the hardware */
1071 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1072 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1073 ioapic_i8259.pin = i8259_pin;
1074 ioapic_i8259.apic = i8259_apic;
1076 /* Complain if the MP table and the hardware disagree */
1077 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1078 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1080 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1084 * Do not trust the IO-APIC being empty at bootup
1090 * Not an __init, needed by the reboot code
1092 void disable_IO_APIC(void)
1095 * Clear the IO-APIC before rebooting:
1100 * If the i8259 is routed through an IOAPIC
1101 * Put that IOAPIC in virtual wire mode
1102 * so legacy interrupts can be delivered.
1104 if (ioapic_i8259.pin != -1) {
1105 struct IO_APIC_route_entry entry;
1107 memset(&entry, 0, sizeof(entry));
1108 entry.mask = 0; /* Enabled */
1109 entry.trigger = 0; /* Edge */
1111 entry.polarity = 0; /* High */
1112 entry.delivery_status = 0;
1113 entry.dest_mode = 0; /* Physical */
1114 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1116 entry.dest.physical.physical_dest =
1117 GET_APIC_ID(apic_read(APIC_ID));
1120 * Add it to the IO-APIC irq-routing table:
1122 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1125 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1129 * There is a nasty bug in some older SMP boards, their mptable lies
1130 * about the timer IRQ. We do the following to work around the situation:
1132 * - timer IRQ defaults to IO-APIC IRQ
1133 * - if this function detects that timer IRQs are defunct, then we fall
1134 * back to ISA timer IRQs
1136 static int __init timer_irq_works(void)
1138 unsigned long t1 = jiffies;
1141 /* Let ten ticks pass... */
1142 mdelay((10 * 1000) / HZ);
1145 * Expect a few ticks at least, to be sure some possible
1146 * glue logic does not lock up after one or two first
1147 * ticks in a non-ExtINT mode. Also the local APIC
1148 * might have cached one ExtINT interrupt. Finally, at
1149 * least one tick may be lost due to delays.
1153 if (jiffies - t1 > 4)
1159 * In the SMP+IOAPIC case it might happen that there are an unspecified
1160 * number of pending IRQ events unhandled. These cases are very rare,
1161 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1162 * better to do it this way as thus we do not have to be aware of
1163 * 'pending' interrupts in the IRQ path, except at this point.
1166 * Edge triggered needs to resend any interrupt
1167 * that was delayed but this is now handled in the device
1172 * Starting up a edge-triggered IO-APIC interrupt is
1173 * nasty - we need to make sure that we get the edge.
1174 * If it is already asserted for some reason, we need
1175 * return 1 to indicate that is was pending.
1177 * This is not complete - we should be able to fake
1178 * an edge even if it isn't on the 8259A...
1181 static unsigned int startup_ioapic_irq(unsigned int irq)
1183 int was_pending = 0;
1184 unsigned long flags;
1186 spin_lock_irqsave(&ioapic_lock, flags);
1188 disable_8259A_irq(irq);
1189 if (i8259A_irq_pending(irq))
1192 __unmask_IO_APIC_irq(irq);
1193 spin_unlock_irqrestore(&ioapic_lock, flags);
1198 static int ioapic_retrigger_irq(unsigned int irq)
1200 send_IPI_self(IO_APIC_VECTOR(irq));
1206 * Level and edge triggered IO-APIC interrupts need different handling,
1207 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1208 * handled with the level-triggered descriptor, but that one has slightly
1209 * more overhead. Level-triggered interrupts cannot be handled with the
1210 * edge-triggered handler, without risking IRQ storms and other ugly
1214 static void ack_apic_edge(unsigned int irq)
1216 move_native_irq(irq);
1220 static void ack_apic_level(unsigned int irq)
1222 int do_unmask_irq = 0;
1224 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1225 /* If we are moving the irq we need to mask it */
1226 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1228 mask_IO_APIC_irq(irq);
1233 * We must acknowledge the irq before we move it or the acknowledge will
1234 * not propogate properly.
1238 /* Now we can move and renable the irq */
1239 move_masked_irq(irq);
1240 if (unlikely(do_unmask_irq))
1241 unmask_IO_APIC_irq(irq);
1244 static struct irq_chip ioapic_chip __read_mostly = {
1246 .startup = startup_ioapic_irq,
1247 .mask = mask_IO_APIC_irq,
1248 .unmask = unmask_IO_APIC_irq,
1249 .ack = ack_apic_edge,
1250 .eoi = ack_apic_level,
1252 .set_affinity = set_ioapic_affinity_irq,
1254 .retrigger = ioapic_retrigger_irq,
1257 static inline void init_IO_APIC_traps(void)
1262 * NOTE! The local APIC isn't very good at handling
1263 * multiple interrupts at the same interrupt level.
1264 * As the interrupt level is determined by taking the
1265 * vector number and shifting that right by 4, we
1266 * want to spread these out a bit so that they don't
1267 * all fall in the same interrupt level.
1269 * Also, we've got to be careful not to trash gate
1270 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1272 for (irq = 0; irq < NR_IRQS ; irq++) {
1274 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1276 * Hmm.. We don't have an entry for this,
1277 * so default to an old-fashioned 8259
1278 * interrupt if we can..
1281 make_8259A_irq(irq);
1283 /* Strange. Oh, well.. */
1284 irq_desc[irq].chip = &no_irq_chip;
1289 static void enable_lapic_irq (unsigned int irq)
1293 v = apic_read(APIC_LVT0);
1294 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1297 static void disable_lapic_irq (unsigned int irq)
1301 v = apic_read(APIC_LVT0);
1302 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1305 static void ack_lapic_irq (unsigned int irq)
1310 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1312 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1313 .typename = "local-APIC-edge",
1314 .startup = NULL, /* startup_irq() not used for IRQ0 */
1315 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1316 .enable = enable_lapic_irq,
1317 .disable = disable_lapic_irq,
1318 .ack = ack_lapic_irq,
1319 .end = end_lapic_irq,
1322 static void setup_nmi (void)
1325 * Dirty trick to enable the NMI watchdog ...
1326 * We put the 8259A master into AEOI mode and
1327 * unmask on all local APICs LVT0 as NMI.
1329 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1330 * is from Maciej W. Rozycki - so we do not have to EOI from
1331 * the NMI handler or the timer interrupt.
1333 printk(KERN_INFO "activating NMI Watchdog ...");
1335 enable_NMI_through_LVT0(NULL);
1341 * This looks a bit hackish but it's about the only one way of sending
1342 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1343 * not support the ExtINT mode, unfortunately. We need to send these
1344 * cycles as some i82489DX-based boards have glue logic that keeps the
1345 * 8259A interrupt line asserted until INTA. --macro
1347 static inline void unlock_ExtINT_logic(void)
1350 struct IO_APIC_route_entry entry0, entry1;
1351 unsigned char save_control, save_freq_select;
1352 unsigned long flags;
1354 pin = find_isa_irq_pin(8, mp_INT);
1355 apic = find_isa_irq_apic(8, mp_INT);
1359 spin_lock_irqsave(&ioapic_lock, flags);
1360 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1361 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1362 spin_unlock_irqrestore(&ioapic_lock, flags);
1363 clear_IO_APIC_pin(apic, pin);
1365 memset(&entry1, 0, sizeof(entry1));
1367 entry1.dest_mode = 0; /* physical delivery */
1368 entry1.mask = 0; /* unmask IRQ now */
1369 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1370 entry1.delivery_mode = dest_ExtINT;
1371 entry1.polarity = entry0.polarity;
1375 spin_lock_irqsave(&ioapic_lock, flags);
1376 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1377 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1378 spin_unlock_irqrestore(&ioapic_lock, flags);
1380 save_control = CMOS_READ(RTC_CONTROL);
1381 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1382 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1384 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1389 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1393 CMOS_WRITE(save_control, RTC_CONTROL);
1394 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1395 clear_IO_APIC_pin(apic, pin);
1397 spin_lock_irqsave(&ioapic_lock, flags);
1398 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1399 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1400 spin_unlock_irqrestore(&ioapic_lock, flags);
1403 int timer_uses_ioapic_pin_0;
1406 * This code may look a bit paranoid, but it's supposed to cooperate with
1407 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1408 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1409 * fanatically on his truly buggy board.
1411 * FIXME: really need to revamp this for modern platforms only.
1413 static inline void check_timer(void)
1415 int apic1, pin1, apic2, pin2;
1419 * get/set the timer IRQ vector:
1421 disable_8259A_irq(0);
1422 vector = assign_irq_vector(0);
1423 set_intr_gate(vector, interrupt[0]);
1426 * Subtle, code in do_timer_interrupt() expects an AEOI
1427 * mode for the 8259A whenever interrupts are routed
1428 * through I/O APICs. Also IRQ0 has to be enabled in
1429 * the 8259A which implies the virtual wire has to be
1430 * disabled in the local APIC.
1432 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1434 if (timer_over_8254 > 0)
1435 enable_8259A_irq(0);
1437 pin1 = find_isa_irq_pin(0, mp_INT);
1438 apic1 = find_isa_irq_apic(0, mp_INT);
1439 pin2 = ioapic_i8259.pin;
1440 apic2 = ioapic_i8259.apic;
1443 timer_uses_ioapic_pin_0 = 1;
1445 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1446 vector, apic1, pin1, apic2, pin2);
1450 * Ok, does IRQ0 through the IOAPIC work?
1452 unmask_IO_APIC_irq(0);
1453 if (!no_timer_check && timer_irq_works()) {
1454 nmi_watchdog_default();
1455 if (nmi_watchdog == NMI_IO_APIC) {
1456 disable_8259A_irq(0);
1458 enable_8259A_irq(0);
1460 if (disable_timer_pin_1 > 0)
1461 clear_IO_APIC_pin(0, pin1);
1464 clear_IO_APIC_pin(apic1, pin1);
1465 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1466 "connected to IO-APIC\n");
1469 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1470 "through the 8259A ... ");
1472 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1475 * legacy devices should be connected to IO APIC #0
1477 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1478 if (timer_irq_works()) {
1479 apic_printk(APIC_VERBOSE," works.\n");
1480 nmi_watchdog_default();
1481 if (nmi_watchdog == NMI_IO_APIC) {
1487 * Cleanup, just in case ...
1489 clear_IO_APIC_pin(apic2, pin2);
1491 apic_printk(APIC_VERBOSE," failed.\n");
1493 if (nmi_watchdog == NMI_IO_APIC) {
1494 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1498 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1500 disable_8259A_irq(0);
1501 irq_desc[0].chip = &lapic_irq_type;
1502 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1503 enable_8259A_irq(0);
1505 if (timer_irq_works()) {
1506 apic_printk(APIC_VERBOSE," works.\n");
1509 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1510 apic_printk(APIC_VERBOSE," failed.\n");
1512 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1516 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1518 unlock_ExtINT_logic();
1520 if (timer_irq_works()) {
1521 apic_printk(APIC_VERBOSE," works.\n");
1524 apic_printk(APIC_VERBOSE," failed :(.\n");
1525 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1528 static int __init notimercheck(char *s)
1533 __setup("no_timer_check", notimercheck);
1537 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1538 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1539 * Linux doesn't really care, as it's not actually used
1540 * for any interrupt handling anyway.
1542 #define PIC_IRQS (1<<2)
1544 void __init setup_IO_APIC(void)
1549 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1551 io_apic_irqs = ~PIC_IRQS;
1553 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1556 setup_IO_APIC_irqs();
1557 init_IO_APIC_traps();
1563 struct sysfs_ioapic_data {
1564 struct sys_device dev;
1565 struct IO_APIC_route_entry entry[0];
1567 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1569 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1571 struct IO_APIC_route_entry *entry;
1572 struct sysfs_ioapic_data *data;
1575 data = container_of(dev, struct sysfs_ioapic_data, dev);
1576 entry = data->entry;
1577 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1578 *entry = ioapic_read_entry(dev->id, i);
1583 static int ioapic_resume(struct sys_device *dev)
1585 struct IO_APIC_route_entry *entry;
1586 struct sysfs_ioapic_data *data;
1587 unsigned long flags;
1588 union IO_APIC_reg_00 reg_00;
1591 data = container_of(dev, struct sysfs_ioapic_data, dev);
1592 entry = data->entry;
1594 spin_lock_irqsave(&ioapic_lock, flags);
1595 reg_00.raw = io_apic_read(dev->id, 0);
1596 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1597 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1598 io_apic_write(dev->id, 0, reg_00.raw);
1600 spin_unlock_irqrestore(&ioapic_lock, flags);
1601 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1602 ioapic_write_entry(dev->id, i, entry[i]);
1607 static struct sysdev_class ioapic_sysdev_class = {
1608 set_kset_name("ioapic"),
1609 .suspend = ioapic_suspend,
1610 .resume = ioapic_resume,
1613 static int __init ioapic_init_sysfs(void)
1615 struct sys_device * dev;
1616 int i, size, error = 0;
1618 error = sysdev_class_register(&ioapic_sysdev_class);
1622 for (i = 0; i < nr_ioapics; i++ ) {
1623 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1624 * sizeof(struct IO_APIC_route_entry);
1625 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1626 if (!mp_ioapic_data[i]) {
1627 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1630 memset(mp_ioapic_data[i], 0, size);
1631 dev = &mp_ioapic_data[i]->dev;
1633 dev->cls = &ioapic_sysdev_class;
1634 error = sysdev_register(dev);
1636 kfree(mp_ioapic_data[i]);
1637 mp_ioapic_data[i] = NULL;
1638 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1646 device_initcall(ioapic_init_sysfs);
1649 * Dynamic irq allocate and deallocation
1651 int create_irq(void)
1653 /* Allocate an unused irq */
1657 unsigned long flags;
1660 spin_lock_irqsave(&vector_lock, flags);
1661 for (new = (NR_IRQS - 1); new >= 0; new--) {
1662 if (platform_legacy_irq(new))
1664 if (irq_vector[new] != 0)
1666 vector = __assign_irq_vector(new);
1667 if (likely(vector > 0))
1671 spin_unlock_irqrestore(&vector_lock, flags);
1674 set_intr_gate(vector, interrupt[irq]);
1675 dynamic_irq_init(irq);
1680 void destroy_irq(unsigned int irq)
1682 unsigned long flags;
1684 dynamic_irq_cleanup(irq);
1686 spin_lock_irqsave(&vector_lock, flags);
1687 irq_vector[irq] = 0;
1688 spin_unlock_irqrestore(&vector_lock, flags);
1692 * MSI mesage composition
1694 #ifdef CONFIG_PCI_MSI
1695 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1697 /* For now always this code always uses physical delivery
1703 vector = assign_irq_vector(irq);
1708 cpu_set(first_cpu(cpu_online_map), tmp);
1709 dest = cpu_mask_to_apicid(tmp);
1711 msg->address_hi = MSI_ADDR_BASE_HI;
1714 ((INT_DEST_MODE == 0) ?
1715 MSI_ADDR_DEST_MODE_PHYSICAL:
1716 MSI_ADDR_DEST_MODE_LOGICAL) |
1717 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1718 MSI_ADDR_REDIRECTION_CPU:
1719 MSI_ADDR_REDIRECTION_LOWPRI) |
1720 MSI_ADDR_DEST_ID(dest);
1723 MSI_DATA_TRIGGER_EDGE |
1724 MSI_DATA_LEVEL_ASSERT |
1725 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1726 MSI_DATA_DELIVERY_FIXED:
1727 MSI_DATA_DELIVERY_LOWPRI) |
1728 MSI_DATA_VECTOR(vector);
1733 static void msi_msg_teardown(unsigned int irq)
1738 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
1743 vector = assign_irq_vector(irq);
1745 dest = cpu_mask_to_apicid(mask);
1747 msg->data &= ~MSI_DATA_VECTOR_MASK;
1748 msg->data |= MSI_DATA_VECTOR(vector);
1749 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1750 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
1754 struct msi_ops arch_msi_ops = {
1755 .needs_64bit_address = 0,
1756 .setup = msi_msg_setup,
1757 .teardown = msi_msg_teardown,
1758 .target = msi_msg_set_affinity,
1763 /* --------------------------------------------------------------------------
1764 ACPI-based IOAPIC Configuration
1765 -------------------------------------------------------------------------- */
1769 #define IO_APIC_MAX_ID 0xFE
1771 int __init io_apic_get_redir_entries (int ioapic)
1773 union IO_APIC_reg_01 reg_01;
1774 unsigned long flags;
1776 spin_lock_irqsave(&ioapic_lock, flags);
1777 reg_01.raw = io_apic_read(ioapic, 1);
1778 spin_unlock_irqrestore(&ioapic_lock, flags);
1780 return reg_01.bits.entries;
1784 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1786 struct IO_APIC_route_entry entry;
1787 unsigned long flags;
1789 if (!IO_APIC_IRQ(irq)) {
1790 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1796 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1797 * Note that we mask (disable) IRQs now -- these get enabled when the
1798 * corresponding device driver registers for this IRQ.
1801 memset(&entry,0,sizeof(entry));
1803 entry.delivery_mode = INT_DELIVERY_MODE;
1804 entry.dest_mode = INT_DEST_MODE;
1805 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1806 entry.trigger = triggering;
1807 entry.polarity = polarity;
1808 entry.mask = 1; /* Disabled (masked) */
1810 irq = gsi_irq_sharing(irq);
1812 * IRQs < 16 are already in the irq_2_pin[] map
1815 add_pin_to_irq(irq, ioapic, pin);
1817 entry.vector = assign_irq_vector(irq);
1819 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1820 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1821 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1822 triggering, polarity);
1824 ioapic_register_intr(irq, entry.vector, triggering);
1826 if (!ioapic && (irq < 16))
1827 disable_8259A_irq(irq);
1829 ioapic_write_entry(ioapic, pin, entry);
1831 spin_lock_irqsave(&ioapic_lock, flags);
1832 set_native_irq_info(irq, TARGET_CPUS);
1833 spin_unlock_irqrestore(&ioapic_lock, flags);
1838 #endif /* CONFIG_ACPI */
1842 * This function currently is only a helper for the i386 smp boot process where
1843 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1844 * so mask in all cases should simply be TARGET_CPUS
1847 void __init setup_ioapic_dest(void)
1849 int pin, ioapic, irq, irq_entry;
1851 if (skip_ioapic_setup == 1)
1854 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1855 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1856 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1857 if (irq_entry == -1)
1859 irq = pin_2_irq(irq_entry, ioapic, pin);
1860 set_ioapic_affinity_irq(irq, TARGET_CPUS);