2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
19 #include <linux/sort.h>
21 #include <asm/pci_x86.h>
24 #define PREFIX "PCI: "
26 /* Indicate if the mmcfg resources have been placed into the resource table. */
27 static int __initdata pci_mmcfg_resources_inserted;
29 static __init void free_all_mmcfg(void)
31 pci_mmcfg_arch_free();
32 pci_mmcfg_config_num = 0;
33 kfree(pci_mmcfg_config);
34 pci_mmcfg_config = NULL;
37 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
40 struct pci_mmcfg_region *new;
41 int new_num = pci_mmcfg_config_num + 1;
42 int i = pci_mmcfg_config_num;
47 new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
51 if (pci_mmcfg_config) {
52 memcpy(new, pci_mmcfg_config,
53 sizeof(pci_mmcfg_config[0]) * new_num);
54 kfree(pci_mmcfg_config);
56 pci_mmcfg_config = new;
58 pci_mmcfg_config_num++;
59 pci_mmcfg_config[i].address = addr;
60 pci_mmcfg_config[i].pci_segment = segment;
61 pci_mmcfg_config[i].start_bus_number = start;
62 pci_mmcfg_config[i].end_bus_number = end;
64 return &pci_mmcfg_config[i];
67 static const char __init *pci_mmcfg_e7520(void)
70 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
73 if (win == 0x0000 || win == 0xf000)
76 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
79 return "Intel Corporation E7520 Memory Controller Hub";
82 static const char __init *pci_mmcfg_intel_945(void)
84 u32 pciexbar, mask = 0, len = 0;
86 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
93 switch ((pciexbar >> 1) & 3) {
110 /* Errata #2, things break when not aligned on a 256Mb boundary */
111 /* Can only happen in 64M/128M mode */
113 if ((pciexbar & mask) & 0x0fffffffU)
116 /* Don't hit the APIC registers and their friends */
117 if ((pciexbar & mask) >= 0xf0000000U)
120 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
123 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
126 static const char __init *pci_mmcfg_amd_fam10h(void)
128 u32 low, high, address;
131 unsigned segnbits = 0, busnbits, end_bus;
133 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
136 address = MSR_FAM10H_MMIO_CONF_BASE;
137 if (rdmsr_safe(address, &low, &high))
144 /* mmconfig is not enable */
145 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
148 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
150 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
151 FAM10H_MMIO_CONF_BUSRANGE_MASK;
154 * only handle bus 0 ?
161 segnbits = busnbits - 8;
165 end_bus = (1 << busnbits) - 1;
166 for (i = 0; i < (1 << segnbits); i++)
167 if (pci_mmconfig_add(i, 0, end_bus,
168 base + (1<<28) * i) == NULL) {
173 return "AMD Family 10h NB";
176 static bool __initdata mcp55_checked;
177 static const char __init *pci_mmcfg_nvidia_mcp55(void)
180 int mcp55_mmconf_found = 0;
182 static const u32 extcfg_regnum = 0x90;
183 static const u32 extcfg_regsize = 4;
184 static const u32 extcfg_enable_mask = 1<<31;
185 static const u32 extcfg_start_mask = 0xff<<16;
186 static const int extcfg_start_shift = 16;
187 static const u32 extcfg_size_mask = 0x3<<28;
188 static const int extcfg_size_shift = 28;
189 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
190 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
191 static const int extcfg_base_lshift = 25;
194 * do check if amd fam10h already took over
196 if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
199 mcp55_checked = true;
200 for (bus = 0; bus < 256; bus++) {
204 int start, size_index, end;
206 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
208 device = (l >> 16) & 0xffff;
210 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
213 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
214 extcfg_regsize, &extcfg);
216 if (!(extcfg & extcfg_enable_mask))
219 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
220 base = extcfg & extcfg_base_mask[size_index];
221 /* base could > 4G */
222 base <<= extcfg_base_lshift;
223 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
224 end = start + extcfg_sizebus[size_index] - 1;
225 if (pci_mmconfig_add(0, start, end, base) == NULL)
227 mcp55_mmconf_found++;
230 if (!mcp55_mmconf_found)
233 return "nVidia MCP55";
236 struct pci_mmcfg_hostbridge_probe {
241 const char *(*probe)(void);
244 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
245 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
246 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
247 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
248 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
249 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
250 0x1200, pci_mmcfg_amd_fam10h },
251 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
252 0x1200, pci_mmcfg_amd_fam10h },
253 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
254 0x0369, pci_mmcfg_nvidia_mcp55 },
257 static int __init cmp_mmcfg(const void *x1, const void *x2)
259 const typeof(pci_mmcfg_config[0]) *m1 = x1;
260 const typeof(pci_mmcfg_config[0]) *m2 = x2;
263 start1 = m1->start_bus_number;
264 start2 = m2->start_bus_number;
266 return start1 - start2;
269 static void __init pci_mmcfg_check_end_bus_number(void)
272 typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
274 /* sort them at first */
275 sort(pci_mmcfg_config, pci_mmcfg_config_num,
276 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
279 if (pci_mmcfg_config_num > 0) {
280 i = pci_mmcfg_config_num - 1;
281 cfg = &pci_mmcfg_config[i];
282 if (cfg->end_bus_number < cfg->start_bus_number)
283 cfg->end_bus_number = 255;
286 /* don't overlap please */
287 for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
288 cfg = &pci_mmcfg_config[i];
289 cfgx = &pci_mmcfg_config[i+1];
291 if (cfg->end_bus_number < cfg->start_bus_number)
292 cfg->end_bus_number = 255;
294 if (cfg->end_bus_number >= cfgx->start_bus_number)
295 cfg->end_bus_number = cfgx->start_bus_number - 1;
299 static int __init pci_mmcfg_check_hostbridge(void)
312 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
313 bus = pci_mmcfg_probes[i].bus;
314 devfn = pci_mmcfg_probes[i].devfn;
315 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
317 device = (l >> 16) & 0xffff;
320 if (pci_mmcfg_probes[i].vendor == vendor &&
321 pci_mmcfg_probes[i].device == device)
322 name = pci_mmcfg_probes[i].probe();
325 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
329 /* some end_bus_number is crazy, fix it */
330 pci_mmcfg_check_end_bus_number();
332 return pci_mmcfg_config_num != 0;
335 static void __init pci_mmcfg_insert_resources(void)
337 #define PCI_MMCFG_RESOURCE_NAME_LEN 24
339 struct resource *res;
343 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
344 pci_mmcfg_config_num, GFP_KERNEL);
346 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
350 names = (void *)&res[pci_mmcfg_config_num];
351 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
352 struct pci_mmcfg_region *cfg = &pci_mmcfg_config[i];
353 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
355 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
356 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
357 cfg->start_bus_number, cfg->end_bus_number);
358 res->start = cfg->address +
359 PCI_MMCFG_BUS_OFFSET(cfg->start_bus_number);
360 res->end = res->start + PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
361 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
362 insert_resource(&iomem_resource, res);
363 names += PCI_MMCFG_RESOURCE_NAME_LEN;
366 /* Mark that the resources have been inserted. */
367 pci_mmcfg_resources_inserted = 1;
370 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
373 struct resource *mcfg_res = data;
374 struct acpi_resource_address64 address;
377 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
378 struct acpi_resource_fixed_memory32 *fixmem32 =
379 &res->data.fixed_memory32;
382 if ((mcfg_res->start >= fixmem32->address) &&
383 (mcfg_res->end < (fixmem32->address +
384 fixmem32->address_length))) {
386 return AE_CTRL_TERMINATE;
389 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
390 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
393 status = acpi_resource_to_address64(res, &address);
394 if (ACPI_FAILURE(status) ||
395 (address.address_length <= 0) ||
396 (address.resource_type != ACPI_MEMORY_RANGE))
399 if ((mcfg_res->start >= address.minimum) &&
400 (mcfg_res->end < (address.minimum + address.address_length))) {
402 return AE_CTRL_TERMINATE;
407 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
408 void *context, void **rv)
410 struct resource *mcfg_res = context;
412 acpi_walk_resources(handle, METHOD_NAME__CRS,
413 check_mcfg_resource, context);
416 return AE_CTRL_TERMINATE;
421 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
423 struct resource mcfg_res;
425 mcfg_res.start = start;
426 mcfg_res.end = end - 1;
429 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
432 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
435 return mcfg_res.flags;
438 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
440 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
441 u64 addr, u64 size, int i,
442 typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
447 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
449 if (size < (16UL<<20))
453 if (size >= (16UL<<20) || size == old_size) {
455 "PCI: MCFG area at %Lx reserved in %s\n",
456 addr, with_e820?"E820":"ACPI motherboard resources");
459 if (old_size != size) {
460 /* update end_bus_number */
461 cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
462 printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
463 "segment %hu buses %u - %u\n",
464 i, (unsigned long)cfg->address, cfg->pci_segment,
465 (unsigned int)cfg->start_bus_number,
466 (unsigned int)cfg->end_bus_number);
473 static void __init pci_mmcfg_reject_broken(int early)
475 typeof(pci_mmcfg_config[0]) *cfg;
478 if (pci_mmcfg_config_num == 0)
481 for (i = 0; i < pci_mmcfg_config_num; i++) {
482 int num_buses, valid = 0;
485 cfg = &pci_mmcfg_config[i];
486 addr = cfg->address +
487 PCI_MMCFG_BUS_OFFSET(cfg->start_bus_number);
488 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
489 size = PCI_MMCFG_BUS_OFFSET(num_buses);
490 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
491 "segment %hu buses %u - %u\n",
492 i, (unsigned long)cfg->address, cfg->pci_segment,
493 (unsigned int)cfg->start_bus_number,
494 (unsigned int)cfg->end_bus_number);
496 if (!early && !acpi_disabled)
497 valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
503 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
504 " reserved in ACPI motherboard resources\n",
507 /* Don't try to do this check unless configuration
508 type 1 is available. how about type 2 ?*/
510 valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
519 printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
523 static int __initdata known_bridge;
525 /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */
526 struct pci_mmcfg_region *pci_mmcfg_config;
527 int pci_mmcfg_config_num;
529 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
530 struct acpi_mcfg_allocation *cfg)
534 if (cfg->address < 0xFFFFFFFF)
537 if (!strcmp(mcfg->header.oem_id, "SGI"))
540 if (mcfg->header.revision >= 1) {
541 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
546 printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx "
547 "is above 4GB, ignored\n", cfg->pci_segment,
548 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
552 static int __init pci_parse_mcfg(struct acpi_table_header *header)
554 struct acpi_table_mcfg *mcfg;
555 struct acpi_mcfg_allocation *cfg_table, *cfg;
562 mcfg = (struct acpi_table_mcfg *)header;
564 /* how many config structures do we have */
567 i = header->length - sizeof(struct acpi_table_mcfg);
568 while (i >= sizeof(struct acpi_mcfg_allocation)) {
570 i -= sizeof(struct acpi_mcfg_allocation);
573 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
577 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
578 for (i = 0; i < entries; i++) {
580 if (acpi_mcfg_check_entry(mcfg, cfg)) {
585 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
586 cfg->end_bus_number, cfg->address) == NULL) {
587 printk(KERN_WARNING PREFIX
588 "no memory for MCFG entries\n");
597 static void __init __pci_mmcfg_init(int early)
599 /* MMCONFIG disabled */
600 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
603 /* MMCONFIG already enabled */
604 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
607 /* for late to exit */
612 if (pci_mmcfg_check_hostbridge())
617 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
619 pci_mmcfg_reject_broken(early);
621 if (pci_mmcfg_config_num == 0)
624 if (pci_mmcfg_arch_init())
625 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
628 * Signal not to attempt to insert mmcfg resources because
629 * the architecture mmcfg setup could not initialize.
631 pci_mmcfg_resources_inserted = 1;
635 void __init pci_mmcfg_early_init(void)
640 void __init pci_mmcfg_late_init(void)
645 static int __init pci_mmcfg_late_insert_resources(void)
648 * If resources are already inserted or we are not using MMCONFIG,
649 * don't insert the resources.
651 if ((pci_mmcfg_resources_inserted == 1) ||
652 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
653 (pci_mmcfg_config_num == 0))
657 * Attempt to insert the mmcfg resources but not with the busy flag
658 * marked so it won't cause request errors when __request_region is
661 pci_mmcfg_insert_resources();
667 * Perform MMCONFIG resource insertion after PCI initialization to allow for
668 * misprogrammed MCFG tables that state larger sizes but actually conflict
669 * with other system resources.
671 late_initcall(pci_mmcfg_late_insert_resources);