3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf
15 #include <linux/oprofile.h>
16 #include <linux/device.h>
17 #include <linux/pci.h>
19 #include <asm/ptrace.h>
23 #include "op_x86_model.h"
24 #include "op_counter.h"
26 #define NUM_COUNTERS 4
27 #define NUM_CONTROLS 4
29 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
30 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
31 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
32 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
33 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
34 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
35 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
37 static unsigned long reset_value[NUM_COUNTERS];
39 #ifdef CONFIG_OPROFILE_IBS
41 /* IbsFetchCtl bits/masks */
42 #define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
43 #define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
44 #define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */
47 #define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */
48 #define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */
50 #define IBS_FETCH_SIZE 6
51 #define IBS_OP_SIZE 12
53 static int has_ibs; /* AMD Family10h and later */
55 struct op_ibs_config {
56 unsigned long op_enabled;
57 unsigned long fetch_enabled;
58 unsigned long max_cnt_fetch;
59 unsigned long max_cnt_op;
60 unsigned long rand_en;
61 unsigned long dispatched_ops;
64 static struct op_ibs_config ibs_config;
68 /* functions for op_amd_spec */
70 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
74 for (i = 0; i < NUM_COUNTERS; i++) {
75 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
76 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
78 msrs->counters[i].addr = 0;
81 for (i = 0; i < NUM_CONTROLS; i++) {
82 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
83 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
85 msrs->controls[i].addr = 0;
90 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
92 unsigned int low, high;
95 /* clear all counters */
96 for (i = 0 ; i < NUM_CONTROLS; ++i) {
97 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
99 rdmsr(msrs->controls[i].addr, low, high);
102 wrmsr(msrs->controls[i].addr, low, high);
105 /* avoid a false detection of ctr overflows in NMI handler */
106 for (i = 0; i < NUM_COUNTERS; ++i) {
107 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
109 wrmsr(msrs->counters[i].addr, -1, -1);
112 /* enable active counters */
113 for (i = 0; i < NUM_COUNTERS; ++i) {
114 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
115 reset_value[i] = counter_config[i].count;
117 wrmsr(msrs->counters[i].addr, -(unsigned int)counter_config[i].count, -1);
119 rdmsr(msrs->controls[i].addr, low, high);
122 CTRL_SET_ENABLE(low);
123 CTRL_SET_USR(low, counter_config[i].user);
124 CTRL_SET_KERN(low, counter_config[i].kernel);
125 CTRL_SET_UM(low, counter_config[i].unit_mask);
126 CTRL_SET_EVENT_LOW(low, counter_config[i].event);
127 CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
128 CTRL_SET_HOST_ONLY(high, 0);
129 CTRL_SET_GUEST_ONLY(high, 0);
131 wrmsr(msrs->controls[i].addr, low, high);
138 #ifdef CONFIG_OPROFILE_IBS
141 op_amd_handle_ibs(struct pt_regs * const regs,
142 struct op_msrs const * const msrs)
146 struct op_entry entry;
151 if (ibs_config.fetch_enabled) {
152 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
153 if (high & IBS_FETCH_HIGH_VALID_BIT) {
154 rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
155 oprofile_write_reserve(&entry, regs, msr,
156 IBS_FETCH_CODE, IBS_FETCH_SIZE);
157 oprofile_add_data(&entry, (u32)msr);
158 oprofile_add_data(&entry, (u32)(msr >> 32));
159 oprofile_add_data(&entry, low);
160 oprofile_add_data(&entry, high);
161 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
162 oprofile_add_data(&entry, (u32)msr);
163 oprofile_add_data(&entry, (u32)(msr >> 32));
164 oprofile_write_commit(&entry);
166 /* reenable the IRQ */
167 high &= ~IBS_FETCH_HIGH_VALID_BIT;
168 high |= IBS_FETCH_HIGH_ENABLE;
169 low &= IBS_FETCH_LOW_MAX_CNT_MASK;
170 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
174 if (ibs_config.op_enabled) {
175 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
176 if (low & IBS_OP_LOW_VALID_BIT) {
177 rdmsrl(MSR_AMD64_IBSOPRIP, msr);
178 oprofile_write_reserve(&entry, regs, msr,
179 IBS_OP_CODE, IBS_OP_SIZE);
180 oprofile_add_data(&entry, (u32)msr);
181 oprofile_add_data(&entry, (u32)(msr >> 32));
182 rdmsrl(MSR_AMD64_IBSOPDATA, msr);
183 oprofile_add_data(&entry, (u32)msr);
184 oprofile_add_data(&entry, (u32)(msr >> 32));
185 rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
186 oprofile_add_data(&entry, (u32)msr);
187 oprofile_add_data(&entry, (u32)(msr >> 32));
188 rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
189 oprofile_add_data(&entry, (u32)msr);
190 oprofile_add_data(&entry, (u32)(msr >> 32));
191 rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
192 oprofile_add_data(&entry, (u32)msr);
193 oprofile_add_data(&entry, (u32)(msr >> 32));
194 rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
195 oprofile_add_data(&entry, (u32)msr);
196 oprofile_add_data(&entry, (u32)(msr >> 32));
197 oprofile_write_commit(&entry);
199 /* reenable the IRQ */
201 low &= ~IBS_OP_LOW_VALID_BIT;
202 low |= IBS_OP_LOW_ENABLE;
203 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
210 static inline void op_amd_start_ibs(void)
212 unsigned int low, high;
213 if (has_ibs && ibs_config.fetch_enabled) {
214 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
215 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
216 + IBS_FETCH_HIGH_ENABLE;
217 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
220 if (has_ibs && ibs_config.op_enabled) {
221 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
222 + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
225 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
229 static void op_amd_stop_ibs(void)
231 unsigned int low, high;
232 if (has_ibs && ibs_config.fetch_enabled) {
233 /* clear max count and enable */
236 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
239 if (has_ibs && ibs_config.op_enabled) {
240 /* clear max count and enable */
243 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
249 static inline int op_amd_handle_ibs(struct pt_regs * const regs,
250 struct op_msrs const * const msrs) { }
251 static inline void op_amd_start_ibs(void) { }
252 static inline void op_amd_stop_ibs(void) { }
256 static int op_amd_check_ctrs(struct pt_regs * const regs,
257 struct op_msrs const * const msrs)
259 unsigned int low, high;
262 for (i = 0 ; i < NUM_COUNTERS; ++i) {
265 rdmsr(msrs->counters[i].addr, low, high);
266 if (CTR_OVERFLOWED(low)) {
267 oprofile_add_sample(regs, i);
268 wrmsr(msrs->counters[i].addr, -(unsigned int)reset_value[i], -1);
272 op_amd_handle_ibs(regs, msrs);
274 /* See op_model_ppro.c */
278 static void op_amd_start(struct op_msrs const * const msrs)
280 unsigned int low, high;
282 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
283 if (reset_value[i]) {
284 rdmsr(msrs->controls[i].addr, low, high);
285 CTRL_SET_ACTIVE(low);
286 wrmsr(msrs->controls[i].addr, low, high);
293 static void op_amd_stop(struct op_msrs const * const msrs)
295 unsigned int low, high;
299 * Subtle: stop on all counters to avoid race with setting our
302 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
305 rdmsr(msrs->controls[i].addr, low, high);
306 CTRL_SET_INACTIVE(low);
307 wrmsr(msrs->controls[i].addr, low, high);
313 static void op_amd_shutdown(struct op_msrs const * const msrs)
317 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
318 if (CTR_IS_RESERVED(msrs, i))
319 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
321 for (i = 0 ; i < NUM_CONTROLS ; ++i) {
322 if (CTRL_IS_RESERVED(msrs, i))
323 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
327 #ifdef CONFIG_OPROFILE_IBS
329 static u8 ibs_eilvt_off;
331 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
333 ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
336 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
338 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
341 static int init_ibs_nmi(void)
343 #define IBSCTL_LVTOFFSETVAL (1 << 8)
345 struct pci_dev *cpu_cfg;
350 on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
355 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
356 PCI_DEVICE_ID_AMD_10H_NB_MISC,
361 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
362 | IBSCTL_LVTOFFSETVAL);
363 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
364 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
365 pci_dev_put(cpu_cfg);
366 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
367 "IBSCTL = 0x%08x", value);
373 printk(KERN_DEBUG "No CPU node configured for IBS");
379 /* Works only for 64bit with proper numa implementation. */
380 if (nodes != num_possible_nodes()) {
381 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
382 "found: %d, expected %d",
383 nodes, num_possible_nodes());
390 /* uninitialize the APIC for the IBS interrupts if needed */
391 static void clear_ibs_nmi(void)
394 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
397 /* initialize the APIC for the IBS interrupts if available */
398 static void ibs_init(void)
400 has_ibs = boot_cpu_has(X86_FEATURE_IBS);
405 if (init_ibs_nmi()) {
410 printk(KERN_INFO "oprofile: AMD IBS detected\n");
413 static void ibs_exit(void)
421 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
423 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
428 /* architecture specific files */
429 if (create_arch_files)
430 ret = create_arch_files(sb, root);
438 /* model specific files */
440 /* setup some reasonable defaults */
441 ibs_config.max_cnt_fetch = 250000;
442 ibs_config.fetch_enabled = 0;
443 ibs_config.max_cnt_op = 250000;
444 ibs_config.op_enabled = 0;
445 ibs_config.dispatched_ops = 1;
447 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
448 oprofilefs_create_ulong(sb, dir, "enable",
449 &ibs_config.fetch_enabled);
450 oprofilefs_create_ulong(sb, dir, "max_count",
451 &ibs_config.max_cnt_fetch);
452 oprofilefs_create_ulong(sb, dir, "rand_enable",
453 &ibs_config.rand_en);
455 dir = oprofilefs_mkdir(sb, root, "ibs_op");
456 oprofilefs_create_ulong(sb, dir, "enable",
457 &ibs_config.op_enabled);
458 oprofilefs_create_ulong(sb, dir, "max_count",
459 &ibs_config.max_cnt_op);
460 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
461 &ibs_config.dispatched_ops);
466 static int op_amd_init(struct oprofile_operations *ops)
469 create_arch_files = ops->create_files;
470 ops->create_files = setup_ibs_files;
474 static void op_amd_exit(void)
483 static int op_amd_init(struct oprofile_operations *ops)
488 static void op_amd_exit(void) {}
490 #endif /* CONFIG_OPROFILE_IBS */
492 struct op_x86_model_spec const op_amd_spec = {
495 .num_counters = NUM_COUNTERS,
496 .num_controls = NUM_CONTROLS,
497 .fill_in_addresses = &op_amd_fill_in_addresses,
498 .setup_ctrs = &op_amd_setup_ctrs,
499 .check_ctrs = &op_amd_check_ctrs,
500 .start = &op_amd_start,
501 .stop = &op_amd_stop,
502 .shutdown = &op_amd_shutdown