3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf <barry.kasindorf@amd.com>
13 * @author Jason Yeh <jason.yeh@amd.com>
14 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
22 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
29 #include "op_x86_model.h"
30 #include "op_counter.h"
32 #define NUM_COUNTERS 4
33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
34 #define NUM_VIRT_COUNTERS 32
36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
39 #define OP_EVENT_MASK 0x0FFF
40 #define OP_CTR_OVERFLOW (1ULL<<31)
42 #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
46 #define IBS_FETCH_SIZE 6
47 #define IBS_OP_SIZE 12
51 struct op_ibs_config {
52 unsigned long op_enabled;
53 unsigned long fetch_enabled;
54 unsigned long max_cnt_fetch;
55 unsigned long max_cnt_op;
56 unsigned long rand_en;
57 unsigned long dispatched_ops;
60 static struct op_ibs_config ibs_config;
61 static u64 ibs_op_ctl;
64 * IBS cpuid feature detection
67 #define IBS_CPUID_FEATURES 0x8000001b
70 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
71 * bit 0 is used to indicate the existence of IBS.
73 #define IBS_CAPS_AVAIL (1LL<<0)
74 #define IBS_CAPS_RDWROPCNT (1LL<<3)
75 #define IBS_CAPS_OPCNT (1LL<<4)
78 * IBS randomization macros
80 #define IBS_RANDOM_BITS 12
81 #define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
82 #define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
84 static u32 get_ibs_caps(void)
87 unsigned int max_level;
89 if (!boot_cpu_has(X86_FEATURE_IBS))
92 /* check IBS cpuid feature flags */
93 max_level = cpuid_eax(0x80000000);
94 if (max_level < IBS_CPUID_FEATURES)
95 return IBS_CAPS_AVAIL;
97 ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
98 if (!(ibs_caps & IBS_CAPS_AVAIL))
99 /* cpuid flags not valid */
100 return IBS_CAPS_AVAIL;
105 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
107 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
108 struct op_msrs const * const msrs)
113 /* enable active counters */
114 for (i = 0; i < NUM_COUNTERS; ++i) {
115 int virt = op_x86_phys_to_virt(i);
116 if (!reset_value[virt])
118 rdmsrl(msrs->controls[i].addr, val);
119 val &= model->reserved;
120 val |= op_x86_get_ctrl(model, &counter_config[virt]);
121 wrmsrl(msrs->controls[i].addr, val);
127 /* functions for op_amd_spec */
129 static void op_amd_shutdown(struct op_msrs const * const msrs)
133 for (i = 0; i < NUM_COUNTERS; ++i) {
134 if (!msrs->counters[i].addr)
136 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
137 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
141 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
145 for (i = 0; i < NUM_COUNTERS; i++) {
146 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
148 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
149 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
152 /* both registers must be reserved */
153 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
154 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
157 if (!counter_config[i].enabled)
159 op_x86_warn_reserved(i);
160 op_amd_shutdown(msrs);
167 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
168 struct op_msrs const * const msrs)
173 /* setup reset_value */
174 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
175 if (counter_config[i].enabled
176 && msrs->counters[op_x86_virt_to_phys(i)].addr)
177 reset_value[i] = counter_config[i].count;
182 /* clear all counters */
183 for (i = 0; i < NUM_COUNTERS; ++i) {
184 if (!msrs->controls[i].addr)
186 rdmsrl(msrs->controls[i].addr, val);
187 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
188 op_x86_warn_in_use(i);
189 val &= model->reserved;
190 wrmsrl(msrs->controls[i].addr, val);
192 * avoid a false detection of ctr overflows in NMI
195 wrmsrl(msrs->counters[i].addr, -1LL);
198 /* enable active counters */
199 for (i = 0; i < NUM_COUNTERS; ++i) {
200 int virt = op_x86_phys_to_virt(i);
201 if (!reset_value[virt])
204 /* setup counter registers */
205 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
207 /* setup control registers */
208 rdmsrl(msrs->controls[i].addr, val);
209 val &= model->reserved;
210 val |= op_x86_get_ctrl(model, &counter_config[virt]);
211 wrmsrl(msrs->controls[i].addr, val);
216 * 16-bit Linear Feedback Shift Register (LFSR)
219 * Feedback polynomial = X + X + X + X + 1
221 static unsigned int lfsr_random(void)
223 static unsigned int lfsr_value = 0xF00D;
226 /* Compute next bit to shift in */
227 bit = ((lfsr_value >> 0) ^
230 (lfsr_value >> 5)) & 0x0001;
232 /* Advance to next register value */
233 lfsr_value = (lfsr_value >> 1) | (bit << 15);
239 * IBS software randomization
241 * The IBS periodic op counter is randomized in software. The lower 12
242 * bits of the 20 bit counter are randomized. IbsOpCurCnt is
243 * initialized with a 12 bit random value.
245 static inline u64 op_amd_randomize_ibs_op(u64 val)
247 unsigned int random = lfsr_random();
249 if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
251 * Work around if the hw can not write to IbsOpCurCnt
253 * Randomize the lower 8 bits of the 16 bit
254 * IbsOpMaxCnt [15:0] value in the range of -128 to
255 * +127 by adding/subtracting an offset to the
256 * maximum count (IbsOpMaxCnt).
258 * To avoid over or underflows and protect upper bits
259 * starting at bit 16, the initial value for
260 * IbsOpMaxCnt must fit in the range from 0x0081 to
263 val += (s8)(random >> 4);
265 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
271 op_amd_handle_ibs(struct pt_regs * const regs,
272 struct op_msrs const * const msrs)
275 struct op_entry entry;
280 if (ibs_config.fetch_enabled) {
281 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
282 if (ctl & IBS_FETCH_VAL) {
283 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
284 oprofile_write_reserve(&entry, regs, val,
285 IBS_FETCH_CODE, IBS_FETCH_SIZE);
286 oprofile_add_data64(&entry, val);
287 oprofile_add_data64(&entry, ctl);
288 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
289 oprofile_add_data64(&entry, val);
290 oprofile_write_commit(&entry);
292 /* reenable the IRQ */
293 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
294 ctl |= IBS_FETCH_ENABLE;
295 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
299 if (ibs_config.op_enabled) {
300 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
301 if (ctl & IBS_OP_VAL) {
302 rdmsrl(MSR_AMD64_IBSOPRIP, val);
303 oprofile_write_reserve(&entry, regs, val,
304 IBS_OP_CODE, IBS_OP_SIZE);
305 oprofile_add_data64(&entry, val);
306 rdmsrl(MSR_AMD64_IBSOPDATA, val);
307 oprofile_add_data64(&entry, val);
308 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
309 oprofile_add_data64(&entry, val);
310 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
311 oprofile_add_data64(&entry, val);
312 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
313 oprofile_add_data64(&entry, val);
314 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
315 oprofile_add_data64(&entry, val);
316 oprofile_write_commit(&entry);
318 /* reenable the IRQ */
319 ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
320 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
325 static inline void op_amd_start_ibs(void)
332 if (ibs_config.fetch_enabled) {
333 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
334 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
335 val |= IBS_FETCH_ENABLE;
336 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
339 if (ibs_config.op_enabled) {
340 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
341 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
343 * IbsOpCurCnt not supported. See
344 * op_amd_randomize_ibs_op() for details.
346 ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
349 * The start value is randomized with a
350 * positive offset, we need to compensate it
351 * with the half of the randomized range. Also
354 ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
357 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
358 ibs_op_ctl |= IBS_OP_CNT_CTL;
359 ibs_op_ctl |= IBS_OP_ENABLE;
360 val = op_amd_randomize_ibs_op(ibs_op_ctl);
361 wrmsrl(MSR_AMD64_IBSOPCTL, val);
365 static void op_amd_stop_ibs(void)
370 if (ibs_config.fetch_enabled)
371 /* clear max count and enable */
372 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
374 if (ibs_config.op_enabled)
375 /* clear max count and enable */
376 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
379 static int op_amd_check_ctrs(struct pt_regs * const regs,
380 struct op_msrs const * const msrs)
385 for (i = 0; i < NUM_COUNTERS; ++i) {
386 int virt = op_x86_phys_to_virt(i);
387 if (!reset_value[virt])
389 rdmsrl(msrs->counters[i].addr, val);
390 /* bit is clear if overflowed: */
391 if (val & OP_CTR_OVERFLOW)
393 oprofile_add_sample(regs, virt);
394 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
397 op_amd_handle_ibs(regs, msrs);
399 /* See op_model_ppro.c */
403 static void op_amd_start(struct op_msrs const * const msrs)
408 for (i = 0; i < NUM_COUNTERS; ++i) {
409 if (!reset_value[op_x86_phys_to_virt(i)])
411 rdmsrl(msrs->controls[i].addr, val);
412 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
413 wrmsrl(msrs->controls[i].addr, val);
419 static void op_amd_stop(struct op_msrs const * const msrs)
425 * Subtle: stop on all counters to avoid race with setting our
428 for (i = 0; i < NUM_COUNTERS; ++i) {
429 if (!reset_value[op_x86_phys_to_virt(i)])
431 rdmsrl(msrs->controls[i].addr, val);
432 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
433 wrmsrl(msrs->controls[i].addr, val);
439 static u8 ibs_eilvt_off;
441 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
443 ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
446 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
448 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
451 static int init_ibs_nmi(void)
453 #define IBSCTL_LVTOFFSETVAL (1 << 8)
455 struct pci_dev *cpu_cfg;
460 on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
465 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
466 PCI_DEVICE_ID_AMD_10H_NB_MISC,
471 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
472 | IBSCTL_LVTOFFSETVAL);
473 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
474 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
475 pci_dev_put(cpu_cfg);
476 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
477 "IBSCTL = 0x%08x", value);
483 printk(KERN_DEBUG "No CPU node configured for IBS");
490 /* uninitialize the APIC for the IBS interrupts if needed */
491 static void clear_ibs_nmi(void)
494 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
497 /* initialize the APIC for the IBS interrupts if available */
498 static void ibs_init(void)
500 ibs_caps = get_ibs_caps();
505 if (init_ibs_nmi()) {
510 printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
514 static void ibs_exit(void)
522 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
524 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
529 /* architecture specific files */
530 if (create_arch_files)
531 ret = create_arch_files(sb, root);
539 /* model specific files */
541 /* setup some reasonable defaults */
542 ibs_config.max_cnt_fetch = 250000;
543 ibs_config.fetch_enabled = 0;
544 ibs_config.max_cnt_op = 250000;
545 ibs_config.op_enabled = 0;
546 ibs_config.dispatched_ops = 0;
548 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
549 oprofilefs_create_ulong(sb, dir, "enable",
550 &ibs_config.fetch_enabled);
551 oprofilefs_create_ulong(sb, dir, "max_count",
552 &ibs_config.max_cnt_fetch);
553 oprofilefs_create_ulong(sb, dir, "rand_enable",
554 &ibs_config.rand_en);
556 dir = oprofilefs_mkdir(sb, root, "ibs_op");
557 oprofilefs_create_ulong(sb, dir, "enable",
558 &ibs_config.op_enabled);
559 oprofilefs_create_ulong(sb, dir, "max_count",
560 &ibs_config.max_cnt_op);
561 if (ibs_caps & IBS_CAPS_OPCNT)
562 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
563 &ibs_config.dispatched_ops);
568 static int op_amd_init(struct oprofile_operations *ops)
571 create_arch_files = ops->create_files;
572 ops->create_files = setup_ibs_files;
576 static void op_amd_exit(void)
581 struct op_x86_model_spec op_amd_spec = {
582 .num_counters = NUM_COUNTERS,
583 .num_controls = NUM_COUNTERS,
584 .num_virt_counters = NUM_VIRT_COUNTERS,
585 .reserved = MSR_AMD_EVENTSEL_RESERVED,
586 .event_mask = OP_EVENT_MASK,
589 .fill_in_addresses = &op_amd_fill_in_addresses,
590 .setup_ctrs = &op_amd_setup_ctrs,
591 .check_ctrs = &op_amd_check_ctrs,
592 .start = &op_amd_start,
593 .stop = &op_amd_stop,
594 .shutdown = &op_amd_shutdown,
595 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
596 .switch_ctrl = &op_mux_switch_ctrl,