4 * @remark Copyright 2002-2009 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
8 * @author Robert Richter <robert.richter@amd.com>
9 * @author Barry Kasindorf <barry.kasindorf@amd.com>
10 * @author Jason Yeh <jason.yeh@amd.com>
11 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
14 #include <linux/init.h>
15 #include <linux/notifier.h>
16 #include <linux/smp.h>
17 #include <linux/oprofile.h>
18 #include <linux/sysdev.h>
19 #include <linux/slab.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kdebug.h>
22 #include <linux/cpu.h>
27 #include "op_counter.h"
28 #include "op_x86_model.h"
30 static struct op_x86_model_spec *model;
31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
34 /* 0 == registered but off, 1 == registered and on */
35 static int nmi_enabled = 0;
38 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
39 extern atomic_t multiplex_counter;
42 struct op_counter_config counter_config[OP_MAX_COUNTER];
44 /* common functions */
46 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
47 struct op_counter_config *counter_config)
50 u16 event = (u16)counter_config->event;
52 val |= ARCH_PERFMON_EVENTSEL_INT;
53 val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
54 val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
55 val |= (counter_config->unit_mask & 0xFF) << 8;
56 event &= model->event_mask ? model->event_mask : 0xFF;
58 val |= (event & 0x0F00) << 24;
64 static int profile_exceptions_notify(struct notifier_block *self,
65 unsigned long val, void *data)
67 struct die_args *args = (struct die_args *)data;
68 int ret = NOTIFY_DONE;
69 int cpu = smp_processor_id();
74 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
83 static void nmi_cpu_save_registers(struct op_msrs *msrs)
85 struct op_msr *counters = msrs->counters;
86 struct op_msr *controls = msrs->controls;
89 for (i = 0; i < model->num_counters; ++i) {
91 rdmsrl(counters[i].addr, counters[i].saved);
94 for (i = 0; i < model->num_controls; ++i) {
96 rdmsrl(controls[i].addr, controls[i].saved);
100 static void nmi_cpu_start(void *dummy)
102 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
106 static int nmi_start(void)
108 on_each_cpu(nmi_cpu_start, NULL, 1);
112 static void nmi_cpu_stop(void *dummy)
114 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
118 static void nmi_stop(void)
120 on_each_cpu(nmi_cpu_stop, NULL, 1);
123 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
125 static DEFINE_PER_CPU(int, switch_index);
127 static inline int has_mux(void)
129 return !!model->switch_ctrl;
132 inline int op_x86_phys_to_virt(int phys)
134 return __get_cpu_var(switch_index) + phys;
137 static void nmi_shutdown_mux(void)
144 for_each_possible_cpu(i) {
145 kfree(per_cpu(cpu_msrs, i).multiplex);
146 per_cpu(cpu_msrs, i).multiplex = NULL;
147 per_cpu(switch_index, i) = 0;
151 static int nmi_setup_mux(void)
153 size_t multiplex_size =
154 sizeof(struct op_msr) * model->num_virt_counters;
160 for_each_possible_cpu(i) {
161 per_cpu(cpu_msrs, i).multiplex =
162 kmalloc(multiplex_size, GFP_KERNEL);
163 if (!per_cpu(cpu_msrs, i).multiplex)
170 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
173 struct op_msr *multiplex = msrs->multiplex;
178 for (i = 0; i < model->num_virt_counters; ++i) {
179 if (counter_config[i].enabled) {
180 multiplex[i].saved = -(u64)counter_config[i].count;
182 multiplex[i].addr = 0;
183 multiplex[i].saved = 0;
187 per_cpu(switch_index, cpu) = 0;
190 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
192 struct op_msr *multiplex = msrs->multiplex;
195 for (i = 0; i < model->num_counters; ++i) {
196 int virt = op_x86_phys_to_virt(i);
197 if (multiplex[virt].addr)
198 rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
202 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
204 struct op_msr *multiplex = msrs->multiplex;
207 for (i = 0; i < model->num_counters; ++i) {
208 int virt = op_x86_phys_to_virt(i);
209 if (multiplex[virt].addr)
210 wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
214 static void nmi_cpu_switch(void *dummy)
216 int cpu = smp_processor_id();
217 int si = per_cpu(switch_index, cpu);
218 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
221 nmi_cpu_save_mpx_registers(msrs);
223 /* move to next set */
224 si += model->num_counters;
225 if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
226 per_cpu(switch_index, cpu) = 0;
228 per_cpu(switch_index, cpu) = si;
230 model->switch_ctrl(model, msrs);
231 nmi_cpu_restore_mpx_registers(msrs);
238 * Quick check to see if multiplexing is necessary.
239 * The check should be sufficient since counters are used
242 static int nmi_multiplex_on(void)
244 return counter_config[model->num_counters].count ? 0 : -EINVAL;
247 static int nmi_switch_event(void)
250 return -ENOSYS; /* not implemented */
251 if (nmi_multiplex_on() < 0)
252 return -EINVAL; /* not necessary */
254 on_each_cpu(nmi_cpu_switch, NULL, 1);
256 atomic_inc(&multiplex_counter);
261 static inline void mux_init(struct oprofile_operations *ops)
264 ops->switch_events = nmi_switch_event;
269 inline int op_x86_phys_to_virt(int phys) { return phys; }
270 static inline void nmi_shutdown_mux(void) { }
271 static inline int nmi_setup_mux(void) { return 1; }
273 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
274 static inline void mux_init(struct oprofile_operations *ops) { }
278 static void free_msrs(void)
281 for_each_possible_cpu(i) {
282 kfree(per_cpu(cpu_msrs, i).counters);
283 per_cpu(cpu_msrs, i).counters = NULL;
284 kfree(per_cpu(cpu_msrs, i).controls);
285 per_cpu(cpu_msrs, i).controls = NULL;
289 static int allocate_msrs(void)
291 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
292 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
295 for_each_possible_cpu(i) {
296 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
298 if (!per_cpu(cpu_msrs, i).counters)
300 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
302 if (!per_cpu(cpu_msrs, i).controls)
309 static void nmi_cpu_setup(void *dummy)
311 int cpu = smp_processor_id();
312 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
313 nmi_cpu_save_registers(msrs);
314 spin_lock(&oprofilefs_lock);
315 model->setup_ctrs(model, msrs);
316 nmi_cpu_setup_mux(cpu, msrs);
317 spin_unlock(&oprofilefs_lock);
318 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
319 apic_write(APIC_LVTPC, APIC_DM_NMI);
322 static struct notifier_block profile_exceptions_nb = {
323 .notifier_call = profile_exceptions_notify,
328 static int nmi_setup(void)
333 if (!allocate_msrs())
335 else if (!nmi_setup_mux())
338 err = register_die_notifier(&profile_exceptions_nb);
346 /* We need to serialize save and setup for HT because the subset
347 * of msrs are distinct for save and setup operations
350 /* Assume saved/restored counters are the same on all CPUs */
351 model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
352 for_each_possible_cpu(cpu) {
354 memcpy(per_cpu(cpu_msrs, cpu).counters,
355 per_cpu(cpu_msrs, 0).counters,
356 sizeof(struct op_msr) * model->num_counters);
358 memcpy(per_cpu(cpu_msrs, cpu).controls,
359 per_cpu(cpu_msrs, 0).controls,
360 sizeof(struct op_msr) * model->num_controls);
361 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
362 memcpy(per_cpu(cpu_msrs, cpu).multiplex,
363 per_cpu(cpu_msrs, 0).multiplex,
364 sizeof(struct op_msr) * model->num_virt_counters);
368 on_each_cpu(nmi_cpu_setup, NULL, 1);
373 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
375 struct op_msr *counters = msrs->counters;
376 struct op_msr *controls = msrs->controls;
379 for (i = 0; i < model->num_controls; ++i) {
380 if (controls[i].addr)
381 wrmsrl(controls[i].addr, controls[i].saved);
384 for (i = 0; i < model->num_counters; ++i) {
385 if (counters[i].addr)
386 wrmsrl(counters[i].addr, counters[i].saved);
390 static void nmi_cpu_shutdown(void *dummy)
393 int cpu = smp_processor_id();
394 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
396 /* restoring APIC_LVTPC can trigger an apic error because the delivery
397 * mode and vector nr combination can be illegal. That's by design: on
398 * power on apic lvt contain a zero vector nr which are legal only for
399 * NMI delivery mode. So inhibit apic err before restoring lvtpc
401 v = apic_read(APIC_LVTERR);
402 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
403 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
404 apic_write(APIC_LVTERR, v);
405 nmi_cpu_restore_registers(msrs);
408 static void nmi_shutdown(void)
410 struct op_msrs *msrs;
413 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
414 unregister_die_notifier(&profile_exceptions_nb);
416 msrs = &get_cpu_var(cpu_msrs);
417 model->shutdown(msrs);
419 put_cpu_var(cpu_msrs);
422 static int nmi_create_files(struct super_block *sb, struct dentry *root)
426 for (i = 0; i < model->num_virt_counters; ++i) {
430 #ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
431 /* quick little hack to _not_ expose a counter if it is not
432 * available for use. This should protect userspace app.
433 * NOTE: assumes 1:1 mapping here (that counters are organized
434 * sequentially in their struct assignment).
436 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
438 #endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
440 snprintf(buf, sizeof(buf), "%d", i);
441 dir = oprofilefs_mkdir(sb, root, buf);
442 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
443 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
444 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
445 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
446 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
447 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
454 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
457 int cpu = (unsigned long)data;
459 case CPU_DOWN_FAILED:
461 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
463 case CPU_DOWN_PREPARE:
464 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
470 static struct notifier_block oprofile_cpu_nb = {
471 .notifier_call = oprofile_cpu_notifier
477 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
479 /* Only one CPU left, just stop that one */
480 if (nmi_enabled == 1)
485 static int nmi_resume(struct sys_device *dev)
487 if (nmi_enabled == 1)
492 static struct sysdev_class oprofile_sysclass = {
494 .resume = nmi_resume,
495 .suspend = nmi_suspend,
498 static struct sys_device device_oprofile = {
500 .cls = &oprofile_sysclass,
503 static int __init init_sysfs(void)
507 error = sysdev_class_register(&oprofile_sysclass);
509 error = sysdev_register(&device_oprofile);
513 static void exit_sysfs(void)
515 sysdev_unregister(&device_oprofile);
516 sysdev_class_unregister(&oprofile_sysclass);
520 #define init_sysfs() do { } while (0)
521 #define exit_sysfs() do { } while (0)
522 #endif /* CONFIG_PM */
524 static int __init p4_init(char **cpu_type)
526 __u8 cpu_model = boot_cpu_data.x86_model;
528 if (cpu_model > 6 || cpu_model == 5)
532 *cpu_type = "i386/p4";
536 switch (smp_num_siblings) {
538 *cpu_type = "i386/p4";
543 *cpu_type = "i386/p4-ht";
544 model = &op_p4_ht2_spec;
549 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
550 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
554 static int force_arch_perfmon;
555 static int force_cpu_type(const char *str, struct kernel_param *kp)
557 if (!strcmp(str, "arch_perfmon")) {
558 force_arch_perfmon = 1;
559 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
564 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
566 static int __init ppro_init(char **cpu_type)
568 __u8 cpu_model = boot_cpu_data.x86_model;
569 struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
571 if (force_arch_perfmon && cpu_has_arch_perfmon)
576 *cpu_type = "i386/ppro";
579 *cpu_type = "i386/pii";
583 *cpu_type = "i386/piii";
587 *cpu_type = "i386/p6_mobile";
590 *cpu_type = "i386/core";
593 *cpu_type = "i386/core_2";
596 spec = &op_arch_perfmon_spec;
597 *cpu_type = "i386/core_i7";
600 *cpu_type = "i386/atom";
611 /* in order to get sysfs right */
612 static int using_nmi;
614 int __init op_nmi_init(struct oprofile_operations *ops)
616 __u8 vendor = boot_cpu_data.x86_vendor;
617 __u8 family = boot_cpu_data.x86;
618 char *cpu_type = NULL;
626 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
630 cpu_type = "i386/athlon";
634 * Actually it could be i386/hammer too, but
635 * give user space an consistent name.
637 cpu_type = "x86-64/hammer";
640 cpu_type = "x86-64/family10";
643 cpu_type = "x86-64/family11h";
648 model = &op_amd_spec;
651 case X86_VENDOR_INTEL:
658 /* A P6-class processor */
660 ppro_init(&cpu_type);
670 if (!cpu_has_arch_perfmon)
673 /* use arch perfmon as fallback */
674 cpu_type = "i386/arch_perfmon";
675 model = &op_arch_perfmon_spec;
683 register_cpu_notifier(&oprofile_cpu_nb);
685 /* default values, can be overwritten by model */
686 ops->create_files = nmi_create_files;
687 ops->setup = nmi_setup;
688 ops->shutdown = nmi_shutdown;
689 ops->start = nmi_start;
690 ops->stop = nmi_stop;
691 ops->cpu_type = cpu_type;
694 ret = model->init(ops);
698 if (!model->num_virt_counters)
699 model->num_virt_counters = model->num_counters;
705 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
709 void op_nmi_exit(void)
714 unregister_cpu_notifier(&oprofile_cpu_nb);