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   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2008 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/notifier.h>
  13 #include <linux/smp.h>
  14 #include <linux/oprofile.h>
  15 #include <linux/sysdev.h>
  16 #include <linux/slab.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/cpu.h>
  20 #include <asm/nmi.h>
  21 #include <asm/msr.h>
  22 #include <asm/apic.h>
  23
  24 #include "op_counter.h"
  25 #include "op_x86_model.h"
  26
  27 static struct op_x86_model_spec const *model;
  28 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  29 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  30
  31 static int nmi_start(void);
  32 static void nmi_stop(void);
  33 static void nmi_cpu_start(void *dummy);
  34 static void nmi_cpu_stop(void *dummy);
  35
  36 /* 0 == registered but off, 1 == registered and on */
  37 static int nmi_enabled = 0;
  38
  39 #ifdef CONFIG_SMP
  40 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
  41                                  void *data)
  42 {
  43         int cpu = (unsigned long)data;
  44         switch (action) {
  45         case CPU_DOWN_FAILED:
  46         case CPU_ONLINE:
  47                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
  48                 break;
  49         case CPU_DOWN_PREPARE:
  50                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
  51                 break;
  52         }
  53         return NOTIFY_DONE;
  54 }
  55
  56 static struct notifier_block oprofile_cpu_nb = {
  57         .notifier_call = oprofile_cpu_notifier
  58 };
  59 #endif
  60
  61 #ifdef CONFIG_PM
  62
  63 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
  64 {
  65         /* Only one CPU left, just stop that one */
  66         if (nmi_enabled == 1)
  67                 nmi_cpu_stop(NULL);
  68         return 0;
  69 }
  70
  71 static int nmi_resume(struct sys_device *dev)
  72 {
  73         if (nmi_enabled == 1)
  74                 nmi_cpu_start(NULL);
  75         return 0;
  76 }
  77
  78 static struct sysdev_class oprofile_sysclass = {
  79         .name           = "oprofile",
  80         .resume         = nmi_resume,
  81         .suspend        = nmi_suspend,
  82 };
  83
  84 static struct sys_device device_oprofile = {
  85         .id     = 0,
  86         .cls    = &oprofile_sysclass,
  87 };
  88
  89 static int __init init_sysfs(void)
  90 {
  91         int error;
  92
  93         error = sysdev_class_register(&oprofile_sysclass);
  94         if (!error)
  95                 error = sysdev_register(&device_oprofile);
  96         return error;
  97 }
  98
  99 static void exit_sysfs(void)
 100 {
 101         sysdev_unregister(&device_oprofile);
 102         sysdev_class_unregister(&oprofile_sysclass);
 103 }
 104
 105 #else
 106 #define init_sysfs() do { } while (0)
 107 #define exit_sysfs() do { } while (0)
 108 #endif /* CONFIG_PM */
 109
 110 static int profile_exceptions_notify(struct notifier_block *self,
 111                                      unsigned long val, void *data)
 112 {
 113         struct die_args *args = (struct die_args *)data;
 114         int ret = NOTIFY_DONE;
 115         int cpu = smp_processor_id();
 116
 117         switch (val) {
 118         case DIE_NMI:
 119                 if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
 120                         ret = NOTIFY_STOP;
 121                 break;
 122         default:
 123                 break;
 124         }
 125         return ret;
 126 }
 127
 128 static void nmi_cpu_save_registers(struct op_msrs *msrs)
 129 {
 130         unsigned int const nr_ctrs = model->num_counters;
 131         unsigned int const nr_ctrls = model->num_controls;
 132         struct op_msr *counters = msrs->counters;
 133         struct op_msr *controls = msrs->controls;
 134         unsigned int i;
 135
 136         for (i = 0; i < nr_ctrs; ++i) {
 137                 if (counters[i].addr) {
 138                         rdmsr(counters[i].addr,
 139                                 counters[i].saved.low,
 140                                 counters[i].saved.high);
 141                 }
 142         }
 143
 144         for (i = 0; i < nr_ctrls; ++i) {
 145                 if (controls[i].addr) {
 146                         rdmsr(controls[i].addr,
 147                                 controls[i].saved.low,
 148                                 controls[i].saved.high);
 149                 }
 150         }
 151 }
 152
 153 static void nmi_save_registers(void *dummy)
 154 {
 155         int cpu = smp_processor_id();
 156         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 157         nmi_cpu_save_registers(msrs);
 158 }
 159
 160 static void free_msrs(void)
 161 {
 162         int i;
 163         for_each_possible_cpu(i) {
 164                 kfree(per_cpu(cpu_msrs, i).counters);
 165                 per_cpu(cpu_msrs, i).counters = NULL;
 166                 kfree(per_cpu(cpu_msrs, i).controls);
 167                 per_cpu(cpu_msrs, i).controls = NULL;
 168         }
 169 }
 170
 171 static int allocate_msrs(void)
 172 {
 173         int success = 1;
 174         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 175         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 176
 177         int i;
 178         for_each_possible_cpu(i) {
 179                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 180                                                                 GFP_KERNEL);
 181                 if (!per_cpu(cpu_msrs, i).counters) {
 182                         success = 0;
 183                         break;
 184                 }
 185                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 186                                                                 GFP_KERNEL);
 187                 if (!per_cpu(cpu_msrs, i).controls) {
 188                         success = 0;
 189                         break;
 190                 }
 191         }
 192
 193         if (!success)
 194                 free_msrs();
 195
 196         return success;
 197 }
 198
 199 static void nmi_cpu_setup(void *dummy)
 200 {
 201         int cpu = smp_processor_id();
 202         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 203         spin_lock(&oprofilefs_lock);
 204         model->setup_ctrs(msrs);
 205         spin_unlock(&oprofilefs_lock);
 206         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 207         apic_write(APIC_LVTPC, APIC_DM_NMI);
 208 }
 209
 210 static struct notifier_block profile_exceptions_nb = {
 211         .notifier_call = profile_exceptions_notify,
 212         .next = NULL,
 213         .priority = 0
 214 };
 215
 216 static int nmi_setup(void)
 217 {
 218         int err = 0;
 219         int cpu;
 220
 221         if (!allocate_msrs())
 222                 return -ENOMEM;
 223
 224         err = register_die_notifier(&profile_exceptions_nb);
 225         if (err) {
 226                 free_msrs();
 227                 return err;
 228         }
 229
 230         /* We need to serialize save and setup for HT because the subset
 231          * of msrs are distinct for save and setup operations
 232          */
 233
 234         /* Assume saved/restored counters are the same on all CPUs */
 235         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 236         for_each_possible_cpu(cpu) {
 237                 if (cpu != 0) {
 238                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 239                                 per_cpu(cpu_msrs, 0).counters,
 240                                 sizeof(struct op_msr) * model->num_counters);
 241
 242                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 243                                 per_cpu(cpu_msrs, 0).controls,
 244                                 sizeof(struct op_msr) * model->num_controls);
 245                 }
 246
 247         }
 248         on_each_cpu(nmi_save_registers, NULL, 1);
 249         on_each_cpu(nmi_cpu_setup, NULL, 1);
 250         nmi_enabled = 1;
 251         return 0;
 252 }
 253
 254 static void nmi_restore_registers(struct op_msrs *msrs)
 255 {
 256         unsigned int const nr_ctrs = model->num_counters;
 257         unsigned int const nr_ctrls = model->num_controls;
 258         struct op_msr *counters = msrs->counters;
 259         struct op_msr *controls = msrs->controls;
 260         unsigned int i;
 261
 262         for (i = 0; i < nr_ctrls; ++i) {
 263                 if (controls[i].addr) {
 264                         wrmsr(controls[i].addr,
 265                                 controls[i].saved.low,
 266                                 controls[i].saved.high);
 267                 }
 268         }
 269
 270         for (i = 0; i < nr_ctrs; ++i) {
 271                 if (counters[i].addr) {
 272                         wrmsr(counters[i].addr,
 273                                 counters[i].saved.low,
 274                                 counters[i].saved.high);
 275                 }
 276         }
 277 }
 278
 279 static void nmi_cpu_shutdown(void *dummy)
 280 {
 281         unsigned int v;
 282         int cpu = smp_processor_id();
 283         struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
 284
 285         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 286          * mode and vector nr combination can be illegal. That's by design: on
 287          * power on apic lvt contain a zero vector nr which are legal only for
 288          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 289          */
 290         v = apic_read(APIC_LVTERR);
 291         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 292         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 293         apic_write(APIC_LVTERR, v);
 294         nmi_restore_registers(msrs);
 295 }
 296
 297 static void nmi_shutdown(void)
 298 {
 299         struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
 300         nmi_enabled = 0;
 301         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 302         unregister_die_notifier(&profile_exceptions_nb);
 303         model->shutdown(msrs);
 304         free_msrs();
 305         put_cpu_var(cpu_msrs);
 306 }
 307
 308 static void nmi_cpu_start(void *dummy)
 309 {
 310         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 311         model->start(msrs);
 312 }
 313
 314 static int nmi_start(void)
 315 {
 316         on_each_cpu(nmi_cpu_start, NULL, 1);
 317         return 0;
 318 }
 319
 320 static void nmi_cpu_stop(void *dummy)
 321 {
 322         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 323         model->stop(msrs);
 324 }
 325
 326 static void nmi_stop(void)
 327 {
 328         on_each_cpu(nmi_cpu_stop, NULL, 1);
 329 }
 330
 331 struct op_counter_config counter_config[OP_MAX_COUNTER];
 332
 333 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 334 {
 335         unsigned int i;
 336
 337         for (i = 0; i < model->num_counters; ++i) {
 338                 struct dentry *dir;
 339                 char buf[4];
 340
 341                 /* quick little hack to _not_ expose a counter if it is not
 342                  * available for use.  This should protect userspace app.
 343                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 344                  *        sequentially in their struct assignment).
 345                  */
 346                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 347                         continue;
 348
 349                 snprintf(buf,  sizeof(buf), "%d", i);
 350                 dir = oprofilefs_mkdir(sb, root, buf);
 351                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 352                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 353                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 354                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 355                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 356                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int p4force;
 363 module_param(p4force, int, 0);
 364
 365 static int __init p4_init(char **cpu_type)
 366 {
 367         __u8 cpu_model = boot_cpu_data.x86_model;
 368
 369         if (!p4force && (cpu_model > 6 || cpu_model == 5))
 370                 return 0;
 371
 372 #ifndef CONFIG_SMP
 373         *cpu_type = "i386/p4";
 374         model = &op_p4_spec;
 375         return 1;
 376 #else
 377         switch (smp_num_siblings) {
 378         case 1:
 379                 *cpu_type = "i386/p4";
 380                 model = &op_p4_spec;
 381                 return 1;
 382
 383         case 2:
 384                 *cpu_type = "i386/p4-ht";
 385                 model = &op_p4_ht2_spec;
 386                 return 1;
 387         }
 388 #endif
 389
 390         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 391         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 392         return 0;
 393 }
 394
 395 static int __init ppro_init(char **cpu_type)
 396 {
 397         __u8 cpu_model = boot_cpu_data.x86_model;
 398
 399         switch (cpu_model) {
 400         case 0 ... 2:
 401                 *cpu_type = "i386/ppro";
 402                 break;
 403         case 3 ... 5:
 404                 *cpu_type = "i386/pii";
 405                 break;
 406         case 6 ... 8:
 407                 *cpu_type = "i386/piii";
 408                 break;
 409         case 9:
 410                 *cpu_type = "i386/p6_mobile";
 411                 break;
 412         case 10 ... 13:
 413                 *cpu_type = "i386/p6";
 414                 break;
 415         case 14:
 416                 *cpu_type = "i386/core";
 417                 break;
 418         case 15: case 23:
 419                 *cpu_type = "i386/core_2";
 420                 break;
 421         case 26:
 422                 *cpu_type = "i386/core_2";
 423                 break;
 424         default:
 425                 /* Unknown */
 426                 return 0;
 427         }
 428
 429         model = &op_ppro_spec;
 430         return 1;
 431 }
 432
 433 /* in order to get sysfs right */
 434 static int using_nmi;
 435
 436 int __init op_nmi_init(struct oprofile_operations *ops)
 437 {
 438         __u8 vendor = boot_cpu_data.x86_vendor;
 439         __u8 family = boot_cpu_data.x86;
 440         char *cpu_type;
 441         int ret = 0;
 442
 443         if (!cpu_has_apic)
 444                 return -ENODEV;
 445
 446         switch (vendor) {
 447         case X86_VENDOR_AMD:
 448                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 449
 450                 switch (family) {
 451                 default:
 452                         return -ENODEV;
 453                 case 6:
 454                         model = &op_amd_spec;
 455                         cpu_type = "i386/athlon";
 456                         break;
 457                 case 0xf:
 458                         model = &op_amd_spec;
 459                         /* Actually it could be i386/hammer too, but give
 460                          user space an consistent name. */
 461                         cpu_type = "x86-64/hammer";
 462                         break;
 463                 case 0x10:
 464                         model = &op_amd_spec;
 465                         cpu_type = "x86-64/family10";
 466                         break;
 467                 case 0x11:
 468                         model = &op_amd_spec;
 469                         cpu_type = "x86-64/family11h";
 470                         break;
 471                 }
 472                 break;
 473
 474         case X86_VENDOR_INTEL:
 475                 switch (family) {
 476                         /* Pentium IV */
 477                 case 0xf:
 478                         if (!p4_init(&cpu_type))
 479                                 return -ENODEV;
 480                         break;
 481
 482                         /* A P6-class processor */
 483                 case 6:
 484                         if (!ppro_init(&cpu_type))
 485                                 return -ENODEV;
 486                         break;
 487
 488                 default:
 489                         return -ENODEV;
 490                 }
 491                 break;
 492
 493         default:
 494                 return -ENODEV;
 495         }
 496
 497 #ifdef CONFIG_SMP
 498         register_cpu_notifier(&oprofile_cpu_nb);
 499 #endif
 500         /* default values, can be overwritten by model */
 501         ops->create_files = nmi_create_files;
 502         ops->setup = nmi_setup;
 503         ops->shutdown = nmi_shutdown;
 504         ops->start = nmi_start;
 505         ops->stop = nmi_stop;
 506         ops->cpu_type = cpu_type;
 507
 508         if (model->init)
 509                 ret = model->init(ops);
 510         if (ret)
 511                 return ret;
 512
 513         init_sysfs();
 514         using_nmi = 1;
 515         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 516         return 0;
 517 }
 518
 519 void op_nmi_exit(void)
 520 {
 521         if (using_nmi) {
 522                 exit_sysfs();
 523 #ifdef CONFIG_SMP
 524                 unregister_cpu_notifier(&oprofile_cpu_nb);
 525 #endif
 526         }
 527         if (model->exit)
 528                 model->exit();
 529 }