2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
26 #include "kvm_cache_regs.h"
29 #include <linux/clocksource.h>
30 #include <linux/interrupt.h>
31 #include <linux/kvm.h>
33 #include <linux/vmalloc.h>
34 #include <linux/module.h>
35 #include <linux/mman.h>
36 #include <linux/highmem.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/cpufreq.h>
40 #include <trace/events/kvm.h>
41 #undef TRACE_INCLUDE_FILE
42 #define CREATE_TRACE_POINTS
45 #include <asm/uaccess.h>
51 #define MAX_IO_MSRS 256
52 #define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56 #define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
62 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
64 #define KVM_MAX_MCE_BANKS 32
65 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
72 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
74 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
77 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
80 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
83 struct kvm_x86_ops *kvm_x86_ops;
84 EXPORT_SYMBOL_GPL(kvm_x86_ops);
87 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
89 struct kvm_stats_debugfs_item debugfs_entries[] = {
90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
102 { "hypercalls", VCPU_STAT(hypercalls) },
103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
110 { "irq_injections", VCPU_STAT(irq_injections) },
111 { "nmi_injections", VCPU_STAT(nmi_injections) },
112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
119 { "mmu_unsync", VM_STAT(mmu_unsync) },
120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
121 { "largepages", VM_STAT(lpages) },
125 unsigned long segment_base(u16 selector)
127 struct descriptor_table gdt;
128 struct desc_struct *d;
129 unsigned long table_base;
135 asm("sgdt %0" : "=m"(gdt));
136 table_base = gdt.base;
138 if (selector & 4) { /* from ldt */
141 asm("sldt %0" : "=g"(ldt_selector));
142 table_base = segment_base(ldt_selector);
144 d = (struct desc_struct *)(table_base + (selector & ~7));
145 v = d->base0 | ((unsigned long)d->base1 << 16) |
146 ((unsigned long)d->base2 << 24);
148 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
149 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
153 EXPORT_SYMBOL_GPL(segment_base);
155 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
157 if (irqchip_in_kernel(vcpu->kvm))
158 return vcpu->arch.apic_base;
160 return vcpu->arch.apic_base;
162 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
164 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
166 /* TODO: reserve bits check */
167 if (irqchip_in_kernel(vcpu->kvm))
168 kvm_lapic_set_base(vcpu, data);
170 vcpu->arch.apic_base = data;
172 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
174 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
176 WARN_ON(vcpu->arch.exception.pending);
177 vcpu->arch.exception.pending = true;
178 vcpu->arch.exception.has_error_code = false;
179 vcpu->arch.exception.nr = nr;
181 EXPORT_SYMBOL_GPL(kvm_queue_exception);
183 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
186 ++vcpu->stat.pf_guest;
188 if (vcpu->arch.exception.pending) {
189 switch(vcpu->arch.exception.nr) {
191 /* triple fault -> shutdown */
192 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
195 vcpu->arch.exception.nr = DF_VECTOR;
196 vcpu->arch.exception.error_code = 0;
199 /* replace previous exception with a new one in a hope
200 that instruction re-execution will regenerate lost
202 vcpu->arch.exception.pending = false;
206 vcpu->arch.cr2 = addr;
207 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
210 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
212 vcpu->arch.nmi_pending = 1;
214 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
216 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
218 WARN_ON(vcpu->arch.exception.pending);
219 vcpu->arch.exception.pending = true;
220 vcpu->arch.exception.has_error_code = true;
221 vcpu->arch.exception.nr = nr;
222 vcpu->arch.exception.error_code = error_code;
224 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
226 static void __queue_exception(struct kvm_vcpu *vcpu)
228 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
229 vcpu->arch.exception.has_error_code,
230 vcpu->arch.exception.error_code);
234 * Load the pae pdptrs. Return true is they are all valid.
236 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
238 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
239 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
242 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
244 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
245 offset * sizeof(u64), sizeof(pdpte));
250 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
251 if (is_present_gpte(pdpte[i]) &&
252 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
259 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
260 __set_bit(VCPU_EXREG_PDPTR,
261 (unsigned long *)&vcpu->arch.regs_avail);
262 __set_bit(VCPU_EXREG_PDPTR,
263 (unsigned long *)&vcpu->arch.regs_dirty);
268 EXPORT_SYMBOL_GPL(load_pdptrs);
270 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
272 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
276 if (is_long_mode(vcpu) || !is_pae(vcpu))
279 if (!test_bit(VCPU_EXREG_PDPTR,
280 (unsigned long *)&vcpu->arch.regs_avail))
283 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
286 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
292 void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
294 if (cr0 & CR0_RESERVED_BITS) {
295 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
296 cr0, vcpu->arch.cr0);
297 kvm_inject_gp(vcpu, 0);
301 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
302 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
303 kvm_inject_gp(vcpu, 0);
307 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
308 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
309 "and a clear PE flag\n");
310 kvm_inject_gp(vcpu, 0);
314 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
316 if ((vcpu->arch.shadow_efer & EFER_LME)) {
320 printk(KERN_DEBUG "set_cr0: #GP, start paging "
321 "in long mode while PAE is disabled\n");
322 kvm_inject_gp(vcpu, 0);
325 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
327 printk(KERN_DEBUG "set_cr0: #GP, start paging "
328 "in long mode while CS.L == 1\n");
329 kvm_inject_gp(vcpu, 0);
335 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
336 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
338 kvm_inject_gp(vcpu, 0);
344 kvm_x86_ops->set_cr0(vcpu, cr0);
345 vcpu->arch.cr0 = cr0;
347 kvm_mmu_reset_context(vcpu);
350 EXPORT_SYMBOL_GPL(kvm_set_cr0);
352 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
354 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
356 EXPORT_SYMBOL_GPL(kvm_lmsw);
358 void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
360 unsigned long old_cr4 = vcpu->arch.cr4;
361 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
363 if (cr4 & CR4_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
365 kvm_inject_gp(vcpu, 0);
369 if (is_long_mode(vcpu)) {
370 if (!(cr4 & X86_CR4_PAE)) {
371 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
373 kvm_inject_gp(vcpu, 0);
376 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
377 && ((cr4 ^ old_cr4) & pdptr_bits)
378 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
379 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
380 kvm_inject_gp(vcpu, 0);
384 if (cr4 & X86_CR4_VMXE) {
385 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
386 kvm_inject_gp(vcpu, 0);
389 kvm_x86_ops->set_cr4(vcpu, cr4);
390 vcpu->arch.cr4 = cr4;
391 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
392 kvm_mmu_reset_context(vcpu);
394 EXPORT_SYMBOL_GPL(kvm_set_cr4);
396 void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
398 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
399 kvm_mmu_sync_roots(vcpu);
400 kvm_mmu_flush_tlb(vcpu);
404 if (is_long_mode(vcpu)) {
405 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
406 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
407 kvm_inject_gp(vcpu, 0);
412 if (cr3 & CR3_PAE_RESERVED_BITS) {
414 "set_cr3: #GP, reserved bits\n");
415 kvm_inject_gp(vcpu, 0);
418 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
419 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
421 kvm_inject_gp(vcpu, 0);
426 * We don't check reserved bits in nonpae mode, because
427 * this isn't enforced, and VMware depends on this.
432 * Does the new cr3 value map to physical memory? (Note, we
433 * catch an invalid cr3 even in real-mode, because it would
434 * cause trouble later on when we turn on paging anyway.)
436 * A real CPU would silently accept an invalid cr3 and would
437 * attempt to use it - with largely undefined (and often hard
438 * to debug) behavior on the guest side.
440 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
441 kvm_inject_gp(vcpu, 0);
443 vcpu->arch.cr3 = cr3;
444 vcpu->arch.mmu.new_cr3(vcpu);
447 EXPORT_SYMBOL_GPL(kvm_set_cr3);
449 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
451 if (cr8 & CR8_RESERVED_BITS) {
452 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
453 kvm_inject_gp(vcpu, 0);
456 if (irqchip_in_kernel(vcpu->kvm))
457 kvm_lapic_set_tpr(vcpu, cr8);
459 vcpu->arch.cr8 = cr8;
461 EXPORT_SYMBOL_GPL(kvm_set_cr8);
463 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
465 if (irqchip_in_kernel(vcpu->kvm))
466 return kvm_lapic_get_cr8(vcpu);
468 return vcpu->arch.cr8;
470 EXPORT_SYMBOL_GPL(kvm_get_cr8);
472 static inline u32 bit(int bitno)
474 return 1 << (bitno & 31);
478 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
479 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
481 * This list is modified at module load time to reflect the
482 * capabilities of the host cpu.
484 static u32 msrs_to_save[] = {
485 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
488 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
490 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
491 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
494 static unsigned num_msrs_to_save;
496 static u32 emulated_msrs[] = {
497 MSR_IA32_MISC_ENABLE,
500 static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
502 if (efer & efer_reserved_bits) {
503 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
505 kvm_inject_gp(vcpu, 0);
510 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
511 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
512 kvm_inject_gp(vcpu, 0);
516 if (efer & EFER_FFXSR) {
517 struct kvm_cpuid_entry2 *feat;
519 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
520 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
521 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
522 kvm_inject_gp(vcpu, 0);
527 if (efer & EFER_SVME) {
528 struct kvm_cpuid_entry2 *feat;
530 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
531 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
532 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
533 kvm_inject_gp(vcpu, 0);
538 kvm_x86_ops->set_efer(vcpu, efer);
541 efer |= vcpu->arch.shadow_efer & EFER_LMA;
543 vcpu->arch.shadow_efer = efer;
545 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
546 kvm_mmu_reset_context(vcpu);
549 void kvm_enable_efer_bits(u64 mask)
551 efer_reserved_bits &= ~mask;
553 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
557 * Writes msr value into into the appropriate "register".
558 * Returns 0 on success, non-0 otherwise.
559 * Assumes vcpu_load() was already called.
561 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
563 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
567 * Adapt set_msr() to msr_io()'s calling convention
569 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
571 return kvm_set_msr(vcpu, index, *data);
574 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
577 struct pvclock_wall_clock wc;
578 struct timespec now, sys, boot;
585 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
588 * The guest calculates current wall clock time by adding
589 * system time (updated by kvm_write_guest_time below) to the
590 * wall clock specified here. guest system time equals host
591 * system time for us, thus we must fill in host boot time here.
593 now = current_kernel_time();
595 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
597 wc.sec = boot.tv_sec;
598 wc.nsec = boot.tv_nsec;
599 wc.version = version;
601 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
604 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
607 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
609 uint32_t quotient, remainder;
611 /* Don't try to replace with do_div(), this one calculates
612 * "(dividend << 32) / divisor" */
614 : "=a" (quotient), "=d" (remainder)
615 : "0" (0), "1" (dividend), "r" (divisor) );
619 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
621 uint64_t nsecs = 1000000000LL;
626 tps64 = tsc_khz * 1000LL;
627 while (tps64 > nsecs*2) {
632 tps32 = (uint32_t)tps64;
633 while (tps32 <= (uint32_t)nsecs) {
638 hv_clock->tsc_shift = shift;
639 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
641 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
642 __func__, tsc_khz, hv_clock->tsc_shift,
643 hv_clock->tsc_to_system_mul);
646 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
648 static void kvm_write_guest_time(struct kvm_vcpu *v)
652 struct kvm_vcpu_arch *vcpu = &v->arch;
654 unsigned long this_tsc_khz;
656 if ((!vcpu->time_page))
659 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
660 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
661 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
662 vcpu->hv_clock_tsc_khz = this_tsc_khz;
664 put_cpu_var(cpu_tsc_khz);
666 /* Keep irq disabled to prevent changes to the clock */
667 local_irq_save(flags);
668 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
670 local_irq_restore(flags);
672 /* With all the info we got, fill in the values */
674 vcpu->hv_clock.system_time = ts.tv_nsec +
675 (NSEC_PER_SEC * (u64)ts.tv_sec);
677 * The interface expects us to write an even number signaling that the
678 * update is finished. Since the guest won't see the intermediate
679 * state, we just increase by 2 at the end.
681 vcpu->hv_clock.version += 2;
683 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
685 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
686 sizeof(vcpu->hv_clock));
688 kunmap_atomic(shared_kaddr, KM_USER0);
690 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
693 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
695 struct kvm_vcpu_arch *vcpu = &v->arch;
697 if (!vcpu->time_page)
699 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
703 static bool msr_mtrr_valid(unsigned msr)
706 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
707 case MSR_MTRRfix64K_00000:
708 case MSR_MTRRfix16K_80000:
709 case MSR_MTRRfix16K_A0000:
710 case MSR_MTRRfix4K_C0000:
711 case MSR_MTRRfix4K_C8000:
712 case MSR_MTRRfix4K_D0000:
713 case MSR_MTRRfix4K_D8000:
714 case MSR_MTRRfix4K_E0000:
715 case MSR_MTRRfix4K_E8000:
716 case MSR_MTRRfix4K_F0000:
717 case MSR_MTRRfix4K_F8000:
718 case MSR_MTRRdefType:
719 case MSR_IA32_CR_PAT:
727 static bool valid_pat_type(unsigned t)
729 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
732 static bool valid_mtrr_type(unsigned t)
734 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
737 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
741 if (!msr_mtrr_valid(msr))
744 if (msr == MSR_IA32_CR_PAT) {
745 for (i = 0; i < 8; i++)
746 if (!valid_pat_type((data >> (i * 8)) & 0xff))
749 } else if (msr == MSR_MTRRdefType) {
752 return valid_mtrr_type(data & 0xff);
753 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
754 for (i = 0; i < 8 ; i++)
755 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
761 return valid_mtrr_type(data & 0xff);
764 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
766 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
768 if (!mtrr_valid(vcpu, msr, data))
771 if (msr == MSR_MTRRdefType) {
772 vcpu->arch.mtrr_state.def_type = data;
773 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
774 } else if (msr == MSR_MTRRfix64K_00000)
776 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
777 p[1 + msr - MSR_MTRRfix16K_80000] = data;
778 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
779 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
780 else if (msr == MSR_IA32_CR_PAT)
781 vcpu->arch.pat = data;
782 else { /* Variable MTRRs */
783 int idx, is_mtrr_mask;
786 idx = (msr - 0x200) / 2;
787 is_mtrr_mask = msr - 0x200 - 2 * idx;
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
793 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
797 kvm_mmu_reset_context(vcpu);
801 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
803 u64 mcg_cap = vcpu->arch.mcg_cap;
804 unsigned bank_num = mcg_cap & 0xff;
807 case MSR_IA32_MCG_STATUS:
808 vcpu->arch.mcg_status = data;
810 case MSR_IA32_MCG_CTL:
811 if (!(mcg_cap & MCG_CTL_P))
813 if (data != 0 && data != ~(u64)0)
815 vcpu->arch.mcg_ctl = data;
818 if (msr >= MSR_IA32_MC0_CTL &&
819 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
820 u32 offset = msr - MSR_IA32_MC0_CTL;
821 /* only 0 or all 1s can be written to IA32_MCi_CTL */
822 if ((offset & 0x3) == 0 &&
823 data != 0 && data != ~(u64)0)
825 vcpu->arch.mce_banks[offset] = data;
833 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
837 set_efer(vcpu, data);
840 data &= ~(u64)0x40; /* ignore flush filter disable */
842 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
847 case MSR_FAM10H_MMIO_CONF_BASE:
849 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
854 case MSR_AMD64_NB_CFG:
856 case MSR_IA32_DEBUGCTLMSR:
858 /* We support the non-activated case already */
860 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
861 /* Values other than LBR and BTF are vendor-specific,
862 thus reserved and should throw a #GP */
865 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
868 case MSR_IA32_UCODE_REV:
869 case MSR_IA32_UCODE_WRITE:
870 case MSR_VM_HSAVE_PA:
871 case MSR_AMD64_PATCH_LOADER:
873 case 0x200 ... 0x2ff:
874 return set_msr_mtrr(vcpu, msr, data);
875 case MSR_IA32_APICBASE:
876 kvm_set_apic_base(vcpu, data);
878 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
879 return kvm_x2apic_msr_write(vcpu, msr, data);
880 case MSR_IA32_MISC_ENABLE:
881 vcpu->arch.ia32_misc_enable_msr = data;
883 case MSR_KVM_WALL_CLOCK:
884 vcpu->kvm->arch.wall_clock = data;
885 kvm_write_wall_clock(vcpu->kvm, data);
887 case MSR_KVM_SYSTEM_TIME: {
888 if (vcpu->arch.time_page) {
889 kvm_release_page_dirty(vcpu->arch.time_page);
890 vcpu->arch.time_page = NULL;
893 vcpu->arch.time = data;
895 /* we verify if the enable bit is set... */
899 /* ...but clean it before doing the actual write */
900 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
902 vcpu->arch.time_page =
903 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
905 if (is_error_page(vcpu->arch.time_page)) {
906 kvm_release_page_clean(vcpu->arch.time_page);
907 vcpu->arch.time_page = NULL;
910 kvm_request_guest_time_update(vcpu);
913 case MSR_IA32_MCG_CTL:
914 case MSR_IA32_MCG_STATUS:
915 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
916 return set_msr_mce(vcpu, msr, data);
918 /* Performance counters are not protected by a CPUID bit,
919 * so we should check all of them in the generic path for the sake of
920 * cross vendor migration.
921 * Writing a zero into the event select MSRs disables them,
922 * which we perfectly emulate ;-). Any other value should be at least
923 * reported, some guests depend on them.
925 case MSR_P6_EVNTSEL0:
926 case MSR_P6_EVNTSEL1:
927 case MSR_K7_EVNTSEL0:
928 case MSR_K7_EVNTSEL1:
929 case MSR_K7_EVNTSEL2:
930 case MSR_K7_EVNTSEL3:
932 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
933 "0x%x data 0x%llx\n", msr, data);
935 /* at least RHEL 4 unconditionally writes to the perfctr registers,
936 * so we ignore writes to make it happy.
938 case MSR_P6_PERFCTR0:
939 case MSR_P6_PERFCTR1:
940 case MSR_K7_PERFCTR0:
941 case MSR_K7_PERFCTR1:
942 case MSR_K7_PERFCTR2:
943 case MSR_K7_PERFCTR3:
944 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
945 "0x%x data 0x%llx\n", msr, data);
949 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
953 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
960 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
968 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
970 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
973 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
975 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
977 if (!msr_mtrr_valid(msr))
980 if (msr == MSR_MTRRdefType)
981 *pdata = vcpu->arch.mtrr_state.def_type +
982 (vcpu->arch.mtrr_state.enabled << 10);
983 else if (msr == MSR_MTRRfix64K_00000)
985 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
986 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
987 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
988 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
989 else if (msr == MSR_IA32_CR_PAT)
990 *pdata = vcpu->arch.pat;
991 else { /* Variable MTRRs */
992 int idx, is_mtrr_mask;
995 idx = (msr - 0x200) / 2;
996 is_mtrr_mask = msr - 0x200 - 2 * idx;
999 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1002 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1009 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1012 u64 mcg_cap = vcpu->arch.mcg_cap;
1013 unsigned bank_num = mcg_cap & 0xff;
1016 case MSR_IA32_P5_MC_ADDR:
1017 case MSR_IA32_P5_MC_TYPE:
1020 case MSR_IA32_MCG_CAP:
1021 data = vcpu->arch.mcg_cap;
1023 case MSR_IA32_MCG_CTL:
1024 if (!(mcg_cap & MCG_CTL_P))
1026 data = vcpu->arch.mcg_ctl;
1028 case MSR_IA32_MCG_STATUS:
1029 data = vcpu->arch.mcg_status;
1032 if (msr >= MSR_IA32_MC0_CTL &&
1033 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1034 u32 offset = msr - MSR_IA32_MC0_CTL;
1035 data = vcpu->arch.mce_banks[offset];
1044 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1049 case MSR_IA32_PLATFORM_ID:
1050 case MSR_IA32_UCODE_REV:
1051 case MSR_IA32_EBL_CR_POWERON:
1052 case MSR_IA32_DEBUGCTLMSR:
1053 case MSR_IA32_LASTBRANCHFROMIP:
1054 case MSR_IA32_LASTBRANCHTOIP:
1055 case MSR_IA32_LASTINTFROMIP:
1056 case MSR_IA32_LASTINTTOIP:
1059 case MSR_VM_HSAVE_PA:
1060 case MSR_P6_EVNTSEL0:
1061 case MSR_P6_EVNTSEL1:
1062 case MSR_K7_EVNTSEL0:
1063 case MSR_K8_INT_PENDING_MSG:
1064 case MSR_AMD64_NB_CFG:
1065 case MSR_FAM10H_MMIO_CONF_BASE:
1069 data = 0x500 | KVM_NR_VAR_MTRR;
1071 case 0x200 ... 0x2ff:
1072 return get_msr_mtrr(vcpu, msr, pdata);
1073 case 0xcd: /* fsb frequency */
1076 case MSR_IA32_APICBASE:
1077 data = kvm_get_apic_base(vcpu);
1079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1080 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1082 case MSR_IA32_MISC_ENABLE:
1083 data = vcpu->arch.ia32_misc_enable_msr;
1085 case MSR_IA32_PERF_STATUS:
1086 /* TSC increment by tick */
1088 /* CPU multiplier */
1089 data |= (((uint64_t)4ULL) << 40);
1092 data = vcpu->arch.shadow_efer;
1094 case MSR_KVM_WALL_CLOCK:
1095 data = vcpu->kvm->arch.wall_clock;
1097 case MSR_KVM_SYSTEM_TIME:
1098 data = vcpu->arch.time;
1100 case MSR_IA32_P5_MC_ADDR:
1101 case MSR_IA32_P5_MC_TYPE:
1102 case MSR_IA32_MCG_CAP:
1103 case MSR_IA32_MCG_CTL:
1104 case MSR_IA32_MCG_STATUS:
1105 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1106 return get_msr_mce(vcpu, msr, pdata);
1109 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1112 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1120 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1123 * Read or write a bunch of msrs. All parameters are kernel addresses.
1125 * @return number of msrs set successfully.
1127 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1128 struct kvm_msr_entry *entries,
1129 int (*do_msr)(struct kvm_vcpu *vcpu,
1130 unsigned index, u64 *data))
1136 down_read(&vcpu->kvm->slots_lock);
1137 for (i = 0; i < msrs->nmsrs; ++i)
1138 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1140 up_read(&vcpu->kvm->slots_lock);
1148 * Read or write a bunch of msrs. Parameters are user addresses.
1150 * @return number of msrs set successfully.
1152 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1153 int (*do_msr)(struct kvm_vcpu *vcpu,
1154 unsigned index, u64 *data),
1157 struct kvm_msrs msrs;
1158 struct kvm_msr_entry *entries;
1163 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1167 if (msrs.nmsrs >= MAX_IO_MSRS)
1171 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1172 entries = vmalloc(size);
1177 if (copy_from_user(entries, user_msrs->entries, size))
1180 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1185 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1196 int kvm_dev_ioctl_check_extension(long ext)
1201 case KVM_CAP_IRQCHIP:
1203 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1204 case KVM_CAP_SET_TSS_ADDR:
1205 case KVM_CAP_EXT_CPUID:
1206 case KVM_CAP_CLOCKSOURCE:
1208 case KVM_CAP_NOP_IO_DELAY:
1209 case KVM_CAP_MP_STATE:
1210 case KVM_CAP_SYNC_MMU:
1211 case KVM_CAP_REINJECT_CONTROL:
1212 case KVM_CAP_IRQ_INJECT_STATUS:
1213 case KVM_CAP_ASSIGN_DEV_IRQ:
1215 case KVM_CAP_IOEVENTFD:
1217 case KVM_CAP_PIT_STATE2:
1220 case KVM_CAP_COALESCED_MMIO:
1221 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1224 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1226 case KVM_CAP_NR_VCPUS:
1229 case KVM_CAP_NR_MEMSLOTS:
1230 r = KVM_MEMORY_SLOTS;
1232 case KVM_CAP_PV_MMU:
1239 r = KVM_MAX_MCE_BANKS;
1249 long kvm_arch_dev_ioctl(struct file *filp,
1250 unsigned int ioctl, unsigned long arg)
1252 void __user *argp = (void __user *)arg;
1256 case KVM_GET_MSR_INDEX_LIST: {
1257 struct kvm_msr_list __user *user_msr_list = argp;
1258 struct kvm_msr_list msr_list;
1262 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1265 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1266 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1269 if (n < msr_list.nmsrs)
1272 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1273 num_msrs_to_save * sizeof(u32)))
1275 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1277 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1282 case KVM_GET_SUPPORTED_CPUID: {
1283 struct kvm_cpuid2 __user *cpuid_arg = argp;
1284 struct kvm_cpuid2 cpuid;
1287 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1289 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1290 cpuid_arg->entries);
1295 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1300 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1303 mce_cap = KVM_MCE_CAP_SUPPORTED;
1305 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1317 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1319 kvm_x86_ops->vcpu_load(vcpu, cpu);
1320 kvm_request_guest_time_update(vcpu);
1323 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1325 kvm_x86_ops->vcpu_put(vcpu);
1326 kvm_put_guest_fpu(vcpu);
1329 static int is_efer_nx(void)
1331 unsigned long long efer = 0;
1333 rdmsrl_safe(MSR_EFER, &efer);
1334 return efer & EFER_NX;
1337 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1340 struct kvm_cpuid_entry2 *e, *entry;
1343 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1344 e = &vcpu->arch.cpuid_entries[i];
1345 if (e->function == 0x80000001) {
1350 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
1351 entry->edx &= ~(1 << 20);
1352 printk(KERN_INFO "kvm: guest NX capability removed\n");
1356 /* when an old userspace process fills a new kernel module */
1357 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1358 struct kvm_cpuid *cpuid,
1359 struct kvm_cpuid_entry __user *entries)
1362 struct kvm_cpuid_entry *cpuid_entries;
1365 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1368 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1372 if (copy_from_user(cpuid_entries, entries,
1373 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1375 for (i = 0; i < cpuid->nent; i++) {
1376 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1377 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1378 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1379 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1380 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1381 vcpu->arch.cpuid_entries[i].index = 0;
1382 vcpu->arch.cpuid_entries[i].flags = 0;
1383 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1384 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1385 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1387 vcpu->arch.cpuid_nent = cpuid->nent;
1388 cpuid_fix_nx_cap(vcpu);
1390 kvm_apic_set_version(vcpu);
1393 vfree(cpuid_entries);
1398 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1399 struct kvm_cpuid2 *cpuid,
1400 struct kvm_cpuid_entry2 __user *entries)
1405 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1408 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
1409 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
1411 vcpu->arch.cpuid_nent = cpuid->nent;
1412 kvm_apic_set_version(vcpu);
1419 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1420 struct kvm_cpuid2 *cpuid,
1421 struct kvm_cpuid_entry2 __user *entries)
1426 if (cpuid->nent < vcpu->arch.cpuid_nent)
1429 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1430 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
1435 cpuid->nent = vcpu->arch.cpuid_nent;
1439 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1442 entry->function = function;
1443 entry->index = index;
1444 cpuid_count(entry->function, entry->index,
1445 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1449 #define F(x) bit(X86_FEATURE_##x)
1451 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1452 u32 index, int *nent, int maxnent)
1454 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
1455 #ifdef CONFIG_X86_64
1456 unsigned f_lm = F(LM);
1462 const u32 kvm_supported_word0_x86_features =
1463 F(FPU) | F(VME) | F(DE) | F(PSE) |
1464 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1465 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1466 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1467 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1468 0 /* Reserved, DS, ACPI */ | F(MMX) |
1469 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1470 0 /* HTT, TM, Reserved, PBE */;
1471 /* cpuid 0x80000001.edx */
1472 const u32 kvm_supported_word1_x86_features =
1473 F(FPU) | F(VME) | F(DE) | F(PSE) |
1474 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1475 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1476 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1477 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1478 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1479 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1480 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1482 const u32 kvm_supported_word4_x86_features =
1483 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1484 0 /* DS-CPL, VMX, SMX, EST */ |
1485 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1486 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1487 0 /* Reserved, DCA */ | F(XMM4_1) |
1488 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
1489 0 /* Reserved, XSAVE, OSXSAVE */;
1490 /* cpuid 0x80000001.ecx */
1491 const u32 kvm_supported_word6_x86_features =
1492 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1493 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1494 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1495 0 /* SKINIT */ | 0 /* WDT */;
1497 /* all calls to cpuid_count() should be made on the same cpu */
1499 do_cpuid_1_ent(entry, function, index);
1504 entry->eax = min(entry->eax, (u32)0xb);
1507 entry->edx &= kvm_supported_word0_x86_features;
1508 entry->ecx &= kvm_supported_word4_x86_features;
1509 /* we support x2apic emulation even if host does not support
1510 * it since we emulate x2apic in software */
1511 entry->ecx |= F(X2APIC);
1513 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1514 * may return different values. This forces us to get_cpu() before
1515 * issuing the first command, and also to emulate this annoying behavior
1516 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1518 int t, times = entry->eax & 0xff;
1520 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1521 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
1522 for (t = 1; t < times && *nent < maxnent; ++t) {
1523 do_cpuid_1_ent(&entry[t], function, 0);
1524 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1529 /* function 4 and 0xb have additional index. */
1533 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1534 /* read more entries until cache_type is zero */
1535 for (i = 1; *nent < maxnent; ++i) {
1536 cache_type = entry[i - 1].eax & 0x1f;
1539 do_cpuid_1_ent(&entry[i], function, i);
1541 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1549 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1550 /* read more entries until level_type is zero */
1551 for (i = 1; *nent < maxnent; ++i) {
1552 level_type = entry[i - 1].ecx & 0xff00;
1555 do_cpuid_1_ent(&entry[i], function, i);
1557 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1563 entry->eax = min(entry->eax, 0x8000001a);
1566 entry->edx &= kvm_supported_word1_x86_features;
1567 entry->ecx &= kvm_supported_word6_x86_features;
1575 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
1576 struct kvm_cpuid_entry2 __user *entries)
1578 struct kvm_cpuid_entry2 *cpuid_entries;
1579 int limit, nent = 0, r = -E2BIG;
1582 if (cpuid->nent < 1)
1585 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1589 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1590 limit = cpuid_entries[0].eax;
1591 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1592 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1593 &nent, cpuid->nent);
1595 if (nent >= cpuid->nent)
1598 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1599 limit = cpuid_entries[nent - 1].eax;
1600 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1601 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1602 &nent, cpuid->nent);
1604 if (nent >= cpuid->nent)
1608 if (copy_to_user(entries, cpuid_entries,
1609 nent * sizeof(struct kvm_cpuid_entry2)))
1615 vfree(cpuid_entries);
1620 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1621 struct kvm_lapic_state *s)
1624 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
1630 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1631 struct kvm_lapic_state *s)
1634 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1635 kvm_apic_post_state_restore(vcpu);
1641 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1642 struct kvm_interrupt *irq)
1644 if (irq->irq < 0 || irq->irq >= 256)
1646 if (irqchip_in_kernel(vcpu->kvm))
1650 kvm_queue_interrupt(vcpu, irq->irq, false);
1657 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1660 kvm_inject_nmi(vcpu);
1666 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1667 struct kvm_tpr_access_ctl *tac)
1671 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1675 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1679 unsigned bank_num = mcg_cap & 0xff, bank;
1684 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1687 vcpu->arch.mcg_cap = mcg_cap;
1688 /* Init IA32_MCG_CTL to all 1s */
1689 if (mcg_cap & MCG_CTL_P)
1690 vcpu->arch.mcg_ctl = ~(u64)0;
1691 /* Init IA32_MCi_CTL to all 1s */
1692 for (bank = 0; bank < bank_num; bank++)
1693 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1698 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1699 struct kvm_x86_mce *mce)
1701 u64 mcg_cap = vcpu->arch.mcg_cap;
1702 unsigned bank_num = mcg_cap & 0xff;
1703 u64 *banks = vcpu->arch.mce_banks;
1705 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1708 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1709 * reporting is disabled
1711 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1712 vcpu->arch.mcg_ctl != ~(u64)0)
1714 banks += 4 * mce->bank;
1716 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1717 * reporting is disabled for the bank
1719 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1721 if (mce->status & MCI_STATUS_UC) {
1722 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1723 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1724 printk(KERN_DEBUG "kvm: set_mce: "
1725 "injects mce exception while "
1726 "previous one is in progress!\n");
1727 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1730 if (banks[1] & MCI_STATUS_VAL)
1731 mce->status |= MCI_STATUS_OVER;
1732 banks[2] = mce->addr;
1733 banks[3] = mce->misc;
1734 vcpu->arch.mcg_status = mce->mcg_status;
1735 banks[1] = mce->status;
1736 kvm_queue_exception(vcpu, MC_VECTOR);
1737 } else if (!(banks[1] & MCI_STATUS_VAL)
1738 || !(banks[1] & MCI_STATUS_UC)) {
1739 if (banks[1] & MCI_STATUS_VAL)
1740 mce->status |= MCI_STATUS_OVER;
1741 banks[2] = mce->addr;
1742 banks[3] = mce->misc;
1743 banks[1] = mce->status;
1745 banks[1] |= MCI_STATUS_OVER;
1749 long kvm_arch_vcpu_ioctl(struct file *filp,
1750 unsigned int ioctl, unsigned long arg)
1752 struct kvm_vcpu *vcpu = filp->private_data;
1753 void __user *argp = (void __user *)arg;
1755 struct kvm_lapic_state *lapic = NULL;
1758 case KVM_GET_LAPIC: {
1759 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1764 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
1768 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
1773 case KVM_SET_LAPIC: {
1774 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1779 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
1781 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
1787 case KVM_INTERRUPT: {
1788 struct kvm_interrupt irq;
1791 if (copy_from_user(&irq, argp, sizeof irq))
1793 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1800 r = kvm_vcpu_ioctl_nmi(vcpu);
1806 case KVM_SET_CPUID: {
1807 struct kvm_cpuid __user *cpuid_arg = argp;
1808 struct kvm_cpuid cpuid;
1811 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1813 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1818 case KVM_SET_CPUID2: {
1819 struct kvm_cpuid2 __user *cpuid_arg = argp;
1820 struct kvm_cpuid2 cpuid;
1823 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1825 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1826 cpuid_arg->entries);
1831 case KVM_GET_CPUID2: {
1832 struct kvm_cpuid2 __user *cpuid_arg = argp;
1833 struct kvm_cpuid2 cpuid;
1836 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1838 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1839 cpuid_arg->entries);
1843 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1849 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1852 r = msr_io(vcpu, argp, do_set_msr, 0);
1854 case KVM_TPR_ACCESS_REPORTING: {
1855 struct kvm_tpr_access_ctl tac;
1858 if (copy_from_user(&tac, argp, sizeof tac))
1860 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1864 if (copy_to_user(argp, &tac, sizeof tac))
1869 case KVM_SET_VAPIC_ADDR: {
1870 struct kvm_vapic_addr va;
1873 if (!irqchip_in_kernel(vcpu->kvm))
1876 if (copy_from_user(&va, argp, sizeof va))
1879 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1882 case KVM_X86_SETUP_MCE: {
1886 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1888 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1891 case KVM_X86_SET_MCE: {
1892 struct kvm_x86_mce mce;
1895 if (copy_from_user(&mce, argp, sizeof mce))
1897 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1908 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1912 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1914 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1918 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1919 u32 kvm_nr_mmu_pages)
1921 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1924 down_write(&kvm->slots_lock);
1925 spin_lock(&kvm->mmu_lock);
1927 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
1928 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1930 spin_unlock(&kvm->mmu_lock);
1931 up_write(&kvm->slots_lock);
1935 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1937 return kvm->arch.n_alloc_mmu_pages;
1940 gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1943 struct kvm_mem_alias *alias;
1945 for (i = 0; i < kvm->arch.naliases; ++i) {
1946 alias = &kvm->arch.aliases[i];
1947 if (gfn >= alias->base_gfn
1948 && gfn < alias->base_gfn + alias->npages)
1949 return alias->target_gfn + gfn - alias->base_gfn;
1955 * Set a new alias region. Aliases map a portion of physical memory into
1956 * another portion. This is useful for memory windows, for example the PC
1959 static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1960 struct kvm_memory_alias *alias)
1963 struct kvm_mem_alias *p;
1966 /* General sanity checks */
1967 if (alias->memory_size & (PAGE_SIZE - 1))
1969 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1971 if (alias->slot >= KVM_ALIAS_SLOTS)
1973 if (alias->guest_phys_addr + alias->memory_size
1974 < alias->guest_phys_addr)
1976 if (alias->target_phys_addr + alias->memory_size
1977 < alias->target_phys_addr)
1980 down_write(&kvm->slots_lock);
1981 spin_lock(&kvm->mmu_lock);
1983 p = &kvm->arch.aliases[alias->slot];
1984 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1985 p->npages = alias->memory_size >> PAGE_SHIFT;
1986 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1988 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
1989 if (kvm->arch.aliases[n - 1].npages)
1991 kvm->arch.naliases = n;
1993 spin_unlock(&kvm->mmu_lock);
1994 kvm_mmu_zap_all(kvm);
1996 up_write(&kvm->slots_lock);
2004 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2009 switch (chip->chip_id) {
2010 case KVM_IRQCHIP_PIC_MASTER:
2011 memcpy(&chip->chip.pic,
2012 &pic_irqchip(kvm)->pics[0],
2013 sizeof(struct kvm_pic_state));
2015 case KVM_IRQCHIP_PIC_SLAVE:
2016 memcpy(&chip->chip.pic,
2017 &pic_irqchip(kvm)->pics[1],
2018 sizeof(struct kvm_pic_state));
2020 case KVM_IRQCHIP_IOAPIC:
2021 memcpy(&chip->chip.ioapic,
2022 ioapic_irqchip(kvm),
2023 sizeof(struct kvm_ioapic_state));
2032 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2037 switch (chip->chip_id) {
2038 case KVM_IRQCHIP_PIC_MASTER:
2039 spin_lock(&pic_irqchip(kvm)->lock);
2040 memcpy(&pic_irqchip(kvm)->pics[0],
2042 sizeof(struct kvm_pic_state));
2043 spin_unlock(&pic_irqchip(kvm)->lock);
2045 case KVM_IRQCHIP_PIC_SLAVE:
2046 spin_lock(&pic_irqchip(kvm)->lock);
2047 memcpy(&pic_irqchip(kvm)->pics[1],
2049 sizeof(struct kvm_pic_state));
2050 spin_unlock(&pic_irqchip(kvm)->lock);
2052 case KVM_IRQCHIP_IOAPIC:
2053 mutex_lock(&kvm->irq_lock);
2054 memcpy(ioapic_irqchip(kvm),
2056 sizeof(struct kvm_ioapic_state));
2057 mutex_unlock(&kvm->irq_lock);
2063 kvm_pic_update_irq(pic_irqchip(kvm));
2067 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2071 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2072 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2073 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2077 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2081 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2082 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2083 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2084 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2088 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2093 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2094 sizeof(ps->channels));
2095 ps->flags = kvm->arch.vpit->pit_state.flags;
2096 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2100 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2102 int r = 0, start = 0;
2103 u32 prev_legacy, cur_legacy;
2104 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2105 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2106 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2107 if (!prev_legacy && cur_legacy)
2109 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2110 sizeof(kvm->arch.vpit->pit_state.channels));
2111 kvm->arch.vpit->pit_state.flags = ps->flags;
2112 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
2113 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2117 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2118 struct kvm_reinject_control *control)
2120 if (!kvm->arch.vpit)
2122 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2123 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2124 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2129 * Get (and clear) the dirty memory log for a memory slot.
2131 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2132 struct kvm_dirty_log *log)
2136 struct kvm_memory_slot *memslot;
2139 down_write(&kvm->slots_lock);
2141 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2145 /* If nothing is dirty, don't bother messing with page tables. */
2147 spin_lock(&kvm->mmu_lock);
2148 kvm_mmu_slot_remove_write_access(kvm, log->slot);
2149 spin_unlock(&kvm->mmu_lock);
2150 kvm_flush_remote_tlbs(kvm);
2151 memslot = &kvm->memslots[log->slot];
2152 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2153 memset(memslot->dirty_bitmap, 0, n);
2157 up_write(&kvm->slots_lock);
2161 long kvm_arch_vm_ioctl(struct file *filp,
2162 unsigned int ioctl, unsigned long arg)
2164 struct kvm *kvm = filp->private_data;
2165 void __user *argp = (void __user *)arg;
2168 * This union makes it completely explicit to gcc-3.x
2169 * that these two variables' stack usage should be
2170 * combined, not added together.
2173 struct kvm_pit_state ps;
2174 struct kvm_pit_state2 ps2;
2175 struct kvm_memory_alias alias;
2176 struct kvm_pit_config pit_config;
2180 case KVM_SET_TSS_ADDR:
2181 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2185 case KVM_SET_MEMORY_REGION: {
2186 struct kvm_memory_region kvm_mem;
2187 struct kvm_userspace_memory_region kvm_userspace_mem;
2190 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2192 kvm_userspace_mem.slot = kvm_mem.slot;
2193 kvm_userspace_mem.flags = kvm_mem.flags;
2194 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2195 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2196 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2201 case KVM_SET_NR_MMU_PAGES:
2202 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2206 case KVM_GET_NR_MMU_PAGES:
2207 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2209 case KVM_SET_MEMORY_ALIAS:
2211 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
2213 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
2217 case KVM_CREATE_IRQCHIP:
2219 kvm->arch.vpic = kvm_create_pic(kvm);
2220 if (kvm->arch.vpic) {
2221 r = kvm_ioapic_init(kvm);
2223 kfree(kvm->arch.vpic);
2224 kvm->arch.vpic = NULL;
2229 r = kvm_setup_default_irq_routing(kvm);
2231 kfree(kvm->arch.vpic);
2232 kfree(kvm->arch.vioapic);
2236 case KVM_CREATE_PIT:
2237 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2239 case KVM_CREATE_PIT2:
2241 if (copy_from_user(&u.pit_config, argp,
2242 sizeof(struct kvm_pit_config)))
2245 down_write(&kvm->slots_lock);
2248 goto create_pit_unlock;
2250 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
2254 up_write(&kvm->slots_lock);
2256 case KVM_IRQ_LINE_STATUS:
2257 case KVM_IRQ_LINE: {
2258 struct kvm_irq_level irq_event;
2261 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2263 if (irqchip_in_kernel(kvm)) {
2265 mutex_lock(&kvm->irq_lock);
2266 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2267 irq_event.irq, irq_event.level);
2268 mutex_unlock(&kvm->irq_lock);
2269 if (ioctl == KVM_IRQ_LINE_STATUS) {
2270 irq_event.status = status;
2271 if (copy_to_user(argp, &irq_event,
2279 case KVM_GET_IRQCHIP: {
2280 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2281 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2287 if (copy_from_user(chip, argp, sizeof *chip))
2288 goto get_irqchip_out;
2290 if (!irqchip_in_kernel(kvm))
2291 goto get_irqchip_out;
2292 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
2294 goto get_irqchip_out;
2296 if (copy_to_user(argp, chip, sizeof *chip))
2297 goto get_irqchip_out;
2305 case KVM_SET_IRQCHIP: {
2306 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2307 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2313 if (copy_from_user(chip, argp, sizeof *chip))
2314 goto set_irqchip_out;
2316 if (!irqchip_in_kernel(kvm))
2317 goto set_irqchip_out;
2318 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
2320 goto set_irqchip_out;
2330 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
2333 if (!kvm->arch.vpit)
2335 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
2339 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
2346 if (copy_from_user(&u.ps, argp, sizeof u.ps))
2349 if (!kvm->arch.vpit)
2351 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
2357 case KVM_GET_PIT2: {
2359 if (!kvm->arch.vpit)
2361 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2365 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2370 case KVM_SET_PIT2: {
2372 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2375 if (!kvm->arch.vpit)
2377 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2383 case KVM_REINJECT_CONTROL: {
2384 struct kvm_reinject_control control;
2386 if (copy_from_user(&control, argp, sizeof(control)))
2388 r = kvm_vm_ioctl_reinject(kvm, &control);
2401 static void kvm_init_msr_list(void)
2406 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2407 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2410 msrs_to_save[j] = msrs_to_save[i];
2413 num_msrs_to_save = j;
2416 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2419 if (vcpu->arch.apic &&
2420 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2423 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
2426 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
2428 if (vcpu->arch.apic &&
2429 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2432 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
2435 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2436 struct kvm_vcpu *vcpu)
2439 int r = X86EMUL_CONTINUE;
2442 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2443 unsigned offset = addr & (PAGE_SIZE-1);
2444 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
2447 if (gpa == UNMAPPED_GVA) {
2448 r = X86EMUL_PROPAGATE_FAULT;
2451 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
2453 r = X86EMUL_UNHANDLEABLE;
2465 static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2466 struct kvm_vcpu *vcpu)
2469 int r = X86EMUL_CONTINUE;
2472 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2473 unsigned offset = addr & (PAGE_SIZE-1);
2474 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2477 if (gpa == UNMAPPED_GVA) {
2478 r = X86EMUL_PROPAGATE_FAULT;
2481 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2483 r = X86EMUL_UNHANDLEABLE;
2496 static int emulator_read_emulated(unsigned long addr,
2499 struct kvm_vcpu *vcpu)
2503 if (vcpu->mmio_read_completed) {
2504 memcpy(val, vcpu->mmio_data, bytes);
2505 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2506 vcpu->mmio_phys_addr, *(u64 *)val);
2507 vcpu->mmio_read_completed = 0;
2508 return X86EMUL_CONTINUE;
2511 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2513 /* For APIC access vmexit */
2514 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2517 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2518 == X86EMUL_CONTINUE)
2519 return X86EMUL_CONTINUE;
2520 if (gpa == UNMAPPED_GVA)
2521 return X86EMUL_PROPAGATE_FAULT;
2525 * Is this MMIO handled locally?
2527 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2528 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
2529 return X86EMUL_CONTINUE;
2532 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
2534 vcpu->mmio_needed = 1;
2535 vcpu->mmio_phys_addr = gpa;
2536 vcpu->mmio_size = bytes;
2537 vcpu->mmio_is_write = 0;
2539 return X86EMUL_UNHANDLEABLE;
2542 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
2543 const void *val, int bytes)
2547 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
2550 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
2554 static int emulator_write_emulated_onepage(unsigned long addr,
2557 struct kvm_vcpu *vcpu)
2561 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2563 if (gpa == UNMAPPED_GVA) {
2564 kvm_inject_page_fault(vcpu, addr, 2);
2565 return X86EMUL_PROPAGATE_FAULT;
2568 /* For APIC access vmexit */
2569 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2572 if (emulator_write_phys(vcpu, gpa, val, bytes))
2573 return X86EMUL_CONTINUE;
2576 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
2578 * Is this MMIO handled locally?
2580 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
2581 return X86EMUL_CONTINUE;
2583 vcpu->mmio_needed = 1;
2584 vcpu->mmio_phys_addr = gpa;
2585 vcpu->mmio_size = bytes;
2586 vcpu->mmio_is_write = 1;
2587 memcpy(vcpu->mmio_data, val, bytes);
2589 return X86EMUL_CONTINUE;
2592 int emulator_write_emulated(unsigned long addr,
2595 struct kvm_vcpu *vcpu)
2597 /* Crossing a page boundary? */
2598 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2601 now = -addr & ~PAGE_MASK;
2602 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2603 if (rc != X86EMUL_CONTINUE)
2609 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2611 EXPORT_SYMBOL_GPL(emulator_write_emulated);
2613 static int emulator_cmpxchg_emulated(unsigned long addr,
2617 struct kvm_vcpu *vcpu)
2619 static int reported;
2623 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2625 #ifndef CONFIG_X86_64
2626 /* guests cmpxchg8b have to be emulated atomically */
2633 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2635 if (gpa == UNMAPPED_GVA ||
2636 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2639 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2644 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2646 kaddr = kmap_atomic(page, KM_USER0);
2647 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2648 kunmap_atomic(kaddr, KM_USER0);
2649 kvm_release_page_dirty(page);
2654 return emulator_write_emulated(addr, new, bytes, vcpu);
2657 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2659 return kvm_x86_ops->get_segment_base(vcpu, seg);
2662 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2664 kvm_mmu_invlpg(vcpu, address);
2665 return X86EMUL_CONTINUE;
2668 int emulate_clts(struct kvm_vcpu *vcpu)
2670 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
2671 return X86EMUL_CONTINUE;
2674 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2676 struct kvm_vcpu *vcpu = ctxt->vcpu;
2680 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2681 return X86EMUL_CONTINUE;
2683 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
2684 return X86EMUL_UNHANDLEABLE;
2688 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2690 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2693 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2695 /* FIXME: better handling */
2696 return X86EMUL_UNHANDLEABLE;
2698 return X86EMUL_CONTINUE;
2701 void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2704 unsigned long rip = kvm_rip_read(vcpu);
2705 unsigned long rip_linear;
2707 if (!printk_ratelimit())
2710 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2712 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
2714 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2715 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2717 EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2719 static struct x86_emulate_ops emulate_ops = {
2720 .read_std = kvm_read_guest_virt,
2721 .read_emulated = emulator_read_emulated,
2722 .write_emulated = emulator_write_emulated,
2723 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2726 static void cache_all_regs(struct kvm_vcpu *vcpu)
2728 kvm_register_read(vcpu, VCPU_REGS_RAX);
2729 kvm_register_read(vcpu, VCPU_REGS_RSP);
2730 kvm_register_read(vcpu, VCPU_REGS_RIP);
2731 vcpu->arch.regs_dirty = ~0;
2734 int emulate_instruction(struct kvm_vcpu *vcpu,
2735 struct kvm_run *run,
2741 struct decode_cache *c;
2743 kvm_clear_exception_queue(vcpu);
2744 vcpu->arch.mmio_fault_cr2 = cr2;
2746 * TODO: fix x86_emulate.c to use guest_read/write_register
2747 * instead of direct ->regs accesses, can save hundred cycles
2748 * on Intel for instructions that don't read/change RSP, for
2751 cache_all_regs(vcpu);
2753 vcpu->mmio_is_write = 0;
2754 vcpu->arch.pio.string = 0;
2756 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
2758 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2760 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2761 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2762 vcpu->arch.emulate_ctxt.mode =
2763 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
2764 ? X86EMUL_MODE_REAL : cs_l
2765 ? X86EMUL_MODE_PROT64 : cs_db
2766 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2768 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2770 /* Only allow emulation of specific instructions on #UD
2771 * (namely VMMCALL, sysenter, sysexit, syscall)*/
2772 c = &vcpu->arch.emulate_ctxt.decode;
2773 if (emulation_type & EMULTYPE_TRAP_UD) {
2775 return EMULATE_FAIL;
2777 case 0x01: /* VMMCALL */
2778 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2779 return EMULATE_FAIL;
2781 case 0x34: /* sysenter */
2782 case 0x35: /* sysexit */
2783 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2784 return EMULATE_FAIL;
2786 case 0x05: /* syscall */
2787 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2788 return EMULATE_FAIL;
2791 return EMULATE_FAIL;
2794 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2795 return EMULATE_FAIL;
2798 ++vcpu->stat.insn_emulation;
2800 ++vcpu->stat.insn_emulation_fail;
2801 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2802 return EMULATE_DONE;
2803 return EMULATE_FAIL;
2807 if (emulation_type & EMULTYPE_SKIP) {
2808 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2809 return EMULATE_DONE;
2812 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2813 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2816 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
2818 if (vcpu->arch.pio.string)
2819 return EMULATE_DO_MMIO;
2821 if ((r || vcpu->mmio_is_write) && run) {
2822 run->exit_reason = KVM_EXIT_MMIO;
2823 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2824 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2825 run->mmio.len = vcpu->mmio_size;
2826 run->mmio.is_write = vcpu->mmio_is_write;
2830 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2831 return EMULATE_DONE;
2832 if (!vcpu->mmio_needed) {
2833 kvm_report_emulation_failure(vcpu, "mmio");
2834 return EMULATE_FAIL;
2836 return EMULATE_DO_MMIO;
2839 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
2841 if (vcpu->mmio_is_write) {
2842 vcpu->mmio_needed = 0;
2843 return EMULATE_DO_MMIO;
2846 return EMULATE_DONE;
2848 EXPORT_SYMBOL_GPL(emulate_instruction);
2850 static int pio_copy_data(struct kvm_vcpu *vcpu)
2852 void *p = vcpu->arch.pio_data;
2853 gva_t q = vcpu->arch.pio.guest_gva;
2857 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2858 if (vcpu->arch.pio.in)
2859 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
2861 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2865 int complete_pio(struct kvm_vcpu *vcpu)
2867 struct kvm_pio_request *io = &vcpu->arch.pio;
2874 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2875 memcpy(&val, vcpu->arch.pio_data, io->size);
2876 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2880 r = pio_copy_data(vcpu);
2887 delta *= io->cur_count;
2889 * The size of the register should really depend on
2890 * current address size.
2892 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2894 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
2900 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2902 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2904 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2906 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2910 io->count -= io->cur_count;
2916 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
2918 /* TODO: String I/O for in kernel device */
2921 if (vcpu->arch.pio.in)
2922 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2923 vcpu->arch.pio.size, pd);
2925 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2926 vcpu->arch.pio.size, pd);
2930 static int pio_string_write(struct kvm_vcpu *vcpu)
2932 struct kvm_pio_request *io = &vcpu->arch.pio;
2933 void *pd = vcpu->arch.pio_data;
2936 for (i = 0; i < io->cur_count; i++) {
2937 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2938 io->port, io->size, pd)) {
2947 int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2948 int size, unsigned port)
2952 vcpu->run->exit_reason = KVM_EXIT_IO;
2953 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2954 vcpu->run->io.size = vcpu->arch.pio.size = size;
2955 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2956 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2957 vcpu->run->io.port = vcpu->arch.pio.port = port;
2958 vcpu->arch.pio.in = in;
2959 vcpu->arch.pio.string = 0;
2960 vcpu->arch.pio.down = 0;
2961 vcpu->arch.pio.rep = 0;
2963 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2966 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2967 memcpy(vcpu->arch.pio_data, &val, 4);
2969 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
2975 EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2977 int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2978 int size, unsigned long count, int down,
2979 gva_t address, int rep, unsigned port)
2981 unsigned now, in_page;
2984 vcpu->run->exit_reason = KVM_EXIT_IO;
2985 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2986 vcpu->run->io.size = vcpu->arch.pio.size = size;
2987 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2988 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2989 vcpu->run->io.port = vcpu->arch.pio.port = port;
2990 vcpu->arch.pio.in = in;
2991 vcpu->arch.pio.string = 1;
2992 vcpu->arch.pio.down = down;
2993 vcpu->arch.pio.rep = rep;
2995 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2999 kvm_x86_ops->skip_emulated_instruction(vcpu);
3004 in_page = PAGE_SIZE - offset_in_page(address);
3006 in_page = offset_in_page(address) + size;
3007 now = min(count, (unsigned long)in_page / size);
3012 * String I/O in reverse. Yuck. Kill the guest, fix later.
3014 pr_unimpl(vcpu, "guest string pio down\n");
3015 kvm_inject_gp(vcpu, 0);
3018 vcpu->run->io.count = now;
3019 vcpu->arch.pio.cur_count = now;
3021 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
3022 kvm_x86_ops->skip_emulated_instruction(vcpu);
3024 vcpu->arch.pio.guest_gva = address;
3026 if (!vcpu->arch.pio.in) {
3027 /* string PIO write */
3028 ret = pio_copy_data(vcpu);
3029 if (ret == X86EMUL_PROPAGATE_FAULT) {
3030 kvm_inject_gp(vcpu, 0);
3033 if (ret == 0 && !pio_string_write(vcpu)) {
3035 if (vcpu->arch.pio.count == 0)
3039 /* no string PIO read support yet */
3043 EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3045 static void bounce_off(void *info)
3050 static unsigned int ref_freq;
3051 static unsigned long tsc_khz_ref;
3053 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3056 struct cpufreq_freqs *freq = data;
3058 struct kvm_vcpu *vcpu;
3059 int i, send_ipi = 0;
3062 ref_freq = freq->old;
3064 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3066 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3068 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3070 spin_lock(&kvm_lock);
3071 list_for_each_entry(kvm, &vm_list, vm_list) {
3072 kvm_for_each_vcpu(i, vcpu, kvm) {
3073 if (vcpu->cpu != freq->cpu)
3075 if (!kvm_request_guest_time_update(vcpu))
3077 if (vcpu->cpu != smp_processor_id())
3081 spin_unlock(&kvm_lock);
3083 if (freq->old < freq->new && send_ipi) {
3085 * We upscale the frequency. Must make the guest
3086 * doesn't see old kvmclock values while running with
3087 * the new frequency, otherwise we risk the guest sees
3088 * time go backwards.
3090 * In case we update the frequency for another cpu
3091 * (which might be in guest context) send an interrupt
3092 * to kick the cpu out of guest context. Next time
3093 * guest context is entered kvmclock will be updated,
3094 * so the guest will not see stale values.
3096 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3101 static struct notifier_block kvmclock_cpufreq_notifier_block = {
3102 .notifier_call = kvmclock_cpufreq_notifier
3105 int kvm_arch_init(void *opaque)
3108 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3111 printk(KERN_ERR "kvm: already loaded the other module\n");
3116 if (!ops->cpu_has_kvm_support()) {
3117 printk(KERN_ERR "kvm: no hardware support\n");
3121 if (ops->disabled_by_bios()) {
3122 printk(KERN_ERR "kvm: disabled by bios\n");
3127 r = kvm_mmu_module_init();
3131 kvm_init_msr_list();
3134 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
3135 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3136 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
3137 PT_DIRTY_MASK, PT64_NX_MASK, 0);
3139 for_each_possible_cpu(cpu)
3140 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3141 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3142 tsc_khz_ref = tsc_khz;
3143 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3144 CPUFREQ_TRANSITION_NOTIFIER);
3153 void kvm_arch_exit(void)
3155 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3156 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3157 CPUFREQ_TRANSITION_NOTIFIER);
3159 kvm_mmu_module_exit();
3162 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3164 ++vcpu->stat.halt_exits;
3165 if (irqchip_in_kernel(vcpu->kvm)) {
3166 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3169 vcpu->run->exit_reason = KVM_EXIT_HLT;
3173 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3175 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3178 if (is_long_mode(vcpu))
3181 return a0 | ((gpa_t)a1 << 32);
3184 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3186 unsigned long nr, a0, a1, a2, a3, ret;
3189 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3190 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3191 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3192 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3193 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
3195 trace_kvm_hypercall(nr, a0, a1, a2, a3);
3197 if (!is_long_mode(vcpu)) {
3206 case KVM_HC_VAPIC_POLL_IRQ:
3210 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3216 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3217 ++vcpu->stat.hypercalls;
3220 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3222 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3224 char instruction[3];
3226 unsigned long rip = kvm_rip_read(vcpu);
3230 * Blow out the MMU to ensure that no other VCPU has an active mapping
3231 * to ensure that the updated hypercall appears atomically across all
3234 kvm_mmu_zap_all(vcpu->kvm);
3236 kvm_x86_ops->patch_hypercall(vcpu, instruction);
3237 if (emulator_write_emulated(rip, instruction, 3, vcpu)
3238 != X86EMUL_CONTINUE)
3244 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3246 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3249 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3251 struct descriptor_table dt = { limit, base };
3253 kvm_x86_ops->set_gdt(vcpu, &dt);
3256 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3258 struct descriptor_table dt = { limit, base };
3260 kvm_x86_ops->set_idt(vcpu, &dt);
3263 void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3264 unsigned long *rflags)
3266 kvm_lmsw(vcpu, msw);
3267 *rflags = kvm_x86_ops->get_rflags(vcpu);
3270 unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3272 unsigned long value;
3274 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3277 value = vcpu->arch.cr0;
3280 value = vcpu->arch.cr2;
3283 value = vcpu->arch.cr3;
3286 value = vcpu->arch.cr4;
3289 value = kvm_get_cr8(vcpu);
3292 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3299 void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3300 unsigned long *rflags)
3304 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
3305 *rflags = kvm_x86_ops->get_rflags(vcpu);
3308 vcpu->arch.cr2 = val;
3311 kvm_set_cr3(vcpu, val);
3314 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
3317 kvm_set_cr8(vcpu, val & 0xfUL);
3320 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3324 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3326 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3327 int j, nent = vcpu->arch.cpuid_nent;
3329 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3330 /* when no next entry is found, the current entry[i] is reselected */
3331 for (j = i + 1; ; j = (j + 1) % nent) {
3332 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
3333 if (ej->function == e->function) {
3334 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3338 return 0; /* silence gcc, even though control never reaches here */
3341 /* find an entry with matching function, matching index (if needed), and that
3342 * should be read next (if it's stateful) */
3343 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3344 u32 function, u32 index)
3346 if (e->function != function)
3348 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3350 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3351 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3356 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3357 u32 function, u32 index)
3360 struct kvm_cpuid_entry2 *best = NULL;
3362 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3363 struct kvm_cpuid_entry2 *e;
3365 e = &vcpu->arch.cpuid_entries[i];
3366 if (is_matching_cpuid_entry(e, function, index)) {
3367 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3368 move_to_next_stateful_cpuid_entry(vcpu, i);
3373 * Both basic or both extended?
3375 if (((e->function ^ function) & 0x80000000) == 0)
3376 if (!best || e->function > best->function)
3382 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3384 struct kvm_cpuid_entry2 *best;
3386 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3388 return best->eax & 0xff;
3392 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3394 u32 function, index;
3395 struct kvm_cpuid_entry2 *best;
3397 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3398 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3399 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3400 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3401 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3402 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3403 best = kvm_find_cpuid_entry(vcpu, function, index);
3405 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3406 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3407 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3408 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
3410 kvm_x86_ops->skip_emulated_instruction(vcpu);
3411 trace_kvm_cpuid(function,
3412 kvm_register_read(vcpu, VCPU_REGS_RAX),
3413 kvm_register_read(vcpu, VCPU_REGS_RBX),
3414 kvm_register_read(vcpu, VCPU_REGS_RCX),
3415 kvm_register_read(vcpu, VCPU_REGS_RDX));
3417 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
3420 * Check if userspace requested an interrupt window, and that the
3421 * interrupt window is open.
3423 * No need to exit to userspace if we already have an interrupt queued.
3425 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3426 struct kvm_run *kvm_run)
3428 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
3429 kvm_run->request_interrupt_window &&
3430 kvm_arch_interrupt_allowed(vcpu));
3433 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3434 struct kvm_run *kvm_run)
3436 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
3437 kvm_run->cr8 = kvm_get_cr8(vcpu);
3438 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3439 if (irqchip_in_kernel(vcpu->kvm))
3440 kvm_run->ready_for_interrupt_injection = 1;
3442 kvm_run->ready_for_interrupt_injection =
3443 kvm_arch_interrupt_allowed(vcpu) &&
3444 !kvm_cpu_has_interrupt(vcpu) &&
3445 !kvm_event_needs_reinjection(vcpu);
3448 static void vapic_enter(struct kvm_vcpu *vcpu)
3450 struct kvm_lapic *apic = vcpu->arch.apic;
3453 if (!apic || !apic->vapic_addr)
3456 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3458 vcpu->arch.apic->vapic_page = page;
3461 static void vapic_exit(struct kvm_vcpu *vcpu)
3463 struct kvm_lapic *apic = vcpu->arch.apic;
3465 if (!apic || !apic->vapic_addr)
3468 down_read(&vcpu->kvm->slots_lock);
3469 kvm_release_page_dirty(apic->vapic_page);
3470 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3471 up_read(&vcpu->kvm->slots_lock);
3474 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3478 if (!kvm_x86_ops->update_cr8_intercept)
3481 if (!vcpu->arch.apic->vapic_addr)
3482 max_irr = kvm_lapic_find_highest_irr(vcpu);
3489 tpr = kvm_lapic_get_cr8(vcpu);
3491 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3494 static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3496 /* try to reinject previous events if any */
3497 if (vcpu->arch.nmi_injected) {
3498 kvm_x86_ops->set_nmi(vcpu);
3502 if (vcpu->arch.interrupt.pending) {
3503 kvm_x86_ops->set_irq(vcpu);
3507 /* try to inject new event if pending */
3508 if (vcpu->arch.nmi_pending) {
3509 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3510 vcpu->arch.nmi_pending = false;
3511 vcpu->arch.nmi_injected = true;
3512 kvm_x86_ops->set_nmi(vcpu);
3514 } else if (kvm_cpu_has_interrupt(vcpu)) {
3515 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
3516 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3518 kvm_x86_ops->set_irq(vcpu);
3523 static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3526 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3527 kvm_run->request_interrupt_window;
3530 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3531 kvm_mmu_unload(vcpu);
3533 r = kvm_mmu_reload(vcpu);
3537 if (vcpu->requests) {
3538 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
3539 __kvm_migrate_timers(vcpu);
3540 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3541 kvm_write_guest_time(vcpu);
3542 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3543 kvm_mmu_sync_roots(vcpu);
3544 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3545 kvm_x86_ops->tlb_flush(vcpu);
3546 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3548 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3552 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3553 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3561 kvm_x86_ops->prepare_guest_switch(vcpu);
3562 kvm_load_guest_fpu(vcpu);
3564 local_irq_disable();
3566 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3567 smp_mb__after_clear_bit();
3569 if (vcpu->requests || need_resched() || signal_pending(current)) {
3570 set_bit(KVM_REQ_KICK, &vcpu->requests);
3577 if (vcpu->arch.exception.pending)
3578 __queue_exception(vcpu);
3580 inject_pending_irq(vcpu, kvm_run);
3582 /* enable NMI/IRQ window open exits if needed */
3583 if (vcpu->arch.nmi_pending)
3584 kvm_x86_ops->enable_nmi_window(vcpu);
3585 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3586 kvm_x86_ops->enable_irq_window(vcpu);
3588 if (kvm_lapic_enabled(vcpu)) {
3589 update_cr8_intercept(vcpu);
3590 kvm_lapic_sync_to_vapic(vcpu);
3593 up_read(&vcpu->kvm->slots_lock);
3597 get_debugreg(vcpu->arch.host_dr6, 6);
3598 get_debugreg(vcpu->arch.host_dr7, 7);
3599 if (unlikely(vcpu->arch.switch_db_regs)) {
3600 get_debugreg(vcpu->arch.host_db[0], 0);
3601 get_debugreg(vcpu->arch.host_db[1], 1);
3602 get_debugreg(vcpu->arch.host_db[2], 2);
3603 get_debugreg(vcpu->arch.host_db[3], 3);
3606 set_debugreg(vcpu->arch.eff_db[0], 0);
3607 set_debugreg(vcpu->arch.eff_db[1], 1);
3608 set_debugreg(vcpu->arch.eff_db[2], 2);
3609 set_debugreg(vcpu->arch.eff_db[3], 3);
3612 trace_kvm_entry(vcpu->vcpu_id);
3613 kvm_x86_ops->run(vcpu, kvm_run);
3615 if (unlikely(vcpu->arch.switch_db_regs)) {
3617 set_debugreg(vcpu->arch.host_db[0], 0);
3618 set_debugreg(vcpu->arch.host_db[1], 1);
3619 set_debugreg(vcpu->arch.host_db[2], 2);
3620 set_debugreg(vcpu->arch.host_db[3], 3);
3622 set_debugreg(vcpu->arch.host_dr6, 6);
3623 set_debugreg(vcpu->arch.host_dr7, 7);
3625 set_bit(KVM_REQ_KICK, &vcpu->requests);
3631 * We must have an instruction between local_irq_enable() and
3632 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3633 * the interrupt shadow. The stat.exits increment will do nicely.
3634 * But we need to prevent reordering, hence this barrier():
3642 down_read(&vcpu->kvm->slots_lock);
3645 * Profile KVM exit RIPs:
3647 if (unlikely(prof_on == KVM_PROFILING)) {
3648 unsigned long rip = kvm_rip_read(vcpu);
3649 profile_hit(KVM_PROFILING, (void *)rip);
3653 kvm_lapic_sync_from_vapic(vcpu);
3655 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
3661 static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3665 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3666 pr_debug("vcpu %d received sipi with vector # %x\n",
3667 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3668 kvm_lapic_reset(vcpu);
3669 r = kvm_arch_vcpu_reset(vcpu);
3672 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3675 down_read(&vcpu->kvm->slots_lock);
3680 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
3681 r = vcpu_enter_guest(vcpu, kvm_run);
3683 up_read(&vcpu->kvm->slots_lock);
3684 kvm_vcpu_block(vcpu);
3685 down_read(&vcpu->kvm->slots_lock);
3686 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3688 switch(vcpu->arch.mp_state) {
3689 case KVM_MP_STATE_HALTED:
3690 vcpu->arch.mp_state =
3691 KVM_MP_STATE_RUNNABLE;
3692 case KVM_MP_STATE_RUNNABLE:
3694 case KVM_MP_STATE_SIPI_RECEIVED:
3705 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3706 if (kvm_cpu_has_pending_timer(vcpu))
3707 kvm_inject_pending_timer_irqs(vcpu);
3709 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3711 kvm_run->exit_reason = KVM_EXIT_INTR;
3712 ++vcpu->stat.request_irq_exits;
3714 if (signal_pending(current)) {
3716 kvm_run->exit_reason = KVM_EXIT_INTR;
3717 ++vcpu->stat.signal_exits;
3719 if (need_resched()) {
3720 up_read(&vcpu->kvm->slots_lock);
3722 down_read(&vcpu->kvm->slots_lock);
3726 up_read(&vcpu->kvm->slots_lock);
3727 post_kvm_run_save(vcpu, kvm_run);
3734 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3741 if (vcpu->sigset_active)
3742 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3744 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
3745 kvm_vcpu_block(vcpu);
3746 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
3751 /* re-sync apic's tpr */
3752 if (!irqchip_in_kernel(vcpu->kvm))
3753 kvm_set_cr8(vcpu, kvm_run->cr8);
3755 if (vcpu->arch.pio.cur_count) {
3756 r = complete_pio(vcpu);
3760 #if CONFIG_HAS_IOMEM
3761 if (vcpu->mmio_needed) {
3762 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3763 vcpu->mmio_read_completed = 1;
3764 vcpu->mmio_needed = 0;
3766 down_read(&vcpu->kvm->slots_lock);
3767 r = emulate_instruction(vcpu, kvm_run,
3768 vcpu->arch.mmio_fault_cr2, 0,
3769 EMULTYPE_NO_DECODE);
3770 up_read(&vcpu->kvm->slots_lock);
3771 if (r == EMULATE_DO_MMIO) {
3773 * Read-modify-write. Back to userspace.
3780 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3781 kvm_register_write(vcpu, VCPU_REGS_RAX,
3782 kvm_run->hypercall.ret);
3784 r = __vcpu_run(vcpu, kvm_run);
3787 if (vcpu->sigset_active)
3788 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3794 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3798 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3799 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3800 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3801 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3802 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3803 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3804 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3805 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3806 #ifdef CONFIG_X86_64
3807 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3808 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3809 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3810 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3811 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3812 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3813 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3814 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
3817 regs->rip = kvm_rip_read(vcpu);
3818 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3821 * Don't leak debug flags in case they were set for guest debugging
3823 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3824 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3831 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3835 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3836 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3837 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3838 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3839 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3840 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3841 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3842 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
3843 #ifdef CONFIG_X86_64
3844 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3845 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3846 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3847 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3848 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3849 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3850 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3851 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3855 kvm_rip_write(vcpu, regs->rip);
3856 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3859 vcpu->arch.exception.pending = false;
3866 void kvm_get_segment(struct kvm_vcpu *vcpu,
3867 struct kvm_segment *var, int seg)
3869 kvm_x86_ops->get_segment(vcpu, var, seg);
3872 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3874 struct kvm_segment cs;
3876 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
3880 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3882 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3883 struct kvm_sregs *sregs)
3885 struct descriptor_table dt;
3889 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3890 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3891 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3892 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3893 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3894 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3896 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3897 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3899 kvm_x86_ops->get_idt(vcpu, &dt);
3900 sregs->idt.limit = dt.limit;
3901 sregs->idt.base = dt.base;
3902 kvm_x86_ops->get_gdt(vcpu, &dt);
3903 sregs->gdt.limit = dt.limit;
3904 sregs->gdt.base = dt.base;
3906 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3907 sregs->cr0 = vcpu->arch.cr0;
3908 sregs->cr2 = vcpu->arch.cr2;
3909 sregs->cr3 = vcpu->arch.cr3;
3910 sregs->cr4 = vcpu->arch.cr4;
3911 sregs->cr8 = kvm_get_cr8(vcpu);
3912 sregs->efer = vcpu->arch.shadow_efer;
3913 sregs->apic_base = kvm_get_apic_base(vcpu);
3915 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
3917 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
3918 set_bit(vcpu->arch.interrupt.nr,
3919 (unsigned long *)sregs->interrupt_bitmap);
3926 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3927 struct kvm_mp_state *mp_state)
3930 mp_state->mp_state = vcpu->arch.mp_state;
3935 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3936 struct kvm_mp_state *mp_state)
3939 vcpu->arch.mp_state = mp_state->mp_state;
3944 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3945 struct kvm_segment *var, int seg)
3947 kvm_x86_ops->set_segment(vcpu, var, seg);
3950 static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3951 struct kvm_segment *kvm_desct)
3953 kvm_desct->base = seg_desc->base0;
3954 kvm_desct->base |= seg_desc->base1 << 16;
3955 kvm_desct->base |= seg_desc->base2 << 24;
3956 kvm_desct->limit = seg_desc->limit0;
3957 kvm_desct->limit |= seg_desc->limit << 16;
3959 kvm_desct->limit <<= 12;
3960 kvm_desct->limit |= 0xfff;
3962 kvm_desct->selector = selector;
3963 kvm_desct->type = seg_desc->type;
3964 kvm_desct->present = seg_desc->p;
3965 kvm_desct->dpl = seg_desc->dpl;
3966 kvm_desct->db = seg_desc->d;
3967 kvm_desct->s = seg_desc->s;
3968 kvm_desct->l = seg_desc->l;
3969 kvm_desct->g = seg_desc->g;
3970 kvm_desct->avl = seg_desc->avl;
3972 kvm_desct->unusable = 1;
3974 kvm_desct->unusable = 0;
3975 kvm_desct->padding = 0;
3978 static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3980 struct descriptor_table *dtable)
3982 if (selector & 1 << 2) {
3983 struct kvm_segment kvm_seg;
3985 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
3987 if (kvm_seg.unusable)
3990 dtable->limit = kvm_seg.limit;
3991 dtable->base = kvm_seg.base;
3994 kvm_x86_ops->get_gdt(vcpu, dtable);
3997 /* allowed just for 8 bytes segments */
3998 static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3999 struct desc_struct *seg_desc)
4002 struct descriptor_table dtable;
4003 u16 index = selector >> 3;
4005 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4007 if (dtable.limit < index * 8 + 7) {
4008 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4011 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4013 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
4016 /* allowed just for 8 bytes segments */
4017 static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4018 struct desc_struct *seg_desc)
4021 struct descriptor_table dtable;
4022 u16 index = selector >> 3;
4024 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4026 if (dtable.limit < index * 8 + 7)
4028 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4030 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
4033 static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
4034 struct desc_struct *seg_desc)
4038 base_addr = seg_desc->base0;
4039 base_addr |= (seg_desc->base1 << 16);
4040 base_addr |= (seg_desc->base2 << 24);
4042 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
4045 static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4047 struct kvm_segment kvm_seg;
4049 kvm_get_segment(vcpu, &kvm_seg, seg);
4050 return kvm_seg.selector;
4053 static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4055 struct kvm_segment *kvm_seg)
4057 struct desc_struct seg_desc;
4059 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4061 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4065 static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
4067 struct kvm_segment segvar = {
4068 .base = selector << 4,
4070 .selector = selector,
4081 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4085 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4086 int type_bits, int seg)
4088 struct kvm_segment kvm_seg;
4090 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4091 return kvm_load_realmode_segment(vcpu, selector, seg);
4092 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4094 kvm_seg.type |= type_bits;
4096 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4097 seg != VCPU_SREG_LDTR)
4099 kvm_seg.unusable = 1;
4101 kvm_set_segment(vcpu, &kvm_seg, seg);
4105 static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4106 struct tss_segment_32 *tss)
4108 tss->cr3 = vcpu->arch.cr3;
4109 tss->eip = kvm_rip_read(vcpu);
4110 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
4111 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4112 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4113 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4114 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4115 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4116 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4117 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4118 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4119 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4120 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4121 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4122 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4123 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4124 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4125 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4128 static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4129 struct tss_segment_32 *tss)
4131 kvm_set_cr3(vcpu, tss->cr3);
4133 kvm_rip_write(vcpu, tss->eip);
4134 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4136 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4137 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4138 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4139 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4140 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4141 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4142 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4143 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
4145 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
4148 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4151 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4154 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4157 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4160 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
4163 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
4168 static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4169 struct tss_segment_16 *tss)
4171 tss->ip = kvm_rip_read(vcpu);
4172 tss->flag = kvm_x86_ops->get_rflags(vcpu);
4173 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4174 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4175 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4176 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4177 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4178 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4179 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4180 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
4182 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4183 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4184 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4185 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4186 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4187 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4190 static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4191 struct tss_segment_16 *tss)
4193 kvm_rip_write(vcpu, tss->ip);
4194 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
4195 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4196 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4197 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4198 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4199 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4200 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4201 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4202 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
4204 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
4207 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4210 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4213 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4216 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4221 static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
4222 u16 old_tss_sel, u32 old_tss_base,
4223 struct desc_struct *nseg_desc)
4225 struct tss_segment_16 tss_segment_16;
4228 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4229 sizeof tss_segment_16))
4232 save_state_to_tss16(vcpu, &tss_segment_16);
4234 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4235 sizeof tss_segment_16))
4238 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4239 &tss_segment_16, sizeof tss_segment_16))
4242 if (old_tss_sel != 0xffff) {
4243 tss_segment_16.prev_task_link = old_tss_sel;
4245 if (kvm_write_guest(vcpu->kvm,
4246 get_tss_base_addr(vcpu, nseg_desc),
4247 &tss_segment_16.prev_task_link,
4248 sizeof tss_segment_16.prev_task_link))
4252 if (load_state_from_tss16(vcpu, &tss_segment_16))
4260 static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
4261 u16 old_tss_sel, u32 old_tss_base,
4262 struct desc_struct *nseg_desc)
4264 struct tss_segment_32 tss_segment_32;
4267 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4268 sizeof tss_segment_32))
4271 save_state_to_tss32(vcpu, &tss_segment_32);
4273 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4274 sizeof tss_segment_32))
4277 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4278 &tss_segment_32, sizeof tss_segment_32))
4281 if (old_tss_sel != 0xffff) {
4282 tss_segment_32.prev_task_link = old_tss_sel;
4284 if (kvm_write_guest(vcpu->kvm,
4285 get_tss_base_addr(vcpu, nseg_desc),
4286 &tss_segment_32.prev_task_link,
4287 sizeof tss_segment_32.prev_task_link))
4291 if (load_state_from_tss32(vcpu, &tss_segment_32))
4299 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4301 struct kvm_segment tr_seg;
4302 struct desc_struct cseg_desc;
4303 struct desc_struct nseg_desc;
4305 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4306 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
4308 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
4310 /* FIXME: Handle errors. Failure to read either TSS or their
4311 * descriptors should generate a pagefault.
4313 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4316 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
4319 if (reason != TASK_SWITCH_IRET) {
4322 cpl = kvm_x86_ops->get_cpl(vcpu);
4323 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4324 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4329 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4330 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4334 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
4335 cseg_desc.type &= ~(1 << 1); //clear the B flag
4336 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
4339 if (reason == TASK_SWITCH_IRET) {
4340 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4341 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4344 /* set back link to prev task only if NT bit is set in eflags
4345 note that old_tss_sel is not used afetr this point */
4346 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4347 old_tss_sel = 0xffff;
4349 /* set back link to prev task only if NT bit is set in eflags
4350 note that old_tss_sel is not used afetr this point */
4351 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4352 old_tss_sel = 0xffff;
4354 if (nseg_desc.type & 8)
4355 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4356 old_tss_base, &nseg_desc);
4358 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4359 old_tss_base, &nseg_desc);
4361 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4362 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4363 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4366 if (reason != TASK_SWITCH_IRET) {
4367 nseg_desc.type |= (1 << 1);
4368 save_guest_segment_descriptor(vcpu, tss_selector,
4372 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4373 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4375 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
4379 EXPORT_SYMBOL_GPL(kvm_task_switch);
4381 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4382 struct kvm_sregs *sregs)
4384 int mmu_reset_needed = 0;
4385 int pending_vec, max_bits;
4386 struct descriptor_table dt;
4390 dt.limit = sregs->idt.limit;
4391 dt.base = sregs->idt.base;
4392 kvm_x86_ops->set_idt(vcpu, &dt);
4393 dt.limit = sregs->gdt.limit;
4394 dt.base = sregs->gdt.base;
4395 kvm_x86_ops->set_gdt(vcpu, &dt);
4397 vcpu->arch.cr2 = sregs->cr2;
4398 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
4399 vcpu->arch.cr3 = sregs->cr3;
4401 kvm_set_cr8(vcpu, sregs->cr8);
4403 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4404 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4405 kvm_set_apic_base(vcpu, sregs->apic_base);
4407 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4409 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4410 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4411 vcpu->arch.cr0 = sregs->cr0;
4413 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
4414 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4415 if (!is_long_mode(vcpu) && is_pae(vcpu))
4416 load_pdptrs(vcpu, vcpu->arch.cr3);
4418 if (mmu_reset_needed)
4419 kvm_mmu_reset_context(vcpu);
4421 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4422 pending_vec = find_first_bit(
4423 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4424 if (pending_vec < max_bits) {
4425 kvm_queue_interrupt(vcpu, pending_vec, false);
4426 pr_debug("Set back pending irq %d\n", pending_vec);
4427 if (irqchip_in_kernel(vcpu->kvm))
4428 kvm_pic_clear_isr_ack(vcpu->kvm);
4431 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4432 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4433 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4434 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4435 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4436 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
4438 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4439 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
4441 /* Older userspace won't unhalt the vcpu on reset. */
4442 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
4443 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4444 !(vcpu->arch.cr0 & X86_CR0_PE))
4445 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4452 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4453 struct kvm_guest_debug *dbg)
4459 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4460 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4461 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4462 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4463 vcpu->arch.switch_db_regs =
4464 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4466 for (i = 0; i < KVM_NR_DB_REGS; i++)
4467 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4468 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4471 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4473 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4474 kvm_queue_exception(vcpu, DB_VECTOR);
4475 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4476 kvm_queue_exception(vcpu, BP_VECTOR);
4484 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4485 * we have asm/x86/processor.h
4496 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4497 #ifdef CONFIG_X86_64
4498 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4500 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4505 * Translate a guest virtual address to a guest physical address.
4507 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4508 struct kvm_translation *tr)
4510 unsigned long vaddr = tr->linear_address;
4514 down_read(&vcpu->kvm->slots_lock);
4515 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
4516 up_read(&vcpu->kvm->slots_lock);
4517 tr->physical_address = gpa;
4518 tr->valid = gpa != UNMAPPED_GVA;
4526 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4528 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4532 memcpy(fpu->fpr, fxsave->st_space, 128);
4533 fpu->fcw = fxsave->cwd;
4534 fpu->fsw = fxsave->swd;
4535 fpu->ftwx = fxsave->twd;
4536 fpu->last_opcode = fxsave->fop;
4537 fpu->last_ip = fxsave->rip;
4538 fpu->last_dp = fxsave->rdp;
4539 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4546 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4548 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4552 memcpy(fxsave->st_space, fpu->fpr, 128);
4553 fxsave->cwd = fpu->fcw;
4554 fxsave->swd = fpu->fsw;
4555 fxsave->twd = fpu->ftwx;
4556 fxsave->fop = fpu->last_opcode;
4557 fxsave->rip = fpu->last_ip;
4558 fxsave->rdp = fpu->last_dp;
4559 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4566 void fx_init(struct kvm_vcpu *vcpu)
4568 unsigned after_mxcsr_mask;
4571 * Touch the fpu the first time in non atomic context as if
4572 * this is the first fpu instruction the exception handler
4573 * will fire before the instruction returns and it'll have to
4574 * allocate ram with GFP_KERNEL.
4577 kvm_fx_save(&vcpu->arch.host_fx_image);
4579 /* Initialize guest FPU by resetting ours and saving into guest's */
4581 kvm_fx_save(&vcpu->arch.host_fx_image);
4583 kvm_fx_save(&vcpu->arch.guest_fx_image);
4584 kvm_fx_restore(&vcpu->arch.host_fx_image);
4587 vcpu->arch.cr0 |= X86_CR0_ET;
4588 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
4589 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4590 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
4591 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4593 EXPORT_SYMBOL_GPL(fx_init);
4595 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4597 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4600 vcpu->guest_fpu_loaded = 1;
4601 kvm_fx_save(&vcpu->arch.host_fx_image);
4602 kvm_fx_restore(&vcpu->arch.guest_fx_image);
4604 EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4606 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4608 if (!vcpu->guest_fpu_loaded)
4611 vcpu->guest_fpu_loaded = 0;
4612 kvm_fx_save(&vcpu->arch.guest_fx_image);
4613 kvm_fx_restore(&vcpu->arch.host_fx_image);
4614 ++vcpu->stat.fpu_reload;
4616 EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
4618 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4620 if (vcpu->arch.time_page) {
4621 kvm_release_page_dirty(vcpu->arch.time_page);
4622 vcpu->arch.time_page = NULL;
4625 kvm_x86_ops->vcpu_free(vcpu);
4628 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4631 return kvm_x86_ops->vcpu_create(kvm, id);
4634 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4638 /* We do fxsave: this must be aligned. */
4639 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
4641 vcpu->arch.mtrr_state.have_fixed = 1;
4643 r = kvm_arch_vcpu_reset(vcpu);
4645 r = kvm_mmu_setup(vcpu);
4652 kvm_x86_ops->vcpu_free(vcpu);
4656 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
4659 kvm_mmu_unload(vcpu);
4662 kvm_x86_ops->vcpu_free(vcpu);
4665 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4667 vcpu->arch.nmi_pending = false;
4668 vcpu->arch.nmi_injected = false;
4670 vcpu->arch.switch_db_regs = 0;
4671 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4672 vcpu->arch.dr6 = DR6_FIXED_1;
4673 vcpu->arch.dr7 = DR7_FIXED_1;
4675 return kvm_x86_ops->vcpu_reset(vcpu);
4678 void kvm_arch_hardware_enable(void *garbage)
4680 kvm_x86_ops->hardware_enable(garbage);
4683 void kvm_arch_hardware_disable(void *garbage)
4685 kvm_x86_ops->hardware_disable(garbage);
4688 int kvm_arch_hardware_setup(void)
4690 return kvm_x86_ops->hardware_setup();
4693 void kvm_arch_hardware_unsetup(void)
4695 kvm_x86_ops->hardware_unsetup();
4698 void kvm_arch_check_processor_compat(void *rtn)
4700 kvm_x86_ops->check_processor_compatibility(rtn);
4703 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4709 BUG_ON(vcpu->kvm == NULL);
4712 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4713 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
4714 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4716 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
4718 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4723 vcpu->arch.pio_data = page_address(page);
4725 r = kvm_mmu_create(vcpu);
4727 goto fail_free_pio_data;
4729 if (irqchip_in_kernel(kvm)) {
4730 r = kvm_create_lapic(vcpu);
4732 goto fail_mmu_destroy;
4735 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4737 if (!vcpu->arch.mce_banks) {
4739 goto fail_mmu_destroy;
4741 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4746 kvm_mmu_destroy(vcpu);
4748 free_page((unsigned long)vcpu->arch.pio_data);
4753 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4755 kvm_free_lapic(vcpu);
4756 down_read(&vcpu->kvm->slots_lock);
4757 kvm_mmu_destroy(vcpu);
4758 up_read(&vcpu->kvm->slots_lock);
4759 free_page((unsigned long)vcpu->arch.pio_data);
4762 struct kvm *kvm_arch_create_vm(void)
4764 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4767 return ERR_PTR(-ENOMEM);
4769 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4770 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
4772 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4773 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4775 rdtscll(kvm->arch.vm_init_tsc);
4780 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4783 kvm_mmu_unload(vcpu);
4787 static void kvm_free_vcpus(struct kvm *kvm)
4790 struct kvm_vcpu *vcpu;
4793 * Unpin any mmu pages first.
4795 kvm_for_each_vcpu(i, vcpu, kvm)
4796 kvm_unload_vcpu_mmu(vcpu);
4797 kvm_for_each_vcpu(i, vcpu, kvm)
4798 kvm_arch_vcpu_free(vcpu);
4800 mutex_lock(&kvm->lock);
4801 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4802 kvm->vcpus[i] = NULL;
4804 atomic_set(&kvm->online_vcpus, 0);
4805 mutex_unlock(&kvm->lock);
4808 void kvm_arch_sync_events(struct kvm *kvm)
4810 kvm_free_all_assigned_devices(kvm);
4813 void kvm_arch_destroy_vm(struct kvm *kvm)
4815 kvm_iommu_unmap_guest(kvm);
4817 kfree(kvm->arch.vpic);
4818 kfree(kvm->arch.vioapic);
4819 kvm_free_vcpus(kvm);
4820 kvm_free_physmem(kvm);
4821 if (kvm->arch.apic_access_page)
4822 put_page(kvm->arch.apic_access_page);
4823 if (kvm->arch.ept_identity_pagetable)
4824 put_page(kvm->arch.ept_identity_pagetable);
4828 int kvm_arch_set_memory_region(struct kvm *kvm,
4829 struct kvm_userspace_memory_region *mem,
4830 struct kvm_memory_slot old,
4833 int npages = mem->memory_size >> PAGE_SHIFT;
4834 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4836 /*To keep backward compatibility with older userspace,
4837 *x86 needs to hanlde !user_alloc case.
4840 if (npages && !old.rmap) {
4841 unsigned long userspace_addr;
4843 down_write(¤t->mm->mmap_sem);
4844 userspace_addr = do_mmap(NULL, 0,
4846 PROT_READ | PROT_WRITE,
4847 MAP_PRIVATE | MAP_ANONYMOUS,
4849 up_write(¤t->mm->mmap_sem);
4851 if (IS_ERR((void *)userspace_addr))
4852 return PTR_ERR((void *)userspace_addr);
4854 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4855 spin_lock(&kvm->mmu_lock);
4856 memslot->userspace_addr = userspace_addr;
4857 spin_unlock(&kvm->mmu_lock);
4859 if (!old.user_alloc && old.rmap) {
4862 down_write(¤t->mm->mmap_sem);
4863 ret = do_munmap(current->mm, old.userspace_addr,
4864 old.npages * PAGE_SIZE);
4865 up_write(¤t->mm->mmap_sem);
4868 "kvm_vm_ioctl_set_memory_region: "
4869 "failed to munmap memory\n");
4874 spin_lock(&kvm->mmu_lock);
4875 if (!kvm->arch.n_requested_mmu_pages) {
4876 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4877 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4880 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4881 spin_unlock(&kvm->mmu_lock);
4882 kvm_flush_remote_tlbs(kvm);
4887 void kvm_arch_flush_shadow(struct kvm *kvm)
4889 kvm_mmu_zap_all(kvm);
4890 kvm_reload_remote_mmus(kvm);
4893 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4895 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4896 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4897 || vcpu->arch.nmi_pending;
4900 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4903 int cpu = vcpu->cpu;
4905 if (waitqueue_active(&vcpu->wq)) {
4906 wake_up_interruptible(&vcpu->wq);
4907 ++vcpu->stat.halt_wakeup;
4911 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4912 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4913 smp_send_reschedule(cpu);
4917 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4919 return kvm_x86_ops->interrupt_allowed(vcpu);
4922 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4923 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4924 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4925 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4926 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);