SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include "kvm_cache_regs.h"
  29 #include "x86.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33 #include <asm/vmx.h>
  34 #include <asm/virtext.h>
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 static int __read_mostly bypass_guest_pf = 1;
  42 module_param(bypass_guest_pf, bool, S_IRUGO);
  43
  44 static int __read_mostly enable_vpid = 1;
  45 module_param_named(vpid, enable_vpid, bool, 0444);
  46
  47 static int __read_mostly flexpriority_enabled = 1;
  48 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  49
  50 static int __read_mostly enable_ept = 1;
  51 module_param_named(ept, enable_ept, bool, S_IRUGO);
  52
  53 static int __read_mostly emulate_invalid_guest_state = 0;
  54 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  55
  56 struct vmcs {
  57         u32 revision_id;
  58         u32 abort;
  59         char data[0];
  60 };
  61
  62 struct vcpu_vmx {
  63         struct kvm_vcpu       vcpu;
  64         struct list_head      local_vcpus_link;
  65         unsigned long         host_rsp;
  66         int                   launched;
  67         u8                    fail;
  68         u32                   idt_vectoring_info;
  69         struct kvm_msr_entry *guest_msrs;
  70         struct kvm_msr_entry *host_msrs;
  71         int                   nmsrs;
  72         int                   save_nmsrs;
  73         int                   msr_offset_efer;
  74 #ifdef CONFIG_X86_64
  75         int                   msr_offset_kernel_gs_base;
  76 #endif
  77         struct vmcs          *vmcs;
  78         struct {
  79                 int           loaded;
  80                 u16           fs_sel, gs_sel, ldt_sel;
  81                 int           gs_ldt_reload_needed;
  82                 int           fs_reload_needed;
  83                 int           guest_efer_loaded;
  84         } host_state;
  85         struct {
  86                 struct {
  87                         bool pending;
  88                         u8 vector;
  89                         unsigned rip;
  90                 } irq;
  91         } rmode;
  92         int vpid;
  93         bool emulation_required;
  94         enum emulation_result invalid_state_emulation_result;
  95
  96         /* Support for vnmi-less CPUs */
  97         int soft_vnmi_blocked;
  98         ktime_t entry_time;
  99         s64 vnmi_blocked_time;
 100 };
 101
 102 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 103 {
 104         return container_of(vcpu, struct vcpu_vmx, vcpu);
 105 }
 106
 107 static int init_rmode(struct kvm *kvm);
 108 static u64 construct_eptp(unsigned long root_hpa);
 109
 110 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 111 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 112 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 113
 114 static unsigned long *vmx_io_bitmap_a;
 115 static unsigned long *vmx_io_bitmap_b;
 116 static unsigned long *vmx_msr_bitmap_legacy;
 117 static unsigned long *vmx_msr_bitmap_longmode;
 118
 119 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 120 static DEFINE_SPINLOCK(vmx_vpid_lock);
 121
 122 static struct vmcs_config {
 123         int size;
 124         int order;
 125         u32 revision_id;
 126         u32 pin_based_exec_ctrl;
 127         u32 cpu_based_exec_ctrl;
 128         u32 cpu_based_2nd_exec_ctrl;
 129         u32 vmexit_ctrl;
 130         u32 vmentry_ctrl;
 131 } vmcs_config;
 132
 133 static struct vmx_capability {
 134         u32 ept;
 135         u32 vpid;
 136 } vmx_capability;
 137
 138 #define VMX_SEGMENT_FIELD(seg)                                  \
 139         [VCPU_SREG_##seg] = {                                   \
 140                 .selector = GUEST_##seg##_SELECTOR,             \
 141                 .base = GUEST_##seg##_BASE,                     \
 142                 .limit = GUEST_##seg##_LIMIT,                   \
 143                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 144         }
 145
 146 static struct kvm_vmx_segment_field {
 147         unsigned selector;
 148         unsigned base;
 149         unsigned limit;
 150         unsigned ar_bytes;
 151 } kvm_vmx_segment_fields[] = {
 152         VMX_SEGMENT_FIELD(CS),
 153         VMX_SEGMENT_FIELD(DS),
 154         VMX_SEGMENT_FIELD(ES),
 155         VMX_SEGMENT_FIELD(FS),
 156         VMX_SEGMENT_FIELD(GS),
 157         VMX_SEGMENT_FIELD(SS),
 158         VMX_SEGMENT_FIELD(TR),
 159         VMX_SEGMENT_FIELD(LDTR),
 160 };
 161
 162 /*
 163  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 164  * away by decrementing the array size.
 165  */
 166 static const u32 vmx_msr_index[] = {
 167 #ifdef CONFIG_X86_64
 168         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 169 #endif
 170         MSR_EFER, MSR_K6_STAR,
 171 };
 172 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 173
 174 static void load_msrs(struct kvm_msr_entry *e, int n)
 175 {
 176         int i;
 177
 178         for (i = 0; i < n; ++i)
 179                 wrmsrl(e[i].index, e[i].data);
 180 }
 181
 182 static void save_msrs(struct kvm_msr_entry *e, int n)
 183 {
 184         int i;
 185
 186         for (i = 0; i < n; ++i)
 187                 rdmsrl(e[i].index, e[i].data);
 188 }
 189
 190 static inline int is_page_fault(u32 intr_info)
 191 {
 192         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 193                              INTR_INFO_VALID_MASK)) ==
 194                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 195 }
 196
 197 static inline int is_no_device(u32 intr_info)
 198 {
 199         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 200                              INTR_INFO_VALID_MASK)) ==
 201                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 202 }
 203
 204 static inline int is_invalid_opcode(u32 intr_info)
 205 {
 206         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 207                              INTR_INFO_VALID_MASK)) ==
 208                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 209 }
 210
 211 static inline int is_external_interrupt(u32 intr_info)
 212 {
 213         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 214                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 215 }
 216
 217 static inline int cpu_has_vmx_msr_bitmap(void)
 218 {
 219         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 220 }
 221
 222 static inline int cpu_has_vmx_tpr_shadow(void)
 223 {
 224         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 225 }
 226
 227 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 228 {
 229         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 230 }
 231
 232 static inline int cpu_has_secondary_exec_ctrls(void)
 233 {
 234         return (vmcs_config.cpu_based_exec_ctrl &
 235                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 236 }
 237
 238 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 239 {
 240         return flexpriority_enabled
 241                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 242                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 243 }
 244
 245 static inline int cpu_has_vmx_invept_individual_addr(void)
 246 {
 247         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 248 }
 249
 250 static inline int cpu_has_vmx_invept_context(void)
 251 {
 252         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 253 }
 254
 255 static inline int cpu_has_vmx_invept_global(void)
 256 {
 257         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 258 }
 259
 260 static inline int cpu_has_vmx_ept(void)
 261 {
 262         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 263                 SECONDARY_EXEC_ENABLE_EPT);
 264 }
 265
 266 static inline int vm_need_ept(void)
 267 {
 268         return (cpu_has_vmx_ept() && enable_ept);
 269 }
 270
 271 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 272 {
 273         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 274                 (irqchip_in_kernel(kvm)));
 275 }
 276
 277 static inline int cpu_has_vmx_vpid(void)
 278 {
 279         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 280                 SECONDARY_EXEC_ENABLE_VPID);
 281 }
 282
 283 static inline int cpu_has_virtual_nmis(void)
 284 {
 285         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 286 }
 287
 288 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 289 {
 290         int i;
 291
 292         for (i = 0; i < vmx->nmsrs; ++i)
 293                 if (vmx->guest_msrs[i].index == msr)
 294                         return i;
 295         return -1;
 296 }
 297
 298 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 299 {
 300     struct {
 301         u64 vpid : 16;
 302         u64 rsvd : 48;
 303         u64 gva;
 304     } operand = { vpid, 0, gva };
 305
 306     asm volatile (__ex(ASM_VMX_INVVPID)
 307                   /* CF==1 or ZF==1 --> rc = -1 */
 308                   "; ja 1f ; ud2 ; 1:"
 309                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 310 }
 311
 312 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 313 {
 314         struct {
 315                 u64 eptp, gpa;
 316         } operand = {eptp, gpa};
 317
 318         asm volatile (__ex(ASM_VMX_INVEPT)
 319                         /* CF==1 or ZF==1 --> rc = -1 */
 320                         "; ja 1f ; ud2 ; 1:\n"
 321                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 322 }
 323
 324 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 325 {
 326         int i;
 327
 328         i = __find_msr_index(vmx, msr);
 329         if (i >= 0)
 330                 return &vmx->guest_msrs[i];
 331         return NULL;
 332 }
 333
 334 static void vmcs_clear(struct vmcs *vmcs)
 335 {
 336         u64 phys_addr = __pa(vmcs);
 337         u8 error;
 338
 339         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 340                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 341                       : "cc", "memory");
 342         if (error)
 343                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 344                        vmcs, phys_addr);
 345 }
 346
 347 static void __vcpu_clear(void *arg)
 348 {
 349         struct vcpu_vmx *vmx = arg;
 350         int cpu = raw_smp_processor_id();
 351
 352         if (vmx->vcpu.cpu == cpu)
 353                 vmcs_clear(vmx->vmcs);
 354         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 355                 per_cpu(current_vmcs, cpu) = NULL;
 356         rdtscll(vmx->vcpu.arch.host_tsc);
 357         list_del(&vmx->local_vcpus_link);
 358         vmx->vcpu.cpu = -1;
 359         vmx->launched = 0;
 360 }
 361
 362 static void vcpu_clear(struct vcpu_vmx *vmx)
 363 {
 364         if (vmx->vcpu.cpu == -1)
 365                 return;
 366         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 367 }
 368
 369 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 370 {
 371         if (vmx->vpid == 0)
 372                 return;
 373
 374         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 375 }
 376
 377 static inline void ept_sync_global(void)
 378 {
 379         if (cpu_has_vmx_invept_global())
 380                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 381 }
 382
 383 static inline void ept_sync_context(u64 eptp)
 384 {
 385         if (vm_need_ept()) {
 386                 if (cpu_has_vmx_invept_context())
 387                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 388                 else
 389                         ept_sync_global();
 390         }
 391 }
 392
 393 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 394 {
 395         if (vm_need_ept()) {
 396                 if (cpu_has_vmx_invept_individual_addr())
 397                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 398                                         eptp, gpa);
 399                 else
 400                         ept_sync_context(eptp);
 401         }
 402 }
 403
 404 static unsigned long vmcs_readl(unsigned long field)
 405 {
 406         unsigned long value;
 407
 408         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 409                       : "=a"(value) : "d"(field) : "cc");
 410         return value;
 411 }
 412
 413 static u16 vmcs_read16(unsigned long field)
 414 {
 415         return vmcs_readl(field);
 416 }
 417
 418 static u32 vmcs_read32(unsigned long field)
 419 {
 420         return vmcs_readl(field);
 421 }
 422
 423 static u64 vmcs_read64(unsigned long field)
 424 {
 425 #ifdef CONFIG_X86_64
 426         return vmcs_readl(field);
 427 #else
 428         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 429 #endif
 430 }
 431
 432 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 433 {
 434         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 435                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 436         dump_stack();
 437 }
 438
 439 static void vmcs_writel(unsigned long field, unsigned long value)
 440 {
 441         u8 error;
 442
 443         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 444                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 445         if (unlikely(error))
 446                 vmwrite_error(field, value);
 447 }
 448
 449 static void vmcs_write16(unsigned long field, u16 value)
 450 {
 451         vmcs_writel(field, value);
 452 }
 453
 454 static void vmcs_write32(unsigned long field, u32 value)
 455 {
 456         vmcs_writel(field, value);
 457 }
 458
 459 static void vmcs_write64(unsigned long field, u64 value)
 460 {
 461         vmcs_writel(field, value);
 462 #ifndef CONFIG_X86_64
 463         asm volatile ("");
 464         vmcs_writel(field+1, value >> 32);
 465 #endif
 466 }
 467
 468 static void vmcs_clear_bits(unsigned long field, u32 mask)
 469 {
 470         vmcs_writel(field, vmcs_readl(field) & ~mask);
 471 }
 472
 473 static void vmcs_set_bits(unsigned long field, u32 mask)
 474 {
 475         vmcs_writel(field, vmcs_readl(field) | mask);
 476 }
 477
 478 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 479 {
 480         u32 eb;
 481
 482         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 483         if (!vcpu->fpu_active)
 484                 eb |= 1u << NM_VECTOR;
 485         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 486                 if (vcpu->guest_debug &
 487                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 488                         eb |= 1u << DB_VECTOR;
 489                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 490                         eb |= 1u << BP_VECTOR;
 491         }
 492         if (vcpu->arch.rmode.active)
 493                 eb = ~0;
 494         if (vm_need_ept())
 495                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 496         vmcs_write32(EXCEPTION_BITMAP, eb);
 497 }
 498
 499 static void reload_tss(void)
 500 {
 501         /*
 502          * VT restores TR but not its size.  Useless.
 503          */
 504         struct descriptor_table gdt;
 505         struct desc_struct *descs;
 506
 507         kvm_get_gdt(&gdt);
 508         descs = (void *)gdt.base;
 509         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 510         load_TR_desc();
 511 }
 512
 513 static void load_transition_efer(struct vcpu_vmx *vmx)
 514 {
 515         int efer_offset = vmx->msr_offset_efer;
 516         u64 host_efer = vmx->host_msrs[efer_offset].data;
 517         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 518         u64 ignore_bits;
 519
 520         if (efer_offset < 0)
 521                 return;
 522         /*
 523          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 524          * outside long mode
 525          */
 526         ignore_bits = EFER_NX | EFER_SCE;
 527 #ifdef CONFIG_X86_64
 528         ignore_bits |= EFER_LMA | EFER_LME;
 529         /* SCE is meaningful only in long mode on Intel */
 530         if (guest_efer & EFER_LMA)
 531                 ignore_bits &= ~(u64)EFER_SCE;
 532 #endif
 533         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 534                 return;
 535
 536         vmx->host_state.guest_efer_loaded = 1;
 537         guest_efer &= ~ignore_bits;
 538         guest_efer |= host_efer & ignore_bits;
 539         wrmsrl(MSR_EFER, guest_efer);
 540         vmx->vcpu.stat.efer_reload++;
 541 }
 542
 543 static void reload_host_efer(struct vcpu_vmx *vmx)
 544 {
 545         if (vmx->host_state.guest_efer_loaded) {
 546                 vmx->host_state.guest_efer_loaded = 0;
 547                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 548         }
 549 }
 550
 551 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 552 {
 553         struct vcpu_vmx *vmx = to_vmx(vcpu);
 554
 555         if (vmx->host_state.loaded)
 556                 return;
 557
 558         vmx->host_state.loaded = 1;
 559         /*
 560          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 561          * allow segment selectors with cpl > 0 or ti == 1.
 562          */
 563         vmx->host_state.ldt_sel = kvm_read_ldt();
 564         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 565         vmx->host_state.fs_sel = kvm_read_fs();
 566         if (!(vmx->host_state.fs_sel & 7)) {
 567                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 568                 vmx->host_state.fs_reload_needed = 0;
 569         } else {
 570                 vmcs_write16(HOST_FS_SELECTOR, 0);
 571                 vmx->host_state.fs_reload_needed = 1;
 572         }
 573         vmx->host_state.gs_sel = kvm_read_gs();
 574         if (!(vmx->host_state.gs_sel & 7))
 575                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 576         else {
 577                 vmcs_write16(HOST_GS_SELECTOR, 0);
 578                 vmx->host_state.gs_ldt_reload_needed = 1;
 579         }
 580
 581 #ifdef CONFIG_X86_64
 582         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 583         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 584 #else
 585         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 586         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 587 #endif
 588
 589 #ifdef CONFIG_X86_64
 590         if (is_long_mode(&vmx->vcpu))
 591                 save_msrs(vmx->host_msrs +
 592                           vmx->msr_offset_kernel_gs_base, 1);
 593
 594 #endif
 595         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 596         load_transition_efer(vmx);
 597 }
 598
 599 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 600 {
 601         unsigned long flags;
 602
 603         if (!vmx->host_state.loaded)
 604                 return;
 605
 606         ++vmx->vcpu.stat.host_state_reload;
 607         vmx->host_state.loaded = 0;
 608         if (vmx->host_state.fs_reload_needed)
 609                 kvm_load_fs(vmx->host_state.fs_sel);
 610         if (vmx->host_state.gs_ldt_reload_needed) {
 611                 kvm_load_ldt(vmx->host_state.ldt_sel);
 612                 /*
 613                  * If we have to reload gs, we must take care to
 614                  * preserve our gs base.
 615                  */
 616                 local_irq_save(flags);
 617                 kvm_load_gs(vmx->host_state.gs_sel);
 618 #ifdef CONFIG_X86_64
 619                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 620 #endif
 621                 local_irq_restore(flags);
 622         }
 623         reload_tss();
 624         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 625         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 626         reload_host_efer(vmx);
 627 }
 628
 629 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 630 {
 631         preempt_disable();
 632         __vmx_load_host_state(vmx);
 633         preempt_enable();
 634 }
 635
 636 /*
 637  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 638  * vcpu mutex is already taken.
 639  */
 640 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 641 {
 642         struct vcpu_vmx *vmx = to_vmx(vcpu);
 643         u64 phys_addr = __pa(vmx->vmcs);
 644         u64 tsc_this, delta, new_offset;
 645
 646         if (vcpu->cpu != cpu) {
 647                 vcpu_clear(vmx);
 648                 kvm_migrate_timers(vcpu);
 649                 vpid_sync_vcpu_all(vmx);
 650                 local_irq_disable();
 651                 list_add(&vmx->local_vcpus_link,
 652                          &per_cpu(vcpus_on_cpu, cpu));
 653                 local_irq_enable();
 654         }
 655
 656         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 657                 u8 error;
 658
 659                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 660                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 661                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 662                               : "cc");
 663                 if (error)
 664                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 665                                vmx->vmcs, phys_addr);
 666         }
 667
 668         if (vcpu->cpu != cpu) {
 669                 struct descriptor_table dt;
 670                 unsigned long sysenter_esp;
 671
 672                 vcpu->cpu = cpu;
 673                 /*
 674                  * Linux uses per-cpu TSS and GDT, so set these when switching
 675                  * processors.
 676                  */
 677                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 678                 kvm_get_gdt(&dt);
 679                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 680
 681                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 682                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 683
 684                 /*
 685                  * Make sure the time stamp counter is monotonous.
 686                  */
 687                 rdtscll(tsc_this);
 688                 if (tsc_this < vcpu->arch.host_tsc) {
 689                         delta = vcpu->arch.host_tsc - tsc_this;
 690                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 691                         vmcs_write64(TSC_OFFSET, new_offset);
 692                 }
 693         }
 694 }
 695
 696 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 697 {
 698         __vmx_load_host_state(to_vmx(vcpu));
 699 }
 700
 701 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 702 {
 703         if (vcpu->fpu_active)
 704                 return;
 705         vcpu->fpu_active = 1;
 706         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 707         if (vcpu->arch.cr0 & X86_CR0_TS)
 708                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 709         update_exception_bitmap(vcpu);
 710 }
 711
 712 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 713 {
 714         if (!vcpu->fpu_active)
 715                 return;
 716         vcpu->fpu_active = 0;
 717         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 718         update_exception_bitmap(vcpu);
 719 }
 720
 721 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 722 {
 723         return vmcs_readl(GUEST_RFLAGS);
 724 }
 725
 726 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 727 {
 728         if (vcpu->arch.rmode.active)
 729                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 730         vmcs_writel(GUEST_RFLAGS, rflags);
 731 }
 732
 733 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 734 {
 735         unsigned long rip;
 736         u32 interruptibility;
 737
 738         rip = kvm_rip_read(vcpu);
 739         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 740         kvm_rip_write(vcpu, rip);
 741
 742         /*
 743          * We emulated an instruction, so temporary interrupt blocking
 744          * should be removed, if set.
 745          */
 746         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 747         if (interruptibility & 3)
 748                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 749                              interruptibility & ~3);
 750         vcpu->arch.interrupt_window_open = 1;
 751 }
 752
 753 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 754                                 bool has_error_code, u32 error_code)
 755 {
 756         struct vcpu_vmx *vmx = to_vmx(vcpu);
 757         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 758
 759         if (has_error_code) {
 760                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 761                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 762         }
 763
 764         if (vcpu->arch.rmode.active) {
 765                 vmx->rmode.irq.pending = true;
 766                 vmx->rmode.irq.vector = nr;
 767                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 768                 if (nr == BP_VECTOR || nr == OF_VECTOR)
 769                         vmx->rmode.irq.rip++;
 770                 intr_info |= INTR_TYPE_SOFT_INTR;
 771                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 772                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 773                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 774                 return;
 775         }
 776
 777         if (nr == BP_VECTOR || nr == OF_VECTOR) {
 778                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 779                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 780         } else
 781                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 782
 783         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 784 }
 785
 786 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 787 {
 788         return false;
 789 }
 790
 791 /*
 792  * Swap MSR entry in host/guest MSR entry array.
 793  */
 794 #ifdef CONFIG_X86_64
 795 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 796 {
 797         struct kvm_msr_entry tmp;
 798
 799         tmp = vmx->guest_msrs[to];
 800         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 801         vmx->guest_msrs[from] = tmp;
 802         tmp = vmx->host_msrs[to];
 803         vmx->host_msrs[to] = vmx->host_msrs[from];
 804         vmx->host_msrs[from] = tmp;
 805 }
 806 #endif
 807
 808 /*
 809  * Set up the vmcs to automatically save and restore system
 810  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 811  * mode, as fiddling with msrs is very expensive.
 812  */
 813 static void setup_msrs(struct vcpu_vmx *vmx)
 814 {
 815         int save_nmsrs;
 816         unsigned long *msr_bitmap;
 817
 818         vmx_load_host_state(vmx);
 819         save_nmsrs = 0;
 820 #ifdef CONFIG_X86_64
 821         if (is_long_mode(&vmx->vcpu)) {
 822                 int index;
 823
 824                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 825                 if (index >= 0)
 826                         move_msr_up(vmx, index, save_nmsrs++);
 827                 index = __find_msr_index(vmx, MSR_LSTAR);
 828                 if (index >= 0)
 829                         move_msr_up(vmx, index, save_nmsrs++);
 830                 index = __find_msr_index(vmx, MSR_CSTAR);
 831                 if (index >= 0)
 832                         move_msr_up(vmx, index, save_nmsrs++);
 833                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 834                 if (index >= 0)
 835                         move_msr_up(vmx, index, save_nmsrs++);
 836                 /*
 837                  * MSR_K6_STAR is only needed on long mode guests, and only
 838                  * if efer.sce is enabled.
 839                  */
 840                 index = __find_msr_index(vmx, MSR_K6_STAR);
 841                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 842                         move_msr_up(vmx, index, save_nmsrs++);
 843         }
 844 #endif
 845         vmx->save_nmsrs = save_nmsrs;
 846
 847 #ifdef CONFIG_X86_64
 848         vmx->msr_offset_kernel_gs_base =
 849                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 850 #endif
 851         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 852
 853         if (cpu_has_vmx_msr_bitmap()) {
 854                 if (is_long_mode(&vmx->vcpu))
 855                         msr_bitmap = vmx_msr_bitmap_longmode;
 856                 else
 857                         msr_bitmap = vmx_msr_bitmap_legacy;
 858
 859                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 860         }
 861 }
 862
 863 /*
 864  * reads and returns guest's timestamp counter "register"
 865  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 866  */
 867 static u64 guest_read_tsc(void)
 868 {
 869         u64 host_tsc, tsc_offset;
 870
 871         rdtscll(host_tsc);
 872         tsc_offset = vmcs_read64(TSC_OFFSET);
 873         return host_tsc + tsc_offset;
 874 }
 875
 876 /*
 877  * writes 'guest_tsc' into guest's timestamp counter "register"
 878  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 879  */
 880 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 881 {
 882         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 883 }
 884
 885 /*
 886  * Reads an msr value (of 'msr_index') into 'pdata'.
 887  * Returns 0 on success, non-0 otherwise.
 888  * Assumes vcpu_load() was already called.
 889  */
 890 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 891 {
 892         u64 data;
 893         struct kvm_msr_entry *msr;
 894
 895         if (!pdata) {
 896                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 897                 return -EINVAL;
 898         }
 899
 900         switch (msr_index) {
 901 #ifdef CONFIG_X86_64
 902         case MSR_FS_BASE:
 903                 data = vmcs_readl(GUEST_FS_BASE);
 904                 break;
 905         case MSR_GS_BASE:
 906                 data = vmcs_readl(GUEST_GS_BASE);
 907                 break;
 908         case MSR_EFER:
 909                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 910 #endif
 911         case MSR_IA32_TIME_STAMP_COUNTER:
 912                 data = guest_read_tsc();
 913                 break;
 914         case MSR_IA32_SYSENTER_CS:
 915                 data = vmcs_read32(GUEST_SYSENTER_CS);
 916                 break;
 917         case MSR_IA32_SYSENTER_EIP:
 918                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 919                 break;
 920         case MSR_IA32_SYSENTER_ESP:
 921                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 922                 break;
 923         default:
 924                 vmx_load_host_state(to_vmx(vcpu));
 925                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 926                 if (msr) {
 927                         data = msr->data;
 928                         break;
 929                 }
 930                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 931         }
 932
 933         *pdata = data;
 934         return 0;
 935 }
 936
 937 /*
 938  * Writes msr value into into the appropriate "register".
 939  * Returns 0 on success, non-0 otherwise.
 940  * Assumes vcpu_load() was already called.
 941  */
 942 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 943 {
 944         struct vcpu_vmx *vmx = to_vmx(vcpu);
 945         struct kvm_msr_entry *msr;
 946         u64 host_tsc;
 947         int ret = 0;
 948
 949         switch (msr_index) {
 950         case MSR_EFER:
 951                 vmx_load_host_state(vmx);
 952                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 953                 break;
 954 #ifdef CONFIG_X86_64
 955         case MSR_FS_BASE:
 956                 vmcs_writel(GUEST_FS_BASE, data);
 957                 break;
 958         case MSR_GS_BASE:
 959                 vmcs_writel(GUEST_GS_BASE, data);
 960                 break;
 961 #endif
 962         case MSR_IA32_SYSENTER_CS:
 963                 vmcs_write32(GUEST_SYSENTER_CS, data);
 964                 break;
 965         case MSR_IA32_SYSENTER_EIP:
 966                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 967                 break;
 968         case MSR_IA32_SYSENTER_ESP:
 969                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 970                 break;
 971         case MSR_IA32_TIME_STAMP_COUNTER:
 972                 rdtscll(host_tsc);
 973                 guest_write_tsc(data, host_tsc);
 974                 break;
 975         case MSR_P6_PERFCTR0:
 976         case MSR_P6_PERFCTR1:
 977         case MSR_P6_EVNTSEL0:
 978         case MSR_P6_EVNTSEL1:
 979                 /*
 980                  * Just discard all writes to the performance counters; this
 981                  * should keep both older linux and windows 64-bit guests
 982                  * happy
 983                  */
 984                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 985
 986                 break;
 987         case MSR_IA32_CR_PAT:
 988                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
 989                         vmcs_write64(GUEST_IA32_PAT, data);
 990                         vcpu->arch.pat = data;
 991                         break;
 992                 }
 993                 /* Otherwise falls through to kvm_set_msr_common */
 994         default:
 995                 vmx_load_host_state(vmx);
 996                 msr = find_msr_entry(vmx, msr_index);
 997                 if (msr) {
 998                         msr->data = data;
 999                         break;
1000                 }
1001                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1002         }
1003
1004         return ret;
1005 }
1006
1007 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1008 {
1009         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1010         switch (reg) {
1011         case VCPU_REGS_RSP:
1012                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1013                 break;
1014         case VCPU_REGS_RIP:
1015                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1016                 break;
1017         default:
1018                 break;
1019         }
1020 }
1021
1022 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1023 {
1024         int old_debug = vcpu->guest_debug;
1025         unsigned long flags;
1026
1027         vcpu->guest_debug = dbg->control;
1028         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1029                 vcpu->guest_debug = 0;
1030
1031         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1032                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1033         else
1034                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1035
1036         flags = vmcs_readl(GUEST_RFLAGS);
1037         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1038                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1039         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1040                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1041         vmcs_writel(GUEST_RFLAGS, flags);
1042
1043         update_exception_bitmap(vcpu);
1044
1045         return 0;
1046 }
1047
1048 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1049 {
1050         if (!vcpu->arch.interrupt.pending)
1051                 return -1;
1052         return vcpu->arch.interrupt.nr;
1053 }
1054
1055 static __init int cpu_has_kvm_support(void)
1056 {
1057         return cpu_has_vmx();
1058 }
1059
1060 static __init int vmx_disabled_by_bios(void)
1061 {
1062         u64 msr;
1063
1064         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1065         return (msr & (FEATURE_CONTROL_LOCKED |
1066                        FEATURE_CONTROL_VMXON_ENABLED))
1067             == FEATURE_CONTROL_LOCKED;
1068         /* locked but not enabled */
1069 }
1070
1071 static void hardware_enable(void *garbage)
1072 {
1073         int cpu = raw_smp_processor_id();
1074         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1075         u64 old;
1076
1077         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1078         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1079         if ((old & (FEATURE_CONTROL_LOCKED |
1080                     FEATURE_CONTROL_VMXON_ENABLED))
1081             != (FEATURE_CONTROL_LOCKED |
1082                 FEATURE_CONTROL_VMXON_ENABLED))
1083                 /* enable and lock */
1084                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1085                        FEATURE_CONTROL_LOCKED |
1086                        FEATURE_CONTROL_VMXON_ENABLED);
1087         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1088         asm volatile (ASM_VMX_VMXON_RAX
1089                       : : "a"(&phys_addr), "m"(phys_addr)
1090                       : "memory", "cc");
1091 }
1092
1093 static void vmclear_local_vcpus(void)
1094 {
1095         int cpu = raw_smp_processor_id();
1096         struct vcpu_vmx *vmx, *n;
1097
1098         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1099                                  local_vcpus_link)
1100                 __vcpu_clear(vmx);
1101 }
1102
1103
1104 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1105  * tricks.
1106  */
1107 static void kvm_cpu_vmxoff(void)
1108 {
1109         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1110         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1111 }
1112
1113 static void hardware_disable(void *garbage)
1114 {
1115         vmclear_local_vcpus();
1116         kvm_cpu_vmxoff();
1117 }
1118
1119 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1120                                       u32 msr, u32 *result)
1121 {
1122         u32 vmx_msr_low, vmx_msr_high;
1123         u32 ctl = ctl_min | ctl_opt;
1124
1125         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1126
1127         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1128         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1129
1130         /* Ensure minimum (required) set of control bits are supported. */
1131         if (ctl_min & ~ctl)
1132                 return -EIO;
1133
1134         *result = ctl;
1135         return 0;
1136 }
1137
1138 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1139 {
1140         u32 vmx_msr_low, vmx_msr_high;
1141         u32 min, opt, min2, opt2;
1142         u32 _pin_based_exec_control = 0;
1143         u32 _cpu_based_exec_control = 0;
1144         u32 _cpu_based_2nd_exec_control = 0;
1145         u32 _vmexit_control = 0;
1146         u32 _vmentry_control = 0;
1147
1148         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1149         opt = PIN_BASED_VIRTUAL_NMIS;
1150         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1151                                 &_pin_based_exec_control) < 0)
1152                 return -EIO;
1153
1154         min = CPU_BASED_HLT_EXITING |
1155 #ifdef CONFIG_X86_64
1156               CPU_BASED_CR8_LOAD_EXITING |
1157               CPU_BASED_CR8_STORE_EXITING |
1158 #endif
1159               CPU_BASED_CR3_LOAD_EXITING |
1160               CPU_BASED_CR3_STORE_EXITING |
1161               CPU_BASED_USE_IO_BITMAPS |
1162               CPU_BASED_MOV_DR_EXITING |
1163               CPU_BASED_USE_TSC_OFFSETING |
1164               CPU_BASED_INVLPG_EXITING;
1165         opt = CPU_BASED_TPR_SHADOW |
1166               CPU_BASED_USE_MSR_BITMAPS |
1167               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1168         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1169                                 &_cpu_based_exec_control) < 0)
1170                 return -EIO;
1171 #ifdef CONFIG_X86_64
1172         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1173                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1174                                            ~CPU_BASED_CR8_STORE_EXITING;
1175 #endif
1176         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1177                 min2 = 0;
1178                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1179                         SECONDARY_EXEC_WBINVD_EXITING |
1180                         SECONDARY_EXEC_ENABLE_VPID |
1181                         SECONDARY_EXEC_ENABLE_EPT;
1182                 if (adjust_vmx_controls(min2, opt2,
1183                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1184                                         &_cpu_based_2nd_exec_control) < 0)
1185                         return -EIO;
1186         }
1187 #ifndef CONFIG_X86_64
1188         if (!(_cpu_based_2nd_exec_control &
1189                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1190                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1191 #endif
1192         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1193                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1194                    enabled */
1195                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1196                          CPU_BASED_CR3_STORE_EXITING |
1197                          CPU_BASED_INVLPG_EXITING);
1198                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1199                                         &_cpu_based_exec_control) < 0)
1200                         return -EIO;
1201                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1202                       vmx_capability.ept, vmx_capability.vpid);
1203         }
1204
1205         if (!cpu_has_vmx_vpid())
1206                 enable_vpid = 0;
1207
1208         min = 0;
1209 #ifdef CONFIG_X86_64
1210         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1211 #endif
1212         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1213         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1214                                 &_vmexit_control) < 0)
1215                 return -EIO;
1216
1217         min = 0;
1218         opt = VM_ENTRY_LOAD_IA32_PAT;
1219         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1220                                 &_vmentry_control) < 0)
1221                 return -EIO;
1222
1223         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1224
1225         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1226         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1227                 return -EIO;
1228
1229 #ifdef CONFIG_X86_64
1230         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1231         if (vmx_msr_high & (1u<<16))
1232                 return -EIO;
1233 #endif
1234
1235         /* Require Write-Back (WB) memory type for VMCS accesses. */
1236         if (((vmx_msr_high >> 18) & 15) != 6)
1237                 return -EIO;
1238
1239         vmcs_conf->size = vmx_msr_high & 0x1fff;
1240         vmcs_conf->order = get_order(vmcs_config.size);
1241         vmcs_conf->revision_id = vmx_msr_low;
1242
1243         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1244         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1245         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1246         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1247         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1248
1249         return 0;
1250 }
1251
1252 static struct vmcs *alloc_vmcs_cpu(int cpu)
1253 {
1254         int node = cpu_to_node(cpu);
1255         struct page *pages;
1256         struct vmcs *vmcs;
1257
1258         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1259         if (!pages)
1260                 return NULL;
1261         vmcs = page_address(pages);
1262         memset(vmcs, 0, vmcs_config.size);
1263         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1264         return vmcs;
1265 }
1266
1267 static struct vmcs *alloc_vmcs(void)
1268 {
1269         return alloc_vmcs_cpu(raw_smp_processor_id());
1270 }
1271
1272 static void free_vmcs(struct vmcs *vmcs)
1273 {
1274         free_pages((unsigned long)vmcs, vmcs_config.order);
1275 }
1276
1277 static void free_kvm_area(void)
1278 {
1279         int cpu;
1280
1281         for_each_online_cpu(cpu)
1282                 free_vmcs(per_cpu(vmxarea, cpu));
1283 }
1284
1285 static __init int alloc_kvm_area(void)
1286 {
1287         int cpu;
1288
1289         for_each_online_cpu(cpu) {
1290                 struct vmcs *vmcs;
1291
1292                 vmcs = alloc_vmcs_cpu(cpu);
1293                 if (!vmcs) {
1294                         free_kvm_area();
1295                         return -ENOMEM;
1296                 }
1297
1298                 per_cpu(vmxarea, cpu) = vmcs;
1299         }
1300         return 0;
1301 }
1302
1303 static __init int hardware_setup(void)
1304 {
1305         if (setup_vmcs_config(&vmcs_config) < 0)
1306                 return -EIO;
1307
1308         if (boot_cpu_has(X86_FEATURE_NX))
1309                 kvm_enable_efer_bits(EFER_NX);
1310
1311         return alloc_kvm_area();
1312 }
1313
1314 static __exit void hardware_unsetup(void)
1315 {
1316         free_kvm_area();
1317 }
1318
1319 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1320 {
1321         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1322
1323         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1324                 vmcs_write16(sf->selector, save->selector);
1325                 vmcs_writel(sf->base, save->base);
1326                 vmcs_write32(sf->limit, save->limit);
1327                 vmcs_write32(sf->ar_bytes, save->ar);
1328         } else {
1329                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1330                         << AR_DPL_SHIFT;
1331                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1332         }
1333 }
1334
1335 static void enter_pmode(struct kvm_vcpu *vcpu)
1336 {
1337         unsigned long flags;
1338         struct vcpu_vmx *vmx = to_vmx(vcpu);
1339
1340         vmx->emulation_required = 1;
1341         vcpu->arch.rmode.active = 0;
1342
1343         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1344         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1345         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1346
1347         flags = vmcs_readl(GUEST_RFLAGS);
1348         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1349         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1350         vmcs_writel(GUEST_RFLAGS, flags);
1351
1352         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1353                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1354
1355         update_exception_bitmap(vcpu);
1356
1357         if (emulate_invalid_guest_state)
1358                 return;
1359
1360         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1361         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1362         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1363         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1364
1365         vmcs_write16(GUEST_SS_SELECTOR, 0);
1366         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1367
1368         vmcs_write16(GUEST_CS_SELECTOR,
1369                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1370         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1371 }
1372
1373 static gva_t rmode_tss_base(struct kvm *kvm)
1374 {
1375         if (!kvm->arch.tss_addr) {
1376                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1377                                  kvm->memslots[0].npages - 3;
1378                 return base_gfn << PAGE_SHIFT;
1379         }
1380         return kvm->arch.tss_addr;
1381 }
1382
1383 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1384 {
1385         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1386
1387         save->selector = vmcs_read16(sf->selector);
1388         save->base = vmcs_readl(sf->base);
1389         save->limit = vmcs_read32(sf->limit);
1390         save->ar = vmcs_read32(sf->ar_bytes);
1391         vmcs_write16(sf->selector, save->base >> 4);
1392         vmcs_write32(sf->base, save->base & 0xfffff);
1393         vmcs_write32(sf->limit, 0xffff);
1394         vmcs_write32(sf->ar_bytes, 0xf3);
1395 }
1396
1397 static void enter_rmode(struct kvm_vcpu *vcpu)
1398 {
1399         unsigned long flags;
1400         struct vcpu_vmx *vmx = to_vmx(vcpu);
1401
1402         vmx->emulation_required = 1;
1403         vcpu->arch.rmode.active = 1;
1404
1405         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1406         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1407
1408         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1409         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1410
1411         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1412         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1413
1414         flags = vmcs_readl(GUEST_RFLAGS);
1415         vcpu->arch.rmode.save_iopl
1416                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1417
1418         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1419
1420         vmcs_writel(GUEST_RFLAGS, flags);
1421         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1422         update_exception_bitmap(vcpu);
1423
1424         if (emulate_invalid_guest_state)
1425                 goto continue_rmode;
1426
1427         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1428         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1429         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1430
1431         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1432         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1433         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1434                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1435         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1436
1437         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1438         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1439         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1440         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1441
1442 continue_rmode:
1443         kvm_mmu_reset_context(vcpu);
1444         init_rmode(vcpu->kvm);
1445 }
1446
1447 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1448 {
1449         struct vcpu_vmx *vmx = to_vmx(vcpu);
1450         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1451
1452         vcpu->arch.shadow_efer = efer;
1453         if (!msr)
1454                 return;
1455         if (efer & EFER_LMA) {
1456                 vmcs_write32(VM_ENTRY_CONTROLS,
1457                              vmcs_read32(VM_ENTRY_CONTROLS) |
1458                              VM_ENTRY_IA32E_MODE);
1459                 msr->data = efer;
1460         } else {
1461                 vmcs_write32(VM_ENTRY_CONTROLS,
1462                              vmcs_read32(VM_ENTRY_CONTROLS) &
1463                              ~VM_ENTRY_IA32E_MODE);
1464
1465                 msr->data = efer & ~EFER_LME;
1466         }
1467         setup_msrs(vmx);
1468 }
1469
1470 #ifdef CONFIG_X86_64
1471
1472 static void enter_lmode(struct kvm_vcpu *vcpu)
1473 {
1474         u32 guest_tr_ar;
1475
1476         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1477         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1478                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1479                        __func__);
1480                 vmcs_write32(GUEST_TR_AR_BYTES,
1481                              (guest_tr_ar & ~AR_TYPE_MASK)
1482                              | AR_TYPE_BUSY_64_TSS);
1483         }
1484         vcpu->arch.shadow_efer |= EFER_LMA;
1485         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1486 }
1487
1488 static void exit_lmode(struct kvm_vcpu *vcpu)
1489 {
1490         vcpu->arch.shadow_efer &= ~EFER_LMA;
1491
1492         vmcs_write32(VM_ENTRY_CONTROLS,
1493                      vmcs_read32(VM_ENTRY_CONTROLS)
1494                      & ~VM_ENTRY_IA32E_MODE);
1495 }
1496
1497 #endif
1498
1499 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1500 {
1501         vpid_sync_vcpu_all(to_vmx(vcpu));
1502         if (vm_need_ept())
1503                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1504 }
1505
1506 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1507 {
1508         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1509         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1510 }
1511
1512 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1513 {
1514         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1515                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1516                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1517                         return;
1518                 }
1519                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1520                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1521                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1522                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1523         }
1524 }
1525
1526 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1527
1528 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1529                                         unsigned long cr0,
1530                                         struct kvm_vcpu *vcpu)
1531 {
1532         if (!(cr0 & X86_CR0_PG)) {
1533                 /* From paging/starting to nonpaging */
1534                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1535                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1536                              (CPU_BASED_CR3_LOAD_EXITING |
1537                               CPU_BASED_CR3_STORE_EXITING));
1538                 vcpu->arch.cr0 = cr0;
1539                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1540                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1541                 *hw_cr0 &= ~X86_CR0_WP;
1542         } else if (!is_paging(vcpu)) {
1543                 /* From nonpaging to paging */
1544                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1545                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1546                              ~(CPU_BASED_CR3_LOAD_EXITING |
1547                                CPU_BASED_CR3_STORE_EXITING));
1548                 vcpu->arch.cr0 = cr0;
1549                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1550                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1551                         *hw_cr0 &= ~X86_CR0_WP;
1552         }
1553 }
1554
1555 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1556                                         struct kvm_vcpu *vcpu)
1557 {
1558         if (!is_paging(vcpu)) {
1559                 *hw_cr4 &= ~X86_CR4_PAE;
1560                 *hw_cr4 |= X86_CR4_PSE;
1561         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1562                 *hw_cr4 &= ~X86_CR4_PAE;
1563 }
1564
1565 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1566 {
1567         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1568                                 KVM_VM_CR0_ALWAYS_ON;
1569
1570         vmx_fpu_deactivate(vcpu);
1571
1572         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1573                 enter_pmode(vcpu);
1574
1575         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1576                 enter_rmode(vcpu);
1577
1578 #ifdef CONFIG_X86_64
1579         if (vcpu->arch.shadow_efer & EFER_LME) {
1580                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1581                         enter_lmode(vcpu);
1582                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1583                         exit_lmode(vcpu);
1584         }
1585 #endif
1586
1587         if (vm_need_ept())
1588                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1589
1590         vmcs_writel(CR0_READ_SHADOW, cr0);
1591         vmcs_writel(GUEST_CR0, hw_cr0);
1592         vcpu->arch.cr0 = cr0;
1593
1594         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1595                 vmx_fpu_activate(vcpu);
1596 }
1597
1598 static u64 construct_eptp(unsigned long root_hpa)
1599 {
1600         u64 eptp;
1601
1602         /* TODO write the value reading from MSR */
1603         eptp = VMX_EPT_DEFAULT_MT |
1604                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1605         eptp |= (root_hpa & PAGE_MASK);
1606
1607         return eptp;
1608 }
1609
1610 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1611 {
1612         unsigned long guest_cr3;
1613         u64 eptp;
1614
1615         guest_cr3 = cr3;
1616         if (vm_need_ept()) {
1617                 eptp = construct_eptp(cr3);
1618                 vmcs_write64(EPT_POINTER, eptp);
1619                 ept_sync_context(eptp);
1620                 ept_load_pdptrs(vcpu);
1621                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1622                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1623         }
1624
1625         vmx_flush_tlb(vcpu);
1626         vmcs_writel(GUEST_CR3, guest_cr3);
1627         if (vcpu->arch.cr0 & X86_CR0_PE)
1628                 vmx_fpu_deactivate(vcpu);
1629 }
1630
1631 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1632 {
1633         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1634                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1635
1636         vcpu->arch.cr4 = cr4;
1637         if (vm_need_ept())
1638                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1639
1640         vmcs_writel(CR4_READ_SHADOW, cr4);
1641         vmcs_writel(GUEST_CR4, hw_cr4);
1642 }
1643
1644 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1645 {
1646         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1647
1648         return vmcs_readl(sf->base);
1649 }
1650
1651 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1652                             struct kvm_segment *var, int seg)
1653 {
1654         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1655         u32 ar;
1656
1657         var->base = vmcs_readl(sf->base);
1658         var->limit = vmcs_read32(sf->limit);
1659         var->selector = vmcs_read16(sf->selector);
1660         ar = vmcs_read32(sf->ar_bytes);
1661         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1662                 ar = 0;
1663         var->type = ar & 15;
1664         var->s = (ar >> 4) & 1;
1665         var->dpl = (ar >> 5) & 3;
1666         var->present = (ar >> 7) & 1;
1667         var->avl = (ar >> 12) & 1;
1668         var->l = (ar >> 13) & 1;
1669         var->db = (ar >> 14) & 1;
1670         var->g = (ar >> 15) & 1;
1671         var->unusable = (ar >> 16) & 1;
1672 }
1673
1674 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1675 {
1676         struct kvm_segment kvm_seg;
1677
1678         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1679                 return 0;
1680
1681         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1682                 return 3;
1683
1684         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1685         return kvm_seg.selector & 3;
1686 }
1687
1688 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1689 {
1690         u32 ar;
1691
1692         if (var->unusable)
1693                 ar = 1 << 16;
1694         else {
1695                 ar = var->type & 15;
1696                 ar |= (var->s & 1) << 4;
1697                 ar |= (var->dpl & 3) << 5;
1698                 ar |= (var->present & 1) << 7;
1699                 ar |= (var->avl & 1) << 12;
1700                 ar |= (var->l & 1) << 13;
1701                 ar |= (var->db & 1) << 14;
1702                 ar |= (var->g & 1) << 15;
1703         }
1704         if (ar == 0) /* a 0 value means unusable */
1705                 ar = AR_UNUSABLE_MASK;
1706
1707         return ar;
1708 }
1709
1710 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1711                             struct kvm_segment *var, int seg)
1712 {
1713         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1714         u32 ar;
1715
1716         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1717                 vcpu->arch.rmode.tr.selector = var->selector;
1718                 vcpu->arch.rmode.tr.base = var->base;
1719                 vcpu->arch.rmode.tr.limit = var->limit;
1720                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1721                 return;
1722         }
1723         vmcs_writel(sf->base, var->base);
1724         vmcs_write32(sf->limit, var->limit);
1725         vmcs_write16(sf->selector, var->selector);
1726         if (vcpu->arch.rmode.active && var->s) {
1727                 /*
1728                  * Hack real-mode segments into vm86 compatibility.
1729                  */
1730                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1731                         vmcs_writel(sf->base, 0xf0000);
1732                 ar = 0xf3;
1733         } else
1734                 ar = vmx_segment_access_rights(var);
1735         vmcs_write32(sf->ar_bytes, ar);
1736 }
1737
1738 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1739 {
1740         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1741
1742         *db = (ar >> 14) & 1;
1743         *l = (ar >> 13) & 1;
1744 }
1745
1746 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1747 {
1748         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1749         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1750 }
1751
1752 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1753 {
1754         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1755         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1756 }
1757
1758 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1759 {
1760         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1761         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1762 }
1763
1764 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1765 {
1766         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1767         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1768 }
1769
1770 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1771 {
1772         struct kvm_segment var;
1773         u32 ar;
1774
1775         vmx_get_segment(vcpu, &var, seg);
1776         ar = vmx_segment_access_rights(&var);
1777
1778         if (var.base != (var.selector << 4))
1779                 return false;
1780         if (var.limit != 0xffff)
1781                 return false;
1782         if (ar != 0xf3)
1783                 return false;
1784
1785         return true;
1786 }
1787
1788 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1789 {
1790         struct kvm_segment cs;
1791         unsigned int cs_rpl;
1792
1793         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1794         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1795
1796         if (cs.unusable)
1797                 return false;
1798         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1799                 return false;
1800         if (!cs.s)
1801                 return false;
1802         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1803                 if (cs.dpl > cs_rpl)
1804                         return false;
1805         } else {
1806                 if (cs.dpl != cs_rpl)
1807                         return false;
1808         }
1809         if (!cs.present)
1810                 return false;
1811
1812         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1813         return true;
1814 }
1815
1816 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1817 {
1818         struct kvm_segment ss;
1819         unsigned int ss_rpl;
1820
1821         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1822         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1823
1824         if (ss.unusable)
1825                 return true;
1826         if (ss.type != 3 && ss.type != 7)
1827                 return false;
1828         if (!ss.s)
1829                 return false;
1830         if (ss.dpl != ss_rpl) /* DPL != RPL */
1831                 return false;
1832         if (!ss.present)
1833                 return false;
1834
1835         return true;
1836 }
1837
1838 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1839 {
1840         struct kvm_segment var;
1841         unsigned int rpl;
1842
1843         vmx_get_segment(vcpu, &var, seg);
1844         rpl = var.selector & SELECTOR_RPL_MASK;
1845
1846         if (var.unusable)
1847                 return true;
1848         if (!var.s)
1849                 return false;
1850         if (!var.present)
1851                 return false;
1852         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1853                 if (var.dpl < rpl) /* DPL < RPL */
1854                         return false;
1855         }
1856
1857         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1858          * rights flags
1859          */
1860         return true;
1861 }
1862
1863 static bool tr_valid(struct kvm_vcpu *vcpu)
1864 {
1865         struct kvm_segment tr;
1866
1867         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1868
1869         if (tr.unusable)
1870                 return false;
1871         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1872                 return false;
1873         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1874                 return false;
1875         if (!tr.present)
1876                 return false;
1877
1878         return true;
1879 }
1880
1881 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1882 {
1883         struct kvm_segment ldtr;
1884
1885         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1886
1887         if (ldtr.unusable)
1888                 return true;
1889         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1890                 return false;
1891         if (ldtr.type != 2)
1892                 return false;
1893         if (!ldtr.present)
1894                 return false;
1895
1896         return true;
1897 }
1898
1899 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1900 {
1901         struct kvm_segment cs, ss;
1902
1903         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1904         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1905
1906         return ((cs.selector & SELECTOR_RPL_MASK) ==
1907                  (ss.selector & SELECTOR_RPL_MASK));
1908 }
1909
1910 /*
1911  * Check if guest state is valid. Returns true if valid, false if
1912  * not.
1913  * We assume that registers are always usable
1914  */
1915 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1916 {
1917         /* real mode guest state checks */
1918         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1919                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1920                         return false;
1921                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1922                         return false;
1923                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1924                         return false;
1925                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1926                         return false;
1927                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1928                         return false;
1929                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1930                         return false;
1931         } else {
1932         /* protected mode guest state checks */
1933                 if (!cs_ss_rpl_check(vcpu))
1934                         return false;
1935                 if (!code_segment_valid(vcpu))
1936                         return false;
1937                 if (!stack_segment_valid(vcpu))
1938                         return false;
1939                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1940                         return false;
1941                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1942                         return false;
1943                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1944                         return false;
1945                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1946                         return false;
1947                 if (!tr_valid(vcpu))
1948                         return false;
1949                 if (!ldtr_valid(vcpu))
1950                         return false;
1951         }
1952         /* TODO:
1953          * - Add checks on RIP
1954          * - Add checks on RFLAGS
1955          */
1956
1957         return true;
1958 }
1959
1960 static int init_rmode_tss(struct kvm *kvm)
1961 {
1962         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1963         u16 data = 0;
1964         int ret = 0;
1965         int r;
1966
1967         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1968         if (r < 0)
1969                 goto out;
1970         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1971         r = kvm_write_guest_page(kvm, fn++, &data,
1972                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1973         if (r < 0)
1974                 goto out;
1975         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1976         if (r < 0)
1977                 goto out;
1978         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1979         if (r < 0)
1980                 goto out;
1981         data = ~0;
1982         r = kvm_write_guest_page(kvm, fn, &data,
1983                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1984                                  sizeof(u8));
1985         if (r < 0)
1986                 goto out;
1987
1988         ret = 1;
1989 out:
1990         return ret;
1991 }
1992
1993 static int init_rmode_identity_map(struct kvm *kvm)
1994 {
1995         int i, r, ret;
1996         pfn_t identity_map_pfn;
1997         u32 tmp;
1998
1999         if (!vm_need_ept())
2000                 return 1;
2001         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2002                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2003                         "haven't been allocated!\n");
2004                 return 0;
2005         }
2006         if (likely(kvm->arch.ept_identity_pagetable_done))
2007                 return 1;
2008         ret = 0;
2009         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2010         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2011         if (r < 0)
2012                 goto out;
2013         /* Set up identity-mapping pagetable for EPT in real mode */
2014         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2015                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2016                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2017                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2018                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2019                 if (r < 0)
2020                         goto out;
2021         }
2022         kvm->arch.ept_identity_pagetable_done = true;
2023         ret = 1;
2024 out:
2025         return ret;
2026 }
2027
2028 static void seg_setup(int seg)
2029 {
2030         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2031
2032         vmcs_write16(sf->selector, 0);
2033         vmcs_writel(sf->base, 0);
2034         vmcs_write32(sf->limit, 0xffff);
2035         vmcs_write32(sf->ar_bytes, 0xf3);
2036 }
2037
2038 static int alloc_apic_access_page(struct kvm *kvm)
2039 {
2040         struct kvm_userspace_memory_region kvm_userspace_mem;
2041         int r = 0;
2042
2043         down_write(&kvm->slots_lock);
2044         if (kvm->arch.apic_access_page)
2045                 goto out;
2046         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2047         kvm_userspace_mem.flags = 0;
2048         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2049         kvm_userspace_mem.memory_size = PAGE_SIZE;
2050         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2051         if (r)
2052                 goto out;
2053
2054         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2055 out:
2056         up_write(&kvm->slots_lock);
2057         return r;
2058 }
2059
2060 static int alloc_identity_pagetable(struct kvm *kvm)
2061 {
2062         struct kvm_userspace_memory_region kvm_userspace_mem;
2063         int r = 0;
2064
2065         down_write(&kvm->slots_lock);
2066         if (kvm->arch.ept_identity_pagetable)
2067                 goto out;
2068         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2069         kvm_userspace_mem.flags = 0;
2070         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2071         kvm_userspace_mem.memory_size = PAGE_SIZE;
2072         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2073         if (r)
2074                 goto out;
2075
2076         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2077                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2078 out:
2079         up_write(&kvm->slots_lock);
2080         return r;
2081 }
2082
2083 static void allocate_vpid(struct vcpu_vmx *vmx)
2084 {
2085         int vpid;
2086
2087         vmx->vpid = 0;
2088         if (!enable_vpid)
2089                 return;
2090         spin_lock(&vmx_vpid_lock);
2091         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2092         if (vpid < VMX_NR_VPIDS) {
2093                 vmx->vpid = vpid;
2094                 __set_bit(vpid, vmx_vpid_bitmap);
2095         }
2096         spin_unlock(&vmx_vpid_lock);
2097 }
2098
2099 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2100 {
2101         int f = sizeof(unsigned long);
2102
2103         if (!cpu_has_vmx_msr_bitmap())
2104                 return;
2105
2106         /*
2107          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2108          * have the write-low and read-high bitmap offsets the wrong way round.
2109          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2110          */
2111         if (msr <= 0x1fff) {
2112                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2113                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2114         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2115                 msr &= 0x1fff;
2116                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2117                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2118         }
2119 }
2120
2121 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2122 {
2123         if (!longmode_only)
2124                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2125         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2126 }
2127
2128 /*
2129  * Sets up the vmcs for emulated real mode.
2130  */
2131 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2132 {
2133         u32 host_sysenter_cs, msr_low, msr_high;
2134         u32 junk;
2135         u64 host_pat, tsc_this, tsc_base;
2136         unsigned long a;
2137         struct descriptor_table dt;
2138         int i;
2139         unsigned long kvm_vmx_return;
2140         u32 exec_control;
2141
2142         /* I/O */
2143         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2144         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2145
2146         if (cpu_has_vmx_msr_bitmap())
2147                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2148
2149         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2150
2151         /* Control */
2152         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2153                 vmcs_config.pin_based_exec_ctrl);
2154
2155         exec_control = vmcs_config.cpu_based_exec_ctrl;
2156         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2157                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2158 #ifdef CONFIG_X86_64
2159                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2160                                 CPU_BASED_CR8_LOAD_EXITING;
2161 #endif
2162         }
2163         if (!vm_need_ept())
2164                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2165                                 CPU_BASED_CR3_LOAD_EXITING  |
2166                                 CPU_BASED_INVLPG_EXITING;
2167         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2168
2169         if (cpu_has_secondary_exec_ctrls()) {
2170                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2171                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2172                         exec_control &=
2173                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2174                 if (vmx->vpid == 0)
2175                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2176                 if (!vm_need_ept())
2177                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2178                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2179         }
2180
2181         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2182         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2183         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2184
2185         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2186         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2187         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2188
2189         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2190         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2191         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2192         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2193         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2194         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2195 #ifdef CONFIG_X86_64
2196         rdmsrl(MSR_FS_BASE, a);
2197         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2198         rdmsrl(MSR_GS_BASE, a);
2199         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2200 #else
2201         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2202         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2203 #endif
2204
2205         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2206
2207         kvm_get_idt(&dt);
2208         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2209
2210         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2211         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2212         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2213         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2214         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2215
2216         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2217         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2218         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2219         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2220         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2221         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2222
2223         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2224                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2225                 host_pat = msr_low | ((u64) msr_high << 32);
2226                 vmcs_write64(HOST_IA32_PAT, host_pat);
2227         }
2228         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2229                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2230                 host_pat = msr_low | ((u64) msr_high << 32);
2231                 /* Write the default value follow host pat */
2232                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2233                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2234                 vmx->vcpu.arch.pat = host_pat;
2235         }
2236
2237         for (i = 0; i < NR_VMX_MSR; ++i) {
2238                 u32 index = vmx_msr_index[i];
2239                 u32 data_low, data_high;
2240                 u64 data;
2241                 int j = vmx->nmsrs;
2242
2243                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2244                         continue;
2245                 if (wrmsr_safe(index, data_low, data_high) < 0)
2246                         continue;
2247                 data = data_low | ((u64)data_high << 32);
2248                 vmx->host_msrs[j].index = index;
2249                 vmx->host_msrs[j].reserved = 0;
2250                 vmx->host_msrs[j].data = data;
2251                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2252                 ++vmx->nmsrs;
2253         }
2254
2255         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2256
2257         /* 22.2.1, 20.8.1 */
2258         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2259
2260         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2261         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2262
2263         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2264         rdtscll(tsc_this);
2265         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2266                 tsc_base = tsc_this;
2267
2268         guest_write_tsc(0, tsc_base);
2269
2270         return 0;
2271 }
2272
2273 static int init_rmode(struct kvm *kvm)
2274 {
2275         if (!init_rmode_tss(kvm))
2276                 return 0;
2277         if (!init_rmode_identity_map(kvm))
2278                 return 0;
2279         return 1;
2280 }
2281
2282 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2283 {
2284         struct vcpu_vmx *vmx = to_vmx(vcpu);
2285         u64 msr;
2286         int ret;
2287
2288         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2289         down_read(&vcpu->kvm->slots_lock);
2290         if (!init_rmode(vmx->vcpu.kvm)) {
2291                 ret = -ENOMEM;
2292                 goto out;
2293         }
2294
2295         vmx->vcpu.arch.rmode.active = 0;
2296
2297         vmx->soft_vnmi_blocked = 0;
2298
2299         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2300         kvm_set_cr8(&vmx->vcpu, 0);
2301         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2302         if (vmx->vcpu.vcpu_id == 0)
2303                 msr |= MSR_IA32_APICBASE_BSP;
2304         kvm_set_apic_base(&vmx->vcpu, msr);
2305
2306         fx_init(&vmx->vcpu);
2307
2308         seg_setup(VCPU_SREG_CS);
2309         /*
2310          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2311          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2312          */
2313         if (vmx->vcpu.vcpu_id == 0) {
2314                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2315                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2316         } else {
2317                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2318                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2319         }
2320
2321         seg_setup(VCPU_SREG_DS);
2322         seg_setup(VCPU_SREG_ES);
2323         seg_setup(VCPU_SREG_FS);
2324         seg_setup(VCPU_SREG_GS);
2325         seg_setup(VCPU_SREG_SS);
2326
2327         vmcs_write16(GUEST_TR_SELECTOR, 0);
2328         vmcs_writel(GUEST_TR_BASE, 0);
2329         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2330         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2331
2332         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2333         vmcs_writel(GUEST_LDTR_BASE, 0);
2334         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2335         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2336
2337         vmcs_write32(GUEST_SYSENTER_CS, 0);
2338         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2339         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2340
2341         vmcs_writel(GUEST_RFLAGS, 0x02);
2342         if (vmx->vcpu.vcpu_id == 0)
2343                 kvm_rip_write(vcpu, 0xfff0);
2344         else
2345                 kvm_rip_write(vcpu, 0);
2346         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2347
2348         vmcs_writel(GUEST_DR7, 0x400);
2349
2350         vmcs_writel(GUEST_GDTR_BASE, 0);
2351         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2352
2353         vmcs_writel(GUEST_IDTR_BASE, 0);
2354         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2355
2356         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2357         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2358         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2359
2360         /* Special registers */
2361         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2362
2363         setup_msrs(vmx);
2364
2365         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2366
2367         if (cpu_has_vmx_tpr_shadow()) {
2368                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2369                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2370                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2371                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2372                 vmcs_write32(TPR_THRESHOLD, 0);
2373         }
2374
2375         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2376                 vmcs_write64(APIC_ACCESS_ADDR,
2377                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2378
2379         if (vmx->vpid != 0)
2380                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2381
2382         vmx->vcpu.arch.cr0 = 0x60000010;
2383         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2384         vmx_set_cr4(&vmx->vcpu, 0);
2385         vmx_set_efer(&vmx->vcpu, 0);
2386         vmx_fpu_activate(&vmx->vcpu);
2387         update_exception_bitmap(&vmx->vcpu);
2388
2389         vpid_sync_vcpu_all(vmx);
2390
2391         ret = 0;
2392
2393         /* HACK: Don't enable emulation on guest boot/reset */
2394         vmx->emulation_required = 0;
2395
2396 out:
2397         up_read(&vcpu->kvm->slots_lock);
2398         return ret;
2399 }
2400
2401 static void enable_irq_window(struct kvm_vcpu *vcpu)
2402 {
2403         u32 cpu_based_vm_exec_control;
2404
2405         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2406         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2407         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2408 }
2409
2410 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2411 {
2412         u32 cpu_based_vm_exec_control;
2413
2414         if (!cpu_has_virtual_nmis()) {
2415                 enable_irq_window(vcpu);
2416                 return;
2417         }
2418
2419         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2420         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2421         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2422 }
2423
2424 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2425 {
2426         struct vcpu_vmx *vmx = to_vmx(vcpu);
2427
2428         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2429
2430         ++vcpu->stat.irq_injections;
2431         if (vcpu->arch.rmode.active) {
2432                 vmx->rmode.irq.pending = true;
2433                 vmx->rmode.irq.vector = irq;
2434                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2435                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2436                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2437                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2438                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2439                 return;
2440         }
2441         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2442                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2443 }
2444
2445 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2446 {
2447         struct vcpu_vmx *vmx = to_vmx(vcpu);
2448
2449         if (!cpu_has_virtual_nmis()) {
2450                 /*
2451                  * Tracking the NMI-blocked state in software is built upon
2452                  * finding the next open IRQ window. This, in turn, depends on
2453                  * well-behaving guests: They have to keep IRQs disabled at
2454                  * least as long as the NMI handler runs. Otherwise we may
2455                  * cause NMI nesting, maybe breaking the guest. But as this is
2456                  * highly unlikely, we can live with the residual risk.
2457                  */
2458                 vmx->soft_vnmi_blocked = 1;
2459                 vmx->vnmi_blocked_time = 0;
2460         }
2461
2462         ++vcpu->stat.nmi_injections;
2463         if (vcpu->arch.rmode.active) {
2464                 vmx->rmode.irq.pending = true;
2465                 vmx->rmode.irq.vector = NMI_VECTOR;
2466                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2467                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2468                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2469                              INTR_INFO_VALID_MASK);
2470                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2471                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2472                 return;
2473         }
2474         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2475                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2476 }
2477
2478 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2479 {
2480         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2481
2482         vcpu->arch.nmi_window_open =
2483                 !(guest_intr & (GUEST_INTR_STATE_STI |
2484                                 GUEST_INTR_STATE_MOV_SS |
2485                                 GUEST_INTR_STATE_NMI));
2486         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2487                 vcpu->arch.nmi_window_open = 0;
2488
2489         vcpu->arch.interrupt_window_open =
2490                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2491                  !(guest_intr & (GUEST_INTR_STATE_STI |
2492                                  GUEST_INTR_STATE_MOV_SS)));
2493 }
2494
2495 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2496                                        struct kvm_run *kvm_run)
2497 {
2498         vmx_update_window_states(vcpu);
2499
2500         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2501                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2502                                 GUEST_INTR_STATE_STI |
2503                                 GUEST_INTR_STATE_MOV_SS);
2504
2505         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2506                 if (vcpu->arch.interrupt.pending) {
2507                         enable_nmi_window(vcpu);
2508                 } else if (vcpu->arch.nmi_window_open) {
2509                         vcpu->arch.nmi_pending = false;
2510                         vcpu->arch.nmi_injected = true;
2511                 } else {
2512                         enable_nmi_window(vcpu);
2513                         return;
2514                 }
2515         }
2516         if (vcpu->arch.nmi_injected) {
2517                 vmx_inject_nmi(vcpu);
2518                 if (vcpu->arch.nmi_pending)
2519                         enable_nmi_window(vcpu);
2520                 else if (vcpu->arch.irq_summary
2521                          || kvm_run->request_interrupt_window)
2522                         enable_irq_window(vcpu);
2523                 return;
2524         }
2525
2526         if (vcpu->arch.interrupt_window_open) {
2527                 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2528                         kvm_queue_interrupt(vcpu, kvm_pop_irq(vcpu));
2529
2530                 if (vcpu->arch.interrupt.pending)
2531                         vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2532         }
2533         if (!vcpu->arch.interrupt_window_open &&
2534             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2535                 enable_irq_window(vcpu);
2536 }
2537
2538 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2539 {
2540         int ret;
2541         struct kvm_userspace_memory_region tss_mem = {
2542                 .slot = TSS_PRIVATE_MEMSLOT,
2543                 .guest_phys_addr = addr,
2544                 .memory_size = PAGE_SIZE * 3,
2545                 .flags = 0,
2546         };
2547
2548         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2549         if (ret)
2550                 return ret;
2551         kvm->arch.tss_addr = addr;
2552         return 0;
2553 }
2554
2555 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2556                                   int vec, u32 err_code)
2557 {
2558         /*
2559          * Instruction with address size override prefix opcode 0x67
2560          * Cause the #SS fault with 0 error code in VM86 mode.
2561          */
2562         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2563                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2564                         return 1;
2565         /*
2566          * Forward all other exceptions that are valid in real mode.
2567          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2568          *        the required debugging infrastructure rework.
2569          */
2570         switch (vec) {
2571         case DB_VECTOR:
2572                 if (vcpu->guest_debug &
2573                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2574                         return 0;
2575                 kvm_queue_exception(vcpu, vec);
2576                 return 1;
2577         case BP_VECTOR:
2578                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2579                         return 0;
2580                 /* fall through */
2581         case DE_VECTOR:
2582         case OF_VECTOR:
2583         case BR_VECTOR:
2584         case UD_VECTOR:
2585         case DF_VECTOR:
2586         case SS_VECTOR:
2587         case GP_VECTOR:
2588         case MF_VECTOR:
2589                 kvm_queue_exception(vcpu, vec);
2590                 return 1;
2591         }
2592         return 0;
2593 }
2594
2595 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2596 {
2597         struct vcpu_vmx *vmx = to_vmx(vcpu);
2598         u32 intr_info, ex_no, error_code;
2599         unsigned long cr2, rip, dr6;
2600         u32 vect_info;
2601         enum emulation_result er;
2602
2603         vect_info = vmx->idt_vectoring_info;
2604         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2605
2606         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2607                                                 !is_page_fault(intr_info))
2608                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2609                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2610
2611         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2612                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2613                 kvm_push_irq(vcpu, irq);
2614         }
2615
2616         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2617                 return 1;  /* already handled by vmx_vcpu_run() */
2618
2619         if (is_no_device(intr_info)) {
2620                 vmx_fpu_activate(vcpu);
2621                 return 1;
2622         }
2623
2624         if (is_invalid_opcode(intr_info)) {
2625                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2626                 if (er != EMULATE_DONE)
2627                         kvm_queue_exception(vcpu, UD_VECTOR);
2628                 return 1;
2629         }
2630
2631         error_code = 0;
2632         rip = kvm_rip_read(vcpu);
2633         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2634                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2635         if (is_page_fault(intr_info)) {
2636                 /* EPT won't cause page fault directly */
2637                 if (vm_need_ept())
2638                         BUG();
2639                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2640                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2641                             (u32)((u64)cr2 >> 32), handler);
2642                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2643                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2644                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2645         }
2646
2647         if (vcpu->arch.rmode.active &&
2648             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2649                                                                 error_code)) {
2650                 if (vcpu->arch.halt_request) {
2651                         vcpu->arch.halt_request = 0;
2652                         return kvm_emulate_halt(vcpu);
2653                 }
2654                 return 1;
2655         }
2656
2657         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2658         switch (ex_no) {
2659         case DB_VECTOR:
2660                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2661                 if (!(vcpu->guest_debug &
2662                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2663                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2664                         kvm_queue_exception(vcpu, DB_VECTOR);
2665                         return 1;
2666                 }
2667                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2668                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2669                 /* fall through */
2670         case BP_VECTOR:
2671                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2672                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2673                 kvm_run->debug.arch.exception = ex_no;
2674                 break;
2675         default:
2676                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2677                 kvm_run->ex.exception = ex_no;
2678                 kvm_run->ex.error_code = error_code;
2679                 break;
2680         }
2681         return 0;
2682 }
2683
2684 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2685                                      struct kvm_run *kvm_run)
2686 {
2687         ++vcpu->stat.irq_exits;
2688         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2689         return 1;
2690 }
2691
2692 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2693 {
2694         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2695         return 0;
2696 }
2697
2698 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2699 {
2700         unsigned long exit_qualification;
2701         int size, in, string;
2702         unsigned port;
2703
2704         ++vcpu->stat.io_exits;
2705         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2706         string = (exit_qualification & 16) != 0;
2707
2708         if (string) {
2709                 if (emulate_instruction(vcpu,
2710                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2711                         return 0;
2712                 return 1;
2713         }
2714
2715         size = (exit_qualification & 7) + 1;
2716         in = (exit_qualification & 8) != 0;
2717         port = exit_qualification >> 16;
2718
2719         skip_emulated_instruction(vcpu);
2720         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2721 }
2722
2723 static void
2724 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2725 {
2726         /*
2727          * Patch in the VMCALL instruction:
2728          */
2729         hypercall[0] = 0x0f;
2730         hypercall[1] = 0x01;
2731         hypercall[2] = 0xc1;
2732 }
2733
2734 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2735 {
2736         unsigned long exit_qualification;
2737         int cr;
2738         int reg;
2739
2740         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2741         cr = exit_qualification & 15;
2742         reg = (exit_qualification >> 8) & 15;
2743         switch ((exit_qualification >> 4) & 3) {
2744         case 0: /* mov to cr */
2745                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2746                             (u32)kvm_register_read(vcpu, reg),
2747                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2748                             handler);
2749                 switch (cr) {
2750                 case 0:
2751                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2752                         skip_emulated_instruction(vcpu);
2753                         return 1;
2754                 case 3:
2755                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2756                         skip_emulated_instruction(vcpu);
2757                         return 1;
2758                 case 4:
2759                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2760                         skip_emulated_instruction(vcpu);
2761                         return 1;
2762                 case 8:
2763                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2764                         skip_emulated_instruction(vcpu);
2765                         if (irqchip_in_kernel(vcpu->kvm))
2766                                 return 1;
2767                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2768                         return 0;
2769                 };
2770                 break;
2771         case 2: /* clts */
2772                 vmx_fpu_deactivate(vcpu);
2773                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2774                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2775                 vmx_fpu_activate(vcpu);
2776                 KVMTRACE_0D(CLTS, vcpu, handler);
2777                 skip_emulated_instruction(vcpu);
2778                 return 1;
2779         case 1: /*mov from cr*/
2780                 switch (cr) {
2781                 case 3:
2782                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2783                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2784                                     (u32)kvm_register_read(vcpu, reg),
2785                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2786                                     handler);
2787                         skip_emulated_instruction(vcpu);
2788                         return 1;
2789                 case 8:
2790                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2791                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2792                                     (u32)kvm_register_read(vcpu, reg), handler);
2793                         skip_emulated_instruction(vcpu);
2794                         return 1;
2795                 }
2796                 break;
2797         case 3: /* lmsw */
2798                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2799
2800                 skip_emulated_instruction(vcpu);
2801                 return 1;
2802         default:
2803                 break;
2804         }
2805         kvm_run->exit_reason = 0;
2806         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2807                (int)(exit_qualification >> 4) & 3, cr);
2808         return 0;
2809 }
2810
2811 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2812 {
2813         unsigned long exit_qualification;
2814         unsigned long val;
2815         int dr, reg;
2816
2817         dr = vmcs_readl(GUEST_DR7);
2818         if (dr & DR7_GD) {
2819                 /*
2820                  * As the vm-exit takes precedence over the debug trap, we
2821                  * need to emulate the latter, either for the host or the
2822                  * guest debugging itself.
2823                  */
2824                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2825                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2826                         kvm_run->debug.arch.dr7 = dr;
2827                         kvm_run->debug.arch.pc =
2828                                 vmcs_readl(GUEST_CS_BASE) +
2829                                 vmcs_readl(GUEST_RIP);
2830                         kvm_run->debug.arch.exception = DB_VECTOR;
2831                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2832                         return 0;
2833                 } else {
2834                         vcpu->arch.dr7 &= ~DR7_GD;
2835                         vcpu->arch.dr6 |= DR6_BD;
2836                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2837                         kvm_queue_exception(vcpu, DB_VECTOR);
2838                         return 1;
2839                 }
2840         }
2841
2842         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2843         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2844         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2845         if (exit_qualification & TYPE_MOV_FROM_DR) {
2846                 switch (dr) {
2847                 case 0 ... 3:
2848                         val = vcpu->arch.db[dr];
2849                         break;
2850                 case 6:
2851                         val = vcpu->arch.dr6;
2852                         break;
2853                 case 7:
2854                         val = vcpu->arch.dr7;
2855                         break;
2856                 default:
2857                         val = 0;
2858                 }
2859                 kvm_register_write(vcpu, reg, val);
2860                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2861         } else {
2862                 val = vcpu->arch.regs[reg];
2863                 switch (dr) {
2864                 case 0 ... 3:
2865                         vcpu->arch.db[dr] = val;
2866                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2867                                 vcpu->arch.eff_db[dr] = val;
2868                         break;
2869                 case 4 ... 5:
2870                         if (vcpu->arch.cr4 & X86_CR4_DE)
2871                                 kvm_queue_exception(vcpu, UD_VECTOR);
2872                         break;
2873                 case 6:
2874                         if (val & 0xffffffff00000000ULL) {
2875                                 kvm_queue_exception(vcpu, GP_VECTOR);
2876                                 break;
2877                         }
2878                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2879                         break;
2880                 case 7:
2881                         if (val & 0xffffffff00000000ULL) {
2882                                 kvm_queue_exception(vcpu, GP_VECTOR);
2883                                 break;
2884                         }
2885                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2886                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2887                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2888                                 vcpu->arch.switch_db_regs =
2889                                         (val & DR7_BP_EN_MASK);
2890                         }
2891                         break;
2892                 }
2893                 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2894         }
2895         skip_emulated_instruction(vcpu);
2896         return 1;
2897 }
2898
2899 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2900 {
2901         kvm_emulate_cpuid(vcpu);
2902         return 1;
2903 }
2904
2905 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2906 {
2907         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2908         u64 data;
2909
2910         if (vmx_get_msr(vcpu, ecx, &data)) {
2911                 kvm_inject_gp(vcpu, 0);
2912                 return 1;
2913         }
2914
2915         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2916                     handler);
2917
2918         /* FIXME: handling of bits 32:63 of rax, rdx */
2919         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2920         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2921         skip_emulated_instruction(vcpu);
2922         return 1;
2923 }
2924
2925 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2926 {
2927         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2928         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2929                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2930
2931         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2932                     handler);
2933
2934         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2935                 kvm_inject_gp(vcpu, 0);
2936                 return 1;
2937         }
2938
2939         skip_emulated_instruction(vcpu);
2940         return 1;
2941 }
2942
2943 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2944                                       struct kvm_run *kvm_run)
2945 {
2946         return 1;
2947 }
2948
2949 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2950                                    struct kvm_run *kvm_run)
2951 {
2952         u32 cpu_based_vm_exec_control;
2953
2954         /* clear pending irq */
2955         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2956         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2957         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2958
2959         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2960         ++vcpu->stat.irq_window_exits;
2961
2962         /*
2963          * If the user space waits to inject interrupts, exit as soon as
2964          * possible
2965          */
2966         if (kvm_run->request_interrupt_window &&
2967             !vcpu->arch.irq_summary) {
2968                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2969                 return 0;
2970         }
2971         return 1;
2972 }
2973
2974 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2975 {
2976         skip_emulated_instruction(vcpu);
2977         return kvm_emulate_halt(vcpu);
2978 }
2979
2980 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2981 {
2982         skip_emulated_instruction(vcpu);
2983         kvm_emulate_hypercall(vcpu);
2984         return 1;
2985 }
2986
2987 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2988 {
2989         u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2990
2991         kvm_mmu_invlpg(vcpu, exit_qualification);
2992         skip_emulated_instruction(vcpu);
2993         return 1;
2994 }
2995
2996 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2997 {
2998         skip_emulated_instruction(vcpu);
2999         /* TODO: Add support for VT-d/pass-through device */
3000         return 1;
3001 }
3002
3003 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3004 {
3005         u64 exit_qualification;
3006         enum emulation_result er;
3007         unsigned long offset;
3008
3009         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3010         offset = exit_qualification & 0xffful;
3011
3012         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3013
3014         if (er !=  EMULATE_DONE) {
3015                 printk(KERN_ERR
3016                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3017                        offset);
3018                 return -ENOTSUPP;
3019         }
3020         return 1;
3021 }
3022
3023 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3024 {
3025         struct vcpu_vmx *vmx = to_vmx(vcpu);
3026         unsigned long exit_qualification;
3027         u16 tss_selector;
3028         int reason;
3029
3030         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3031
3032         reason = (u32)exit_qualification >> 30;
3033         if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3034             (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3035             (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3036             == INTR_TYPE_NMI_INTR) {
3037                 vcpu->arch.nmi_injected = false;
3038                 if (cpu_has_virtual_nmis())
3039                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3040                                       GUEST_INTR_STATE_NMI);
3041         }
3042         tss_selector = exit_qualification;
3043
3044         if (!kvm_task_switch(vcpu, tss_selector, reason))
3045                 return 0;
3046
3047         /* clear all local breakpoint enable flags */
3048         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3049
3050         /*
3051          * TODO: What about debug traps on tss switch?
3052          *       Are we supposed to inject them and update dr6?
3053          */
3054
3055         return 1;
3056 }
3057
3058 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3059 {
3060         u64 exit_qualification;
3061         gpa_t gpa;
3062         int gla_validity;
3063
3064         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3065
3066         if (exit_qualification & (1 << 6)) {
3067                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3068                 return -ENOTSUPP;
3069         }
3070
3071         gla_validity = (exit_qualification >> 7) & 0x3;
3072         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3073                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3074                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3075                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3076                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3077                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3078                         (long unsigned int)exit_qualification);
3079                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3080                 kvm_run->hw.hardware_exit_reason = 0;
3081                 return -ENOTSUPP;
3082         }
3083
3084         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3085         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3086 }
3087
3088 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3089 {
3090         u32 cpu_based_vm_exec_control;
3091
3092         /* clear pending NMI */
3093         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3094         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3095         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3096         ++vcpu->stat.nmi_window_exits;
3097
3098         return 1;
3099 }
3100
3101 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3102                                 struct kvm_run *kvm_run)
3103 {
3104         struct vcpu_vmx *vmx = to_vmx(vcpu);
3105         enum emulation_result err = EMULATE_DONE;
3106
3107         preempt_enable();
3108         local_irq_enable();
3109
3110         while (!guest_state_valid(vcpu)) {
3111                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3112
3113                 if (err == EMULATE_DO_MMIO)
3114                         break;
3115
3116                 if (err != EMULATE_DONE) {
3117                         kvm_report_emulation_failure(vcpu, "emulation failure");
3118                         return;
3119                 }
3120
3121                 if (signal_pending(current))
3122                         break;
3123                 if (need_resched())
3124                         schedule();
3125         }
3126
3127         local_irq_disable();
3128         preempt_disable();
3129
3130         vmx->invalid_state_emulation_result = err;
3131 }
3132
3133 /*
3134  * The exit handlers return 1 if the exit was handled fully and guest execution
3135  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3136  * to be done to userspace and return 0.
3137  */
3138 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3139                                       struct kvm_run *kvm_run) = {
3140         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3141         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3142         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3143         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3144         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3145         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3146         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3147         [EXIT_REASON_CPUID]                   = handle_cpuid,
3148         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3149         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3150         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3151         [EXIT_REASON_HLT]                     = handle_halt,
3152         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3153         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3154         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3155         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3156         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3157         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3158         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3159 };
3160
3161 static const int kvm_vmx_max_exit_handlers =
3162         ARRAY_SIZE(kvm_vmx_exit_handlers);
3163
3164 /*
3165  * The guest has exited.  See if we can fix it or if we need userspace
3166  * assistance.
3167  */
3168 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3169 {
3170         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3171         struct vcpu_vmx *vmx = to_vmx(vcpu);
3172         u32 vectoring_info = vmx->idt_vectoring_info;
3173
3174         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3175                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3176
3177         /* If we need to emulate an MMIO from handle_invalid_guest_state
3178          * we just return 0 */
3179         if (vmx->emulation_required && emulate_invalid_guest_state) {
3180                 if (guest_state_valid(vcpu))
3181                         vmx->emulation_required = 0;
3182                 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3183         }
3184
3185         /* Access CR3 don't cause VMExit in paging mode, so we need
3186          * to sync with guest real CR3. */
3187         if (vm_need_ept() && is_paging(vcpu)) {
3188                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3189                 ept_load_pdptrs(vcpu);
3190         }
3191
3192         if (unlikely(vmx->fail)) {
3193                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3194                 kvm_run->fail_entry.hardware_entry_failure_reason
3195                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3196                 return 0;
3197         }
3198
3199         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3200                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3201                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3202                         exit_reason != EXIT_REASON_TASK_SWITCH))
3203                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3204                        "(0x%x) and exit reason is 0x%x\n",
3205                        __func__, vectoring_info, exit_reason);
3206
3207         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3208                 if (vcpu->arch.interrupt_window_open) {
3209                         vmx->soft_vnmi_blocked = 0;
3210                         vcpu->arch.nmi_window_open = 1;
3211                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3212                            vcpu->arch.nmi_pending) {
3213                         /*
3214                          * This CPU don't support us in finding the end of an
3215                          * NMI-blocked window if the guest runs with IRQs
3216                          * disabled. So we pull the trigger after 1 s of
3217                          * futile waiting, but inform the user about this.
3218                          */
3219                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3220                                "state on VCPU %d after 1 s timeout\n",
3221                                __func__, vcpu->vcpu_id);
3222                         vmx->soft_vnmi_blocked = 0;
3223                         vmx->vcpu.arch.nmi_window_open = 1;
3224                 }
3225         }
3226
3227         if (exit_reason < kvm_vmx_max_exit_handlers
3228             && kvm_vmx_exit_handlers[exit_reason])
3229                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3230         else {
3231                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3232                 kvm_run->hw.hardware_exit_reason = exit_reason;
3233         }
3234         return 0;
3235 }
3236
3237 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3238 {
3239         int max_irr, tpr;
3240
3241         if (!vm_need_tpr_shadow(vcpu->kvm))
3242                 return;
3243
3244         if (!kvm_lapic_enabled(vcpu) ||
3245             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3246                 vmcs_write32(TPR_THRESHOLD, 0);
3247                 return;
3248         }
3249
3250         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3251         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3252 }
3253
3254 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3255 {
3256         u32 exit_intr_info;
3257         u32 idt_vectoring_info;
3258         bool unblock_nmi;
3259         u8 vector;
3260         int type;
3261         bool idtv_info_valid;
3262         u32 error;
3263
3264         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3265         if (cpu_has_virtual_nmis()) {
3266                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3267                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3268                 /*
3269                  * SDM 3: 25.7.1.2
3270                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3271                  * a guest IRET fault.
3272                  */
3273                 if (unblock_nmi && vector != DF_VECTOR)
3274                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3275                                       GUEST_INTR_STATE_NMI);
3276         } else if (unlikely(vmx->soft_vnmi_blocked))
3277                 vmx->vnmi_blocked_time +=
3278                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3279
3280         idt_vectoring_info = vmx->idt_vectoring_info;
3281         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3282         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3283         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3284         if (vmx->vcpu.arch.nmi_injected) {
3285                 /*
3286                  * SDM 3: 25.7.1.2
3287                  * Clear bit "block by NMI" before VM entry if a NMI delivery
3288                  * faulted.
3289                  */
3290                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3291                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3292                                         GUEST_INTR_STATE_NMI);
3293                 else
3294                         vmx->vcpu.arch.nmi_injected = false;
3295         }
3296         kvm_clear_exception_queue(&vmx->vcpu);
3297         if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3298                                 type == INTR_TYPE_SOFT_EXCEPTION)) {
3299                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3300                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3301                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
3302                 } else
3303                         kvm_queue_exception(&vmx->vcpu, vector);
3304                 vmx->idt_vectoring_info = 0;
3305         }
3306         kvm_clear_interrupt_queue(&vmx->vcpu);
3307         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3308                 kvm_queue_interrupt(&vmx->vcpu, vector);
3309                 vmx->idt_vectoring_info = 0;
3310         }
3311 }
3312
3313 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3314 {
3315         update_tpr_threshold(vcpu);
3316
3317         vmx_update_window_states(vcpu);
3318
3319         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3320                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3321                                 GUEST_INTR_STATE_STI |
3322                                 GUEST_INTR_STATE_MOV_SS);
3323
3324         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3325                 if (vcpu->arch.interrupt.pending) {
3326                         enable_nmi_window(vcpu);
3327                 } else if (vcpu->arch.nmi_window_open) {
3328                         vcpu->arch.nmi_pending = false;
3329                         vcpu->arch.nmi_injected = true;
3330                 } else {
3331                         enable_nmi_window(vcpu);
3332                         return;
3333                 }
3334         }
3335         if (vcpu->arch.nmi_injected) {
3336                 vmx_inject_nmi(vcpu);
3337                 if (vcpu->arch.nmi_pending)
3338                         enable_nmi_window(vcpu);
3339                 else if (kvm_cpu_has_interrupt(vcpu))
3340                         enable_irq_window(vcpu);
3341                 return;
3342         }
3343         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3344                 if (vcpu->arch.interrupt_window_open)
3345                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3346                 else
3347                         enable_irq_window(vcpu);
3348         }
3349         if (vcpu->arch.interrupt.pending) {
3350                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3351                 if (kvm_cpu_has_interrupt(vcpu))
3352                         enable_irq_window(vcpu);
3353         }
3354 }
3355
3356 /*
3357  * Failure to inject an interrupt should give us the information
3358  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3359  * when fetching the interrupt redirection bitmap in the real-mode
3360  * tss, this doesn't happen.  So we do it ourselves.
3361  */
3362 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3363 {
3364         vmx->rmode.irq.pending = 0;
3365         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3366                 return;
3367         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3368         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3369                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3370                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3371                 return;
3372         }
3373         vmx->idt_vectoring_info =
3374                 VECTORING_INFO_VALID_MASK
3375                 | INTR_TYPE_EXT_INTR
3376                 | vmx->rmode.irq.vector;
3377 }
3378
3379 #ifdef CONFIG_X86_64
3380 #define R "r"
3381 #define Q "q"
3382 #else
3383 #define R "e"
3384 #define Q "l"
3385 #endif
3386
3387 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3388 {
3389         struct vcpu_vmx *vmx = to_vmx(vcpu);
3390         u32 intr_info;
3391
3392         /* Record the guest's net vcpu time for enforced NMI injections. */
3393         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3394                 vmx->entry_time = ktime_get();
3395
3396         /* Handle invalid guest state instead of entering VMX */
3397         if (vmx->emulation_required && emulate_invalid_guest_state) {
3398                 handle_invalid_guest_state(vcpu, kvm_run);
3399                 return;
3400         }
3401
3402         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3403                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3404         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3405                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3406
3407         /*
3408          * Loading guest fpu may have cleared host cr0.ts
3409          */
3410         vmcs_writel(HOST_CR0, read_cr0());
3411
3412         set_debugreg(vcpu->arch.dr6, 6);
3413
3414         asm(
3415                 /* Store host registers */
3416                 "push %%"R"dx; push %%"R"bp;"
3417                 "push %%"R"cx \n\t"
3418                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3419                 "je 1f \n\t"
3420                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3421                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3422                 "1: \n\t"
3423                 /* Check if vmlaunch of vmresume is needed */
3424                 "cmpl $0, %c[launched](%0) \n\t"
3425                 /* Load guest registers.  Don't clobber flags. */
3426                 "mov %c[cr2](%0), %%"R"ax \n\t"
3427                 "mov %%"R"ax, %%cr2 \n\t"
3428                 "mov %c[rax](%0), %%"R"ax \n\t"
3429                 "mov %c[rbx](%0), %%"R"bx \n\t"
3430                 "mov %c[rdx](%0), %%"R"dx \n\t"
3431                 "mov %c[rsi](%0), %%"R"si \n\t"
3432                 "mov %c[rdi](%0), %%"R"di \n\t"
3433                 "mov %c[rbp](%0), %%"R"bp \n\t"
3434 #ifdef CONFIG_X86_64
3435                 "mov %c[r8](%0),  %%r8  \n\t"
3436                 "mov %c[r9](%0),  %%r9  \n\t"
3437                 "mov %c[r10](%0), %%r10 \n\t"
3438                 "mov %c[r11](%0), %%r11 \n\t"
3439                 "mov %c[r12](%0), %%r12 \n\t"
3440                 "mov %c[r13](%0), %%r13 \n\t"
3441                 "mov %c[r14](%0), %%r14 \n\t"
3442                 "mov %c[r15](%0), %%r15 \n\t"
3443 #endif
3444                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3445
3446                 /* Enter guest mode */
3447                 "jne .Llaunched \n\t"
3448                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3449                 "jmp .Lkvm_vmx_return \n\t"
3450                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3451                 ".Lkvm_vmx_return: "
3452                 /* Save guest registers, load host registers, keep flags */
3453                 "xchg %0,     (%%"R"sp) \n\t"
3454                 "mov %%"R"ax, %c[rax](%0) \n\t"
3455                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3456                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3457                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3458                 "mov %%"R"si, %c[rsi](%0) \n\t"
3459                 "mov %%"R"di, %c[rdi](%0) \n\t"
3460                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3461 #ifdef CONFIG_X86_64
3462                 "mov %%r8,  %c[r8](%0) \n\t"
3463                 "mov %%r9,  %c[r9](%0) \n\t"
3464                 "mov %%r10, %c[r10](%0) \n\t"
3465                 "mov %%r11, %c[r11](%0) \n\t"
3466                 "mov %%r12, %c[r12](%0) \n\t"
3467                 "mov %%r13, %c[r13](%0) \n\t"
3468                 "mov %%r14, %c[r14](%0) \n\t"
3469                 "mov %%r15, %c[r15](%0) \n\t"
3470 #endif
3471                 "mov %%cr2, %%"R"ax   \n\t"
3472                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3473
3474                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3475                 "setbe %c[fail](%0) \n\t"
3476               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3477                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3478                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3479                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3480                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3481                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3482                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3483                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3484                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3485                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3486                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3487 #ifdef CONFIG_X86_64
3488                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3489                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3490                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3491                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3492                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3493                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3494                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3495                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3496 #endif
3497                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3498               : "cc", "memory"
3499                 , R"bx", R"di", R"si"
3500 #ifdef CONFIG_X86_64
3501                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3502 #endif
3503               );
3504
3505         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3506         vcpu->arch.regs_dirty = 0;
3507
3508         get_debugreg(vcpu->arch.dr6, 6);
3509
3510         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3511         if (vmx->rmode.irq.pending)
3512                 fixup_rmode_irq(vmx);
3513
3514         vmx_update_window_states(vcpu);
3515
3516         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3517         vmx->launched = 1;
3518
3519         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3520
3521         /* We need to handle NMIs before interrupts are enabled */
3522         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3523             (intr_info & INTR_INFO_VALID_MASK)) {
3524                 KVMTRACE_0D(NMI, vcpu, handler);
3525                 asm("int $2");
3526         }
3527
3528         vmx_complete_interrupts(vmx);
3529 }
3530
3531 #undef R
3532 #undef Q
3533
3534 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3535 {
3536         struct vcpu_vmx *vmx = to_vmx(vcpu);
3537
3538         if (vmx->vmcs) {
3539                 vcpu_clear(vmx);
3540                 free_vmcs(vmx->vmcs);
3541                 vmx->vmcs = NULL;
3542         }
3543 }
3544
3545 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3546 {
3547         struct vcpu_vmx *vmx = to_vmx(vcpu);
3548
3549         spin_lock(&vmx_vpid_lock);
3550         if (vmx->vpid != 0)
3551                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3552         spin_unlock(&vmx_vpid_lock);
3553         vmx_free_vmcs(vcpu);
3554         kfree(vmx->host_msrs);
3555         kfree(vmx->guest_msrs);
3556         kvm_vcpu_uninit(vcpu);
3557         kmem_cache_free(kvm_vcpu_cache, vmx);
3558 }
3559
3560 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3561 {
3562         int err;
3563         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3564         int cpu;
3565
3566         if (!vmx)
3567                 return ERR_PTR(-ENOMEM);
3568
3569         allocate_vpid(vmx);
3570
3571         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3572         if (err)
3573                 goto free_vcpu;
3574
3575         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3576         if (!vmx->guest_msrs) {
3577                 err = -ENOMEM;
3578                 goto uninit_vcpu;
3579         }
3580
3581         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3582         if (!vmx->host_msrs)
3583                 goto free_guest_msrs;
3584
3585         vmx->vmcs = alloc_vmcs();
3586         if (!vmx->vmcs)
3587                 goto free_msrs;
3588
3589         vmcs_clear(vmx->vmcs);
3590
3591         cpu = get_cpu();
3592         vmx_vcpu_load(&vmx->vcpu, cpu);
3593         err = vmx_vcpu_setup(vmx);
3594         vmx_vcpu_put(&vmx->vcpu);
3595         put_cpu();
3596         if (err)
3597                 goto free_vmcs;
3598         if (vm_need_virtualize_apic_accesses(kvm))
3599                 if (alloc_apic_access_page(kvm) != 0)
3600                         goto free_vmcs;
3601
3602         if (vm_need_ept())
3603                 if (alloc_identity_pagetable(kvm) != 0)
3604                         goto free_vmcs;
3605
3606         return &vmx->vcpu;
3607
3608 free_vmcs:
3609         free_vmcs(vmx->vmcs);
3610 free_msrs:
3611         kfree(vmx->host_msrs);
3612 free_guest_msrs:
3613         kfree(vmx->guest_msrs);
3614 uninit_vcpu:
3615         kvm_vcpu_uninit(&vmx->vcpu);
3616 free_vcpu:
3617         kmem_cache_free(kvm_vcpu_cache, vmx);
3618         return ERR_PTR(err);
3619 }
3620
3621 static void __init vmx_check_processor_compat(void *rtn)
3622 {
3623         struct vmcs_config vmcs_conf;
3624
3625         *(int *)rtn = 0;
3626         if (setup_vmcs_config(&vmcs_conf) < 0)
3627                 *(int *)rtn = -EIO;
3628         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3629                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3630                                 smp_processor_id());
3631                 *(int *)rtn = -EIO;
3632         }
3633 }
3634
3635 static int get_ept_level(void)
3636 {
3637         return VMX_EPT_DEFAULT_GAW + 1;
3638 }
3639
3640 static int vmx_get_mt_mask_shift(void)
3641 {
3642         return VMX_EPT_MT_EPTE_SHIFT;
3643 }
3644
3645 static struct kvm_x86_ops vmx_x86_ops = {
3646         .cpu_has_kvm_support = cpu_has_kvm_support,
3647         .disabled_by_bios = vmx_disabled_by_bios,
3648         .hardware_setup = hardware_setup,
3649         .hardware_unsetup = hardware_unsetup,
3650         .check_processor_compatibility = vmx_check_processor_compat,
3651         .hardware_enable = hardware_enable,
3652         .hardware_disable = hardware_disable,
3653         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3654
3655         .vcpu_create = vmx_create_vcpu,
3656         .vcpu_free = vmx_free_vcpu,
3657         .vcpu_reset = vmx_vcpu_reset,
3658
3659         .prepare_guest_switch = vmx_save_host_state,
3660         .vcpu_load = vmx_vcpu_load,
3661         .vcpu_put = vmx_vcpu_put,
3662
3663         .set_guest_debug = set_guest_debug,
3664         .get_msr = vmx_get_msr,
3665         .set_msr = vmx_set_msr,
3666         .get_segment_base = vmx_get_segment_base,
3667         .get_segment = vmx_get_segment,
3668         .set_segment = vmx_set_segment,
3669         .get_cpl = vmx_get_cpl,
3670         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3671         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3672         .set_cr0 = vmx_set_cr0,
3673         .set_cr3 = vmx_set_cr3,
3674         .set_cr4 = vmx_set_cr4,
3675         .set_efer = vmx_set_efer,
3676         .get_idt = vmx_get_idt,
3677         .set_idt = vmx_set_idt,
3678         .get_gdt = vmx_get_gdt,
3679         .set_gdt = vmx_set_gdt,
3680         .cache_reg = vmx_cache_reg,
3681         .get_rflags = vmx_get_rflags,
3682         .set_rflags = vmx_set_rflags,
3683
3684         .tlb_flush = vmx_flush_tlb,
3685
3686         .run = vmx_vcpu_run,
3687         .handle_exit = vmx_handle_exit,
3688         .skip_emulated_instruction = skip_emulated_instruction,
3689         .patch_hypercall = vmx_patch_hypercall,
3690         .get_irq = vmx_get_irq,
3691         .set_irq = vmx_inject_irq,
3692         .queue_exception = vmx_queue_exception,
3693         .exception_injected = vmx_exception_injected,
3694         .inject_pending_irq = vmx_intr_assist,
3695         .inject_pending_vectors = do_interrupt_requests,
3696
3697         .set_tss_addr = vmx_set_tss_addr,
3698         .get_tdp_level = get_ept_level,
3699         .get_mt_mask_shift = vmx_get_mt_mask_shift,
3700 };
3701
3702 static int __init vmx_init(void)
3703 {
3704         int r;
3705
3706         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3707         if (!vmx_io_bitmap_a)
3708                 return -ENOMEM;
3709
3710         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3711         if (!vmx_io_bitmap_b) {
3712                 r = -ENOMEM;
3713                 goto out;
3714         }
3715
3716         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3717         if (!vmx_msr_bitmap_legacy) {
3718                 r = -ENOMEM;
3719                 goto out1;
3720         }
3721
3722         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3723         if (!vmx_msr_bitmap_longmode) {
3724                 r = -ENOMEM;
3725                 goto out2;
3726         }
3727
3728         /*
3729          * Allow direct access to the PC debug port (it is often used for I/O
3730          * delays, but the vmexits simply slow things down).
3731          */
3732         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3733         clear_bit(0x80, vmx_io_bitmap_a);
3734
3735         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3736
3737         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3738         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3739
3740         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3741
3742         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3743         if (r)
3744                 goto out3;
3745
3746         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3747         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3748         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3749         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3750         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3751         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3752
3753         if (vm_need_ept()) {
3754                 bypass_guest_pf = 0;
3755                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3756                         VMX_EPT_WRITABLE_MASK);
3757                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3758                                 VMX_EPT_EXECUTABLE_MASK,
3759                                 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3760                 kvm_enable_tdp();
3761         } else
3762                 kvm_disable_tdp();
3763
3764         if (bypass_guest_pf)
3765                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3766
3767         ept_sync_global();
3768
3769         return 0;
3770
3771 out3:
3772         free_page((unsigned long)vmx_msr_bitmap_longmode);
3773 out2:
3774         free_page((unsigned long)vmx_msr_bitmap_legacy);
3775 out1:
3776         free_page((unsigned long)vmx_io_bitmap_b);
3777 out:
3778         free_page((unsigned long)vmx_io_bitmap_a);
3779         return r;
3780 }
3781
3782 static void __exit vmx_exit(void)
3783 {
3784         free_page((unsigned long)vmx_msr_bitmap_legacy);
3785         free_page((unsigned long)vmx_msr_bitmap_longmode);
3786         free_page((unsigned long)vmx_io_bitmap_b);
3787         free_page((unsigned long)vmx_io_bitmap_a);
3788
3789         kvm_exit();
3790 }
3791
3792 module_init(vmx_init)
3793 module_exit(vmx_exit)