SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 struct vmcs {
  65         u32 revision_id;
  66         u32 abort;
  67         char data[0];
  68 };
  69
  70 struct vcpu_vmx {
  71         struct kvm_vcpu       vcpu;
  72         struct list_head      local_vcpus_link;
  73         unsigned long         host_rsp;
  74         int                   launched;
  75         u8                    fail;
  76         u32                   idt_vectoring_info;
  77         struct kvm_msr_entry *guest_msrs;
  78         struct kvm_msr_entry *host_msrs;
  79         int                   nmsrs;
  80         int                   save_nmsrs;
  81         int                   msr_offset_efer;
  82 #ifdef CONFIG_X86_64
  83         int                   msr_offset_kernel_gs_base;
  84 #endif
  85         struct vmcs          *vmcs;
  86         struct {
  87                 int           loaded;
  88                 u16           fs_sel, gs_sel, ldt_sel;
  89                 int           gs_ldt_reload_needed;
  90                 int           fs_reload_needed;
  91                 int           guest_efer_loaded;
  92         } host_state;
  93         struct {
  94                 int vm86_active;
  95                 u8 save_iopl;
  96                 struct kvm_save_segment {
  97                         u16 selector;
  98                         unsigned long base;
  99                         u32 limit;
 100                         u32 ar;
 101                 } tr, es, ds, fs, gs;
 102                 struct {
 103                         bool pending;
 104                         u8 vector;
 105                         unsigned rip;
 106                 } irq;
 107         } rmode;
 108         int vpid;
 109         bool emulation_required;
 110
 111         /* Support for vnmi-less CPUs */
 112         int soft_vnmi_blocked;
 113         ktime_t entry_time;
 114         s64 vnmi_blocked_time;
 115         u32 exit_reason;
 116 };
 117
 118 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 119 {
 120         return container_of(vcpu, struct vcpu_vmx, vcpu);
 121 }
 122
 123 static int init_rmode(struct kvm *kvm);
 124 static u64 construct_eptp(unsigned long root_hpa);
 125
 126 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 127 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 128 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 129
 130 static unsigned long *vmx_io_bitmap_a;
 131 static unsigned long *vmx_io_bitmap_b;
 132 static unsigned long *vmx_msr_bitmap_legacy;
 133 static unsigned long *vmx_msr_bitmap_longmode;
 134
 135 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 136 static DEFINE_SPINLOCK(vmx_vpid_lock);
 137
 138 static struct vmcs_config {
 139         int size;
 140         int order;
 141         u32 revision_id;
 142         u32 pin_based_exec_ctrl;
 143         u32 cpu_based_exec_ctrl;
 144         u32 cpu_based_2nd_exec_ctrl;
 145         u32 vmexit_ctrl;
 146         u32 vmentry_ctrl;
 147 } vmcs_config;
 148
 149 static struct vmx_capability {
 150         u32 ept;
 151         u32 vpid;
 152 } vmx_capability;
 153
 154 #define VMX_SEGMENT_FIELD(seg)                                  \
 155         [VCPU_SREG_##seg] = {                                   \
 156                 .selector = GUEST_##seg##_SELECTOR,             \
 157                 .base = GUEST_##seg##_BASE,                     \
 158                 .limit = GUEST_##seg##_LIMIT,                   \
 159                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 160         }
 161
 162 static struct kvm_vmx_segment_field {
 163         unsigned selector;
 164         unsigned base;
 165         unsigned limit;
 166         unsigned ar_bytes;
 167 } kvm_vmx_segment_fields[] = {
 168         VMX_SEGMENT_FIELD(CS),
 169         VMX_SEGMENT_FIELD(DS),
 170         VMX_SEGMENT_FIELD(ES),
 171         VMX_SEGMENT_FIELD(FS),
 172         VMX_SEGMENT_FIELD(GS),
 173         VMX_SEGMENT_FIELD(SS),
 174         VMX_SEGMENT_FIELD(TR),
 175         VMX_SEGMENT_FIELD(LDTR),
 176 };
 177
 178 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 179
 180 /*
 181  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 182  * away by decrementing the array size.
 183  */
 184 static const u32 vmx_msr_index[] = {
 185 #ifdef CONFIG_X86_64
 186         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 187 #endif
 188         MSR_EFER, MSR_K6_STAR,
 189 };
 190 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 191
 192 static void load_msrs(struct kvm_msr_entry *e, int n)
 193 {
 194         int i;
 195
 196         for (i = 0; i < n; ++i)
 197                 wrmsrl(e[i].index, e[i].data);
 198 }
 199
 200 static void save_msrs(struct kvm_msr_entry *e, int n)
 201 {
 202         int i;
 203
 204         for (i = 0; i < n; ++i)
 205                 rdmsrl(e[i].index, e[i].data);
 206 }
 207
 208 static inline int is_page_fault(u32 intr_info)
 209 {
 210         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 211                              INTR_INFO_VALID_MASK)) ==
 212                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 213 }
 214
 215 static inline int is_no_device(u32 intr_info)
 216 {
 217         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 218                              INTR_INFO_VALID_MASK)) ==
 219                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 220 }
 221
 222 static inline int is_invalid_opcode(u32 intr_info)
 223 {
 224         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 225                              INTR_INFO_VALID_MASK)) ==
 226                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 227 }
 228
 229 static inline int is_external_interrupt(u32 intr_info)
 230 {
 231         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 232                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 233 }
 234
 235 static inline int is_machine_check(u32 intr_info)
 236 {
 237         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 238                              INTR_INFO_VALID_MASK)) ==
 239                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 240 }
 241
 242 static inline int cpu_has_vmx_msr_bitmap(void)
 243 {
 244         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 245 }
 246
 247 static inline int cpu_has_vmx_tpr_shadow(void)
 248 {
 249         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 250 }
 251
 252 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 253 {
 254         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 255 }
 256
 257 static inline int cpu_has_secondary_exec_ctrls(void)
 258 {
 259         return vmcs_config.cpu_based_exec_ctrl &
 260                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 261 }
 262
 263 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 264 {
 265         return vmcs_config.cpu_based_2nd_exec_ctrl &
 266                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 267 }
 268
 269 static inline bool cpu_has_vmx_flexpriority(void)
 270 {
 271         return cpu_has_vmx_tpr_shadow() &&
 272                 cpu_has_vmx_virtualize_apic_accesses();
 273 }
 274
 275 static inline bool cpu_has_vmx_ept_execute_only(void)
 276 {
 277         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 278 }
 279
 280 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 281 {
 282         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 283 }
 284
 285 static inline bool cpu_has_vmx_eptp_writeback(void)
 286 {
 287         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 288 }
 289
 290 static inline bool cpu_has_vmx_ept_2m_page(void)
 291 {
 292         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 293 }
 294
 295 static inline int cpu_has_vmx_invept_individual_addr(void)
 296 {
 297         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 298 }
 299
 300 static inline int cpu_has_vmx_invept_context(void)
 301 {
 302         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 303 }
 304
 305 static inline int cpu_has_vmx_invept_global(void)
 306 {
 307         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 308 }
 309
 310 static inline int cpu_has_vmx_ept(void)
 311 {
 312         return vmcs_config.cpu_based_2nd_exec_ctrl &
 313                 SECONDARY_EXEC_ENABLE_EPT;
 314 }
 315
 316 static inline int cpu_has_vmx_unrestricted_guest(void)
 317 {
 318         return vmcs_config.cpu_based_2nd_exec_ctrl &
 319                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 320 }
 321
 322 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 323 {
 324         return flexpriority_enabled &&
 325                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 326                 (irqchip_in_kernel(kvm));
 327 }
 328
 329 static inline int cpu_has_vmx_vpid(void)
 330 {
 331         return vmcs_config.cpu_based_2nd_exec_ctrl &
 332                 SECONDARY_EXEC_ENABLE_VPID;
 333 }
 334
 335 static inline int cpu_has_virtual_nmis(void)
 336 {
 337         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 338 }
 339
 340 static inline bool report_flexpriority(void)
 341 {
 342         return flexpriority_enabled;
 343 }
 344
 345 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 346 {
 347         int i;
 348
 349         for (i = 0; i < vmx->nmsrs; ++i)
 350                 if (vmx->guest_msrs[i].index == msr)
 351                         return i;
 352         return -1;
 353 }
 354
 355 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 356 {
 357     struct {
 358         u64 vpid : 16;
 359         u64 rsvd : 48;
 360         u64 gva;
 361     } operand = { vpid, 0, gva };
 362
 363     asm volatile (__ex(ASM_VMX_INVVPID)
 364                   /* CF==1 or ZF==1 --> rc = -1 */
 365                   "; ja 1f ; ud2 ; 1:"
 366                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 367 }
 368
 369 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 370 {
 371         struct {
 372                 u64 eptp, gpa;
 373         } operand = {eptp, gpa};
 374
 375         asm volatile (__ex(ASM_VMX_INVEPT)
 376                         /* CF==1 or ZF==1 --> rc = -1 */
 377                         "; ja 1f ; ud2 ; 1:\n"
 378                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 379 }
 380
 381 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 382 {
 383         int i;
 384
 385         i = __find_msr_index(vmx, msr);
 386         if (i >= 0)
 387                 return &vmx->guest_msrs[i];
 388         return NULL;
 389 }
 390
 391 static void vmcs_clear(struct vmcs *vmcs)
 392 {
 393         u64 phys_addr = __pa(vmcs);
 394         u8 error;
 395
 396         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 397                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 398                       : "cc", "memory");
 399         if (error)
 400                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 401                        vmcs, phys_addr);
 402 }
 403
 404 static void __vcpu_clear(void *arg)
 405 {
 406         struct vcpu_vmx *vmx = arg;
 407         int cpu = raw_smp_processor_id();
 408
 409         if (vmx->vcpu.cpu == cpu)
 410                 vmcs_clear(vmx->vmcs);
 411         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 412                 per_cpu(current_vmcs, cpu) = NULL;
 413         rdtscll(vmx->vcpu.arch.host_tsc);
 414         list_del(&vmx->local_vcpus_link);
 415         vmx->vcpu.cpu = -1;
 416         vmx->launched = 0;
 417 }
 418
 419 static void vcpu_clear(struct vcpu_vmx *vmx)
 420 {
 421         if (vmx->vcpu.cpu == -1)
 422                 return;
 423         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 424 }
 425
 426 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 427 {
 428         if (vmx->vpid == 0)
 429                 return;
 430
 431         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 432 }
 433
 434 static inline void ept_sync_global(void)
 435 {
 436         if (cpu_has_vmx_invept_global())
 437                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 438 }
 439
 440 static inline void ept_sync_context(u64 eptp)
 441 {
 442         if (enable_ept) {
 443                 if (cpu_has_vmx_invept_context())
 444                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 445                 else
 446                         ept_sync_global();
 447         }
 448 }
 449
 450 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 451 {
 452         if (enable_ept) {
 453                 if (cpu_has_vmx_invept_individual_addr())
 454                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 455                                         eptp, gpa);
 456                 else
 457                         ept_sync_context(eptp);
 458         }
 459 }
 460
 461 static unsigned long vmcs_readl(unsigned long field)
 462 {
 463         unsigned long value;
 464
 465         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 466                       : "=a"(value) : "d"(field) : "cc");
 467         return value;
 468 }
 469
 470 static u16 vmcs_read16(unsigned long field)
 471 {
 472         return vmcs_readl(field);
 473 }
 474
 475 static u32 vmcs_read32(unsigned long field)
 476 {
 477         return vmcs_readl(field);
 478 }
 479
 480 static u64 vmcs_read64(unsigned long field)
 481 {
 482 #ifdef CONFIG_X86_64
 483         return vmcs_readl(field);
 484 #else
 485         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 486 #endif
 487 }
 488
 489 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 490 {
 491         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 492                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 493         dump_stack();
 494 }
 495
 496 static void vmcs_writel(unsigned long field, unsigned long value)
 497 {
 498         u8 error;
 499
 500         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 501                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 502         if (unlikely(error))
 503                 vmwrite_error(field, value);
 504 }
 505
 506 static void vmcs_write16(unsigned long field, u16 value)
 507 {
 508         vmcs_writel(field, value);
 509 }
 510
 511 static void vmcs_write32(unsigned long field, u32 value)
 512 {
 513         vmcs_writel(field, value);
 514 }
 515
 516 static void vmcs_write64(unsigned long field, u64 value)
 517 {
 518         vmcs_writel(field, value);
 519 #ifndef CONFIG_X86_64
 520         asm volatile ("");
 521         vmcs_writel(field+1, value >> 32);
 522 #endif
 523 }
 524
 525 static void vmcs_clear_bits(unsigned long field, u32 mask)
 526 {
 527         vmcs_writel(field, vmcs_readl(field) & ~mask);
 528 }
 529
 530 static void vmcs_set_bits(unsigned long field, u32 mask)
 531 {
 532         vmcs_writel(field, vmcs_readl(field) | mask);
 533 }
 534
 535 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 536 {
 537         u32 eb;
 538
 539         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 540         if (!vcpu->fpu_active)
 541                 eb |= 1u << NM_VECTOR;
 542         /*
 543          * Unconditionally intercept #DB so we can maintain dr6 without
 544          * reading it every exit.
 545          */
 546         eb |= 1u << DB_VECTOR;
 547         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 548                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 549                         eb |= 1u << BP_VECTOR;
 550         }
 551         if (to_vmx(vcpu)->rmode.vm86_active)
 552                 eb = ~0;
 553         if (enable_ept)
 554                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 555         vmcs_write32(EXCEPTION_BITMAP, eb);
 556 }
 557
 558 static void reload_tss(void)
 559 {
 560         /*
 561          * VT restores TR but not its size.  Useless.
 562          */
 563         struct descriptor_table gdt;
 564         struct desc_struct *descs;
 565
 566         kvm_get_gdt(&gdt);
 567         descs = (void *)gdt.base;
 568         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 569         load_TR_desc();
 570 }
 571
 572 static void load_transition_efer(struct vcpu_vmx *vmx)
 573 {
 574         int efer_offset = vmx->msr_offset_efer;
 575         u64 host_efer;
 576         u64 guest_efer;
 577         u64 ignore_bits;
 578
 579         if (efer_offset < 0)
 580                 return;
 581         host_efer = vmx->host_msrs[efer_offset].data;
 582         guest_efer = vmx->guest_msrs[efer_offset].data;
 583
 584         /*
 585          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 586          * outside long mode
 587          */
 588         ignore_bits = EFER_NX | EFER_SCE;
 589 #ifdef CONFIG_X86_64
 590         ignore_bits |= EFER_LMA | EFER_LME;
 591         /* SCE is meaningful only in long mode on Intel */
 592         if (guest_efer & EFER_LMA)
 593                 ignore_bits &= ~(u64)EFER_SCE;
 594 #endif
 595         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 596                 return;
 597
 598         vmx->host_state.guest_efer_loaded = 1;
 599         guest_efer &= ~ignore_bits;
 600         guest_efer |= host_efer & ignore_bits;
 601         wrmsrl(MSR_EFER, guest_efer);
 602         vmx->vcpu.stat.efer_reload++;
 603 }
 604
 605 static void reload_host_efer(struct vcpu_vmx *vmx)
 606 {
 607         if (vmx->host_state.guest_efer_loaded) {
 608                 vmx->host_state.guest_efer_loaded = 0;
 609                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 610         }
 611 }
 612
 613 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 614 {
 615         struct vcpu_vmx *vmx = to_vmx(vcpu);
 616
 617         if (vmx->host_state.loaded)
 618                 return;
 619
 620         vmx->host_state.loaded = 1;
 621         /*
 622          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 623          * allow segment selectors with cpl > 0 or ti == 1.
 624          */
 625         vmx->host_state.ldt_sel = kvm_read_ldt();
 626         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 627         vmx->host_state.fs_sel = kvm_read_fs();
 628         if (!(vmx->host_state.fs_sel & 7)) {
 629                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 630                 vmx->host_state.fs_reload_needed = 0;
 631         } else {
 632                 vmcs_write16(HOST_FS_SELECTOR, 0);
 633                 vmx->host_state.fs_reload_needed = 1;
 634         }
 635         vmx->host_state.gs_sel = kvm_read_gs();
 636         if (!(vmx->host_state.gs_sel & 7))
 637                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 638         else {
 639                 vmcs_write16(HOST_GS_SELECTOR, 0);
 640                 vmx->host_state.gs_ldt_reload_needed = 1;
 641         }
 642
 643 #ifdef CONFIG_X86_64
 644         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 645         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 646 #else
 647         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 648         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 649 #endif
 650
 651 #ifdef CONFIG_X86_64
 652         if (is_long_mode(&vmx->vcpu))
 653                 save_msrs(vmx->host_msrs +
 654                           vmx->msr_offset_kernel_gs_base, 1);
 655
 656 #endif
 657         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 658         load_transition_efer(vmx);
 659 }
 660
 661 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 662 {
 663         unsigned long flags;
 664
 665         if (!vmx->host_state.loaded)
 666                 return;
 667
 668         ++vmx->vcpu.stat.host_state_reload;
 669         vmx->host_state.loaded = 0;
 670         if (vmx->host_state.fs_reload_needed)
 671                 kvm_load_fs(vmx->host_state.fs_sel);
 672         if (vmx->host_state.gs_ldt_reload_needed) {
 673                 kvm_load_ldt(vmx->host_state.ldt_sel);
 674                 /*
 675                  * If we have to reload gs, we must take care to
 676                  * preserve our gs base.
 677                  */
 678                 local_irq_save(flags);
 679                 kvm_load_gs(vmx->host_state.gs_sel);
 680 #ifdef CONFIG_X86_64
 681                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 682 #endif
 683                 local_irq_restore(flags);
 684         }
 685         reload_tss();
 686         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 687         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 688         reload_host_efer(vmx);
 689 }
 690
 691 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 692 {
 693         preempt_disable();
 694         __vmx_load_host_state(vmx);
 695         preempt_enable();
 696 }
 697
 698 /*
 699  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 700  * vcpu mutex is already taken.
 701  */
 702 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 703 {
 704         struct vcpu_vmx *vmx = to_vmx(vcpu);
 705         u64 phys_addr = __pa(vmx->vmcs);
 706         u64 tsc_this, delta, new_offset;
 707
 708         if (vcpu->cpu != cpu) {
 709                 vcpu_clear(vmx);
 710                 kvm_migrate_timers(vcpu);
 711                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 712                 local_irq_disable();
 713                 list_add(&vmx->local_vcpus_link,
 714                          &per_cpu(vcpus_on_cpu, cpu));
 715                 local_irq_enable();
 716         }
 717
 718         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 719                 u8 error;
 720
 721                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 722                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 723                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 724                               : "cc");
 725                 if (error)
 726                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 727                                vmx->vmcs, phys_addr);
 728         }
 729
 730         if (vcpu->cpu != cpu) {
 731                 struct descriptor_table dt;
 732                 unsigned long sysenter_esp;
 733
 734                 vcpu->cpu = cpu;
 735                 /*
 736                  * Linux uses per-cpu TSS and GDT, so set these when switching
 737                  * processors.
 738                  */
 739                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 740                 kvm_get_gdt(&dt);
 741                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 742
 743                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 744                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 745
 746                 /*
 747                  * Make sure the time stamp counter is monotonous.
 748                  */
 749                 rdtscll(tsc_this);
 750                 if (tsc_this < vcpu->arch.host_tsc) {
 751                         delta = vcpu->arch.host_tsc - tsc_this;
 752                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 753                         vmcs_write64(TSC_OFFSET, new_offset);
 754                 }
 755         }
 756 }
 757
 758 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 759 {
 760         __vmx_load_host_state(to_vmx(vcpu));
 761 }
 762
 763 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 764 {
 765         if (vcpu->fpu_active)
 766                 return;
 767         vcpu->fpu_active = 1;
 768         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 769         if (vcpu->arch.cr0 & X86_CR0_TS)
 770                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 771         update_exception_bitmap(vcpu);
 772 }
 773
 774 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 775 {
 776         if (!vcpu->fpu_active)
 777                 return;
 778         vcpu->fpu_active = 0;
 779         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 780         update_exception_bitmap(vcpu);
 781 }
 782
 783 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 784 {
 785         unsigned long rflags;
 786
 787         rflags = vmcs_readl(GUEST_RFLAGS);
 788         if (to_vmx(vcpu)->rmode.vm86_active)
 789                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 790         return rflags;
 791 }
 792
 793 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 794 {
 795         if (to_vmx(vcpu)->rmode.vm86_active)
 796                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 797         vmcs_writel(GUEST_RFLAGS, rflags);
 798 }
 799
 800 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 801 {
 802         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 803         int ret = 0;
 804
 805         if (interruptibility & GUEST_INTR_STATE_STI)
 806                 ret |= X86_SHADOW_INT_STI;
 807         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 808                 ret |= X86_SHADOW_INT_MOV_SS;
 809
 810         return ret & mask;
 811 }
 812
 813 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 814 {
 815         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 816         u32 interruptibility = interruptibility_old;
 817
 818         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 819
 820         if (mask & X86_SHADOW_INT_MOV_SS)
 821                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 822         if (mask & X86_SHADOW_INT_STI)
 823                 interruptibility |= GUEST_INTR_STATE_STI;
 824
 825         if ((interruptibility != interruptibility_old))
 826                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 827 }
 828
 829 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 830 {
 831         unsigned long rip;
 832
 833         rip = kvm_rip_read(vcpu);
 834         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 835         kvm_rip_write(vcpu, rip);
 836
 837         /* skipping an emulated instruction also counts */
 838         vmx_set_interrupt_shadow(vcpu, 0);
 839 }
 840
 841 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 842                                 bool has_error_code, u32 error_code)
 843 {
 844         struct vcpu_vmx *vmx = to_vmx(vcpu);
 845         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 846
 847         if (has_error_code) {
 848                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 849                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 850         }
 851
 852         if (vmx->rmode.vm86_active) {
 853                 vmx->rmode.irq.pending = true;
 854                 vmx->rmode.irq.vector = nr;
 855                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 856                 if (kvm_exception_is_soft(nr))
 857                         vmx->rmode.irq.rip +=
 858                                 vmx->vcpu.arch.event_exit_inst_len;
 859                 intr_info |= INTR_TYPE_SOFT_INTR;
 860                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 861                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 862                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 863                 return;
 864         }
 865
 866         if (kvm_exception_is_soft(nr)) {
 867                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 868                              vmx->vcpu.arch.event_exit_inst_len);
 869                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 870         } else
 871                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 872
 873         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 874 }
 875
 876 /*
 877  * Swap MSR entry in host/guest MSR entry array.
 878  */
 879 #ifdef CONFIG_X86_64
 880 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 881 {
 882         struct kvm_msr_entry tmp;
 883
 884         tmp = vmx->guest_msrs[to];
 885         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 886         vmx->guest_msrs[from] = tmp;
 887         tmp = vmx->host_msrs[to];
 888         vmx->host_msrs[to] = vmx->host_msrs[from];
 889         vmx->host_msrs[from] = tmp;
 890 }
 891 #endif
 892
 893 /*
 894  * Set up the vmcs to automatically save and restore system
 895  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 896  * mode, as fiddling with msrs is very expensive.
 897  */
 898 static void setup_msrs(struct vcpu_vmx *vmx)
 899 {
 900         int save_nmsrs;
 901         unsigned long *msr_bitmap;
 902
 903         vmx_load_host_state(vmx);
 904         save_nmsrs = 0;
 905 #ifdef CONFIG_X86_64
 906         if (is_long_mode(&vmx->vcpu)) {
 907                 int index;
 908
 909                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 910                 if (index >= 0)
 911                         move_msr_up(vmx, index, save_nmsrs++);
 912                 index = __find_msr_index(vmx, MSR_LSTAR);
 913                 if (index >= 0)
 914                         move_msr_up(vmx, index, save_nmsrs++);
 915                 index = __find_msr_index(vmx, MSR_CSTAR);
 916                 if (index >= 0)
 917                         move_msr_up(vmx, index, save_nmsrs++);
 918                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 919                 if (index >= 0)
 920                         move_msr_up(vmx, index, save_nmsrs++);
 921                 /*
 922                  * MSR_K6_STAR is only needed on long mode guests, and only
 923                  * if efer.sce is enabled.
 924                  */
 925                 index = __find_msr_index(vmx, MSR_K6_STAR);
 926                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 927                         move_msr_up(vmx, index, save_nmsrs++);
 928         }
 929 #endif
 930         vmx->save_nmsrs = save_nmsrs;
 931
 932 #ifdef CONFIG_X86_64
 933         vmx->msr_offset_kernel_gs_base =
 934                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 935 #endif
 936         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 937
 938         if (cpu_has_vmx_msr_bitmap()) {
 939                 if (is_long_mode(&vmx->vcpu))
 940                         msr_bitmap = vmx_msr_bitmap_longmode;
 941                 else
 942                         msr_bitmap = vmx_msr_bitmap_legacy;
 943
 944                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 945         }
 946 }
 947
 948 /*
 949  * reads and returns guest's timestamp counter "register"
 950  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 951  */
 952 static u64 guest_read_tsc(void)
 953 {
 954         u64 host_tsc, tsc_offset;
 955
 956         rdtscll(host_tsc);
 957         tsc_offset = vmcs_read64(TSC_OFFSET);
 958         return host_tsc + tsc_offset;
 959 }
 960
 961 /*
 962  * writes 'guest_tsc' into guest's timestamp counter "register"
 963  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 964  */
 965 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 966 {
 967         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 968 }
 969
 970 /*
 971  * Reads an msr value (of 'msr_index') into 'pdata'.
 972  * Returns 0 on success, non-0 otherwise.
 973  * Assumes vcpu_load() was already called.
 974  */
 975 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 976 {
 977         u64 data;
 978         struct kvm_msr_entry *msr;
 979
 980         if (!pdata) {
 981                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 982                 return -EINVAL;
 983         }
 984
 985         switch (msr_index) {
 986 #ifdef CONFIG_X86_64
 987         case MSR_FS_BASE:
 988                 data = vmcs_readl(GUEST_FS_BASE);
 989                 break;
 990         case MSR_GS_BASE:
 991                 data = vmcs_readl(GUEST_GS_BASE);
 992                 break;
 993         case MSR_EFER:
 994                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 995 #endif
 996         case MSR_IA32_TSC:
 997                 data = guest_read_tsc();
 998                 break;
 999         case MSR_IA32_SYSENTER_CS:
1000                 data = vmcs_read32(GUEST_SYSENTER_CS);
1001                 break;
1002         case MSR_IA32_SYSENTER_EIP:
1003                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1004                 break;
1005         case MSR_IA32_SYSENTER_ESP:
1006                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1007                 break;
1008         default:
1009                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1010                 if (msr) {
1011                         vmx_load_host_state(to_vmx(vcpu));
1012                         data = msr->data;
1013                         break;
1014                 }
1015                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1016         }
1017
1018         *pdata = data;
1019         return 0;
1020 }
1021
1022 /*
1023  * Writes msr value into into the appropriate "register".
1024  * Returns 0 on success, non-0 otherwise.
1025  * Assumes vcpu_load() was already called.
1026  */
1027 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1028 {
1029         struct vcpu_vmx *vmx = to_vmx(vcpu);
1030         struct kvm_msr_entry *msr;
1031         u64 host_tsc;
1032         int ret = 0;
1033
1034         switch (msr_index) {
1035         case MSR_EFER:
1036                 vmx_load_host_state(vmx);
1037                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1038                 break;
1039 #ifdef CONFIG_X86_64
1040         case MSR_FS_BASE:
1041                 vmcs_writel(GUEST_FS_BASE, data);
1042                 break;
1043         case MSR_GS_BASE:
1044                 vmcs_writel(GUEST_GS_BASE, data);
1045                 break;
1046 #endif
1047         case MSR_IA32_SYSENTER_CS:
1048                 vmcs_write32(GUEST_SYSENTER_CS, data);
1049                 break;
1050         case MSR_IA32_SYSENTER_EIP:
1051                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1052                 break;
1053         case MSR_IA32_SYSENTER_ESP:
1054                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1055                 break;
1056         case MSR_IA32_TSC:
1057                 rdtscll(host_tsc);
1058                 guest_write_tsc(data, host_tsc);
1059                 break;
1060         case MSR_IA32_CR_PAT:
1061                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1062                         vmcs_write64(GUEST_IA32_PAT, data);
1063                         vcpu->arch.pat = data;
1064                         break;
1065                 }
1066                 /* Otherwise falls through to kvm_set_msr_common */
1067         default:
1068                 msr = find_msr_entry(vmx, msr_index);
1069                 if (msr) {
1070                         vmx_load_host_state(vmx);
1071                         msr->data = data;
1072                         break;
1073                 }
1074                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1075         }
1076
1077         return ret;
1078 }
1079
1080 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1081 {
1082         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1083         switch (reg) {
1084         case VCPU_REGS_RSP:
1085                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1086                 break;
1087         case VCPU_REGS_RIP:
1088                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1089                 break;
1090         case VCPU_EXREG_PDPTR:
1091                 if (enable_ept)
1092                         ept_save_pdptrs(vcpu);
1093                 break;
1094         default:
1095                 break;
1096         }
1097 }
1098
1099 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1100 {
1101         int old_debug = vcpu->guest_debug;
1102         unsigned long flags;
1103
1104         vcpu->guest_debug = dbg->control;
1105         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1106                 vcpu->guest_debug = 0;
1107
1108         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1109                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1110         else
1111                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1112
1113         flags = vmcs_readl(GUEST_RFLAGS);
1114         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1115                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1116         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1117                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1118         vmcs_writel(GUEST_RFLAGS, flags);
1119
1120         update_exception_bitmap(vcpu);
1121
1122         return 0;
1123 }
1124
1125 static __init int cpu_has_kvm_support(void)
1126 {
1127         return cpu_has_vmx();
1128 }
1129
1130 static __init int vmx_disabled_by_bios(void)
1131 {
1132         u64 msr;
1133
1134         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1135         return (msr & (FEATURE_CONTROL_LOCKED |
1136                        FEATURE_CONTROL_VMXON_ENABLED))
1137             == FEATURE_CONTROL_LOCKED;
1138         /* locked but not enabled */
1139 }
1140
1141 static void hardware_enable(void *garbage)
1142 {
1143         int cpu = raw_smp_processor_id();
1144         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1145         u64 old;
1146
1147         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1148         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1149         if ((old & (FEATURE_CONTROL_LOCKED |
1150                     FEATURE_CONTROL_VMXON_ENABLED))
1151             != (FEATURE_CONTROL_LOCKED |
1152                 FEATURE_CONTROL_VMXON_ENABLED))
1153                 /* enable and lock */
1154                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1155                        FEATURE_CONTROL_LOCKED |
1156                        FEATURE_CONTROL_VMXON_ENABLED);
1157         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1158         asm volatile (ASM_VMX_VMXON_RAX
1159                       : : "a"(&phys_addr), "m"(phys_addr)
1160                       : "memory", "cc");
1161 }
1162
1163 static void vmclear_local_vcpus(void)
1164 {
1165         int cpu = raw_smp_processor_id();
1166         struct vcpu_vmx *vmx, *n;
1167
1168         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1169                                  local_vcpus_link)
1170                 __vcpu_clear(vmx);
1171 }
1172
1173
1174 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1175  * tricks.
1176  */
1177 static void kvm_cpu_vmxoff(void)
1178 {
1179         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1180         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1181 }
1182
1183 static void hardware_disable(void *garbage)
1184 {
1185         vmclear_local_vcpus();
1186         kvm_cpu_vmxoff();
1187 }
1188
1189 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1190                                       u32 msr, u32 *result)
1191 {
1192         u32 vmx_msr_low, vmx_msr_high;
1193         u32 ctl = ctl_min | ctl_opt;
1194
1195         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1196
1197         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1198         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1199
1200         /* Ensure minimum (required) set of control bits are supported. */
1201         if (ctl_min & ~ctl)
1202                 return -EIO;
1203
1204         *result = ctl;
1205         return 0;
1206 }
1207
1208 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1209 {
1210         u32 vmx_msr_low, vmx_msr_high;
1211         u32 min, opt, min2, opt2;
1212         u32 _pin_based_exec_control = 0;
1213         u32 _cpu_based_exec_control = 0;
1214         u32 _cpu_based_2nd_exec_control = 0;
1215         u32 _vmexit_control = 0;
1216         u32 _vmentry_control = 0;
1217
1218         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1219         opt = PIN_BASED_VIRTUAL_NMIS;
1220         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1221                                 &_pin_based_exec_control) < 0)
1222                 return -EIO;
1223
1224         min = CPU_BASED_HLT_EXITING |
1225 #ifdef CONFIG_X86_64
1226               CPU_BASED_CR8_LOAD_EXITING |
1227               CPU_BASED_CR8_STORE_EXITING |
1228 #endif
1229               CPU_BASED_CR3_LOAD_EXITING |
1230               CPU_BASED_CR3_STORE_EXITING |
1231               CPU_BASED_USE_IO_BITMAPS |
1232               CPU_BASED_MOV_DR_EXITING |
1233               CPU_BASED_USE_TSC_OFFSETING |
1234               CPU_BASED_INVLPG_EXITING;
1235         opt = CPU_BASED_TPR_SHADOW |
1236               CPU_BASED_USE_MSR_BITMAPS |
1237               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1238         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1239                                 &_cpu_based_exec_control) < 0)
1240                 return -EIO;
1241 #ifdef CONFIG_X86_64
1242         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1243                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1244                                            ~CPU_BASED_CR8_STORE_EXITING;
1245 #endif
1246         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1247                 min2 = 0;
1248                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1249                         SECONDARY_EXEC_WBINVD_EXITING |
1250                         SECONDARY_EXEC_ENABLE_VPID |
1251                         SECONDARY_EXEC_ENABLE_EPT |
1252                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
1253                 if (adjust_vmx_controls(min2, opt2,
1254                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1255                                         &_cpu_based_2nd_exec_control) < 0)
1256                         return -EIO;
1257         }
1258 #ifndef CONFIG_X86_64
1259         if (!(_cpu_based_2nd_exec_control &
1260                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1261                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1262 #endif
1263         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1264                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1265                    enabled */
1266                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1267                                              CPU_BASED_CR3_STORE_EXITING |
1268                                              CPU_BASED_INVLPG_EXITING);
1269                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1270                       vmx_capability.ept, vmx_capability.vpid);
1271         }
1272
1273         min = 0;
1274 #ifdef CONFIG_X86_64
1275         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1276 #endif
1277         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1278         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1279                                 &_vmexit_control) < 0)
1280                 return -EIO;
1281
1282         min = 0;
1283         opt = VM_ENTRY_LOAD_IA32_PAT;
1284         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1285                                 &_vmentry_control) < 0)
1286                 return -EIO;
1287
1288         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1289
1290         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1291         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1292                 return -EIO;
1293
1294 #ifdef CONFIG_X86_64
1295         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1296         if (vmx_msr_high & (1u<<16))
1297                 return -EIO;
1298 #endif
1299
1300         /* Require Write-Back (WB) memory type for VMCS accesses. */
1301         if (((vmx_msr_high >> 18) & 15) != 6)
1302                 return -EIO;
1303
1304         vmcs_conf->size = vmx_msr_high & 0x1fff;
1305         vmcs_conf->order = get_order(vmcs_config.size);
1306         vmcs_conf->revision_id = vmx_msr_low;
1307
1308         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1309         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1310         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1311         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1312         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1313
1314         return 0;
1315 }
1316
1317 static struct vmcs *alloc_vmcs_cpu(int cpu)
1318 {
1319         int node = cpu_to_node(cpu);
1320         struct page *pages;
1321         struct vmcs *vmcs;
1322
1323         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1324         if (!pages)
1325                 return NULL;
1326         vmcs = page_address(pages);
1327         memset(vmcs, 0, vmcs_config.size);
1328         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1329         return vmcs;
1330 }
1331
1332 static struct vmcs *alloc_vmcs(void)
1333 {
1334         return alloc_vmcs_cpu(raw_smp_processor_id());
1335 }
1336
1337 static void free_vmcs(struct vmcs *vmcs)
1338 {
1339         free_pages((unsigned long)vmcs, vmcs_config.order);
1340 }
1341
1342 static void free_kvm_area(void)
1343 {
1344         int cpu;
1345
1346         for_each_online_cpu(cpu)
1347                 free_vmcs(per_cpu(vmxarea, cpu));
1348 }
1349
1350 static __init int alloc_kvm_area(void)
1351 {
1352         int cpu;
1353
1354         for_each_online_cpu(cpu) {
1355                 struct vmcs *vmcs;
1356
1357                 vmcs = alloc_vmcs_cpu(cpu);
1358                 if (!vmcs) {
1359                         free_kvm_area();
1360                         return -ENOMEM;
1361                 }
1362
1363                 per_cpu(vmxarea, cpu) = vmcs;
1364         }
1365         return 0;
1366 }
1367
1368 static __init int hardware_setup(void)
1369 {
1370         if (setup_vmcs_config(&vmcs_config) < 0)
1371                 return -EIO;
1372
1373         if (boot_cpu_has(X86_FEATURE_NX))
1374                 kvm_enable_efer_bits(EFER_NX);
1375
1376         if (!cpu_has_vmx_vpid())
1377                 enable_vpid = 0;
1378
1379         if (!cpu_has_vmx_ept()) {
1380                 enable_ept = 0;
1381                 enable_unrestricted_guest = 0;
1382         }
1383
1384         if (!cpu_has_vmx_unrestricted_guest())
1385                 enable_unrestricted_guest = 0;
1386
1387         if (!cpu_has_vmx_flexpriority())
1388                 flexpriority_enabled = 0;
1389
1390         if (!cpu_has_vmx_tpr_shadow())
1391                 kvm_x86_ops->update_cr8_intercept = NULL;
1392
1393         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1394                 kvm_disable_largepages();
1395
1396         return alloc_kvm_area();
1397 }
1398
1399 static __exit void hardware_unsetup(void)
1400 {
1401         free_kvm_area();
1402 }
1403
1404 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1405 {
1406         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1407
1408         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1409                 vmcs_write16(sf->selector, save->selector);
1410                 vmcs_writel(sf->base, save->base);
1411                 vmcs_write32(sf->limit, save->limit);
1412                 vmcs_write32(sf->ar_bytes, save->ar);
1413         } else {
1414                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1415                         << AR_DPL_SHIFT;
1416                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1417         }
1418 }
1419
1420 static void enter_pmode(struct kvm_vcpu *vcpu)
1421 {
1422         unsigned long flags;
1423         struct vcpu_vmx *vmx = to_vmx(vcpu);
1424
1425         vmx->emulation_required = 1;
1426         vmx->rmode.vm86_active = 0;
1427
1428         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1429         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1430         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1431
1432         flags = vmcs_readl(GUEST_RFLAGS);
1433         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1434         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1435         vmcs_writel(GUEST_RFLAGS, flags);
1436
1437         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1438                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1439
1440         update_exception_bitmap(vcpu);
1441
1442         if (emulate_invalid_guest_state)
1443                 return;
1444
1445         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1446         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1447         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1448         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1449
1450         vmcs_write16(GUEST_SS_SELECTOR, 0);
1451         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1452
1453         vmcs_write16(GUEST_CS_SELECTOR,
1454                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1455         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1456 }
1457
1458 static gva_t rmode_tss_base(struct kvm *kvm)
1459 {
1460         if (!kvm->arch.tss_addr) {
1461                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1462                                  kvm->memslots[0].npages - 3;
1463                 return base_gfn << PAGE_SHIFT;
1464         }
1465         return kvm->arch.tss_addr;
1466 }
1467
1468 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1469 {
1470         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1471
1472         save->selector = vmcs_read16(sf->selector);
1473         save->base = vmcs_readl(sf->base);
1474         save->limit = vmcs_read32(sf->limit);
1475         save->ar = vmcs_read32(sf->ar_bytes);
1476         vmcs_write16(sf->selector, save->base >> 4);
1477         vmcs_write32(sf->base, save->base & 0xfffff);
1478         vmcs_write32(sf->limit, 0xffff);
1479         vmcs_write32(sf->ar_bytes, 0xf3);
1480 }
1481
1482 static void enter_rmode(struct kvm_vcpu *vcpu)
1483 {
1484         unsigned long flags;
1485         struct vcpu_vmx *vmx = to_vmx(vcpu);
1486
1487         if (enable_unrestricted_guest)
1488                 return;
1489
1490         vmx->emulation_required = 1;
1491         vmx->rmode.vm86_active = 1;
1492
1493         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1494         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1495
1496         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1497         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1498
1499         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1500         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1501
1502         flags = vmcs_readl(GUEST_RFLAGS);
1503         vmx->rmode.save_iopl
1504                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1505
1506         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1507
1508         vmcs_writel(GUEST_RFLAGS, flags);
1509         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1510         update_exception_bitmap(vcpu);
1511
1512         if (emulate_invalid_guest_state)
1513                 goto continue_rmode;
1514
1515         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1516         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1517         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1518
1519         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1520         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1521         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1522                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1523         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1524
1525         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1526         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1527         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1528         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1529
1530 continue_rmode:
1531         kvm_mmu_reset_context(vcpu);
1532         init_rmode(vcpu->kvm);
1533 }
1534
1535 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1536 {
1537         struct vcpu_vmx *vmx = to_vmx(vcpu);
1538         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1539
1540         vcpu->arch.shadow_efer = efer;
1541         if (!msr)
1542                 return;
1543         if (efer & EFER_LMA) {
1544                 vmcs_write32(VM_ENTRY_CONTROLS,
1545                              vmcs_read32(VM_ENTRY_CONTROLS) |
1546                              VM_ENTRY_IA32E_MODE);
1547                 msr->data = efer;
1548         } else {
1549                 vmcs_write32(VM_ENTRY_CONTROLS,
1550                              vmcs_read32(VM_ENTRY_CONTROLS) &
1551                              ~VM_ENTRY_IA32E_MODE);
1552
1553                 msr->data = efer & ~EFER_LME;
1554         }
1555         setup_msrs(vmx);
1556 }
1557
1558 #ifdef CONFIG_X86_64
1559
1560 static void enter_lmode(struct kvm_vcpu *vcpu)
1561 {
1562         u32 guest_tr_ar;
1563
1564         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1565         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1566                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1567                        __func__);
1568                 vmcs_write32(GUEST_TR_AR_BYTES,
1569                              (guest_tr_ar & ~AR_TYPE_MASK)
1570                              | AR_TYPE_BUSY_64_TSS);
1571         }
1572         vcpu->arch.shadow_efer |= EFER_LMA;
1573         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1574 }
1575
1576 static void exit_lmode(struct kvm_vcpu *vcpu)
1577 {
1578         vcpu->arch.shadow_efer &= ~EFER_LMA;
1579
1580         vmcs_write32(VM_ENTRY_CONTROLS,
1581                      vmcs_read32(VM_ENTRY_CONTROLS)
1582                      & ~VM_ENTRY_IA32E_MODE);
1583 }
1584
1585 #endif
1586
1587 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1588 {
1589         vpid_sync_vcpu_all(to_vmx(vcpu));
1590         if (enable_ept)
1591                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1592 }
1593
1594 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1595 {
1596         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1597         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1598 }
1599
1600 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1601 {
1602         if (!test_bit(VCPU_EXREG_PDPTR,
1603                       (unsigned long *)&vcpu->arch.regs_dirty))
1604                 return;
1605
1606         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1607                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1608                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1609                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1610                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1611         }
1612 }
1613
1614 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1615 {
1616         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1617                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1618                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1619                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1620                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1621         }
1622
1623         __set_bit(VCPU_EXREG_PDPTR,
1624                   (unsigned long *)&vcpu->arch.regs_avail);
1625         __set_bit(VCPU_EXREG_PDPTR,
1626                   (unsigned long *)&vcpu->arch.regs_dirty);
1627 }
1628
1629 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1630
1631 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1632                                         unsigned long cr0,
1633                                         struct kvm_vcpu *vcpu)
1634 {
1635         if (!(cr0 & X86_CR0_PG)) {
1636                 /* From paging/starting to nonpaging */
1637                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1638                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1639                              (CPU_BASED_CR3_LOAD_EXITING |
1640                               CPU_BASED_CR3_STORE_EXITING));
1641                 vcpu->arch.cr0 = cr0;
1642                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1643         } else if (!is_paging(vcpu)) {
1644                 /* From nonpaging to paging */
1645                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1646                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1647                              ~(CPU_BASED_CR3_LOAD_EXITING |
1648                                CPU_BASED_CR3_STORE_EXITING));
1649                 vcpu->arch.cr0 = cr0;
1650                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1651         }
1652
1653         if (!(cr0 & X86_CR0_WP))
1654                 *hw_cr0 &= ~X86_CR0_WP;
1655 }
1656
1657 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1658                                         struct kvm_vcpu *vcpu)
1659 {
1660         if (!is_paging(vcpu)) {
1661                 *hw_cr4 &= ~X86_CR4_PAE;
1662                 *hw_cr4 |= X86_CR4_PSE;
1663         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1664                 *hw_cr4 &= ~X86_CR4_PAE;
1665 }
1666
1667 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1668 {
1669         struct vcpu_vmx *vmx = to_vmx(vcpu);
1670         unsigned long hw_cr0;
1671
1672         if (enable_unrestricted_guest)
1673                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1674                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1675         else
1676                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1677
1678         vmx_fpu_deactivate(vcpu);
1679
1680         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1681                 enter_pmode(vcpu);
1682
1683         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1684                 enter_rmode(vcpu);
1685
1686 #ifdef CONFIG_X86_64
1687         if (vcpu->arch.shadow_efer & EFER_LME) {
1688                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1689                         enter_lmode(vcpu);
1690                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1691                         exit_lmode(vcpu);
1692         }
1693 #endif
1694
1695         if (enable_ept)
1696                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1697
1698         vmcs_writel(CR0_READ_SHADOW, cr0);
1699         vmcs_writel(GUEST_CR0, hw_cr0);
1700         vcpu->arch.cr0 = cr0;
1701
1702         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1703                 vmx_fpu_activate(vcpu);
1704 }
1705
1706 static u64 construct_eptp(unsigned long root_hpa)
1707 {
1708         u64 eptp;
1709
1710         /* TODO write the value reading from MSR */
1711         eptp = VMX_EPT_DEFAULT_MT |
1712                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1713         eptp |= (root_hpa & PAGE_MASK);
1714
1715         return eptp;
1716 }
1717
1718 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1719 {
1720         unsigned long guest_cr3;
1721         u64 eptp;
1722
1723         guest_cr3 = cr3;
1724         if (enable_ept) {
1725                 eptp = construct_eptp(cr3);
1726                 vmcs_write64(EPT_POINTER, eptp);
1727                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1728                         vcpu->kvm->arch.ept_identity_map_addr;
1729         }
1730
1731         vmx_flush_tlb(vcpu);
1732         vmcs_writel(GUEST_CR3, guest_cr3);
1733         if (vcpu->arch.cr0 & X86_CR0_PE)
1734                 vmx_fpu_deactivate(vcpu);
1735 }
1736
1737 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1738 {
1739         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1740                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1741
1742         vcpu->arch.cr4 = cr4;
1743         if (enable_ept)
1744                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1745
1746         vmcs_writel(CR4_READ_SHADOW, cr4);
1747         vmcs_writel(GUEST_CR4, hw_cr4);
1748 }
1749
1750 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1751 {
1752         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1753
1754         return vmcs_readl(sf->base);
1755 }
1756
1757 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1758                             struct kvm_segment *var, int seg)
1759 {
1760         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1761         u32 ar;
1762
1763         var->base = vmcs_readl(sf->base);
1764         var->limit = vmcs_read32(sf->limit);
1765         var->selector = vmcs_read16(sf->selector);
1766         ar = vmcs_read32(sf->ar_bytes);
1767         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1768                 ar = 0;
1769         var->type = ar & 15;
1770         var->s = (ar >> 4) & 1;
1771         var->dpl = (ar >> 5) & 3;
1772         var->present = (ar >> 7) & 1;
1773         var->avl = (ar >> 12) & 1;
1774         var->l = (ar >> 13) & 1;
1775         var->db = (ar >> 14) & 1;
1776         var->g = (ar >> 15) & 1;
1777         var->unusable = (ar >> 16) & 1;
1778 }
1779
1780 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1781 {
1782         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1783                 return 0;
1784
1785         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1786                 return 3;
1787
1788         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1789 }
1790
1791 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1792 {
1793         u32 ar;
1794
1795         if (var->unusable)
1796                 ar = 1 << 16;
1797         else {
1798                 ar = var->type & 15;
1799                 ar |= (var->s & 1) << 4;
1800                 ar |= (var->dpl & 3) << 5;
1801                 ar |= (var->present & 1) << 7;
1802                 ar |= (var->avl & 1) << 12;
1803                 ar |= (var->l & 1) << 13;
1804                 ar |= (var->db & 1) << 14;
1805                 ar |= (var->g & 1) << 15;
1806         }
1807         if (ar == 0) /* a 0 value means unusable */
1808                 ar = AR_UNUSABLE_MASK;
1809
1810         return ar;
1811 }
1812
1813 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1814                             struct kvm_segment *var, int seg)
1815 {
1816         struct vcpu_vmx *vmx = to_vmx(vcpu);
1817         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1818         u32 ar;
1819
1820         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1821                 vmx->rmode.tr.selector = var->selector;
1822                 vmx->rmode.tr.base = var->base;
1823                 vmx->rmode.tr.limit = var->limit;
1824                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1825                 return;
1826         }
1827         vmcs_writel(sf->base, var->base);
1828         vmcs_write32(sf->limit, var->limit);
1829         vmcs_write16(sf->selector, var->selector);
1830         if (vmx->rmode.vm86_active && var->s) {
1831                 /*
1832                  * Hack real-mode segments into vm86 compatibility.
1833                  */
1834                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1835                         vmcs_writel(sf->base, 0xf0000);
1836                 ar = 0xf3;
1837         } else
1838                 ar = vmx_segment_access_rights(var);
1839
1840         /*
1841          *   Fix the "Accessed" bit in AR field of segment registers for older
1842          * qemu binaries.
1843          *   IA32 arch specifies that at the time of processor reset the
1844          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1845          * is setting it to 0 in the usedland code. This causes invalid guest
1846          * state vmexit when "unrestricted guest" mode is turned on.
1847          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1848          * tree. Newer qemu binaries with that qemu fix would not need this
1849          * kvm hack.
1850          */
1851         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1852                 ar |= 0x1; /* Accessed */
1853
1854         vmcs_write32(sf->ar_bytes, ar);
1855 }
1856
1857 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1858 {
1859         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1860
1861         *db = (ar >> 14) & 1;
1862         *l = (ar >> 13) & 1;
1863 }
1864
1865 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1866 {
1867         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1868         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1869 }
1870
1871 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1872 {
1873         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1874         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1875 }
1876
1877 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1878 {
1879         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1880         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1881 }
1882
1883 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1884 {
1885         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1886         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1887 }
1888
1889 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1890 {
1891         struct kvm_segment var;
1892         u32 ar;
1893
1894         vmx_get_segment(vcpu, &var, seg);
1895         ar = vmx_segment_access_rights(&var);
1896
1897         if (var.base != (var.selector << 4))
1898                 return false;
1899         if (var.limit != 0xffff)
1900                 return false;
1901         if (ar != 0xf3)
1902                 return false;
1903
1904         return true;
1905 }
1906
1907 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1908 {
1909         struct kvm_segment cs;
1910         unsigned int cs_rpl;
1911
1912         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1913         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1914
1915         if (cs.unusable)
1916                 return false;
1917         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1918                 return false;
1919         if (!cs.s)
1920                 return false;
1921         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1922                 if (cs.dpl > cs_rpl)
1923                         return false;
1924         } else {
1925                 if (cs.dpl != cs_rpl)
1926                         return false;
1927         }
1928         if (!cs.present)
1929                 return false;
1930
1931         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1932         return true;
1933 }
1934
1935 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1936 {
1937         struct kvm_segment ss;
1938         unsigned int ss_rpl;
1939
1940         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1941         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1942
1943         if (ss.unusable)
1944                 return true;
1945         if (ss.type != 3 && ss.type != 7)
1946                 return false;
1947         if (!ss.s)
1948                 return false;
1949         if (ss.dpl != ss_rpl) /* DPL != RPL */
1950                 return false;
1951         if (!ss.present)
1952                 return false;
1953
1954         return true;
1955 }
1956
1957 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1958 {
1959         struct kvm_segment var;
1960         unsigned int rpl;
1961
1962         vmx_get_segment(vcpu, &var, seg);
1963         rpl = var.selector & SELECTOR_RPL_MASK;
1964
1965         if (var.unusable)
1966                 return true;
1967         if (!var.s)
1968                 return false;
1969         if (!var.present)
1970                 return false;
1971         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1972                 if (var.dpl < rpl) /* DPL < RPL */
1973                         return false;
1974         }
1975
1976         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1977          * rights flags
1978          */
1979         return true;
1980 }
1981
1982 static bool tr_valid(struct kvm_vcpu *vcpu)
1983 {
1984         struct kvm_segment tr;
1985
1986         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1987
1988         if (tr.unusable)
1989                 return false;
1990         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1991                 return false;
1992         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1993                 return false;
1994         if (!tr.present)
1995                 return false;
1996
1997         return true;
1998 }
1999
2000 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2001 {
2002         struct kvm_segment ldtr;
2003
2004         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2005
2006         if (ldtr.unusable)
2007                 return true;
2008         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2009                 return false;
2010         if (ldtr.type != 2)
2011                 return false;
2012         if (!ldtr.present)
2013                 return false;
2014
2015         return true;
2016 }
2017
2018 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2019 {
2020         struct kvm_segment cs, ss;
2021
2022         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2023         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2024
2025         return ((cs.selector & SELECTOR_RPL_MASK) ==
2026                  (ss.selector & SELECTOR_RPL_MASK));
2027 }
2028
2029 /*
2030  * Check if guest state is valid. Returns true if valid, false if
2031  * not.
2032  * We assume that registers are always usable
2033  */
2034 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2035 {
2036         /* real mode guest state checks */
2037         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2038                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2039                         return false;
2040                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2041                         return false;
2042                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2043                         return false;
2044                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2045                         return false;
2046                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2047                         return false;
2048                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2049                         return false;
2050         } else {
2051         /* protected mode guest state checks */
2052                 if (!cs_ss_rpl_check(vcpu))
2053                         return false;
2054                 if (!code_segment_valid(vcpu))
2055                         return false;
2056                 if (!stack_segment_valid(vcpu))
2057                         return false;
2058                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2059                         return false;
2060                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2061                         return false;
2062                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2063                         return false;
2064                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2065                         return false;
2066                 if (!tr_valid(vcpu))
2067                         return false;
2068                 if (!ldtr_valid(vcpu))
2069                         return false;
2070         }
2071         /* TODO:
2072          * - Add checks on RIP
2073          * - Add checks on RFLAGS
2074          */
2075
2076         return true;
2077 }
2078
2079 static int init_rmode_tss(struct kvm *kvm)
2080 {
2081         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2082         u16 data = 0;
2083         int ret = 0;
2084         int r;
2085
2086         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2087         if (r < 0)
2088                 goto out;
2089         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2090         r = kvm_write_guest_page(kvm, fn++, &data,
2091                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2092         if (r < 0)
2093                 goto out;
2094         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2095         if (r < 0)
2096                 goto out;
2097         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2098         if (r < 0)
2099                 goto out;
2100         data = ~0;
2101         r = kvm_write_guest_page(kvm, fn, &data,
2102                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2103                                  sizeof(u8));
2104         if (r < 0)
2105                 goto out;
2106
2107         ret = 1;
2108 out:
2109         return ret;
2110 }
2111
2112 static int init_rmode_identity_map(struct kvm *kvm)
2113 {
2114         int i, r, ret;
2115         pfn_t identity_map_pfn;
2116         u32 tmp;
2117
2118         if (!enable_ept)
2119                 return 1;
2120         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2121                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2122                         "haven't been allocated!\n");
2123                 return 0;
2124         }
2125         if (likely(kvm->arch.ept_identity_pagetable_done))
2126                 return 1;
2127         ret = 0;
2128         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2129         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2130         if (r < 0)
2131                 goto out;
2132         /* Set up identity-mapping pagetable for EPT in real mode */
2133         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2134                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2135                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2136                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2137                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2138                 if (r < 0)
2139                         goto out;
2140         }
2141         kvm->arch.ept_identity_pagetable_done = true;
2142         ret = 1;
2143 out:
2144         return ret;
2145 }
2146
2147 static void seg_setup(int seg)
2148 {
2149         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2150         unsigned int ar;
2151
2152         vmcs_write16(sf->selector, 0);
2153         vmcs_writel(sf->base, 0);
2154         vmcs_write32(sf->limit, 0xffff);
2155         if (enable_unrestricted_guest) {
2156                 ar = 0x93;
2157                 if (seg == VCPU_SREG_CS)
2158                         ar |= 0x08; /* code segment */
2159         } else
2160                 ar = 0xf3;
2161
2162         vmcs_write32(sf->ar_bytes, ar);
2163 }
2164
2165 static int alloc_apic_access_page(struct kvm *kvm)
2166 {
2167         struct kvm_userspace_memory_region kvm_userspace_mem;
2168         int r = 0;
2169
2170         down_write(&kvm->slots_lock);
2171         if (kvm->arch.apic_access_page)
2172                 goto out;
2173         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2174         kvm_userspace_mem.flags = 0;
2175         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2176         kvm_userspace_mem.memory_size = PAGE_SIZE;
2177         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2178         if (r)
2179                 goto out;
2180
2181         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2182 out:
2183         up_write(&kvm->slots_lock);
2184         return r;
2185 }
2186
2187 static int alloc_identity_pagetable(struct kvm *kvm)
2188 {
2189         struct kvm_userspace_memory_region kvm_userspace_mem;
2190         int r = 0;
2191
2192         down_write(&kvm->slots_lock);
2193         if (kvm->arch.ept_identity_pagetable)
2194                 goto out;
2195         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2196         kvm_userspace_mem.flags = 0;
2197         kvm_userspace_mem.guest_phys_addr =
2198                 kvm->arch.ept_identity_map_addr;
2199         kvm_userspace_mem.memory_size = PAGE_SIZE;
2200         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2201         if (r)
2202                 goto out;
2203
2204         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2205                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2206 out:
2207         up_write(&kvm->slots_lock);
2208         return r;
2209 }
2210
2211 static void allocate_vpid(struct vcpu_vmx *vmx)
2212 {
2213         int vpid;
2214
2215         vmx->vpid = 0;
2216         if (!enable_vpid)
2217                 return;
2218         spin_lock(&vmx_vpid_lock);
2219         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2220         if (vpid < VMX_NR_VPIDS) {
2221                 vmx->vpid = vpid;
2222                 __set_bit(vpid, vmx_vpid_bitmap);
2223         }
2224         spin_unlock(&vmx_vpid_lock);
2225 }
2226
2227 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2228 {
2229         int f = sizeof(unsigned long);
2230
2231         if (!cpu_has_vmx_msr_bitmap())
2232                 return;
2233
2234         /*
2235          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2236          * have the write-low and read-high bitmap offsets the wrong way round.
2237          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2238          */
2239         if (msr <= 0x1fff) {
2240                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2241                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2242         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2243                 msr &= 0x1fff;
2244                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2245                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2246         }
2247 }
2248
2249 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2250 {
2251         if (!longmode_only)
2252                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2253         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2254 }
2255
2256 /*
2257  * Sets up the vmcs for emulated real mode.
2258  */
2259 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2260 {
2261         u32 host_sysenter_cs, msr_low, msr_high;
2262         u32 junk;
2263         u64 host_pat, tsc_this, tsc_base;
2264         unsigned long a;
2265         struct descriptor_table dt;
2266         int i;
2267         unsigned long kvm_vmx_return;
2268         u32 exec_control;
2269
2270         /* I/O */
2271         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2272         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2273
2274         if (cpu_has_vmx_msr_bitmap())
2275                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2276
2277         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2278
2279         /* Control */
2280         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2281                 vmcs_config.pin_based_exec_ctrl);
2282
2283         exec_control = vmcs_config.cpu_based_exec_ctrl;
2284         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2285                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2286 #ifdef CONFIG_X86_64
2287                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2288                                 CPU_BASED_CR8_LOAD_EXITING;
2289 #endif
2290         }
2291         if (!enable_ept)
2292                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2293                                 CPU_BASED_CR3_LOAD_EXITING  |
2294                                 CPU_BASED_INVLPG_EXITING;
2295         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2296
2297         if (cpu_has_secondary_exec_ctrls()) {
2298                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2299                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2300                         exec_control &=
2301                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2302                 if (vmx->vpid == 0)
2303                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2304                 if (!enable_ept)
2305                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2306                 if (!enable_unrestricted_guest)
2307                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2308                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2309         }
2310
2311         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2312         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2313         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2314
2315         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2316         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2317         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2318
2319         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2320         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2321         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2322         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2323         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2324         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2325 #ifdef CONFIG_X86_64
2326         rdmsrl(MSR_FS_BASE, a);
2327         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2328         rdmsrl(MSR_GS_BASE, a);
2329         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2330 #else
2331         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2332         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2333 #endif
2334
2335         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2336
2337         kvm_get_idt(&dt);
2338         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2339
2340         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2341         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2342         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2343         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2344         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2345
2346         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2347         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2348         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2349         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2350         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2351         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2352
2353         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2354                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2355                 host_pat = msr_low | ((u64) msr_high << 32);
2356                 vmcs_write64(HOST_IA32_PAT, host_pat);
2357         }
2358         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2359                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2360                 host_pat = msr_low | ((u64) msr_high << 32);
2361                 /* Write the default value follow host pat */
2362                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2363                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2364                 vmx->vcpu.arch.pat = host_pat;
2365         }
2366
2367         for (i = 0; i < NR_VMX_MSR; ++i) {
2368                 u32 index = vmx_msr_index[i];
2369                 u32 data_low, data_high;
2370                 u64 data;
2371                 int j = vmx->nmsrs;
2372
2373                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2374                         continue;
2375                 if (wrmsr_safe(index, data_low, data_high) < 0)
2376                         continue;
2377                 data = data_low | ((u64)data_high << 32);
2378                 vmx->host_msrs[j].index = index;
2379                 vmx->host_msrs[j].reserved = 0;
2380                 vmx->host_msrs[j].data = data;
2381                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2382                 ++vmx->nmsrs;
2383         }
2384
2385         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2386
2387         /* 22.2.1, 20.8.1 */
2388         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2389
2390         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2391         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2392
2393         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2394         rdtscll(tsc_this);
2395         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2396                 tsc_base = tsc_this;
2397
2398         guest_write_tsc(0, tsc_base);
2399
2400         return 0;
2401 }
2402
2403 static int init_rmode(struct kvm *kvm)
2404 {
2405         if (!init_rmode_tss(kvm))
2406                 return 0;
2407         if (!init_rmode_identity_map(kvm))
2408                 return 0;
2409         return 1;
2410 }
2411
2412 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2413 {
2414         struct vcpu_vmx *vmx = to_vmx(vcpu);
2415         u64 msr;
2416         int ret;
2417
2418         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2419         down_read(&vcpu->kvm->slots_lock);
2420         if (!init_rmode(vmx->vcpu.kvm)) {
2421                 ret = -ENOMEM;
2422                 goto out;
2423         }
2424
2425         vmx->rmode.vm86_active = 0;
2426
2427         vmx->soft_vnmi_blocked = 0;
2428
2429         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2430         kvm_set_cr8(&vmx->vcpu, 0);
2431         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2432         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2433                 msr |= MSR_IA32_APICBASE_BSP;
2434         kvm_set_apic_base(&vmx->vcpu, msr);
2435
2436         fx_init(&vmx->vcpu);
2437
2438         seg_setup(VCPU_SREG_CS);
2439         /*
2440          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2441          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2442          */
2443         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2444                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2445                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2446         } else {
2447                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2448                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2449         }
2450
2451         seg_setup(VCPU_SREG_DS);
2452         seg_setup(VCPU_SREG_ES);
2453         seg_setup(VCPU_SREG_FS);
2454         seg_setup(VCPU_SREG_GS);
2455         seg_setup(VCPU_SREG_SS);
2456
2457         vmcs_write16(GUEST_TR_SELECTOR, 0);
2458         vmcs_writel(GUEST_TR_BASE, 0);
2459         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2460         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2461
2462         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2463         vmcs_writel(GUEST_LDTR_BASE, 0);
2464         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2465         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2466
2467         vmcs_write32(GUEST_SYSENTER_CS, 0);
2468         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2469         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2470
2471         vmcs_writel(GUEST_RFLAGS, 0x02);
2472         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2473                 kvm_rip_write(vcpu, 0xfff0);
2474         else
2475                 kvm_rip_write(vcpu, 0);
2476         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2477
2478         vmcs_writel(GUEST_DR7, 0x400);
2479
2480         vmcs_writel(GUEST_GDTR_BASE, 0);
2481         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2482
2483         vmcs_writel(GUEST_IDTR_BASE, 0);
2484         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2485
2486         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2487         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2488         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2489
2490         /* Special registers */
2491         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2492
2493         setup_msrs(vmx);
2494
2495         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2496
2497         if (cpu_has_vmx_tpr_shadow()) {
2498                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2499                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2500                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2501                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2502                 vmcs_write32(TPR_THRESHOLD, 0);
2503         }
2504
2505         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2506                 vmcs_write64(APIC_ACCESS_ADDR,
2507                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2508
2509         if (vmx->vpid != 0)
2510                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2511
2512         vmx->vcpu.arch.cr0 = 0x60000010;
2513         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2514         vmx_set_cr4(&vmx->vcpu, 0);
2515         vmx_set_efer(&vmx->vcpu, 0);
2516         vmx_fpu_activate(&vmx->vcpu);
2517         update_exception_bitmap(&vmx->vcpu);
2518
2519         vpid_sync_vcpu_all(vmx);
2520
2521         ret = 0;
2522
2523         /* HACK: Don't enable emulation on guest boot/reset */
2524         vmx->emulation_required = 0;
2525
2526 out:
2527         up_read(&vcpu->kvm->slots_lock);
2528         return ret;
2529 }
2530
2531 static void enable_irq_window(struct kvm_vcpu *vcpu)
2532 {
2533         u32 cpu_based_vm_exec_control;
2534
2535         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2536         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2537         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2538 }
2539
2540 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2541 {
2542         u32 cpu_based_vm_exec_control;
2543
2544         if (!cpu_has_virtual_nmis()) {
2545                 enable_irq_window(vcpu);
2546                 return;
2547         }
2548
2549         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2550         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2551         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2552 }
2553
2554 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2555 {
2556         struct vcpu_vmx *vmx = to_vmx(vcpu);
2557         uint32_t intr;
2558         int irq = vcpu->arch.interrupt.nr;
2559
2560         trace_kvm_inj_virq(irq);
2561
2562         ++vcpu->stat.irq_injections;
2563         if (vmx->rmode.vm86_active) {
2564                 vmx->rmode.irq.pending = true;
2565                 vmx->rmode.irq.vector = irq;
2566                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2567                 if (vcpu->arch.interrupt.soft)
2568                         vmx->rmode.irq.rip +=
2569                                 vmx->vcpu.arch.event_exit_inst_len;
2570                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2571                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2572                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2573                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2574                 return;
2575         }
2576         intr = irq | INTR_INFO_VALID_MASK;
2577         if (vcpu->arch.interrupt.soft) {
2578                 intr |= INTR_TYPE_SOFT_INTR;
2579                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2580                              vmx->vcpu.arch.event_exit_inst_len);
2581         } else
2582                 intr |= INTR_TYPE_EXT_INTR;
2583         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2584 }
2585
2586 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2587 {
2588         struct vcpu_vmx *vmx = to_vmx(vcpu);
2589
2590         if (!cpu_has_virtual_nmis()) {
2591                 /*
2592                  * Tracking the NMI-blocked state in software is built upon
2593                  * finding the next open IRQ window. This, in turn, depends on
2594                  * well-behaving guests: They have to keep IRQs disabled at
2595                  * least as long as the NMI handler runs. Otherwise we may
2596                  * cause NMI nesting, maybe breaking the guest. But as this is
2597                  * highly unlikely, we can live with the residual risk.
2598                  */
2599                 vmx->soft_vnmi_blocked = 1;
2600                 vmx->vnmi_blocked_time = 0;
2601         }
2602
2603         ++vcpu->stat.nmi_injections;
2604         if (vmx->rmode.vm86_active) {
2605                 vmx->rmode.irq.pending = true;
2606                 vmx->rmode.irq.vector = NMI_VECTOR;
2607                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2608                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2609                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2610                              INTR_INFO_VALID_MASK);
2611                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2612                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2613                 return;
2614         }
2615         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2616                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2617 }
2618
2619 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2620 {
2621         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2622                 return 0;
2623
2624         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2625                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2626                                 GUEST_INTR_STATE_NMI));
2627 }
2628
2629 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2630 {
2631         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2632                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2633                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2634 }
2635
2636 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2637 {
2638         int ret;
2639         struct kvm_userspace_memory_region tss_mem = {
2640                 .slot = TSS_PRIVATE_MEMSLOT,
2641                 .guest_phys_addr = addr,
2642                 .memory_size = PAGE_SIZE * 3,
2643                 .flags = 0,
2644         };
2645
2646         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2647         if (ret)
2648                 return ret;
2649         kvm->arch.tss_addr = addr;
2650         return 0;
2651 }
2652
2653 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2654                                   int vec, u32 err_code)
2655 {
2656         /*
2657          * Instruction with address size override prefix opcode 0x67
2658          * Cause the #SS fault with 0 error code in VM86 mode.
2659          */
2660         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2661                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2662                         return 1;
2663         /*
2664          * Forward all other exceptions that are valid in real mode.
2665          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2666          *        the required debugging infrastructure rework.
2667          */
2668         switch (vec) {
2669         case DB_VECTOR:
2670                 if (vcpu->guest_debug &
2671                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2672                         return 0;
2673                 kvm_queue_exception(vcpu, vec);
2674                 return 1;
2675         case BP_VECTOR:
2676                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2677                         return 0;
2678                 /* fall through */
2679         case DE_VECTOR:
2680         case OF_VECTOR:
2681         case BR_VECTOR:
2682         case UD_VECTOR:
2683         case DF_VECTOR:
2684         case SS_VECTOR:
2685         case GP_VECTOR:
2686         case MF_VECTOR:
2687                 kvm_queue_exception(vcpu, vec);
2688                 return 1;
2689         }
2690         return 0;
2691 }
2692
2693 /*
2694  * Trigger machine check on the host. We assume all the MSRs are already set up
2695  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2696  * We pass a fake environment to the machine check handler because we want
2697  * the guest to be always treated like user space, no matter what context
2698  * it used internally.
2699  */
2700 static void kvm_machine_check(void)
2701 {
2702 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2703         struct pt_regs regs = {
2704                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2705                 .flags = X86_EFLAGS_IF,
2706         };
2707
2708         do_machine_check(&regs, 0);
2709 #endif
2710 }
2711
2712 static int handle_machine_check(struct kvm_vcpu *vcpu)
2713 {
2714         /* already handled by vcpu_run */
2715         return 1;
2716 }
2717
2718 static int handle_exception(struct kvm_vcpu *vcpu)
2719 {
2720         struct vcpu_vmx *vmx = to_vmx(vcpu);
2721         struct kvm_run *kvm_run = vcpu->run;
2722         u32 intr_info, ex_no, error_code;
2723         unsigned long cr2, rip, dr6;
2724         u32 vect_info;
2725         enum emulation_result er;
2726
2727         vect_info = vmx->idt_vectoring_info;
2728         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2729
2730         if (is_machine_check(intr_info))
2731                 return handle_machine_check(vcpu);
2732
2733         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2734                                                 !is_page_fault(intr_info))
2735                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2736                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2737
2738         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2739                 return 1;  /* already handled by vmx_vcpu_run() */
2740
2741         if (is_no_device(intr_info)) {
2742                 vmx_fpu_activate(vcpu);
2743                 return 1;
2744         }
2745
2746         if (is_invalid_opcode(intr_info)) {
2747                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2748                 if (er != EMULATE_DONE)
2749                         kvm_queue_exception(vcpu, UD_VECTOR);
2750                 return 1;
2751         }
2752
2753         error_code = 0;
2754         rip = kvm_rip_read(vcpu);
2755         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2756                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2757         if (is_page_fault(intr_info)) {
2758                 /* EPT won't cause page fault directly */
2759                 if (enable_ept)
2760                         BUG();
2761                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2762                 trace_kvm_page_fault(cr2, error_code);
2763
2764                 if (kvm_event_needs_reinjection(vcpu))
2765                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2766                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2767         }
2768
2769         if (vmx->rmode.vm86_active &&
2770             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2771                                                                 error_code)) {
2772                 if (vcpu->arch.halt_request) {
2773                         vcpu->arch.halt_request = 0;
2774                         return kvm_emulate_halt(vcpu);
2775                 }
2776                 return 1;
2777         }
2778
2779         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2780         switch (ex_no) {
2781         case DB_VECTOR:
2782                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2783                 if (!(vcpu->guest_debug &
2784                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2785                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2786                         kvm_queue_exception(vcpu, DB_VECTOR);
2787                         return 1;
2788                 }
2789                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2790                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2791                 /* fall through */
2792         case BP_VECTOR:
2793                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2794                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2795                 kvm_run->debug.arch.exception = ex_no;
2796                 break;
2797         default:
2798                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2799                 kvm_run->ex.exception = ex_no;
2800                 kvm_run->ex.error_code = error_code;
2801                 break;
2802         }
2803         return 0;
2804 }
2805
2806 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2807 {
2808         ++vcpu->stat.irq_exits;
2809         return 1;
2810 }
2811
2812 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2813 {
2814         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2815         return 0;
2816 }
2817
2818 static int handle_io(struct kvm_vcpu *vcpu)
2819 {
2820         unsigned long exit_qualification;
2821         int size, in, string;
2822         unsigned port;
2823
2824         ++vcpu->stat.io_exits;
2825         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2826         string = (exit_qualification & 16) != 0;
2827
2828         if (string) {
2829                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2830                         return 0;
2831                 return 1;
2832         }
2833
2834         size = (exit_qualification & 7) + 1;
2835         in = (exit_qualification & 8) != 0;
2836         port = exit_qualification >> 16;
2837
2838         skip_emulated_instruction(vcpu);
2839         return kvm_emulate_pio(vcpu, in, size, port);
2840 }
2841
2842 static void
2843 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2844 {
2845         /*
2846          * Patch in the VMCALL instruction:
2847          */
2848         hypercall[0] = 0x0f;
2849         hypercall[1] = 0x01;
2850         hypercall[2] = 0xc1;
2851 }
2852
2853 static int handle_cr(struct kvm_vcpu *vcpu)
2854 {
2855         unsigned long exit_qualification, val;
2856         int cr;
2857         int reg;
2858
2859         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2860         cr = exit_qualification & 15;
2861         reg = (exit_qualification >> 8) & 15;
2862         switch ((exit_qualification >> 4) & 3) {
2863         case 0: /* mov to cr */
2864                 val = kvm_register_read(vcpu, reg);
2865                 trace_kvm_cr_write(cr, val);
2866                 switch (cr) {
2867                 case 0:
2868                         kvm_set_cr0(vcpu, val);
2869                         skip_emulated_instruction(vcpu);
2870                         return 1;
2871                 case 3:
2872                         kvm_set_cr3(vcpu, val);
2873                         skip_emulated_instruction(vcpu);
2874                         return 1;
2875                 case 4:
2876                         kvm_set_cr4(vcpu, val);
2877                         skip_emulated_instruction(vcpu);
2878                         return 1;
2879                 case 8: {
2880                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2881                                 u8 cr8 = kvm_register_read(vcpu, reg);
2882                                 kvm_set_cr8(vcpu, cr8);
2883                                 skip_emulated_instruction(vcpu);
2884                                 if (irqchip_in_kernel(vcpu->kvm))
2885                                         return 1;
2886                                 if (cr8_prev <= cr8)
2887                                         return 1;
2888                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2889                                 return 0;
2890                         }
2891                 };
2892                 break;
2893         case 2: /* clts */
2894                 vmx_fpu_deactivate(vcpu);
2895                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2896                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2897                 vmx_fpu_activate(vcpu);
2898                 skip_emulated_instruction(vcpu);
2899                 return 1;
2900         case 1: /*mov from cr*/
2901                 switch (cr) {
2902                 case 3:
2903                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2904                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2905                         skip_emulated_instruction(vcpu);
2906                         return 1;
2907                 case 8:
2908                         val = kvm_get_cr8(vcpu);
2909                         kvm_register_write(vcpu, reg, val);
2910                         trace_kvm_cr_read(cr, val);
2911                         skip_emulated_instruction(vcpu);
2912                         return 1;
2913                 }
2914                 break;
2915         case 3: /* lmsw */
2916                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2917
2918                 skip_emulated_instruction(vcpu);
2919                 return 1;
2920         default:
2921                 break;
2922         }
2923         vcpu->run->exit_reason = 0;
2924         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2925                (int)(exit_qualification >> 4) & 3, cr);
2926         return 0;
2927 }
2928
2929 static int handle_dr(struct kvm_vcpu *vcpu)
2930 {
2931         unsigned long exit_qualification;
2932         unsigned long val;
2933         int dr, reg;
2934
2935         if (!kvm_require_cpl(vcpu, 0))
2936                 return 1;
2937         dr = vmcs_readl(GUEST_DR7);
2938         if (dr & DR7_GD) {
2939                 /*
2940                  * As the vm-exit takes precedence over the debug trap, we
2941                  * need to emulate the latter, either for the host or the
2942                  * guest debugging itself.
2943                  */
2944                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2945                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2946                         vcpu->run->debug.arch.dr7 = dr;
2947                         vcpu->run->debug.arch.pc =
2948                                 vmcs_readl(GUEST_CS_BASE) +
2949                                 vmcs_readl(GUEST_RIP);
2950                         vcpu->run->debug.arch.exception = DB_VECTOR;
2951                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
2952                         return 0;
2953                 } else {
2954                         vcpu->arch.dr7 &= ~DR7_GD;
2955                         vcpu->arch.dr6 |= DR6_BD;
2956                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2957                         kvm_queue_exception(vcpu, DB_VECTOR);
2958                         return 1;
2959                 }
2960         }
2961
2962         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2963         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2964         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2965         if (exit_qualification & TYPE_MOV_FROM_DR) {
2966                 switch (dr) {
2967                 case 0 ... 3:
2968                         val = vcpu->arch.db[dr];
2969                         break;
2970                 case 6:
2971                         val = vcpu->arch.dr6;
2972                         break;
2973                 case 7:
2974                         val = vcpu->arch.dr7;
2975                         break;
2976                 default:
2977                         val = 0;
2978                 }
2979                 kvm_register_write(vcpu, reg, val);
2980         } else {
2981                 val = vcpu->arch.regs[reg];
2982                 switch (dr) {
2983                 case 0 ... 3:
2984                         vcpu->arch.db[dr] = val;
2985                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2986                                 vcpu->arch.eff_db[dr] = val;
2987                         break;
2988                 case 4 ... 5:
2989                         if (vcpu->arch.cr4 & X86_CR4_DE)
2990                                 kvm_queue_exception(vcpu, UD_VECTOR);
2991                         break;
2992                 case 6:
2993                         if (val & 0xffffffff00000000ULL) {
2994                                 kvm_queue_exception(vcpu, GP_VECTOR);
2995                                 break;
2996                         }
2997                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2998                         break;
2999                 case 7:
3000                         if (val & 0xffffffff00000000ULL) {
3001                                 kvm_queue_exception(vcpu, GP_VECTOR);
3002                                 break;
3003                         }
3004                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3005                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3006                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3007                                 vcpu->arch.switch_db_regs =
3008                                         (val & DR7_BP_EN_MASK);
3009                         }
3010                         break;
3011                 }
3012         }
3013         skip_emulated_instruction(vcpu);
3014         return 1;
3015 }
3016
3017 static int handle_cpuid(struct kvm_vcpu *vcpu)
3018 {
3019         kvm_emulate_cpuid(vcpu);
3020         return 1;
3021 }
3022
3023 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3024 {
3025         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3026         u64 data;
3027
3028         if (vmx_get_msr(vcpu, ecx, &data)) {
3029                 kvm_inject_gp(vcpu, 0);
3030                 return 1;
3031         }
3032
3033         trace_kvm_msr_read(ecx, data);
3034
3035         /* FIXME: handling of bits 32:63 of rax, rdx */
3036         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3037         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3038         skip_emulated_instruction(vcpu);
3039         return 1;
3040 }
3041
3042 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3043 {
3044         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3045         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3046                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3047
3048         trace_kvm_msr_write(ecx, data);
3049
3050         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3051                 kvm_inject_gp(vcpu, 0);
3052                 return 1;
3053         }
3054
3055         skip_emulated_instruction(vcpu);
3056         return 1;
3057 }
3058
3059 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3060 {
3061         return 1;
3062 }
3063
3064 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3065 {
3066         u32 cpu_based_vm_exec_control;
3067
3068         /* clear pending irq */
3069         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3070         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3071         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3072
3073         ++vcpu->stat.irq_window_exits;
3074
3075         /*
3076          * If the user space waits to inject interrupts, exit as soon as
3077          * possible
3078          */
3079         if (!irqchip_in_kernel(vcpu->kvm) &&
3080             vcpu->run->request_interrupt_window &&
3081             !kvm_cpu_has_interrupt(vcpu)) {
3082                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3083                 return 0;
3084         }
3085         return 1;
3086 }
3087
3088 static int handle_halt(struct kvm_vcpu *vcpu)
3089 {
3090         skip_emulated_instruction(vcpu);
3091         return kvm_emulate_halt(vcpu);
3092 }
3093
3094 static int handle_vmcall(struct kvm_vcpu *vcpu)
3095 {
3096         skip_emulated_instruction(vcpu);
3097         kvm_emulate_hypercall(vcpu);
3098         return 1;
3099 }
3100
3101 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3102 {
3103         kvm_queue_exception(vcpu, UD_VECTOR);
3104         return 1;
3105 }
3106
3107 static int handle_invlpg(struct kvm_vcpu *vcpu)
3108 {
3109         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3110
3111         kvm_mmu_invlpg(vcpu, exit_qualification);
3112         skip_emulated_instruction(vcpu);
3113         return 1;
3114 }
3115
3116 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3117 {
3118         skip_emulated_instruction(vcpu);
3119         /* TODO: Add support for VT-d/pass-through device */
3120         return 1;
3121 }
3122
3123 static int handle_apic_access(struct kvm_vcpu *vcpu)
3124 {
3125         unsigned long exit_qualification;
3126         enum emulation_result er;
3127         unsigned long offset;
3128
3129         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3130         offset = exit_qualification & 0xffful;
3131
3132         er = emulate_instruction(vcpu, 0, 0, 0);
3133
3134         if (er !=  EMULATE_DONE) {
3135                 printk(KERN_ERR
3136                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3137                        offset);
3138                 return -ENOEXEC;
3139         }
3140         return 1;
3141 }
3142
3143 static int handle_task_switch(struct kvm_vcpu *vcpu)
3144 {
3145         struct vcpu_vmx *vmx = to_vmx(vcpu);
3146         unsigned long exit_qualification;
3147         u16 tss_selector;
3148         int reason, type, idt_v;
3149
3150         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3151         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3152
3153         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3154
3155         reason = (u32)exit_qualification >> 30;
3156         if (reason == TASK_SWITCH_GATE && idt_v) {
3157                 switch (type) {
3158                 case INTR_TYPE_NMI_INTR:
3159                         vcpu->arch.nmi_injected = false;
3160                         if (cpu_has_virtual_nmis())
3161                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3162                                               GUEST_INTR_STATE_NMI);
3163                         break;
3164                 case INTR_TYPE_EXT_INTR:
3165                 case INTR_TYPE_SOFT_INTR:
3166                         kvm_clear_interrupt_queue(vcpu);
3167                         break;
3168                 case INTR_TYPE_HARD_EXCEPTION:
3169                 case INTR_TYPE_SOFT_EXCEPTION:
3170                         kvm_clear_exception_queue(vcpu);
3171                         break;
3172                 default:
3173                         break;
3174                 }
3175         }
3176         tss_selector = exit_qualification;
3177
3178         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3179                        type != INTR_TYPE_EXT_INTR &&
3180                        type != INTR_TYPE_NMI_INTR))
3181                 skip_emulated_instruction(vcpu);
3182
3183         if (!kvm_task_switch(vcpu, tss_selector, reason))
3184                 return 0;
3185
3186         /* clear all local breakpoint enable flags */
3187         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3188
3189         /*
3190          * TODO: What about debug traps on tss switch?
3191          *       Are we supposed to inject them and update dr6?
3192          */
3193
3194         return 1;
3195 }
3196
3197 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3198 {
3199         unsigned long exit_qualification;
3200         gpa_t gpa;
3201         int gla_validity;
3202
3203         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3204
3205         if (exit_qualification & (1 << 6)) {
3206                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3207                 return -EINVAL;
3208         }
3209
3210         gla_validity = (exit_qualification >> 7) & 0x3;
3211         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3212                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3213                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3214                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3215                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3216                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3217                         (long unsigned int)exit_qualification);
3218                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3219                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3220                 return 0;
3221         }
3222
3223         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3224         trace_kvm_page_fault(gpa, exit_qualification);
3225         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3226 }
3227
3228 static u64 ept_rsvd_mask(u64 spte, int level)
3229 {
3230         int i;
3231         u64 mask = 0;
3232
3233         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3234                 mask |= (1ULL << i);
3235
3236         if (level > 2)
3237                 /* bits 7:3 reserved */
3238                 mask |= 0xf8;
3239         else if (level == 2) {
3240                 if (spte & (1ULL << 7))
3241                         /* 2MB ref, bits 20:12 reserved */
3242                         mask |= 0x1ff000;
3243                 else
3244                         /* bits 6:3 reserved */
3245                         mask |= 0x78;
3246         }
3247
3248         return mask;
3249 }
3250
3251 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3252                                        int level)
3253 {
3254         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3255
3256         /* 010b (write-only) */
3257         WARN_ON((spte & 0x7) == 0x2);
3258
3259         /* 110b (write/execute) */
3260         WARN_ON((spte & 0x7) == 0x6);
3261
3262         /* 100b (execute-only) and value not supported by logical processor */
3263         if (!cpu_has_vmx_ept_execute_only())
3264                 WARN_ON((spte & 0x7) == 0x4);
3265
3266         /* not 000b */
3267         if ((spte & 0x7)) {
3268                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3269
3270                 if (rsvd_bits != 0) {
3271                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3272                                          __func__, rsvd_bits);
3273                         WARN_ON(1);
3274                 }
3275
3276                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3277                         u64 ept_mem_type = (spte & 0x38) >> 3;
3278
3279                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3280                             ept_mem_type == 7) {
3281                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3282                                                 __func__, ept_mem_type);
3283                                 WARN_ON(1);
3284                         }
3285                 }
3286         }
3287 }
3288
3289 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3290 {
3291         u64 sptes[4];
3292         int nr_sptes, i;
3293         gpa_t gpa;
3294
3295         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3296
3297         printk(KERN_ERR "EPT: Misconfiguration.\n");
3298         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3299
3300         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3301
3302         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3303                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3304
3305         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3306         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3307
3308         return 0;
3309 }
3310
3311 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3312 {
3313         u32 cpu_based_vm_exec_control;
3314
3315         /* clear pending NMI */
3316         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3317         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3318         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3319         ++vcpu->stat.nmi_window_exits;
3320
3321         return 1;
3322 }
3323
3324 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3325 {
3326         struct vcpu_vmx *vmx = to_vmx(vcpu);
3327         enum emulation_result err = EMULATE_DONE;
3328         int ret = 1;
3329
3330         while (!guest_state_valid(vcpu)) {
3331                 err = emulate_instruction(vcpu, 0, 0, 0);
3332
3333                 if (err == EMULATE_DO_MMIO) {
3334                         ret = 0;
3335                         goto out;
3336                 }
3337
3338                 if (err != EMULATE_DONE) {
3339                         kvm_report_emulation_failure(vcpu, "emulation failure");
3340                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3341                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3342                         ret = 0;
3343                         goto out;
3344                 }
3345
3346                 if (signal_pending(current))
3347                         goto out;
3348                 if (need_resched())
3349                         schedule();
3350         }
3351
3352         vmx->emulation_required = 0;
3353 out:
3354         return ret;
3355 }
3356
3357 /*
3358  * The exit handlers return 1 if the exit was handled fully and guest execution
3359  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3360  * to be done to userspace and return 0.
3361  */
3362 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3363         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3364         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3365         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3366         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3367         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3368         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3369         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3370         [EXIT_REASON_CPUID]                   = handle_cpuid,
3371         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3372         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3373         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3374         [EXIT_REASON_HLT]                     = handle_halt,
3375         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3376         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3377         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3378         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3379         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3380         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3381         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3382         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3383         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3384         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3385         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3386         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3387         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3388         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3389         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3390         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3391         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3392         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3393 };
3394
3395 static const int kvm_vmx_max_exit_handlers =
3396         ARRAY_SIZE(kvm_vmx_exit_handlers);
3397
3398 /*
3399  * The guest has exited.  See if we can fix it or if we need userspace
3400  * assistance.
3401  */
3402 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3403 {
3404         struct vcpu_vmx *vmx = to_vmx(vcpu);
3405         u32 exit_reason = vmx->exit_reason;
3406         u32 vectoring_info = vmx->idt_vectoring_info;
3407
3408         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3409
3410         /* If guest state is invalid, start emulating */
3411         if (vmx->emulation_required && emulate_invalid_guest_state)
3412                 return handle_invalid_guest_state(vcpu);
3413
3414         /* Access CR3 don't cause VMExit in paging mode, so we need
3415          * to sync with guest real CR3. */
3416         if (enable_ept && is_paging(vcpu))
3417                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3418
3419         if (unlikely(vmx->fail)) {
3420                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3421                 vcpu->run->fail_entry.hardware_entry_failure_reason
3422                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3423                 return 0;
3424         }
3425
3426         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3427                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3428                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3429                         exit_reason != EXIT_REASON_TASK_SWITCH))
3430                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3431                        "(0x%x) and exit reason is 0x%x\n",
3432                        __func__, vectoring_info, exit_reason);
3433
3434         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3435                 if (vmx_interrupt_allowed(vcpu)) {
3436                         vmx->soft_vnmi_blocked = 0;
3437                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3438                            vcpu->arch.nmi_pending) {
3439                         /*
3440                          * This CPU don't support us in finding the end of an
3441                          * NMI-blocked window if the guest runs with IRQs
3442                          * disabled. So we pull the trigger after 1 s of
3443                          * futile waiting, but inform the user about this.
3444                          */
3445                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3446                                "state on VCPU %d after 1 s timeout\n",
3447                                __func__, vcpu->vcpu_id);
3448                         vmx->soft_vnmi_blocked = 0;
3449                 }
3450         }
3451
3452         if (exit_reason < kvm_vmx_max_exit_handlers
3453             && kvm_vmx_exit_handlers[exit_reason])
3454                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3455         else {
3456                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3457                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3458         }
3459         return 0;
3460 }
3461
3462 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3463 {
3464         if (irr == -1 || tpr < irr) {
3465                 vmcs_write32(TPR_THRESHOLD, 0);
3466                 return;
3467         }
3468
3469         vmcs_write32(TPR_THRESHOLD, irr);
3470 }
3471
3472 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3473 {
3474         u32 exit_intr_info;
3475         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3476         bool unblock_nmi;
3477         u8 vector;
3478         int type;
3479         bool idtv_info_valid;
3480
3481         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3482
3483         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3484
3485         /* Handle machine checks before interrupts are enabled */
3486         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3487             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3488                 && is_machine_check(exit_intr_info)))
3489                 kvm_machine_check();
3490
3491         /* We need to handle NMIs before interrupts are enabled */
3492         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3493             (exit_intr_info & INTR_INFO_VALID_MASK))
3494                 asm("int $2");
3495
3496         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3497
3498         if (cpu_has_virtual_nmis()) {
3499                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3500                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3501                 /*
3502                  * SDM 3: 27.7.1.2 (September 2008)
3503                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3504                  * a guest IRET fault.
3505                  * SDM 3: 23.2.2 (September 2008)
3506                  * Bit 12 is undefined in any of the following cases:
3507                  *  If the VM exit sets the valid bit in the IDT-vectoring
3508                  *   information field.
3509                  *  If the VM exit is due to a double fault.
3510                  */
3511                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3512                     vector != DF_VECTOR && !idtv_info_valid)
3513                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3514                                       GUEST_INTR_STATE_NMI);
3515         } else if (unlikely(vmx->soft_vnmi_blocked))
3516                 vmx->vnmi_blocked_time +=
3517                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3518
3519         vmx->vcpu.arch.nmi_injected = false;
3520         kvm_clear_exception_queue(&vmx->vcpu);
3521         kvm_clear_interrupt_queue(&vmx->vcpu);
3522
3523         if (!idtv_info_valid)
3524                 return;
3525
3526         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3527         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3528
3529         switch (type) {
3530         case INTR_TYPE_NMI_INTR:
3531                 vmx->vcpu.arch.nmi_injected = true;
3532                 /*
3533                  * SDM 3: 27.7.1.2 (September 2008)
3534                  * Clear bit "block by NMI" before VM entry if a NMI
3535                  * delivery faulted.
3536                  */
3537                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3538                                 GUEST_INTR_STATE_NMI);
3539                 break;
3540         case INTR_TYPE_SOFT_EXCEPTION:
3541                 vmx->vcpu.arch.event_exit_inst_len =
3542                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3543                 /* fall through */
3544         case INTR_TYPE_HARD_EXCEPTION:
3545                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3546                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3547                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3548                 } else
3549                         kvm_queue_exception(&vmx->vcpu, vector);
3550                 break;
3551         case INTR_TYPE_SOFT_INTR:
3552                 vmx->vcpu.arch.event_exit_inst_len =
3553                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3554                 /* fall through */
3555         case INTR_TYPE_EXT_INTR:
3556                 kvm_queue_interrupt(&vmx->vcpu, vector,
3557                         type == INTR_TYPE_SOFT_INTR);
3558                 break;
3559         default:
3560                 break;
3561         }
3562 }
3563
3564 /*
3565  * Failure to inject an interrupt should give us the information
3566  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3567  * when fetching the interrupt redirection bitmap in the real-mode
3568  * tss, this doesn't happen.  So we do it ourselves.
3569  */
3570 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3571 {
3572         vmx->rmode.irq.pending = 0;
3573         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3574                 return;
3575         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3576         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3577                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3578                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3579                 return;
3580         }
3581         vmx->idt_vectoring_info =
3582                 VECTORING_INFO_VALID_MASK
3583                 | INTR_TYPE_EXT_INTR
3584                 | vmx->rmode.irq.vector;
3585 }
3586
3587 #ifdef CONFIG_X86_64
3588 #define R "r"
3589 #define Q "q"
3590 #else
3591 #define R "e"
3592 #define Q "l"
3593 #endif
3594
3595 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3596 {
3597         struct vcpu_vmx *vmx = to_vmx(vcpu);
3598
3599         if (enable_ept && is_paging(vcpu)) {
3600                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3601                 ept_load_pdptrs(vcpu);
3602         }
3603         /* Record the guest's net vcpu time for enforced NMI injections. */
3604         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3605                 vmx->entry_time = ktime_get();
3606
3607         /* Don't enter VMX if guest state is invalid, let the exit handler
3608            start emulation until we arrive back to a valid state */
3609         if (vmx->emulation_required && emulate_invalid_guest_state)
3610                 return;
3611
3612         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3613                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3614         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3615                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3616
3617         /* When single-stepping over STI and MOV SS, we must clear the
3618          * corresponding interruptibility bits in the guest state. Otherwise
3619          * vmentry fails as it then expects bit 14 (BS) in pending debug
3620          * exceptions being set, but that's not correct for the guest debugging
3621          * case. */
3622         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3623                 vmx_set_interrupt_shadow(vcpu, 0);
3624
3625         /*
3626          * Loading guest fpu may have cleared host cr0.ts
3627          */
3628         vmcs_writel(HOST_CR0, read_cr0());
3629
3630         if (vcpu->arch.switch_db_regs)
3631                 set_debugreg(vcpu->arch.dr6, 6);
3632
3633         asm(
3634                 /* Store host registers */
3635                 "push %%"R"dx; push %%"R"bp;"
3636                 "push %%"R"cx \n\t"
3637                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3638                 "je 1f \n\t"
3639                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3640                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3641                 "1: \n\t"
3642                 /* Reload cr2 if changed */
3643                 "mov %c[cr2](%0), %%"R"ax \n\t"
3644                 "mov %%cr2, %%"R"dx \n\t"
3645                 "cmp %%"R"ax, %%"R"dx \n\t"
3646                 "je 2f \n\t"
3647                 "mov %%"R"ax, %%cr2 \n\t"
3648                 "2: \n\t"
3649                 /* Check if vmlaunch of vmresume is needed */
3650                 "cmpl $0, %c[launched](%0) \n\t"
3651                 /* Load guest registers.  Don't clobber flags. */
3652                 "mov %c[rax](%0), %%"R"ax \n\t"
3653                 "mov %c[rbx](%0), %%"R"bx \n\t"
3654                 "mov %c[rdx](%0), %%"R"dx \n\t"
3655                 "mov %c[rsi](%0), %%"R"si \n\t"
3656                 "mov %c[rdi](%0), %%"R"di \n\t"
3657                 "mov %c[rbp](%0), %%"R"bp \n\t"
3658 #ifdef CONFIG_X86_64
3659                 "mov %c[r8](%0),  %%r8  \n\t"
3660                 "mov %c[r9](%0),  %%r9  \n\t"
3661                 "mov %c[r10](%0), %%r10 \n\t"
3662                 "mov %c[r11](%0), %%r11 \n\t"
3663                 "mov %c[r12](%0), %%r12 \n\t"
3664                 "mov %c[r13](%0), %%r13 \n\t"
3665                 "mov %c[r14](%0), %%r14 \n\t"
3666                 "mov %c[r15](%0), %%r15 \n\t"
3667 #endif
3668                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3669
3670                 /* Enter guest mode */
3671                 "jne .Llaunched \n\t"
3672                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3673                 "jmp .Lkvm_vmx_return \n\t"
3674                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3675                 ".Lkvm_vmx_return: "
3676                 /* Save guest registers, load host registers, keep flags */
3677                 "xchg %0,     (%%"R"sp) \n\t"
3678                 "mov %%"R"ax, %c[rax](%0) \n\t"
3679                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3680                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3681                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3682                 "mov %%"R"si, %c[rsi](%0) \n\t"
3683                 "mov %%"R"di, %c[rdi](%0) \n\t"
3684                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3685 #ifdef CONFIG_X86_64
3686                 "mov %%r8,  %c[r8](%0) \n\t"
3687                 "mov %%r9,  %c[r9](%0) \n\t"
3688                 "mov %%r10, %c[r10](%0) \n\t"
3689                 "mov %%r11, %c[r11](%0) \n\t"
3690                 "mov %%r12, %c[r12](%0) \n\t"
3691                 "mov %%r13, %c[r13](%0) \n\t"
3692                 "mov %%r14, %c[r14](%0) \n\t"
3693                 "mov %%r15, %c[r15](%0) \n\t"
3694 #endif
3695                 "mov %%cr2, %%"R"ax   \n\t"
3696                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3697
3698                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3699                 "setbe %c[fail](%0) \n\t"
3700               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3701                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3702                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3703                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3704                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3705                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3706                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3707                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3708                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3709                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3710                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3711 #ifdef CONFIG_X86_64
3712                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3713                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3714                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3715                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3716                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3717                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3718                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3719                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3720 #endif
3721                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3722               : "cc", "memory"
3723                 , R"bx", R"di", R"si"
3724 #ifdef CONFIG_X86_64
3725                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3726 #endif
3727               );
3728
3729         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3730                                   | (1 << VCPU_EXREG_PDPTR));
3731         vcpu->arch.regs_dirty = 0;
3732
3733         if (vcpu->arch.switch_db_regs)
3734                 get_debugreg(vcpu->arch.dr6, 6);
3735
3736         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3737         if (vmx->rmode.irq.pending)
3738                 fixup_rmode_irq(vmx);
3739
3740         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3741         vmx->launched = 1;
3742
3743         vmx_complete_interrupts(vmx);
3744 }
3745
3746 #undef R
3747 #undef Q
3748
3749 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3750 {
3751         struct vcpu_vmx *vmx = to_vmx(vcpu);
3752
3753         if (vmx->vmcs) {
3754                 vcpu_clear(vmx);
3755                 free_vmcs(vmx->vmcs);
3756                 vmx->vmcs = NULL;
3757         }
3758 }
3759
3760 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3761 {
3762         struct vcpu_vmx *vmx = to_vmx(vcpu);
3763
3764         spin_lock(&vmx_vpid_lock);
3765         if (vmx->vpid != 0)
3766                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3767         spin_unlock(&vmx_vpid_lock);
3768         vmx_free_vmcs(vcpu);
3769         kfree(vmx->host_msrs);
3770         kfree(vmx->guest_msrs);
3771         kvm_vcpu_uninit(vcpu);
3772         kmem_cache_free(kvm_vcpu_cache, vmx);
3773 }
3774
3775 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3776 {
3777         int err;
3778         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3779         int cpu;
3780
3781         if (!vmx)
3782                 return ERR_PTR(-ENOMEM);
3783
3784         allocate_vpid(vmx);
3785
3786         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3787         if (err)
3788                 goto free_vcpu;
3789
3790         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3791         if (!vmx->guest_msrs) {
3792                 err = -ENOMEM;
3793                 goto uninit_vcpu;
3794         }
3795
3796         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3797         if (!vmx->host_msrs)
3798                 goto free_guest_msrs;
3799
3800         vmx->vmcs = alloc_vmcs();
3801         if (!vmx->vmcs)
3802                 goto free_msrs;
3803
3804         vmcs_clear(vmx->vmcs);
3805
3806         cpu = get_cpu();
3807         vmx_vcpu_load(&vmx->vcpu, cpu);
3808         err = vmx_vcpu_setup(vmx);
3809         vmx_vcpu_put(&vmx->vcpu);
3810         put_cpu();
3811         if (err)
3812                 goto free_vmcs;
3813         if (vm_need_virtualize_apic_accesses(kvm))
3814                 if (alloc_apic_access_page(kvm) != 0)
3815                         goto free_vmcs;
3816
3817         if (enable_ept) {
3818                 if (!kvm->arch.ept_identity_map_addr)
3819                         kvm->arch.ept_identity_map_addr =
3820                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3821                 if (alloc_identity_pagetable(kvm) != 0)
3822                         goto free_vmcs;
3823         }
3824
3825         return &vmx->vcpu;
3826
3827 free_vmcs:
3828         free_vmcs(vmx->vmcs);
3829 free_msrs:
3830         kfree(vmx->host_msrs);
3831 free_guest_msrs:
3832         kfree(vmx->guest_msrs);
3833 uninit_vcpu:
3834         kvm_vcpu_uninit(&vmx->vcpu);
3835 free_vcpu:
3836         kmem_cache_free(kvm_vcpu_cache, vmx);
3837         return ERR_PTR(err);
3838 }
3839
3840 static void __init vmx_check_processor_compat(void *rtn)
3841 {
3842         struct vmcs_config vmcs_conf;
3843
3844         *(int *)rtn = 0;
3845         if (setup_vmcs_config(&vmcs_conf) < 0)
3846                 *(int *)rtn = -EIO;
3847         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3848                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3849                                 smp_processor_id());
3850                 *(int *)rtn = -EIO;
3851         }
3852 }
3853
3854 static int get_ept_level(void)
3855 {
3856         return VMX_EPT_DEFAULT_GAW + 1;
3857 }
3858
3859 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3860 {
3861         u64 ret;
3862
3863         /* For VT-d and EPT combination
3864          * 1. MMIO: always map as UC
3865          * 2. EPT with VT-d:
3866          *   a. VT-d without snooping control feature: can't guarantee the
3867          *      result, try to trust guest.
3868          *   b. VT-d with snooping control feature: snooping control feature of
3869          *      VT-d engine can guarantee the cache correctness. Just set it
3870          *      to WB to keep consistent with host. So the same as item 3.
3871          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3872          *    consistent with host MTRR
3873          */
3874         if (is_mmio)
3875                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3876         else if (vcpu->kvm->arch.iommu_domain &&
3877                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3878                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3879                       VMX_EPT_MT_EPTE_SHIFT;
3880         else
3881                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3882                         | VMX_EPT_IGMT_BIT;
3883
3884         return ret;
3885 }
3886
3887 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3888         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3889         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3890         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3891         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3892         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3893         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3894         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3895         { EXIT_REASON_CPUID,                   "cpuid" },
3896         { EXIT_REASON_MSR_READ,                "rdmsr" },
3897         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3898         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3899         { EXIT_REASON_HLT,                     "halt" },
3900         { EXIT_REASON_INVLPG,                  "invlpg" },
3901         { EXIT_REASON_VMCALL,                  "hypercall" },
3902         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3903         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3904         { EXIT_REASON_WBINVD,                  "wbinvd" },
3905         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3906         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3907         { -1, NULL }
3908 };
3909
3910 static bool vmx_gb_page_enable(void)
3911 {
3912         return false;
3913 }
3914
3915 static struct kvm_x86_ops vmx_x86_ops = {
3916         .cpu_has_kvm_support = cpu_has_kvm_support,
3917         .disabled_by_bios = vmx_disabled_by_bios,
3918         .hardware_setup = hardware_setup,
3919         .hardware_unsetup = hardware_unsetup,
3920         .check_processor_compatibility = vmx_check_processor_compat,
3921         .hardware_enable = hardware_enable,
3922         .hardware_disable = hardware_disable,
3923         .cpu_has_accelerated_tpr = report_flexpriority,
3924
3925         .vcpu_create = vmx_create_vcpu,
3926         .vcpu_free = vmx_free_vcpu,
3927         .vcpu_reset = vmx_vcpu_reset,
3928
3929         .prepare_guest_switch = vmx_save_host_state,
3930         .vcpu_load = vmx_vcpu_load,
3931         .vcpu_put = vmx_vcpu_put,
3932
3933         .set_guest_debug = set_guest_debug,
3934         .get_msr = vmx_get_msr,
3935         .set_msr = vmx_set_msr,
3936         .get_segment_base = vmx_get_segment_base,
3937         .get_segment = vmx_get_segment,
3938         .set_segment = vmx_set_segment,
3939         .get_cpl = vmx_get_cpl,
3940         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3941         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3942         .set_cr0 = vmx_set_cr0,
3943         .set_cr3 = vmx_set_cr3,
3944         .set_cr4 = vmx_set_cr4,
3945         .set_efer = vmx_set_efer,
3946         .get_idt = vmx_get_idt,
3947         .set_idt = vmx_set_idt,
3948         .get_gdt = vmx_get_gdt,
3949         .set_gdt = vmx_set_gdt,
3950         .cache_reg = vmx_cache_reg,
3951         .get_rflags = vmx_get_rflags,
3952         .set_rflags = vmx_set_rflags,
3953
3954         .tlb_flush = vmx_flush_tlb,
3955
3956         .run = vmx_vcpu_run,
3957         .handle_exit = vmx_handle_exit,
3958         .skip_emulated_instruction = skip_emulated_instruction,
3959         .set_interrupt_shadow = vmx_set_interrupt_shadow,
3960         .get_interrupt_shadow = vmx_get_interrupt_shadow,
3961         .patch_hypercall = vmx_patch_hypercall,
3962         .set_irq = vmx_inject_irq,
3963         .set_nmi = vmx_inject_nmi,
3964         .queue_exception = vmx_queue_exception,
3965         .interrupt_allowed = vmx_interrupt_allowed,
3966         .nmi_allowed = vmx_nmi_allowed,
3967         .enable_nmi_window = enable_nmi_window,
3968         .enable_irq_window = enable_irq_window,
3969         .update_cr8_intercept = update_cr8_intercept,
3970
3971         .set_tss_addr = vmx_set_tss_addr,
3972         .get_tdp_level = get_ept_level,
3973         .get_mt_mask = vmx_get_mt_mask,
3974
3975         .exit_reasons_str = vmx_exit_reasons_str,
3976         .gb_page_enable = vmx_gb_page_enable,
3977 };
3978
3979 static int __init vmx_init(void)
3980 {
3981         int r;
3982
3983         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3984         if (!vmx_io_bitmap_a)
3985                 return -ENOMEM;
3986
3987         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3988         if (!vmx_io_bitmap_b) {
3989                 r = -ENOMEM;
3990                 goto out;
3991         }
3992
3993         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3994         if (!vmx_msr_bitmap_legacy) {
3995                 r = -ENOMEM;
3996                 goto out1;
3997         }
3998
3999         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4000         if (!vmx_msr_bitmap_longmode) {
4001                 r = -ENOMEM;
4002                 goto out2;
4003         }
4004
4005         /*
4006          * Allow direct access to the PC debug port (it is often used for I/O
4007          * delays, but the vmexits simply slow things down).
4008          */
4009         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4010         clear_bit(0x80, vmx_io_bitmap_a);
4011
4012         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4013
4014         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4015         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4016
4017         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4018
4019         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4020         if (r)
4021                 goto out3;
4022
4023         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4024         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4025         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4026         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4027         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4028         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4029
4030         if (enable_ept) {
4031                 bypass_guest_pf = 0;
4032                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4033                         VMX_EPT_WRITABLE_MASK);
4034                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4035                                 VMX_EPT_EXECUTABLE_MASK);
4036                 kvm_enable_tdp();
4037         } else
4038                 kvm_disable_tdp();
4039
4040         if (bypass_guest_pf)
4041                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4042
4043         ept_sync_global();
4044
4045         return 0;
4046
4047 out3:
4048         free_page((unsigned long)vmx_msr_bitmap_longmode);
4049 out2:
4050         free_page((unsigned long)vmx_msr_bitmap_legacy);
4051 out1:
4052         free_page((unsigned long)vmx_io_bitmap_b);
4053 out:
4054         free_page((unsigned long)vmx_io_bitmap_a);
4055         return r;
4056 }
4057
4058 static void __exit vmx_exit(void)
4059 {
4060         free_page((unsigned long)vmx_msr_bitmap_legacy);
4061         free_page((unsigned long)vmx_msr_bitmap_longmode);
4062         free_page((unsigned long)vmx_io_bitmap_b);
4063         free_page((unsigned long)vmx_io_bitmap_a);
4064
4065         kvm_exit();
4066 }
4067
4068 module_init(vmx_init)
4069 module_exit(vmx_exit)