SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include "kvm_cache_regs.h"
  29 #include "x86.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33 #include <asm/vmx.h>
  34 #include <asm/virtext.h>
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 static int __read_mostly bypass_guest_pf = 1;
  42 module_param(bypass_guest_pf, bool, S_IRUGO);
  43
  44 static int __read_mostly enable_vpid = 1;
  45 module_param_named(vpid, enable_vpid, bool, 0444);
  46
  47 static int __read_mostly flexpriority_enabled = 1;
  48 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  49
  50 static int __read_mostly enable_ept = 1;
  51 module_param_named(ept, enable_ept, bool, S_IRUGO);
  52
  53 static int __read_mostly emulate_invalid_guest_state = 0;
  54 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  55
  56 struct vmcs {
  57         u32 revision_id;
  58         u32 abort;
  59         char data[0];
  60 };
  61
  62 struct vcpu_vmx {
  63         struct kvm_vcpu       vcpu;
  64         struct list_head      local_vcpus_link;
  65         unsigned long         host_rsp;
  66         int                   launched;
  67         u8                    fail;
  68         u32                   idt_vectoring_info;
  69         struct kvm_msr_entry *guest_msrs;
  70         struct kvm_msr_entry *host_msrs;
  71         int                   nmsrs;
  72         int                   save_nmsrs;
  73         int                   msr_offset_efer;
  74 #ifdef CONFIG_X86_64
  75         int                   msr_offset_kernel_gs_base;
  76 #endif
  77         struct vmcs          *vmcs;
  78         struct {
  79                 int           loaded;
  80                 u16           fs_sel, gs_sel, ldt_sel;
  81                 int           gs_ldt_reload_needed;
  82                 int           fs_reload_needed;
  83                 int           guest_efer_loaded;
  84         } host_state;
  85         struct {
  86                 struct {
  87                         bool pending;
  88                         u8 vector;
  89                         unsigned rip;
  90                 } irq;
  91         } rmode;
  92         int vpid;
  93         bool emulation_required;
  94         enum emulation_result invalid_state_emulation_result;
  95
  96         /* Support for vnmi-less CPUs */
  97         int soft_vnmi_blocked;
  98         ktime_t entry_time;
  99         s64 vnmi_blocked_time;
 100 };
 101
 102 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 103 {
 104         return container_of(vcpu, struct vcpu_vmx, vcpu);
 105 }
 106
 107 static int init_rmode(struct kvm *kvm);
 108 static u64 construct_eptp(unsigned long root_hpa);
 109
 110 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 111 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 112 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 113
 114 static unsigned long *vmx_io_bitmap_a;
 115 static unsigned long *vmx_io_bitmap_b;
 116 static unsigned long *vmx_msr_bitmap_legacy;
 117 static unsigned long *vmx_msr_bitmap_longmode;
 118
 119 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 120 static DEFINE_SPINLOCK(vmx_vpid_lock);
 121
 122 static struct vmcs_config {
 123         int size;
 124         int order;
 125         u32 revision_id;
 126         u32 pin_based_exec_ctrl;
 127         u32 cpu_based_exec_ctrl;
 128         u32 cpu_based_2nd_exec_ctrl;
 129         u32 vmexit_ctrl;
 130         u32 vmentry_ctrl;
 131 } vmcs_config;
 132
 133 static struct vmx_capability {
 134         u32 ept;
 135         u32 vpid;
 136 } vmx_capability;
 137
 138 #define VMX_SEGMENT_FIELD(seg)                                  \
 139         [VCPU_SREG_##seg] = {                                   \
 140                 .selector = GUEST_##seg##_SELECTOR,             \
 141                 .base = GUEST_##seg##_BASE,                     \
 142                 .limit = GUEST_##seg##_LIMIT,                   \
 143                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 144         }
 145
 146 static struct kvm_vmx_segment_field {
 147         unsigned selector;
 148         unsigned base;
 149         unsigned limit;
 150         unsigned ar_bytes;
 151 } kvm_vmx_segment_fields[] = {
 152         VMX_SEGMENT_FIELD(CS),
 153         VMX_SEGMENT_FIELD(DS),
 154         VMX_SEGMENT_FIELD(ES),
 155         VMX_SEGMENT_FIELD(FS),
 156         VMX_SEGMENT_FIELD(GS),
 157         VMX_SEGMENT_FIELD(SS),
 158         VMX_SEGMENT_FIELD(TR),
 159         VMX_SEGMENT_FIELD(LDTR),
 160 };
 161
 162 /*
 163  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 164  * away by decrementing the array size.
 165  */
 166 static const u32 vmx_msr_index[] = {
 167 #ifdef CONFIG_X86_64
 168         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 169 #endif
 170         MSR_EFER, MSR_K6_STAR,
 171 };
 172 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 173
 174 static void load_msrs(struct kvm_msr_entry *e, int n)
 175 {
 176         int i;
 177
 178         for (i = 0; i < n; ++i)
 179                 wrmsrl(e[i].index, e[i].data);
 180 }
 181
 182 static void save_msrs(struct kvm_msr_entry *e, int n)
 183 {
 184         int i;
 185
 186         for (i = 0; i < n; ++i)
 187                 rdmsrl(e[i].index, e[i].data);
 188 }
 189
 190 static inline int is_page_fault(u32 intr_info)
 191 {
 192         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 193                              INTR_INFO_VALID_MASK)) ==
 194                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 195 }
 196
 197 static inline int is_no_device(u32 intr_info)
 198 {
 199         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 200                              INTR_INFO_VALID_MASK)) ==
 201                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 202 }
 203
 204 static inline int is_invalid_opcode(u32 intr_info)
 205 {
 206         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 207                              INTR_INFO_VALID_MASK)) ==
 208                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 209 }
 210
 211 static inline int is_external_interrupt(u32 intr_info)
 212 {
 213         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 214                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 215 }
 216
 217 static inline int cpu_has_vmx_msr_bitmap(void)
 218 {
 219         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 220 }
 221
 222 static inline int cpu_has_vmx_tpr_shadow(void)
 223 {
 224         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 225 }
 226
 227 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 228 {
 229         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 230 }
 231
 232 static inline int cpu_has_secondary_exec_ctrls(void)
 233 {
 234         return (vmcs_config.cpu_based_exec_ctrl &
 235                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 236 }
 237
 238 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 239 {
 240         return flexpriority_enabled
 241                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 242                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 243 }
 244
 245 static inline int cpu_has_vmx_invept_individual_addr(void)
 246 {
 247         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 248 }
 249
 250 static inline int cpu_has_vmx_invept_context(void)
 251 {
 252         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 253 }
 254
 255 static inline int cpu_has_vmx_invept_global(void)
 256 {
 257         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 258 }
 259
 260 static inline int cpu_has_vmx_ept(void)
 261 {
 262         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 263                 SECONDARY_EXEC_ENABLE_EPT);
 264 }
 265
 266 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 267 {
 268         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 269                 (irqchip_in_kernel(kvm)));
 270 }
 271
 272 static inline int cpu_has_vmx_vpid(void)
 273 {
 274         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 275                 SECONDARY_EXEC_ENABLE_VPID);
 276 }
 277
 278 static inline int cpu_has_virtual_nmis(void)
 279 {
 280         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 281 }
 282
 283 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 284 {
 285         int i;
 286
 287         for (i = 0; i < vmx->nmsrs; ++i)
 288                 if (vmx->guest_msrs[i].index == msr)
 289                         return i;
 290         return -1;
 291 }
 292
 293 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 294 {
 295     struct {
 296         u64 vpid : 16;
 297         u64 rsvd : 48;
 298         u64 gva;
 299     } operand = { vpid, 0, gva };
 300
 301     asm volatile (__ex(ASM_VMX_INVVPID)
 302                   /* CF==1 or ZF==1 --> rc = -1 */
 303                   "; ja 1f ; ud2 ; 1:"
 304                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 305 }
 306
 307 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 308 {
 309         struct {
 310                 u64 eptp, gpa;
 311         } operand = {eptp, gpa};
 312
 313         asm volatile (__ex(ASM_VMX_INVEPT)
 314                         /* CF==1 or ZF==1 --> rc = -1 */
 315                         "; ja 1f ; ud2 ; 1:\n"
 316                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 317 }
 318
 319 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 320 {
 321         int i;
 322
 323         i = __find_msr_index(vmx, msr);
 324         if (i >= 0)
 325                 return &vmx->guest_msrs[i];
 326         return NULL;
 327 }
 328
 329 static void vmcs_clear(struct vmcs *vmcs)
 330 {
 331         u64 phys_addr = __pa(vmcs);
 332         u8 error;
 333
 334         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 335                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 336                       : "cc", "memory");
 337         if (error)
 338                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 339                        vmcs, phys_addr);
 340 }
 341
 342 static void __vcpu_clear(void *arg)
 343 {
 344         struct vcpu_vmx *vmx = arg;
 345         int cpu = raw_smp_processor_id();
 346
 347         if (vmx->vcpu.cpu == cpu)
 348                 vmcs_clear(vmx->vmcs);
 349         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 350                 per_cpu(current_vmcs, cpu) = NULL;
 351         rdtscll(vmx->vcpu.arch.host_tsc);
 352         list_del(&vmx->local_vcpus_link);
 353         vmx->vcpu.cpu = -1;
 354         vmx->launched = 0;
 355 }
 356
 357 static void vcpu_clear(struct vcpu_vmx *vmx)
 358 {
 359         if (vmx->vcpu.cpu == -1)
 360                 return;
 361         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 362 }
 363
 364 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 365 {
 366         if (vmx->vpid == 0)
 367                 return;
 368
 369         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 370 }
 371
 372 static inline void ept_sync_global(void)
 373 {
 374         if (cpu_has_vmx_invept_global())
 375                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 376 }
 377
 378 static inline void ept_sync_context(u64 eptp)
 379 {
 380         if (enable_ept) {
 381                 if (cpu_has_vmx_invept_context())
 382                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 383                 else
 384                         ept_sync_global();
 385         }
 386 }
 387
 388 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 389 {
 390         if (enable_ept) {
 391                 if (cpu_has_vmx_invept_individual_addr())
 392                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 393                                         eptp, gpa);
 394                 else
 395                         ept_sync_context(eptp);
 396         }
 397 }
 398
 399 static unsigned long vmcs_readl(unsigned long field)
 400 {
 401         unsigned long value;
 402
 403         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 404                       : "=a"(value) : "d"(field) : "cc");
 405         return value;
 406 }
 407
 408 static u16 vmcs_read16(unsigned long field)
 409 {
 410         return vmcs_readl(field);
 411 }
 412
 413 static u32 vmcs_read32(unsigned long field)
 414 {
 415         return vmcs_readl(field);
 416 }
 417
 418 static u64 vmcs_read64(unsigned long field)
 419 {
 420 #ifdef CONFIG_X86_64
 421         return vmcs_readl(field);
 422 #else
 423         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 424 #endif
 425 }
 426
 427 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 428 {
 429         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 430                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 431         dump_stack();
 432 }
 433
 434 static void vmcs_writel(unsigned long field, unsigned long value)
 435 {
 436         u8 error;
 437
 438         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 439                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 440         if (unlikely(error))
 441                 vmwrite_error(field, value);
 442 }
 443
 444 static void vmcs_write16(unsigned long field, u16 value)
 445 {
 446         vmcs_writel(field, value);
 447 }
 448
 449 static void vmcs_write32(unsigned long field, u32 value)
 450 {
 451         vmcs_writel(field, value);
 452 }
 453
 454 static void vmcs_write64(unsigned long field, u64 value)
 455 {
 456         vmcs_writel(field, value);
 457 #ifndef CONFIG_X86_64
 458         asm volatile ("");
 459         vmcs_writel(field+1, value >> 32);
 460 #endif
 461 }
 462
 463 static void vmcs_clear_bits(unsigned long field, u32 mask)
 464 {
 465         vmcs_writel(field, vmcs_readl(field) & ~mask);
 466 }
 467
 468 static void vmcs_set_bits(unsigned long field, u32 mask)
 469 {
 470         vmcs_writel(field, vmcs_readl(field) | mask);
 471 }
 472
 473 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 474 {
 475         u32 eb;
 476
 477         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 478         if (!vcpu->fpu_active)
 479                 eb |= 1u << NM_VECTOR;
 480         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 481                 if (vcpu->guest_debug &
 482                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 483                         eb |= 1u << DB_VECTOR;
 484                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 485                         eb |= 1u << BP_VECTOR;
 486         }
 487         if (vcpu->arch.rmode.active)
 488                 eb = ~0;
 489         if (enable_ept)
 490                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 491         vmcs_write32(EXCEPTION_BITMAP, eb);
 492 }
 493
 494 static void reload_tss(void)
 495 {
 496         /*
 497          * VT restores TR but not its size.  Useless.
 498          */
 499         struct descriptor_table gdt;
 500         struct desc_struct *descs;
 501
 502         kvm_get_gdt(&gdt);
 503         descs = (void *)gdt.base;
 504         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 505         load_TR_desc();
 506 }
 507
 508 static void load_transition_efer(struct vcpu_vmx *vmx)
 509 {
 510         int efer_offset = vmx->msr_offset_efer;
 511         u64 host_efer = vmx->host_msrs[efer_offset].data;
 512         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 513         u64 ignore_bits;
 514
 515         if (efer_offset < 0)
 516                 return;
 517         /*
 518          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 519          * outside long mode
 520          */
 521         ignore_bits = EFER_NX | EFER_SCE;
 522 #ifdef CONFIG_X86_64
 523         ignore_bits |= EFER_LMA | EFER_LME;
 524         /* SCE is meaningful only in long mode on Intel */
 525         if (guest_efer & EFER_LMA)
 526                 ignore_bits &= ~(u64)EFER_SCE;
 527 #endif
 528         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 529                 return;
 530
 531         vmx->host_state.guest_efer_loaded = 1;
 532         guest_efer &= ~ignore_bits;
 533         guest_efer |= host_efer & ignore_bits;
 534         wrmsrl(MSR_EFER, guest_efer);
 535         vmx->vcpu.stat.efer_reload++;
 536 }
 537
 538 static void reload_host_efer(struct vcpu_vmx *vmx)
 539 {
 540         if (vmx->host_state.guest_efer_loaded) {
 541                 vmx->host_state.guest_efer_loaded = 0;
 542                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 543         }
 544 }
 545
 546 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 547 {
 548         struct vcpu_vmx *vmx = to_vmx(vcpu);
 549
 550         if (vmx->host_state.loaded)
 551                 return;
 552
 553         vmx->host_state.loaded = 1;
 554         /*
 555          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 556          * allow segment selectors with cpl > 0 or ti == 1.
 557          */
 558         vmx->host_state.ldt_sel = kvm_read_ldt();
 559         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 560         vmx->host_state.fs_sel = kvm_read_fs();
 561         if (!(vmx->host_state.fs_sel & 7)) {
 562                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 563                 vmx->host_state.fs_reload_needed = 0;
 564         } else {
 565                 vmcs_write16(HOST_FS_SELECTOR, 0);
 566                 vmx->host_state.fs_reload_needed = 1;
 567         }
 568         vmx->host_state.gs_sel = kvm_read_gs();
 569         if (!(vmx->host_state.gs_sel & 7))
 570                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 571         else {
 572                 vmcs_write16(HOST_GS_SELECTOR, 0);
 573                 vmx->host_state.gs_ldt_reload_needed = 1;
 574         }
 575
 576 #ifdef CONFIG_X86_64
 577         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 578         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 579 #else
 580         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 581         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 582 #endif
 583
 584 #ifdef CONFIG_X86_64
 585         if (is_long_mode(&vmx->vcpu))
 586                 save_msrs(vmx->host_msrs +
 587                           vmx->msr_offset_kernel_gs_base, 1);
 588
 589 #endif
 590         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 591         load_transition_efer(vmx);
 592 }
 593
 594 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 595 {
 596         unsigned long flags;
 597
 598         if (!vmx->host_state.loaded)
 599                 return;
 600
 601         ++vmx->vcpu.stat.host_state_reload;
 602         vmx->host_state.loaded = 0;
 603         if (vmx->host_state.fs_reload_needed)
 604                 kvm_load_fs(vmx->host_state.fs_sel);
 605         if (vmx->host_state.gs_ldt_reload_needed) {
 606                 kvm_load_ldt(vmx->host_state.ldt_sel);
 607                 /*
 608                  * If we have to reload gs, we must take care to
 609                  * preserve our gs base.
 610                  */
 611                 local_irq_save(flags);
 612                 kvm_load_gs(vmx->host_state.gs_sel);
 613 #ifdef CONFIG_X86_64
 614                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 615 #endif
 616                 local_irq_restore(flags);
 617         }
 618         reload_tss();
 619         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 620         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 621         reload_host_efer(vmx);
 622 }
 623
 624 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 625 {
 626         preempt_disable();
 627         __vmx_load_host_state(vmx);
 628         preempt_enable();
 629 }
 630
 631 /*
 632  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 633  * vcpu mutex is already taken.
 634  */
 635 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 636 {
 637         struct vcpu_vmx *vmx = to_vmx(vcpu);
 638         u64 phys_addr = __pa(vmx->vmcs);
 639         u64 tsc_this, delta, new_offset;
 640
 641         if (vcpu->cpu != cpu) {
 642                 vcpu_clear(vmx);
 643                 kvm_migrate_timers(vcpu);
 644                 vpid_sync_vcpu_all(vmx);
 645                 local_irq_disable();
 646                 list_add(&vmx->local_vcpus_link,
 647                          &per_cpu(vcpus_on_cpu, cpu));
 648                 local_irq_enable();
 649         }
 650
 651         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 652                 u8 error;
 653
 654                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 655                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 656                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 657                               : "cc");
 658                 if (error)
 659                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 660                                vmx->vmcs, phys_addr);
 661         }
 662
 663         if (vcpu->cpu != cpu) {
 664                 struct descriptor_table dt;
 665                 unsigned long sysenter_esp;
 666
 667                 vcpu->cpu = cpu;
 668                 /*
 669                  * Linux uses per-cpu TSS and GDT, so set these when switching
 670                  * processors.
 671                  */
 672                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 673                 kvm_get_gdt(&dt);
 674                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 675
 676                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 677                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 678
 679                 /*
 680                  * Make sure the time stamp counter is monotonous.
 681                  */
 682                 rdtscll(tsc_this);
 683                 if (tsc_this < vcpu->arch.host_tsc) {
 684                         delta = vcpu->arch.host_tsc - tsc_this;
 685                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 686                         vmcs_write64(TSC_OFFSET, new_offset);
 687                 }
 688         }
 689 }
 690
 691 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 692 {
 693         __vmx_load_host_state(to_vmx(vcpu));
 694 }
 695
 696 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 697 {
 698         if (vcpu->fpu_active)
 699                 return;
 700         vcpu->fpu_active = 1;
 701         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 702         if (vcpu->arch.cr0 & X86_CR0_TS)
 703                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 704         update_exception_bitmap(vcpu);
 705 }
 706
 707 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 708 {
 709         if (!vcpu->fpu_active)
 710                 return;
 711         vcpu->fpu_active = 0;
 712         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 713         update_exception_bitmap(vcpu);
 714 }
 715
 716 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 717 {
 718         return vmcs_readl(GUEST_RFLAGS);
 719 }
 720
 721 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 722 {
 723         if (vcpu->arch.rmode.active)
 724                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 725         vmcs_writel(GUEST_RFLAGS, rflags);
 726 }
 727
 728 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 729 {
 730         unsigned long rip;
 731         u32 interruptibility;
 732
 733         rip = kvm_rip_read(vcpu);
 734         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 735         kvm_rip_write(vcpu, rip);
 736
 737         /*
 738          * We emulated an instruction, so temporary interrupt blocking
 739          * should be removed, if set.
 740          */
 741         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 742         if (interruptibility & 3)
 743                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 744                              interruptibility & ~3);
 745         vcpu->arch.interrupt_window_open = 1;
 746 }
 747
 748 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 749                                 bool has_error_code, u32 error_code)
 750 {
 751         struct vcpu_vmx *vmx = to_vmx(vcpu);
 752         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 753
 754         if (has_error_code) {
 755                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 756                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 757         }
 758
 759         if (vcpu->arch.rmode.active) {
 760                 vmx->rmode.irq.pending = true;
 761                 vmx->rmode.irq.vector = nr;
 762                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 763                 if (nr == BP_VECTOR || nr == OF_VECTOR)
 764                         vmx->rmode.irq.rip++;
 765                 intr_info |= INTR_TYPE_SOFT_INTR;
 766                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 767                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 768                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 769                 return;
 770         }
 771
 772         if (nr == BP_VECTOR || nr == OF_VECTOR) {
 773                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 774                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 775         } else
 776                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 777
 778         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 779 }
 780
 781 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 782 {
 783         return false;
 784 }
 785
 786 /*
 787  * Swap MSR entry in host/guest MSR entry array.
 788  */
 789 #ifdef CONFIG_X86_64
 790 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 791 {
 792         struct kvm_msr_entry tmp;
 793
 794         tmp = vmx->guest_msrs[to];
 795         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 796         vmx->guest_msrs[from] = tmp;
 797         tmp = vmx->host_msrs[to];
 798         vmx->host_msrs[to] = vmx->host_msrs[from];
 799         vmx->host_msrs[from] = tmp;
 800 }
 801 #endif
 802
 803 /*
 804  * Set up the vmcs to automatically save and restore system
 805  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 806  * mode, as fiddling with msrs is very expensive.
 807  */
 808 static void setup_msrs(struct vcpu_vmx *vmx)
 809 {
 810         int save_nmsrs;
 811         unsigned long *msr_bitmap;
 812
 813         vmx_load_host_state(vmx);
 814         save_nmsrs = 0;
 815 #ifdef CONFIG_X86_64
 816         if (is_long_mode(&vmx->vcpu)) {
 817                 int index;
 818
 819                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 820                 if (index >= 0)
 821                         move_msr_up(vmx, index, save_nmsrs++);
 822                 index = __find_msr_index(vmx, MSR_LSTAR);
 823                 if (index >= 0)
 824                         move_msr_up(vmx, index, save_nmsrs++);
 825                 index = __find_msr_index(vmx, MSR_CSTAR);
 826                 if (index >= 0)
 827                         move_msr_up(vmx, index, save_nmsrs++);
 828                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 829                 if (index >= 0)
 830                         move_msr_up(vmx, index, save_nmsrs++);
 831                 /*
 832                  * MSR_K6_STAR is only needed on long mode guests, and only
 833                  * if efer.sce is enabled.
 834                  */
 835                 index = __find_msr_index(vmx, MSR_K6_STAR);
 836                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 837                         move_msr_up(vmx, index, save_nmsrs++);
 838         }
 839 #endif
 840         vmx->save_nmsrs = save_nmsrs;
 841
 842 #ifdef CONFIG_X86_64
 843         vmx->msr_offset_kernel_gs_base =
 844                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 845 #endif
 846         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 847
 848         if (cpu_has_vmx_msr_bitmap()) {
 849                 if (is_long_mode(&vmx->vcpu))
 850                         msr_bitmap = vmx_msr_bitmap_longmode;
 851                 else
 852                         msr_bitmap = vmx_msr_bitmap_legacy;
 853
 854                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 855         }
 856 }
 857
 858 /*
 859  * reads and returns guest's timestamp counter "register"
 860  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 861  */
 862 static u64 guest_read_tsc(void)
 863 {
 864         u64 host_tsc, tsc_offset;
 865
 866         rdtscll(host_tsc);
 867         tsc_offset = vmcs_read64(TSC_OFFSET);
 868         return host_tsc + tsc_offset;
 869 }
 870
 871 /*
 872  * writes 'guest_tsc' into guest's timestamp counter "register"
 873  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 874  */
 875 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 876 {
 877         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 878 }
 879
 880 /*
 881  * Reads an msr value (of 'msr_index') into 'pdata'.
 882  * Returns 0 on success, non-0 otherwise.
 883  * Assumes vcpu_load() was already called.
 884  */
 885 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 886 {
 887         u64 data;
 888         struct kvm_msr_entry *msr;
 889
 890         if (!pdata) {
 891                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 892                 return -EINVAL;
 893         }
 894
 895         switch (msr_index) {
 896 #ifdef CONFIG_X86_64
 897         case MSR_FS_BASE:
 898                 data = vmcs_readl(GUEST_FS_BASE);
 899                 break;
 900         case MSR_GS_BASE:
 901                 data = vmcs_readl(GUEST_GS_BASE);
 902                 break;
 903         case MSR_EFER:
 904                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 905 #endif
 906         case MSR_IA32_TIME_STAMP_COUNTER:
 907                 data = guest_read_tsc();
 908                 break;
 909         case MSR_IA32_SYSENTER_CS:
 910                 data = vmcs_read32(GUEST_SYSENTER_CS);
 911                 break;
 912         case MSR_IA32_SYSENTER_EIP:
 913                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 914                 break;
 915         case MSR_IA32_SYSENTER_ESP:
 916                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 917                 break;
 918         default:
 919                 vmx_load_host_state(to_vmx(vcpu));
 920                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 921                 if (msr) {
 922                         data = msr->data;
 923                         break;
 924                 }
 925                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 926         }
 927
 928         *pdata = data;
 929         return 0;
 930 }
 931
 932 /*
 933  * Writes msr value into into the appropriate "register".
 934  * Returns 0 on success, non-0 otherwise.
 935  * Assumes vcpu_load() was already called.
 936  */
 937 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 938 {
 939         struct vcpu_vmx *vmx = to_vmx(vcpu);
 940         struct kvm_msr_entry *msr;
 941         u64 host_tsc;
 942         int ret = 0;
 943
 944         switch (msr_index) {
 945         case MSR_EFER:
 946                 vmx_load_host_state(vmx);
 947                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 948                 break;
 949 #ifdef CONFIG_X86_64
 950         case MSR_FS_BASE:
 951                 vmcs_writel(GUEST_FS_BASE, data);
 952                 break;
 953         case MSR_GS_BASE:
 954                 vmcs_writel(GUEST_GS_BASE, data);
 955                 break;
 956 #endif
 957         case MSR_IA32_SYSENTER_CS:
 958                 vmcs_write32(GUEST_SYSENTER_CS, data);
 959                 break;
 960         case MSR_IA32_SYSENTER_EIP:
 961                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 962                 break;
 963         case MSR_IA32_SYSENTER_ESP:
 964                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 965                 break;
 966         case MSR_IA32_TIME_STAMP_COUNTER:
 967                 rdtscll(host_tsc);
 968                 guest_write_tsc(data, host_tsc);
 969                 break;
 970         case MSR_P6_PERFCTR0:
 971         case MSR_P6_PERFCTR1:
 972         case MSR_P6_EVNTSEL0:
 973         case MSR_P6_EVNTSEL1:
 974                 /*
 975                  * Just discard all writes to the performance counters; this
 976                  * should keep both older linux and windows 64-bit guests
 977                  * happy
 978                  */
 979                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 980
 981                 break;
 982         case MSR_IA32_CR_PAT:
 983                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
 984                         vmcs_write64(GUEST_IA32_PAT, data);
 985                         vcpu->arch.pat = data;
 986                         break;
 987                 }
 988                 /* Otherwise falls through to kvm_set_msr_common */
 989         default:
 990                 vmx_load_host_state(vmx);
 991                 msr = find_msr_entry(vmx, msr_index);
 992                 if (msr) {
 993                         msr->data = data;
 994                         break;
 995                 }
 996                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 997         }
 998
 999         return ret;
1000 }
1001
1002 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1003 {
1004         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1005         switch (reg) {
1006         case VCPU_REGS_RSP:
1007                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1008                 break;
1009         case VCPU_REGS_RIP:
1010                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1011                 break;
1012         default:
1013                 break;
1014         }
1015 }
1016
1017 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1018 {
1019         int old_debug = vcpu->guest_debug;
1020         unsigned long flags;
1021
1022         vcpu->guest_debug = dbg->control;
1023         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1024                 vcpu->guest_debug = 0;
1025
1026         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1028         else
1029                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1030
1031         flags = vmcs_readl(GUEST_RFLAGS);
1032         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1033                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1034         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1035                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1036         vmcs_writel(GUEST_RFLAGS, flags);
1037
1038         update_exception_bitmap(vcpu);
1039
1040         return 0;
1041 }
1042
1043 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1044 {
1045         if (!vcpu->arch.interrupt.pending)
1046                 return -1;
1047         return vcpu->arch.interrupt.nr;
1048 }
1049
1050 static __init int cpu_has_kvm_support(void)
1051 {
1052         return cpu_has_vmx();
1053 }
1054
1055 static __init int vmx_disabled_by_bios(void)
1056 {
1057         u64 msr;
1058
1059         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1060         return (msr & (FEATURE_CONTROL_LOCKED |
1061                        FEATURE_CONTROL_VMXON_ENABLED))
1062             == FEATURE_CONTROL_LOCKED;
1063         /* locked but not enabled */
1064 }
1065
1066 static void hardware_enable(void *garbage)
1067 {
1068         int cpu = raw_smp_processor_id();
1069         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1070         u64 old;
1071
1072         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1073         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1074         if ((old & (FEATURE_CONTROL_LOCKED |
1075                     FEATURE_CONTROL_VMXON_ENABLED))
1076             != (FEATURE_CONTROL_LOCKED |
1077                 FEATURE_CONTROL_VMXON_ENABLED))
1078                 /* enable and lock */
1079                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1080                        FEATURE_CONTROL_LOCKED |
1081                        FEATURE_CONTROL_VMXON_ENABLED);
1082         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1083         asm volatile (ASM_VMX_VMXON_RAX
1084                       : : "a"(&phys_addr), "m"(phys_addr)
1085                       : "memory", "cc");
1086 }
1087
1088 static void vmclear_local_vcpus(void)
1089 {
1090         int cpu = raw_smp_processor_id();
1091         struct vcpu_vmx *vmx, *n;
1092
1093         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1094                                  local_vcpus_link)
1095                 __vcpu_clear(vmx);
1096 }
1097
1098
1099 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1100  * tricks.
1101  */
1102 static void kvm_cpu_vmxoff(void)
1103 {
1104         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1105         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1106 }
1107
1108 static void hardware_disable(void *garbage)
1109 {
1110         vmclear_local_vcpus();
1111         kvm_cpu_vmxoff();
1112 }
1113
1114 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1115                                       u32 msr, u32 *result)
1116 {
1117         u32 vmx_msr_low, vmx_msr_high;
1118         u32 ctl = ctl_min | ctl_opt;
1119
1120         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1121
1122         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1123         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1124
1125         /* Ensure minimum (required) set of control bits are supported. */
1126         if (ctl_min & ~ctl)
1127                 return -EIO;
1128
1129         *result = ctl;
1130         return 0;
1131 }
1132
1133 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1134 {
1135         u32 vmx_msr_low, vmx_msr_high;
1136         u32 min, opt, min2, opt2;
1137         u32 _pin_based_exec_control = 0;
1138         u32 _cpu_based_exec_control = 0;
1139         u32 _cpu_based_2nd_exec_control = 0;
1140         u32 _vmexit_control = 0;
1141         u32 _vmentry_control = 0;
1142
1143         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1144         opt = PIN_BASED_VIRTUAL_NMIS;
1145         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1146                                 &_pin_based_exec_control) < 0)
1147                 return -EIO;
1148
1149         min = CPU_BASED_HLT_EXITING |
1150 #ifdef CONFIG_X86_64
1151               CPU_BASED_CR8_LOAD_EXITING |
1152               CPU_BASED_CR8_STORE_EXITING |
1153 #endif
1154               CPU_BASED_CR3_LOAD_EXITING |
1155               CPU_BASED_CR3_STORE_EXITING |
1156               CPU_BASED_USE_IO_BITMAPS |
1157               CPU_BASED_MOV_DR_EXITING |
1158               CPU_BASED_USE_TSC_OFFSETING |
1159               CPU_BASED_INVLPG_EXITING;
1160         opt = CPU_BASED_TPR_SHADOW |
1161               CPU_BASED_USE_MSR_BITMAPS |
1162               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1163         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1164                                 &_cpu_based_exec_control) < 0)
1165                 return -EIO;
1166 #ifdef CONFIG_X86_64
1167         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1168                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1169                                            ~CPU_BASED_CR8_STORE_EXITING;
1170 #endif
1171         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1172                 min2 = 0;
1173                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1174                         SECONDARY_EXEC_WBINVD_EXITING |
1175                         SECONDARY_EXEC_ENABLE_VPID |
1176                         SECONDARY_EXEC_ENABLE_EPT;
1177                 if (adjust_vmx_controls(min2, opt2,
1178                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1179                                         &_cpu_based_2nd_exec_control) < 0)
1180                         return -EIO;
1181         }
1182 #ifndef CONFIG_X86_64
1183         if (!(_cpu_based_2nd_exec_control &
1184                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1185                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1186 #endif
1187         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1188                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1189                    enabled */
1190                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1191                          CPU_BASED_CR3_STORE_EXITING |
1192                          CPU_BASED_INVLPG_EXITING);
1193                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1194                                         &_cpu_based_exec_control) < 0)
1195                         return -EIO;
1196                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1197                       vmx_capability.ept, vmx_capability.vpid);
1198         }
1199
1200         if (!cpu_has_vmx_vpid())
1201                 enable_vpid = 0;
1202
1203         if (!cpu_has_vmx_ept())
1204                 enable_ept = 0;
1205
1206         min = 0;
1207 #ifdef CONFIG_X86_64
1208         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1209 #endif
1210         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1211         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1212                                 &_vmexit_control) < 0)
1213                 return -EIO;
1214
1215         min = 0;
1216         opt = VM_ENTRY_LOAD_IA32_PAT;
1217         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1218                                 &_vmentry_control) < 0)
1219                 return -EIO;
1220
1221         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1222
1223         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1224         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1225                 return -EIO;
1226
1227 #ifdef CONFIG_X86_64
1228         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1229         if (vmx_msr_high & (1u<<16))
1230                 return -EIO;
1231 #endif
1232
1233         /* Require Write-Back (WB) memory type for VMCS accesses. */
1234         if (((vmx_msr_high >> 18) & 15) != 6)
1235                 return -EIO;
1236
1237         vmcs_conf->size = vmx_msr_high & 0x1fff;
1238         vmcs_conf->order = get_order(vmcs_config.size);
1239         vmcs_conf->revision_id = vmx_msr_low;
1240
1241         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1242         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1243         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1244         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1245         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1246
1247         return 0;
1248 }
1249
1250 static struct vmcs *alloc_vmcs_cpu(int cpu)
1251 {
1252         int node = cpu_to_node(cpu);
1253         struct page *pages;
1254         struct vmcs *vmcs;
1255
1256         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1257         if (!pages)
1258                 return NULL;
1259         vmcs = page_address(pages);
1260         memset(vmcs, 0, vmcs_config.size);
1261         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1262         return vmcs;
1263 }
1264
1265 static struct vmcs *alloc_vmcs(void)
1266 {
1267         return alloc_vmcs_cpu(raw_smp_processor_id());
1268 }
1269
1270 static void free_vmcs(struct vmcs *vmcs)
1271 {
1272         free_pages((unsigned long)vmcs, vmcs_config.order);
1273 }
1274
1275 static void free_kvm_area(void)
1276 {
1277         int cpu;
1278
1279         for_each_online_cpu(cpu)
1280                 free_vmcs(per_cpu(vmxarea, cpu));
1281 }
1282
1283 static __init int alloc_kvm_area(void)
1284 {
1285         int cpu;
1286
1287         for_each_online_cpu(cpu) {
1288                 struct vmcs *vmcs;
1289
1290                 vmcs = alloc_vmcs_cpu(cpu);
1291                 if (!vmcs) {
1292                         free_kvm_area();
1293                         return -ENOMEM;
1294                 }
1295
1296                 per_cpu(vmxarea, cpu) = vmcs;
1297         }
1298         return 0;
1299 }
1300
1301 static __init int hardware_setup(void)
1302 {
1303         if (setup_vmcs_config(&vmcs_config) < 0)
1304                 return -EIO;
1305
1306         if (boot_cpu_has(X86_FEATURE_NX))
1307                 kvm_enable_efer_bits(EFER_NX);
1308
1309         return alloc_kvm_area();
1310 }
1311
1312 static __exit void hardware_unsetup(void)
1313 {
1314         free_kvm_area();
1315 }
1316
1317 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1318 {
1319         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1320
1321         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1322                 vmcs_write16(sf->selector, save->selector);
1323                 vmcs_writel(sf->base, save->base);
1324                 vmcs_write32(sf->limit, save->limit);
1325                 vmcs_write32(sf->ar_bytes, save->ar);
1326         } else {
1327                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1328                         << AR_DPL_SHIFT;
1329                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1330         }
1331 }
1332
1333 static void enter_pmode(struct kvm_vcpu *vcpu)
1334 {
1335         unsigned long flags;
1336         struct vcpu_vmx *vmx = to_vmx(vcpu);
1337
1338         vmx->emulation_required = 1;
1339         vcpu->arch.rmode.active = 0;
1340
1341         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1342         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1343         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1344
1345         flags = vmcs_readl(GUEST_RFLAGS);
1346         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1347         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1348         vmcs_writel(GUEST_RFLAGS, flags);
1349
1350         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1351                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1352
1353         update_exception_bitmap(vcpu);
1354
1355         if (emulate_invalid_guest_state)
1356                 return;
1357
1358         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1359         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1360         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1361         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1362
1363         vmcs_write16(GUEST_SS_SELECTOR, 0);
1364         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1365
1366         vmcs_write16(GUEST_CS_SELECTOR,
1367                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1368         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1369 }
1370
1371 static gva_t rmode_tss_base(struct kvm *kvm)
1372 {
1373         if (!kvm->arch.tss_addr) {
1374                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1375                                  kvm->memslots[0].npages - 3;
1376                 return base_gfn << PAGE_SHIFT;
1377         }
1378         return kvm->arch.tss_addr;
1379 }
1380
1381 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1382 {
1383         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1384
1385         save->selector = vmcs_read16(sf->selector);
1386         save->base = vmcs_readl(sf->base);
1387         save->limit = vmcs_read32(sf->limit);
1388         save->ar = vmcs_read32(sf->ar_bytes);
1389         vmcs_write16(sf->selector, save->base >> 4);
1390         vmcs_write32(sf->base, save->base & 0xfffff);
1391         vmcs_write32(sf->limit, 0xffff);
1392         vmcs_write32(sf->ar_bytes, 0xf3);
1393 }
1394
1395 static void enter_rmode(struct kvm_vcpu *vcpu)
1396 {
1397         unsigned long flags;
1398         struct vcpu_vmx *vmx = to_vmx(vcpu);
1399
1400         vmx->emulation_required = 1;
1401         vcpu->arch.rmode.active = 1;
1402
1403         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1404         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1405
1406         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1407         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1408
1409         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1410         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1411
1412         flags = vmcs_readl(GUEST_RFLAGS);
1413         vcpu->arch.rmode.save_iopl
1414                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1415
1416         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1417
1418         vmcs_writel(GUEST_RFLAGS, flags);
1419         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1420         update_exception_bitmap(vcpu);
1421
1422         if (emulate_invalid_guest_state)
1423                 goto continue_rmode;
1424
1425         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1426         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1427         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1428
1429         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1430         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1431         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1432                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1433         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1434
1435         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1436         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1437         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1438         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1439
1440 continue_rmode:
1441         kvm_mmu_reset_context(vcpu);
1442         init_rmode(vcpu->kvm);
1443 }
1444
1445 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1446 {
1447         struct vcpu_vmx *vmx = to_vmx(vcpu);
1448         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1449
1450         vcpu->arch.shadow_efer = efer;
1451         if (!msr)
1452                 return;
1453         if (efer & EFER_LMA) {
1454                 vmcs_write32(VM_ENTRY_CONTROLS,
1455                              vmcs_read32(VM_ENTRY_CONTROLS) |
1456                              VM_ENTRY_IA32E_MODE);
1457                 msr->data = efer;
1458         } else {
1459                 vmcs_write32(VM_ENTRY_CONTROLS,
1460                              vmcs_read32(VM_ENTRY_CONTROLS) &
1461                              ~VM_ENTRY_IA32E_MODE);
1462
1463                 msr->data = efer & ~EFER_LME;
1464         }
1465         setup_msrs(vmx);
1466 }
1467
1468 #ifdef CONFIG_X86_64
1469
1470 static void enter_lmode(struct kvm_vcpu *vcpu)
1471 {
1472         u32 guest_tr_ar;
1473
1474         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1475         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1476                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1477                        __func__);
1478                 vmcs_write32(GUEST_TR_AR_BYTES,
1479                              (guest_tr_ar & ~AR_TYPE_MASK)
1480                              | AR_TYPE_BUSY_64_TSS);
1481         }
1482         vcpu->arch.shadow_efer |= EFER_LMA;
1483         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1484 }
1485
1486 static void exit_lmode(struct kvm_vcpu *vcpu)
1487 {
1488         vcpu->arch.shadow_efer &= ~EFER_LMA;
1489
1490         vmcs_write32(VM_ENTRY_CONTROLS,
1491                      vmcs_read32(VM_ENTRY_CONTROLS)
1492                      & ~VM_ENTRY_IA32E_MODE);
1493 }
1494
1495 #endif
1496
1497 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1498 {
1499         vpid_sync_vcpu_all(to_vmx(vcpu));
1500         if (enable_ept)
1501                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1502 }
1503
1504 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1505 {
1506         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1507         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1508 }
1509
1510 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1511 {
1512         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1513                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1514                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1515                         return;
1516                 }
1517                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1518                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1519                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1520                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1521         }
1522 }
1523
1524 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1525
1526 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1527                                         unsigned long cr0,
1528                                         struct kvm_vcpu *vcpu)
1529 {
1530         if (!(cr0 & X86_CR0_PG)) {
1531                 /* From paging/starting to nonpaging */
1532                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1533                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1534                              (CPU_BASED_CR3_LOAD_EXITING |
1535                               CPU_BASED_CR3_STORE_EXITING));
1536                 vcpu->arch.cr0 = cr0;
1537                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1538                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1539                 *hw_cr0 &= ~X86_CR0_WP;
1540         } else if (!is_paging(vcpu)) {
1541                 /* From nonpaging to paging */
1542                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1543                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1544                              ~(CPU_BASED_CR3_LOAD_EXITING |
1545                                CPU_BASED_CR3_STORE_EXITING));
1546                 vcpu->arch.cr0 = cr0;
1547                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1548                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1549                         *hw_cr0 &= ~X86_CR0_WP;
1550         }
1551 }
1552
1553 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1554                                         struct kvm_vcpu *vcpu)
1555 {
1556         if (!is_paging(vcpu)) {
1557                 *hw_cr4 &= ~X86_CR4_PAE;
1558                 *hw_cr4 |= X86_CR4_PSE;
1559         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1560                 *hw_cr4 &= ~X86_CR4_PAE;
1561 }
1562
1563 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1564 {
1565         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1566                                 KVM_VM_CR0_ALWAYS_ON;
1567
1568         vmx_fpu_deactivate(vcpu);
1569
1570         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1571                 enter_pmode(vcpu);
1572
1573         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1574                 enter_rmode(vcpu);
1575
1576 #ifdef CONFIG_X86_64
1577         if (vcpu->arch.shadow_efer & EFER_LME) {
1578                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1579                         enter_lmode(vcpu);
1580                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1581                         exit_lmode(vcpu);
1582         }
1583 #endif
1584
1585         if (enable_ept)
1586                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1587
1588         vmcs_writel(CR0_READ_SHADOW, cr0);
1589         vmcs_writel(GUEST_CR0, hw_cr0);
1590         vcpu->arch.cr0 = cr0;
1591
1592         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1593                 vmx_fpu_activate(vcpu);
1594 }
1595
1596 static u64 construct_eptp(unsigned long root_hpa)
1597 {
1598         u64 eptp;
1599
1600         /* TODO write the value reading from MSR */
1601         eptp = VMX_EPT_DEFAULT_MT |
1602                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1603         eptp |= (root_hpa & PAGE_MASK);
1604
1605         return eptp;
1606 }
1607
1608 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1609 {
1610         unsigned long guest_cr3;
1611         u64 eptp;
1612
1613         guest_cr3 = cr3;
1614         if (enable_ept) {
1615                 eptp = construct_eptp(cr3);
1616                 vmcs_write64(EPT_POINTER, eptp);
1617                 ept_sync_context(eptp);
1618                 ept_load_pdptrs(vcpu);
1619                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1620                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1621         }
1622
1623         vmx_flush_tlb(vcpu);
1624         vmcs_writel(GUEST_CR3, guest_cr3);
1625         if (vcpu->arch.cr0 & X86_CR0_PE)
1626                 vmx_fpu_deactivate(vcpu);
1627 }
1628
1629 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1630 {
1631         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1632                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1633
1634         vcpu->arch.cr4 = cr4;
1635         if (enable_ept)
1636                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1637
1638         vmcs_writel(CR4_READ_SHADOW, cr4);
1639         vmcs_writel(GUEST_CR4, hw_cr4);
1640 }
1641
1642 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1643 {
1644         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1645
1646         return vmcs_readl(sf->base);
1647 }
1648
1649 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1650                             struct kvm_segment *var, int seg)
1651 {
1652         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1653         u32 ar;
1654
1655         var->base = vmcs_readl(sf->base);
1656         var->limit = vmcs_read32(sf->limit);
1657         var->selector = vmcs_read16(sf->selector);
1658         ar = vmcs_read32(sf->ar_bytes);
1659         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1660                 ar = 0;
1661         var->type = ar & 15;
1662         var->s = (ar >> 4) & 1;
1663         var->dpl = (ar >> 5) & 3;
1664         var->present = (ar >> 7) & 1;
1665         var->avl = (ar >> 12) & 1;
1666         var->l = (ar >> 13) & 1;
1667         var->db = (ar >> 14) & 1;
1668         var->g = (ar >> 15) & 1;
1669         var->unusable = (ar >> 16) & 1;
1670 }
1671
1672 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1673 {
1674         struct kvm_segment kvm_seg;
1675
1676         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1677                 return 0;
1678
1679         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1680                 return 3;
1681
1682         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1683         return kvm_seg.selector & 3;
1684 }
1685
1686 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1687 {
1688         u32 ar;
1689
1690         if (var->unusable)
1691                 ar = 1 << 16;
1692         else {
1693                 ar = var->type & 15;
1694                 ar |= (var->s & 1) << 4;
1695                 ar |= (var->dpl & 3) << 5;
1696                 ar |= (var->present & 1) << 7;
1697                 ar |= (var->avl & 1) << 12;
1698                 ar |= (var->l & 1) << 13;
1699                 ar |= (var->db & 1) << 14;
1700                 ar |= (var->g & 1) << 15;
1701         }
1702         if (ar == 0) /* a 0 value means unusable */
1703                 ar = AR_UNUSABLE_MASK;
1704
1705         return ar;
1706 }
1707
1708 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1709                             struct kvm_segment *var, int seg)
1710 {
1711         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1712         u32 ar;
1713
1714         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1715                 vcpu->arch.rmode.tr.selector = var->selector;
1716                 vcpu->arch.rmode.tr.base = var->base;
1717                 vcpu->arch.rmode.tr.limit = var->limit;
1718                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1719                 return;
1720         }
1721         vmcs_writel(sf->base, var->base);
1722         vmcs_write32(sf->limit, var->limit);
1723         vmcs_write16(sf->selector, var->selector);
1724         if (vcpu->arch.rmode.active && var->s) {
1725                 /*
1726                  * Hack real-mode segments into vm86 compatibility.
1727                  */
1728                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1729                         vmcs_writel(sf->base, 0xf0000);
1730                 ar = 0xf3;
1731         } else
1732                 ar = vmx_segment_access_rights(var);
1733         vmcs_write32(sf->ar_bytes, ar);
1734 }
1735
1736 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1737 {
1738         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1739
1740         *db = (ar >> 14) & 1;
1741         *l = (ar >> 13) & 1;
1742 }
1743
1744 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1745 {
1746         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1747         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1748 }
1749
1750 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1751 {
1752         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1753         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1754 }
1755
1756 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1757 {
1758         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1759         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1760 }
1761
1762 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1763 {
1764         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1765         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1766 }
1767
1768 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1769 {
1770         struct kvm_segment var;
1771         u32 ar;
1772
1773         vmx_get_segment(vcpu, &var, seg);
1774         ar = vmx_segment_access_rights(&var);
1775
1776         if (var.base != (var.selector << 4))
1777                 return false;
1778         if (var.limit != 0xffff)
1779                 return false;
1780         if (ar != 0xf3)
1781                 return false;
1782
1783         return true;
1784 }
1785
1786 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1787 {
1788         struct kvm_segment cs;
1789         unsigned int cs_rpl;
1790
1791         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1792         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1793
1794         if (cs.unusable)
1795                 return false;
1796         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1797                 return false;
1798         if (!cs.s)
1799                 return false;
1800         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1801                 if (cs.dpl > cs_rpl)
1802                         return false;
1803         } else {
1804                 if (cs.dpl != cs_rpl)
1805                         return false;
1806         }
1807         if (!cs.present)
1808                 return false;
1809
1810         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1811         return true;
1812 }
1813
1814 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1815 {
1816         struct kvm_segment ss;
1817         unsigned int ss_rpl;
1818
1819         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1820         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1821
1822         if (ss.unusable)
1823                 return true;
1824         if (ss.type != 3 && ss.type != 7)
1825                 return false;
1826         if (!ss.s)
1827                 return false;
1828         if (ss.dpl != ss_rpl) /* DPL != RPL */
1829                 return false;
1830         if (!ss.present)
1831                 return false;
1832
1833         return true;
1834 }
1835
1836 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1837 {
1838         struct kvm_segment var;
1839         unsigned int rpl;
1840
1841         vmx_get_segment(vcpu, &var, seg);
1842         rpl = var.selector & SELECTOR_RPL_MASK;
1843
1844         if (var.unusable)
1845                 return true;
1846         if (!var.s)
1847                 return false;
1848         if (!var.present)
1849                 return false;
1850         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1851                 if (var.dpl < rpl) /* DPL < RPL */
1852                         return false;
1853         }
1854
1855         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1856          * rights flags
1857          */
1858         return true;
1859 }
1860
1861 static bool tr_valid(struct kvm_vcpu *vcpu)
1862 {
1863         struct kvm_segment tr;
1864
1865         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1866
1867         if (tr.unusable)
1868                 return false;
1869         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1870                 return false;
1871         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1872                 return false;
1873         if (!tr.present)
1874                 return false;
1875
1876         return true;
1877 }
1878
1879 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1880 {
1881         struct kvm_segment ldtr;
1882
1883         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1884
1885         if (ldtr.unusable)
1886                 return true;
1887         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1888                 return false;
1889         if (ldtr.type != 2)
1890                 return false;
1891         if (!ldtr.present)
1892                 return false;
1893
1894         return true;
1895 }
1896
1897 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1898 {
1899         struct kvm_segment cs, ss;
1900
1901         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1902         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1903
1904         return ((cs.selector & SELECTOR_RPL_MASK) ==
1905                  (ss.selector & SELECTOR_RPL_MASK));
1906 }
1907
1908 /*
1909  * Check if guest state is valid. Returns true if valid, false if
1910  * not.
1911  * We assume that registers are always usable
1912  */
1913 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1914 {
1915         /* real mode guest state checks */
1916         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1917                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1918                         return false;
1919                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1920                         return false;
1921                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1922                         return false;
1923                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1924                         return false;
1925                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1926                         return false;
1927                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1928                         return false;
1929         } else {
1930         /* protected mode guest state checks */
1931                 if (!cs_ss_rpl_check(vcpu))
1932                         return false;
1933                 if (!code_segment_valid(vcpu))
1934                         return false;
1935                 if (!stack_segment_valid(vcpu))
1936                         return false;
1937                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1938                         return false;
1939                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1940                         return false;
1941                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1942                         return false;
1943                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1944                         return false;
1945                 if (!tr_valid(vcpu))
1946                         return false;
1947                 if (!ldtr_valid(vcpu))
1948                         return false;
1949         }
1950         /* TODO:
1951          * - Add checks on RIP
1952          * - Add checks on RFLAGS
1953          */
1954
1955         return true;
1956 }
1957
1958 static int init_rmode_tss(struct kvm *kvm)
1959 {
1960         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1961         u16 data = 0;
1962         int ret = 0;
1963         int r;
1964
1965         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1966         if (r < 0)
1967                 goto out;
1968         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1969         r = kvm_write_guest_page(kvm, fn++, &data,
1970                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1971         if (r < 0)
1972                 goto out;
1973         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1974         if (r < 0)
1975                 goto out;
1976         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1977         if (r < 0)
1978                 goto out;
1979         data = ~0;
1980         r = kvm_write_guest_page(kvm, fn, &data,
1981                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1982                                  sizeof(u8));
1983         if (r < 0)
1984                 goto out;
1985
1986         ret = 1;
1987 out:
1988         return ret;
1989 }
1990
1991 static int init_rmode_identity_map(struct kvm *kvm)
1992 {
1993         int i, r, ret;
1994         pfn_t identity_map_pfn;
1995         u32 tmp;
1996
1997         if (!enable_ept)
1998                 return 1;
1999         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2000                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2001                         "haven't been allocated!\n");
2002                 return 0;
2003         }
2004         if (likely(kvm->arch.ept_identity_pagetable_done))
2005                 return 1;
2006         ret = 0;
2007         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2008         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2009         if (r < 0)
2010                 goto out;
2011         /* Set up identity-mapping pagetable for EPT in real mode */
2012         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2013                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2014                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2015                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2016                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2017                 if (r < 0)
2018                         goto out;
2019         }
2020         kvm->arch.ept_identity_pagetable_done = true;
2021         ret = 1;
2022 out:
2023         return ret;
2024 }
2025
2026 static void seg_setup(int seg)
2027 {
2028         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2029
2030         vmcs_write16(sf->selector, 0);
2031         vmcs_writel(sf->base, 0);
2032         vmcs_write32(sf->limit, 0xffff);
2033         vmcs_write32(sf->ar_bytes, 0xf3);
2034 }
2035
2036 static int alloc_apic_access_page(struct kvm *kvm)
2037 {
2038         struct kvm_userspace_memory_region kvm_userspace_mem;
2039         int r = 0;
2040
2041         down_write(&kvm->slots_lock);
2042         if (kvm->arch.apic_access_page)
2043                 goto out;
2044         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2045         kvm_userspace_mem.flags = 0;
2046         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2047         kvm_userspace_mem.memory_size = PAGE_SIZE;
2048         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2049         if (r)
2050                 goto out;
2051
2052         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2053 out:
2054         up_write(&kvm->slots_lock);
2055         return r;
2056 }
2057
2058 static int alloc_identity_pagetable(struct kvm *kvm)
2059 {
2060         struct kvm_userspace_memory_region kvm_userspace_mem;
2061         int r = 0;
2062
2063         down_write(&kvm->slots_lock);
2064         if (kvm->arch.ept_identity_pagetable)
2065                 goto out;
2066         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2067         kvm_userspace_mem.flags = 0;
2068         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2069         kvm_userspace_mem.memory_size = PAGE_SIZE;
2070         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2071         if (r)
2072                 goto out;
2073
2074         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2075                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2076 out:
2077         up_write(&kvm->slots_lock);
2078         return r;
2079 }
2080
2081 static void allocate_vpid(struct vcpu_vmx *vmx)
2082 {
2083         int vpid;
2084
2085         vmx->vpid = 0;
2086         if (!enable_vpid)
2087                 return;
2088         spin_lock(&vmx_vpid_lock);
2089         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2090         if (vpid < VMX_NR_VPIDS) {
2091                 vmx->vpid = vpid;
2092                 __set_bit(vpid, vmx_vpid_bitmap);
2093         }
2094         spin_unlock(&vmx_vpid_lock);
2095 }
2096
2097 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2098 {
2099         int f = sizeof(unsigned long);
2100
2101         if (!cpu_has_vmx_msr_bitmap())
2102                 return;
2103
2104         /*
2105          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2106          * have the write-low and read-high bitmap offsets the wrong way round.
2107          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2108          */
2109         if (msr <= 0x1fff) {
2110                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2111                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2112         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2113                 msr &= 0x1fff;
2114                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2115                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2116         }
2117 }
2118
2119 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2120 {
2121         if (!longmode_only)
2122                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2123         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2124 }
2125
2126 /*
2127  * Sets up the vmcs for emulated real mode.
2128  */
2129 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2130 {
2131         u32 host_sysenter_cs, msr_low, msr_high;
2132         u32 junk;
2133         u64 host_pat, tsc_this, tsc_base;
2134         unsigned long a;
2135         struct descriptor_table dt;
2136         int i;
2137         unsigned long kvm_vmx_return;
2138         u32 exec_control;
2139
2140         /* I/O */
2141         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2142         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2143
2144         if (cpu_has_vmx_msr_bitmap())
2145                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2146
2147         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2148
2149         /* Control */
2150         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2151                 vmcs_config.pin_based_exec_ctrl);
2152
2153         exec_control = vmcs_config.cpu_based_exec_ctrl;
2154         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2155                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2156 #ifdef CONFIG_X86_64
2157                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2158                                 CPU_BASED_CR8_LOAD_EXITING;
2159 #endif
2160         }
2161         if (!enable_ept)
2162                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2163                                 CPU_BASED_CR3_LOAD_EXITING  |
2164                                 CPU_BASED_INVLPG_EXITING;
2165         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2166
2167         if (cpu_has_secondary_exec_ctrls()) {
2168                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2169                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2170                         exec_control &=
2171                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2172                 if (vmx->vpid == 0)
2173                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2174                 if (!enable_ept)
2175                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2176                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2177         }
2178
2179         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2180         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2181         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2182
2183         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2184         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2185         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2186
2187         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2188         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2189         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2190         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2191         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2192         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2193 #ifdef CONFIG_X86_64
2194         rdmsrl(MSR_FS_BASE, a);
2195         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2196         rdmsrl(MSR_GS_BASE, a);
2197         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2198 #else
2199         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2200         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2201 #endif
2202
2203         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2204
2205         kvm_get_idt(&dt);
2206         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2207
2208         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2209         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2210         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2211         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2212         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2213
2214         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2215         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2216         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2217         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2218         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2219         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2220
2221         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2222                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2223                 host_pat = msr_low | ((u64) msr_high << 32);
2224                 vmcs_write64(HOST_IA32_PAT, host_pat);
2225         }
2226         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2227                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2228                 host_pat = msr_low | ((u64) msr_high << 32);
2229                 /* Write the default value follow host pat */
2230                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2231                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2232                 vmx->vcpu.arch.pat = host_pat;
2233         }
2234
2235         for (i = 0; i < NR_VMX_MSR; ++i) {
2236                 u32 index = vmx_msr_index[i];
2237                 u32 data_low, data_high;
2238                 u64 data;
2239                 int j = vmx->nmsrs;
2240
2241                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2242                         continue;
2243                 if (wrmsr_safe(index, data_low, data_high) < 0)
2244                         continue;
2245                 data = data_low | ((u64)data_high << 32);
2246                 vmx->host_msrs[j].index = index;
2247                 vmx->host_msrs[j].reserved = 0;
2248                 vmx->host_msrs[j].data = data;
2249                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2250                 ++vmx->nmsrs;
2251         }
2252
2253         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2254
2255         /* 22.2.1, 20.8.1 */
2256         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2257
2258         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2259         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2260
2261         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2262         rdtscll(tsc_this);
2263         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2264                 tsc_base = tsc_this;
2265
2266         guest_write_tsc(0, tsc_base);
2267
2268         return 0;
2269 }
2270
2271 static int init_rmode(struct kvm *kvm)
2272 {
2273         if (!init_rmode_tss(kvm))
2274                 return 0;
2275         if (!init_rmode_identity_map(kvm))
2276                 return 0;
2277         return 1;
2278 }
2279
2280 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2281 {
2282         struct vcpu_vmx *vmx = to_vmx(vcpu);
2283         u64 msr;
2284         int ret;
2285
2286         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2287         down_read(&vcpu->kvm->slots_lock);
2288         if (!init_rmode(vmx->vcpu.kvm)) {
2289                 ret = -ENOMEM;
2290                 goto out;
2291         }
2292
2293         vmx->vcpu.arch.rmode.active = 0;
2294
2295         vmx->soft_vnmi_blocked = 0;
2296
2297         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2298         kvm_set_cr8(&vmx->vcpu, 0);
2299         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2300         if (vmx->vcpu.vcpu_id == 0)
2301                 msr |= MSR_IA32_APICBASE_BSP;
2302         kvm_set_apic_base(&vmx->vcpu, msr);
2303
2304         fx_init(&vmx->vcpu);
2305
2306         seg_setup(VCPU_SREG_CS);
2307         /*
2308          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2309          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2310          */
2311         if (vmx->vcpu.vcpu_id == 0) {
2312                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2313                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2314         } else {
2315                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2316                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2317         }
2318
2319         seg_setup(VCPU_SREG_DS);
2320         seg_setup(VCPU_SREG_ES);
2321         seg_setup(VCPU_SREG_FS);
2322         seg_setup(VCPU_SREG_GS);
2323         seg_setup(VCPU_SREG_SS);
2324
2325         vmcs_write16(GUEST_TR_SELECTOR, 0);
2326         vmcs_writel(GUEST_TR_BASE, 0);
2327         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2328         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2329
2330         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2331         vmcs_writel(GUEST_LDTR_BASE, 0);
2332         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2333         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2334
2335         vmcs_write32(GUEST_SYSENTER_CS, 0);
2336         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2337         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2338
2339         vmcs_writel(GUEST_RFLAGS, 0x02);
2340         if (vmx->vcpu.vcpu_id == 0)
2341                 kvm_rip_write(vcpu, 0xfff0);
2342         else
2343                 kvm_rip_write(vcpu, 0);
2344         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2345
2346         vmcs_writel(GUEST_DR7, 0x400);
2347
2348         vmcs_writel(GUEST_GDTR_BASE, 0);
2349         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2350
2351         vmcs_writel(GUEST_IDTR_BASE, 0);
2352         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2353
2354         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2355         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2356         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2357
2358         /* Special registers */
2359         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2360
2361         setup_msrs(vmx);
2362
2363         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2364
2365         if (cpu_has_vmx_tpr_shadow()) {
2366                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2367                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2368                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2369                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2370                 vmcs_write32(TPR_THRESHOLD, 0);
2371         }
2372
2373         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2374                 vmcs_write64(APIC_ACCESS_ADDR,
2375                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2376
2377         if (vmx->vpid != 0)
2378                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2379
2380         vmx->vcpu.arch.cr0 = 0x60000010;
2381         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2382         vmx_set_cr4(&vmx->vcpu, 0);
2383         vmx_set_efer(&vmx->vcpu, 0);
2384         vmx_fpu_activate(&vmx->vcpu);
2385         update_exception_bitmap(&vmx->vcpu);
2386
2387         vpid_sync_vcpu_all(vmx);
2388
2389         ret = 0;
2390
2391         /* HACK: Don't enable emulation on guest boot/reset */
2392         vmx->emulation_required = 0;
2393
2394 out:
2395         up_read(&vcpu->kvm->slots_lock);
2396         return ret;
2397 }
2398
2399 static void enable_irq_window(struct kvm_vcpu *vcpu)
2400 {
2401         u32 cpu_based_vm_exec_control;
2402
2403         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2404         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2405         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2406 }
2407
2408 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2409 {
2410         u32 cpu_based_vm_exec_control;
2411
2412         if (!cpu_has_virtual_nmis()) {
2413                 enable_irq_window(vcpu);
2414                 return;
2415         }
2416
2417         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2418         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2419         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2420 }
2421
2422 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2423 {
2424         struct vcpu_vmx *vmx = to_vmx(vcpu);
2425
2426         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2427
2428         ++vcpu->stat.irq_injections;
2429         if (vcpu->arch.rmode.active) {
2430                 vmx->rmode.irq.pending = true;
2431                 vmx->rmode.irq.vector = irq;
2432                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2433                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2434                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2435                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2436                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2437                 return;
2438         }
2439         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2440                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2441 }
2442
2443 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2444 {
2445         struct vcpu_vmx *vmx = to_vmx(vcpu);
2446
2447         if (!cpu_has_virtual_nmis()) {
2448                 /*
2449                  * Tracking the NMI-blocked state in software is built upon
2450                  * finding the next open IRQ window. This, in turn, depends on
2451                  * well-behaving guests: They have to keep IRQs disabled at
2452                  * least as long as the NMI handler runs. Otherwise we may
2453                  * cause NMI nesting, maybe breaking the guest. But as this is
2454                  * highly unlikely, we can live with the residual risk.
2455                  */
2456                 vmx->soft_vnmi_blocked = 1;
2457                 vmx->vnmi_blocked_time = 0;
2458         }
2459
2460         ++vcpu->stat.nmi_injections;
2461         if (vcpu->arch.rmode.active) {
2462                 vmx->rmode.irq.pending = true;
2463                 vmx->rmode.irq.vector = NMI_VECTOR;
2464                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2465                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2466                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2467                              INTR_INFO_VALID_MASK);
2468                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2469                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2470                 return;
2471         }
2472         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2473                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2474 }
2475
2476 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2477 {
2478         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2479
2480         vcpu->arch.nmi_window_open =
2481                 !(guest_intr & (GUEST_INTR_STATE_STI |
2482                                 GUEST_INTR_STATE_MOV_SS |
2483                                 GUEST_INTR_STATE_NMI));
2484         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2485                 vcpu->arch.nmi_window_open = 0;
2486
2487         vcpu->arch.interrupt_window_open =
2488                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2489                  !(guest_intr & (GUEST_INTR_STATE_STI |
2490                                  GUEST_INTR_STATE_MOV_SS)));
2491 }
2492
2493 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2494 {
2495         vmx_update_window_states(vcpu);
2496         return vcpu->arch.interrupt_window_open;
2497 }
2498
2499 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2500                                        struct kvm_run *kvm_run)
2501 {
2502         vmx_update_window_states(vcpu);
2503
2504         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2505                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2506                                 GUEST_INTR_STATE_STI |
2507                                 GUEST_INTR_STATE_MOV_SS);
2508
2509         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2510                 if (vcpu->arch.interrupt.pending) {
2511                         enable_nmi_window(vcpu);
2512                 } else if (vcpu->arch.nmi_window_open) {
2513                         vcpu->arch.nmi_pending = false;
2514                         vcpu->arch.nmi_injected = true;
2515                 } else {
2516                         enable_nmi_window(vcpu);
2517                         return;
2518                 }
2519         }
2520         if (vcpu->arch.nmi_injected) {
2521                 vmx_inject_nmi(vcpu);
2522                 if (vcpu->arch.nmi_pending)
2523                         enable_nmi_window(vcpu);
2524                 else if (vcpu->arch.irq_summary
2525                          || kvm_run->request_interrupt_window)
2526                         enable_irq_window(vcpu);
2527                 return;
2528         }
2529
2530         if (vcpu->arch.interrupt_window_open) {
2531                 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2532                         kvm_queue_interrupt(vcpu, kvm_pop_irq(vcpu));
2533
2534                 if (vcpu->arch.interrupt.pending)
2535                         vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2536         }
2537         if (!vcpu->arch.interrupt_window_open &&
2538             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2539                 enable_irq_window(vcpu);
2540 }
2541
2542 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2543 {
2544         int ret;
2545         struct kvm_userspace_memory_region tss_mem = {
2546                 .slot = TSS_PRIVATE_MEMSLOT,
2547                 .guest_phys_addr = addr,
2548                 .memory_size = PAGE_SIZE * 3,
2549                 .flags = 0,
2550         };
2551
2552         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2553         if (ret)
2554                 return ret;
2555         kvm->arch.tss_addr = addr;
2556         return 0;
2557 }
2558
2559 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2560                                   int vec, u32 err_code)
2561 {
2562         /*
2563          * Instruction with address size override prefix opcode 0x67
2564          * Cause the #SS fault with 0 error code in VM86 mode.
2565          */
2566         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2567                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2568                         return 1;
2569         /*
2570          * Forward all other exceptions that are valid in real mode.
2571          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2572          *        the required debugging infrastructure rework.
2573          */
2574         switch (vec) {
2575         case DB_VECTOR:
2576                 if (vcpu->guest_debug &
2577                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2578                         return 0;
2579                 kvm_queue_exception(vcpu, vec);
2580                 return 1;
2581         case BP_VECTOR:
2582                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2583                         return 0;
2584                 /* fall through */
2585         case DE_VECTOR:
2586         case OF_VECTOR:
2587         case BR_VECTOR:
2588         case UD_VECTOR:
2589         case DF_VECTOR:
2590         case SS_VECTOR:
2591         case GP_VECTOR:
2592         case MF_VECTOR:
2593                 kvm_queue_exception(vcpu, vec);
2594                 return 1;
2595         }
2596         return 0;
2597 }
2598
2599 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2600 {
2601         struct vcpu_vmx *vmx = to_vmx(vcpu);
2602         u32 intr_info, ex_no, error_code;
2603         unsigned long cr2, rip, dr6;
2604         u32 vect_info;
2605         enum emulation_result er;
2606
2607         vect_info = vmx->idt_vectoring_info;
2608         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2609
2610         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2611                                                 !is_page_fault(intr_info))
2612                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2613                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2614
2615         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2616                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2617                 kvm_push_irq(vcpu, irq);
2618         }
2619
2620         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2621                 return 1;  /* already handled by vmx_vcpu_run() */
2622
2623         if (is_no_device(intr_info)) {
2624                 vmx_fpu_activate(vcpu);
2625                 return 1;
2626         }
2627
2628         if (is_invalid_opcode(intr_info)) {
2629                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2630                 if (er != EMULATE_DONE)
2631                         kvm_queue_exception(vcpu, UD_VECTOR);
2632                 return 1;
2633         }
2634
2635         error_code = 0;
2636         rip = kvm_rip_read(vcpu);
2637         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2638                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2639         if (is_page_fault(intr_info)) {
2640                 /* EPT won't cause page fault directly */
2641                 if (enable_ept)
2642                         BUG();
2643                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2644                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2645                             (u32)((u64)cr2 >> 32), handler);
2646                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2647                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2648                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2649         }
2650
2651         if (vcpu->arch.rmode.active &&
2652             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2653                                                                 error_code)) {
2654                 if (vcpu->arch.halt_request) {
2655                         vcpu->arch.halt_request = 0;
2656                         return kvm_emulate_halt(vcpu);
2657                 }
2658                 return 1;
2659         }
2660
2661         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2662         switch (ex_no) {
2663         case DB_VECTOR:
2664                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2665                 if (!(vcpu->guest_debug &
2666                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2667                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2668                         kvm_queue_exception(vcpu, DB_VECTOR);
2669                         return 1;
2670                 }
2671                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2672                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2673                 /* fall through */
2674         case BP_VECTOR:
2675                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2676                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2677                 kvm_run->debug.arch.exception = ex_no;
2678                 break;
2679         default:
2680                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2681                 kvm_run->ex.exception = ex_no;
2682                 kvm_run->ex.error_code = error_code;
2683                 break;
2684         }
2685         return 0;
2686 }
2687
2688 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2689                                      struct kvm_run *kvm_run)
2690 {
2691         ++vcpu->stat.irq_exits;
2692         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2693         return 1;
2694 }
2695
2696 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2697 {
2698         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2699         return 0;
2700 }
2701
2702 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2703 {
2704         unsigned long exit_qualification;
2705         int size, in, string;
2706         unsigned port;
2707
2708         ++vcpu->stat.io_exits;
2709         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2710         string = (exit_qualification & 16) != 0;
2711
2712         if (string) {
2713                 if (emulate_instruction(vcpu,
2714                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2715                         return 0;
2716                 return 1;
2717         }
2718
2719         size = (exit_qualification & 7) + 1;
2720         in = (exit_qualification & 8) != 0;
2721         port = exit_qualification >> 16;
2722
2723         skip_emulated_instruction(vcpu);
2724         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2725 }
2726
2727 static void
2728 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2729 {
2730         /*
2731          * Patch in the VMCALL instruction:
2732          */
2733         hypercall[0] = 0x0f;
2734         hypercall[1] = 0x01;
2735         hypercall[2] = 0xc1;
2736 }
2737
2738 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2739 {
2740         unsigned long exit_qualification;
2741         int cr;
2742         int reg;
2743
2744         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2745         cr = exit_qualification & 15;
2746         reg = (exit_qualification >> 8) & 15;
2747         switch ((exit_qualification >> 4) & 3) {
2748         case 0: /* mov to cr */
2749                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2750                             (u32)kvm_register_read(vcpu, reg),
2751                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2752                             handler);
2753                 switch (cr) {
2754                 case 0:
2755                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2756                         skip_emulated_instruction(vcpu);
2757                         return 1;
2758                 case 3:
2759                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2760                         skip_emulated_instruction(vcpu);
2761                         return 1;
2762                 case 4:
2763                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2764                         skip_emulated_instruction(vcpu);
2765                         return 1;
2766                 case 8:
2767                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2768                         skip_emulated_instruction(vcpu);
2769                         if (irqchip_in_kernel(vcpu->kvm))
2770                                 return 1;
2771                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2772                         return 0;
2773                 };
2774                 break;
2775         case 2: /* clts */
2776                 vmx_fpu_deactivate(vcpu);
2777                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2778                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2779                 vmx_fpu_activate(vcpu);
2780                 KVMTRACE_0D(CLTS, vcpu, handler);
2781                 skip_emulated_instruction(vcpu);
2782                 return 1;
2783         case 1: /*mov from cr*/
2784                 switch (cr) {
2785                 case 3:
2786                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2787                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2788                                     (u32)kvm_register_read(vcpu, reg),
2789                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2790                                     handler);
2791                         skip_emulated_instruction(vcpu);
2792                         return 1;
2793                 case 8:
2794                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2795                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2796                                     (u32)kvm_register_read(vcpu, reg), handler);
2797                         skip_emulated_instruction(vcpu);
2798                         return 1;
2799                 }
2800                 break;
2801         case 3: /* lmsw */
2802                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2803
2804                 skip_emulated_instruction(vcpu);
2805                 return 1;
2806         default:
2807                 break;
2808         }
2809         kvm_run->exit_reason = 0;
2810         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2811                (int)(exit_qualification >> 4) & 3, cr);
2812         return 0;
2813 }
2814
2815 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2816 {
2817         unsigned long exit_qualification;
2818         unsigned long val;
2819         int dr, reg;
2820
2821         dr = vmcs_readl(GUEST_DR7);
2822         if (dr & DR7_GD) {
2823                 /*
2824                  * As the vm-exit takes precedence over the debug trap, we
2825                  * need to emulate the latter, either for the host or the
2826                  * guest debugging itself.
2827                  */
2828                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2829                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2830                         kvm_run->debug.arch.dr7 = dr;
2831                         kvm_run->debug.arch.pc =
2832                                 vmcs_readl(GUEST_CS_BASE) +
2833                                 vmcs_readl(GUEST_RIP);
2834                         kvm_run->debug.arch.exception = DB_VECTOR;
2835                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2836                         return 0;
2837                 } else {
2838                         vcpu->arch.dr7 &= ~DR7_GD;
2839                         vcpu->arch.dr6 |= DR6_BD;
2840                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2841                         kvm_queue_exception(vcpu, DB_VECTOR);
2842                         return 1;
2843                 }
2844         }
2845
2846         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2847         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2848         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2849         if (exit_qualification & TYPE_MOV_FROM_DR) {
2850                 switch (dr) {
2851                 case 0 ... 3:
2852                         val = vcpu->arch.db[dr];
2853                         break;
2854                 case 6:
2855                         val = vcpu->arch.dr6;
2856                         break;
2857                 case 7:
2858                         val = vcpu->arch.dr7;
2859                         break;
2860                 default:
2861                         val = 0;
2862                 }
2863                 kvm_register_write(vcpu, reg, val);
2864                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2865         } else {
2866                 val = vcpu->arch.regs[reg];
2867                 switch (dr) {
2868                 case 0 ... 3:
2869                         vcpu->arch.db[dr] = val;
2870                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2871                                 vcpu->arch.eff_db[dr] = val;
2872                         break;
2873                 case 4 ... 5:
2874                         if (vcpu->arch.cr4 & X86_CR4_DE)
2875                                 kvm_queue_exception(vcpu, UD_VECTOR);
2876                         break;
2877                 case 6:
2878                         if (val & 0xffffffff00000000ULL) {
2879                                 kvm_queue_exception(vcpu, GP_VECTOR);
2880                                 break;
2881                         }
2882                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2883                         break;
2884                 case 7:
2885                         if (val & 0xffffffff00000000ULL) {
2886                                 kvm_queue_exception(vcpu, GP_VECTOR);
2887                                 break;
2888                         }
2889                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2890                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2891                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2892                                 vcpu->arch.switch_db_regs =
2893                                         (val & DR7_BP_EN_MASK);
2894                         }
2895                         break;
2896                 }
2897                 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2898         }
2899         skip_emulated_instruction(vcpu);
2900         return 1;
2901 }
2902
2903 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2904 {
2905         kvm_emulate_cpuid(vcpu);
2906         return 1;
2907 }
2908
2909 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2910 {
2911         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2912         u64 data;
2913
2914         if (vmx_get_msr(vcpu, ecx, &data)) {
2915                 kvm_inject_gp(vcpu, 0);
2916                 return 1;
2917         }
2918
2919         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2920                     handler);
2921
2922         /* FIXME: handling of bits 32:63 of rax, rdx */
2923         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2924         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2925         skip_emulated_instruction(vcpu);
2926         return 1;
2927 }
2928
2929 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2930 {
2931         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2932         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2933                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2934
2935         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2936                     handler);
2937
2938         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2939                 kvm_inject_gp(vcpu, 0);
2940                 return 1;
2941         }
2942
2943         skip_emulated_instruction(vcpu);
2944         return 1;
2945 }
2946
2947 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2948                                       struct kvm_run *kvm_run)
2949 {
2950         return 1;
2951 }
2952
2953 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2954                                    struct kvm_run *kvm_run)
2955 {
2956         u32 cpu_based_vm_exec_control;
2957
2958         /* clear pending irq */
2959         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2960         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2961         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2962
2963         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2964         ++vcpu->stat.irq_window_exits;
2965
2966         /*
2967          * If the user space waits to inject interrupts, exit as soon as
2968          * possible
2969          */
2970         if (kvm_run->request_interrupt_window &&
2971             !vcpu->arch.irq_summary) {
2972                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2973                 return 0;
2974         }
2975         return 1;
2976 }
2977
2978 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2979 {
2980         skip_emulated_instruction(vcpu);
2981         return kvm_emulate_halt(vcpu);
2982 }
2983
2984 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2985 {
2986         skip_emulated_instruction(vcpu);
2987         kvm_emulate_hypercall(vcpu);
2988         return 1;
2989 }
2990
2991 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2992 {
2993         u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2994
2995         kvm_mmu_invlpg(vcpu, exit_qualification);
2996         skip_emulated_instruction(vcpu);
2997         return 1;
2998 }
2999
3000 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3001 {
3002         skip_emulated_instruction(vcpu);
3003         /* TODO: Add support for VT-d/pass-through device */
3004         return 1;
3005 }
3006
3007 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3008 {
3009         u64 exit_qualification;
3010         enum emulation_result er;
3011         unsigned long offset;
3012
3013         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3014         offset = exit_qualification & 0xffful;
3015
3016         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3017
3018         if (er !=  EMULATE_DONE) {
3019                 printk(KERN_ERR
3020                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3021                        offset);
3022                 return -ENOTSUPP;
3023         }
3024         return 1;
3025 }
3026
3027 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3028 {
3029         struct vcpu_vmx *vmx = to_vmx(vcpu);
3030         unsigned long exit_qualification;
3031         u16 tss_selector;
3032         int reason;
3033
3034         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3035
3036         reason = (u32)exit_qualification >> 30;
3037         if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3038             (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3039             (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3040             == INTR_TYPE_NMI_INTR) {
3041                 vcpu->arch.nmi_injected = false;
3042                 if (cpu_has_virtual_nmis())
3043                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3044                                       GUEST_INTR_STATE_NMI);
3045         }
3046         tss_selector = exit_qualification;
3047
3048         if (!kvm_task_switch(vcpu, tss_selector, reason))
3049                 return 0;
3050
3051         /* clear all local breakpoint enable flags */
3052         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3053
3054         /*
3055          * TODO: What about debug traps on tss switch?
3056          *       Are we supposed to inject them and update dr6?
3057          */
3058
3059         return 1;
3060 }
3061
3062 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3063 {
3064         u64 exit_qualification;
3065         gpa_t gpa;
3066         int gla_validity;
3067
3068         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3069
3070         if (exit_qualification & (1 << 6)) {
3071                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3072                 return -ENOTSUPP;
3073         }
3074
3075         gla_validity = (exit_qualification >> 7) & 0x3;
3076         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3077                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3078                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3079                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3080                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3081                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3082                         (long unsigned int)exit_qualification);
3083                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3084                 kvm_run->hw.hardware_exit_reason = 0;
3085                 return -ENOTSUPP;
3086         }
3087
3088         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3089         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3090 }
3091
3092 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3093 {
3094         u32 cpu_based_vm_exec_control;
3095
3096         /* clear pending NMI */
3097         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3098         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3099         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3100         ++vcpu->stat.nmi_window_exits;
3101
3102         return 1;
3103 }
3104
3105 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3106                                 struct kvm_run *kvm_run)
3107 {
3108         struct vcpu_vmx *vmx = to_vmx(vcpu);
3109         enum emulation_result err = EMULATE_DONE;
3110
3111         preempt_enable();
3112         local_irq_enable();
3113
3114         while (!guest_state_valid(vcpu)) {
3115                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3116
3117                 if (err == EMULATE_DO_MMIO)
3118                         break;
3119
3120                 if (err != EMULATE_DONE) {
3121                         kvm_report_emulation_failure(vcpu, "emulation failure");
3122                         return;
3123                 }
3124
3125                 if (signal_pending(current))
3126                         break;
3127                 if (need_resched())
3128                         schedule();
3129         }
3130
3131         local_irq_disable();
3132         preempt_disable();
3133
3134         vmx->invalid_state_emulation_result = err;
3135 }
3136
3137 /*
3138  * The exit handlers return 1 if the exit was handled fully and guest execution
3139  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3140  * to be done to userspace and return 0.
3141  */
3142 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3143                                       struct kvm_run *kvm_run) = {
3144         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3145         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3146         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3147         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3148         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3149         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3150         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3151         [EXIT_REASON_CPUID]                   = handle_cpuid,
3152         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3153         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3154         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3155         [EXIT_REASON_HLT]                     = handle_halt,
3156         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3157         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3158         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3159         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3160         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3161         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3162         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3163 };
3164
3165 static const int kvm_vmx_max_exit_handlers =
3166         ARRAY_SIZE(kvm_vmx_exit_handlers);
3167
3168 /*
3169  * The guest has exited.  See if we can fix it or if we need userspace
3170  * assistance.
3171  */
3172 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3173 {
3174         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3175         struct vcpu_vmx *vmx = to_vmx(vcpu);
3176         u32 vectoring_info = vmx->idt_vectoring_info;
3177
3178         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3179                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3180
3181         /* If we need to emulate an MMIO from handle_invalid_guest_state
3182          * we just return 0 */
3183         if (vmx->emulation_required && emulate_invalid_guest_state) {
3184                 if (guest_state_valid(vcpu))
3185                         vmx->emulation_required = 0;
3186                 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3187         }
3188
3189         /* Access CR3 don't cause VMExit in paging mode, so we need
3190          * to sync with guest real CR3. */
3191         if (enable_ept && is_paging(vcpu)) {
3192                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3193                 ept_load_pdptrs(vcpu);
3194         }
3195
3196         if (unlikely(vmx->fail)) {
3197                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3198                 kvm_run->fail_entry.hardware_entry_failure_reason
3199                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3200                 return 0;
3201         }
3202
3203         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3204                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3205                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3206                         exit_reason != EXIT_REASON_TASK_SWITCH))
3207                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3208                        "(0x%x) and exit reason is 0x%x\n",
3209                        __func__, vectoring_info, exit_reason);
3210
3211         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3212                 if (vcpu->arch.interrupt_window_open) {
3213                         vmx->soft_vnmi_blocked = 0;
3214                         vcpu->arch.nmi_window_open = 1;
3215                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3216                            vcpu->arch.nmi_pending) {
3217                         /*
3218                          * This CPU don't support us in finding the end of an
3219                          * NMI-blocked window if the guest runs with IRQs
3220                          * disabled. So we pull the trigger after 1 s of
3221                          * futile waiting, but inform the user about this.
3222                          */
3223                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3224                                "state on VCPU %d after 1 s timeout\n",
3225                                __func__, vcpu->vcpu_id);
3226                         vmx->soft_vnmi_blocked = 0;
3227                         vmx->vcpu.arch.nmi_window_open = 1;
3228                 }
3229         }
3230
3231         if (exit_reason < kvm_vmx_max_exit_handlers
3232             && kvm_vmx_exit_handlers[exit_reason])
3233                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3234         else {
3235                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3236                 kvm_run->hw.hardware_exit_reason = exit_reason;
3237         }
3238         return 0;
3239 }
3240
3241 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3242 {
3243         int max_irr, tpr;
3244
3245         if (!vm_need_tpr_shadow(vcpu->kvm))
3246                 return;
3247
3248         if (!kvm_lapic_enabled(vcpu) ||
3249             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3250                 vmcs_write32(TPR_THRESHOLD, 0);
3251                 return;
3252         }
3253
3254         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3255         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3256 }
3257
3258 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3259 {
3260         u32 exit_intr_info;
3261         u32 idt_vectoring_info;
3262         bool unblock_nmi;
3263         u8 vector;
3264         int type;
3265         bool idtv_info_valid;
3266         u32 error;
3267
3268         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3269         if (cpu_has_virtual_nmis()) {
3270                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3271                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3272                 /*
3273                  * SDM 3: 25.7.1.2
3274                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3275                  * a guest IRET fault.
3276                  */
3277                 if (unblock_nmi && vector != DF_VECTOR)
3278                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3279                                       GUEST_INTR_STATE_NMI);
3280         } else if (unlikely(vmx->soft_vnmi_blocked))
3281                 vmx->vnmi_blocked_time +=
3282                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3283
3284         idt_vectoring_info = vmx->idt_vectoring_info;
3285         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3286         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3287         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3288         if (vmx->vcpu.arch.nmi_injected) {
3289                 /*
3290                  * SDM 3: 25.7.1.2
3291                  * Clear bit "block by NMI" before VM entry if a NMI delivery
3292                  * faulted.
3293                  */
3294                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3295                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3296                                         GUEST_INTR_STATE_NMI);
3297                 else
3298                         vmx->vcpu.arch.nmi_injected = false;
3299         }
3300         kvm_clear_exception_queue(&vmx->vcpu);
3301         if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3302                                 type == INTR_TYPE_SOFT_EXCEPTION)) {
3303                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3304                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3305                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
3306                 } else
3307                         kvm_queue_exception(&vmx->vcpu, vector);
3308                 vmx->idt_vectoring_info = 0;
3309         }
3310         kvm_clear_interrupt_queue(&vmx->vcpu);
3311         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3312                 kvm_queue_interrupt(&vmx->vcpu, vector);
3313                 vmx->idt_vectoring_info = 0;
3314         }
3315 }
3316
3317 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3318 {
3319         update_tpr_threshold(vcpu);
3320
3321         vmx_update_window_states(vcpu);
3322
3323         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3324                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3325                                 GUEST_INTR_STATE_STI |
3326                                 GUEST_INTR_STATE_MOV_SS);
3327
3328         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3329                 if (vcpu->arch.interrupt.pending) {
3330                         enable_nmi_window(vcpu);
3331                 } else if (vcpu->arch.nmi_window_open) {
3332                         vcpu->arch.nmi_pending = false;
3333                         vcpu->arch.nmi_injected = true;
3334                 } else {
3335                         enable_nmi_window(vcpu);
3336                         return;
3337                 }
3338         }
3339         if (vcpu->arch.nmi_injected) {
3340                 vmx_inject_nmi(vcpu);
3341                 if (vcpu->arch.nmi_pending)
3342                         enable_nmi_window(vcpu);
3343                 else if (kvm_cpu_has_interrupt(vcpu))
3344                         enable_irq_window(vcpu);
3345                 return;
3346         }
3347         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3348                 if (vcpu->arch.interrupt_window_open)
3349                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3350                 else
3351                         enable_irq_window(vcpu);
3352         }
3353         if (vcpu->arch.interrupt.pending) {
3354                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3355                 if (kvm_cpu_has_interrupt(vcpu))
3356                         enable_irq_window(vcpu);
3357         }
3358 }
3359
3360 /*
3361  * Failure to inject an interrupt should give us the information
3362  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3363  * when fetching the interrupt redirection bitmap in the real-mode
3364  * tss, this doesn't happen.  So we do it ourselves.
3365  */
3366 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3367 {
3368         vmx->rmode.irq.pending = 0;
3369         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3370                 return;
3371         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3372         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3373                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3374                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3375                 return;
3376         }
3377         vmx->idt_vectoring_info =
3378                 VECTORING_INFO_VALID_MASK
3379                 | INTR_TYPE_EXT_INTR
3380                 | vmx->rmode.irq.vector;
3381 }
3382
3383 #ifdef CONFIG_X86_64
3384 #define R "r"
3385 #define Q "q"
3386 #else
3387 #define R "e"
3388 #define Q "l"
3389 #endif
3390
3391 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3392 {
3393         struct vcpu_vmx *vmx = to_vmx(vcpu);
3394         u32 intr_info;
3395
3396         /* Record the guest's net vcpu time for enforced NMI injections. */
3397         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3398                 vmx->entry_time = ktime_get();
3399
3400         /* Handle invalid guest state instead of entering VMX */
3401         if (vmx->emulation_required && emulate_invalid_guest_state) {
3402                 handle_invalid_guest_state(vcpu, kvm_run);
3403                 return;
3404         }
3405
3406         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3407                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3408         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3409                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3410
3411         /*
3412          * Loading guest fpu may have cleared host cr0.ts
3413          */
3414         vmcs_writel(HOST_CR0, read_cr0());
3415
3416         set_debugreg(vcpu->arch.dr6, 6);
3417
3418         asm(
3419                 /* Store host registers */
3420                 "push %%"R"dx; push %%"R"bp;"
3421                 "push %%"R"cx \n\t"
3422                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3423                 "je 1f \n\t"
3424                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3425                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3426                 "1: \n\t"
3427                 /* Check if vmlaunch of vmresume is needed */
3428                 "cmpl $0, %c[launched](%0) \n\t"
3429                 /* Load guest registers.  Don't clobber flags. */
3430                 "mov %c[cr2](%0), %%"R"ax \n\t"
3431                 "mov %%"R"ax, %%cr2 \n\t"
3432                 "mov %c[rax](%0), %%"R"ax \n\t"
3433                 "mov %c[rbx](%0), %%"R"bx \n\t"
3434                 "mov %c[rdx](%0), %%"R"dx \n\t"
3435                 "mov %c[rsi](%0), %%"R"si \n\t"
3436                 "mov %c[rdi](%0), %%"R"di \n\t"
3437                 "mov %c[rbp](%0), %%"R"bp \n\t"
3438 #ifdef CONFIG_X86_64
3439                 "mov %c[r8](%0),  %%r8  \n\t"
3440                 "mov %c[r9](%0),  %%r9  \n\t"
3441                 "mov %c[r10](%0), %%r10 \n\t"
3442                 "mov %c[r11](%0), %%r11 \n\t"
3443                 "mov %c[r12](%0), %%r12 \n\t"
3444                 "mov %c[r13](%0), %%r13 \n\t"
3445                 "mov %c[r14](%0), %%r14 \n\t"
3446                 "mov %c[r15](%0), %%r15 \n\t"
3447 #endif
3448                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3449
3450                 /* Enter guest mode */
3451                 "jne .Llaunched \n\t"
3452                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3453                 "jmp .Lkvm_vmx_return \n\t"
3454                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3455                 ".Lkvm_vmx_return: "
3456                 /* Save guest registers, load host registers, keep flags */
3457                 "xchg %0,     (%%"R"sp) \n\t"
3458                 "mov %%"R"ax, %c[rax](%0) \n\t"
3459                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3460                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3461                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3462                 "mov %%"R"si, %c[rsi](%0) \n\t"
3463                 "mov %%"R"di, %c[rdi](%0) \n\t"
3464                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3465 #ifdef CONFIG_X86_64
3466                 "mov %%r8,  %c[r8](%0) \n\t"
3467                 "mov %%r9,  %c[r9](%0) \n\t"
3468                 "mov %%r10, %c[r10](%0) \n\t"
3469                 "mov %%r11, %c[r11](%0) \n\t"
3470                 "mov %%r12, %c[r12](%0) \n\t"
3471                 "mov %%r13, %c[r13](%0) \n\t"
3472                 "mov %%r14, %c[r14](%0) \n\t"
3473                 "mov %%r15, %c[r15](%0) \n\t"
3474 #endif
3475                 "mov %%cr2, %%"R"ax   \n\t"
3476                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3477
3478                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3479                 "setbe %c[fail](%0) \n\t"
3480               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3481                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3482                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3483                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3484                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3485                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3486                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3487                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3488                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3489                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3490                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3491 #ifdef CONFIG_X86_64
3492                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3493                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3494                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3495                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3496                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3497                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3498                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3499                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3500 #endif
3501                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3502               : "cc", "memory"
3503                 , R"bx", R"di", R"si"
3504 #ifdef CONFIG_X86_64
3505                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3506 #endif
3507               );
3508
3509         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3510         vcpu->arch.regs_dirty = 0;
3511
3512         get_debugreg(vcpu->arch.dr6, 6);
3513
3514         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3515         if (vmx->rmode.irq.pending)
3516                 fixup_rmode_irq(vmx);
3517
3518         vmx_update_window_states(vcpu);
3519
3520         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3521         vmx->launched = 1;
3522
3523         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3524
3525         /* We need to handle NMIs before interrupts are enabled */
3526         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3527             (intr_info & INTR_INFO_VALID_MASK)) {
3528                 KVMTRACE_0D(NMI, vcpu, handler);
3529                 asm("int $2");
3530         }
3531
3532         vmx_complete_interrupts(vmx);
3533 }
3534
3535 #undef R
3536 #undef Q
3537
3538 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3539 {
3540         struct vcpu_vmx *vmx = to_vmx(vcpu);
3541
3542         if (vmx->vmcs) {
3543                 vcpu_clear(vmx);
3544                 free_vmcs(vmx->vmcs);
3545                 vmx->vmcs = NULL;
3546         }
3547 }
3548
3549 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3550 {
3551         struct vcpu_vmx *vmx = to_vmx(vcpu);
3552
3553         spin_lock(&vmx_vpid_lock);
3554         if (vmx->vpid != 0)
3555                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3556         spin_unlock(&vmx_vpid_lock);
3557         vmx_free_vmcs(vcpu);
3558         kfree(vmx->host_msrs);
3559         kfree(vmx->guest_msrs);
3560         kvm_vcpu_uninit(vcpu);
3561         kmem_cache_free(kvm_vcpu_cache, vmx);
3562 }
3563
3564 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3565 {
3566         int err;
3567         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3568         int cpu;
3569
3570         if (!vmx)
3571                 return ERR_PTR(-ENOMEM);
3572
3573         allocate_vpid(vmx);
3574
3575         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3576         if (err)
3577                 goto free_vcpu;
3578
3579         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3580         if (!vmx->guest_msrs) {
3581                 err = -ENOMEM;
3582                 goto uninit_vcpu;
3583         }
3584
3585         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3586         if (!vmx->host_msrs)
3587                 goto free_guest_msrs;
3588
3589         vmx->vmcs = alloc_vmcs();
3590         if (!vmx->vmcs)
3591                 goto free_msrs;
3592
3593         vmcs_clear(vmx->vmcs);
3594
3595         cpu = get_cpu();
3596         vmx_vcpu_load(&vmx->vcpu, cpu);
3597         err = vmx_vcpu_setup(vmx);
3598         vmx_vcpu_put(&vmx->vcpu);
3599         put_cpu();
3600         if (err)
3601                 goto free_vmcs;
3602         if (vm_need_virtualize_apic_accesses(kvm))
3603                 if (alloc_apic_access_page(kvm) != 0)
3604                         goto free_vmcs;
3605
3606         if (enable_ept)
3607                 if (alloc_identity_pagetable(kvm) != 0)
3608                         goto free_vmcs;
3609
3610         return &vmx->vcpu;
3611
3612 free_vmcs:
3613         free_vmcs(vmx->vmcs);
3614 free_msrs:
3615         kfree(vmx->host_msrs);
3616 free_guest_msrs:
3617         kfree(vmx->guest_msrs);
3618 uninit_vcpu:
3619         kvm_vcpu_uninit(&vmx->vcpu);
3620 free_vcpu:
3621         kmem_cache_free(kvm_vcpu_cache, vmx);
3622         return ERR_PTR(err);
3623 }
3624
3625 static void __init vmx_check_processor_compat(void *rtn)
3626 {
3627         struct vmcs_config vmcs_conf;
3628
3629         *(int *)rtn = 0;
3630         if (setup_vmcs_config(&vmcs_conf) < 0)
3631                 *(int *)rtn = -EIO;
3632         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3633                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3634                                 smp_processor_id());
3635                 *(int *)rtn = -EIO;
3636         }
3637 }
3638
3639 static int get_ept_level(void)
3640 {
3641         return VMX_EPT_DEFAULT_GAW + 1;
3642 }
3643
3644 static int vmx_get_mt_mask_shift(void)
3645 {
3646         return VMX_EPT_MT_EPTE_SHIFT;
3647 }
3648
3649 static struct kvm_x86_ops vmx_x86_ops = {
3650         .cpu_has_kvm_support = cpu_has_kvm_support,
3651         .disabled_by_bios = vmx_disabled_by_bios,
3652         .hardware_setup = hardware_setup,
3653         .hardware_unsetup = hardware_unsetup,
3654         .check_processor_compatibility = vmx_check_processor_compat,
3655         .hardware_enable = hardware_enable,
3656         .hardware_disable = hardware_disable,
3657         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3658
3659         .vcpu_create = vmx_create_vcpu,
3660         .vcpu_free = vmx_free_vcpu,
3661         .vcpu_reset = vmx_vcpu_reset,
3662
3663         .prepare_guest_switch = vmx_save_host_state,
3664         .vcpu_load = vmx_vcpu_load,
3665         .vcpu_put = vmx_vcpu_put,
3666
3667         .set_guest_debug = set_guest_debug,
3668         .get_msr = vmx_get_msr,
3669         .set_msr = vmx_set_msr,
3670         .get_segment_base = vmx_get_segment_base,
3671         .get_segment = vmx_get_segment,
3672         .set_segment = vmx_set_segment,
3673         .get_cpl = vmx_get_cpl,
3674         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3675         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3676         .set_cr0 = vmx_set_cr0,
3677         .set_cr3 = vmx_set_cr3,
3678         .set_cr4 = vmx_set_cr4,
3679         .set_efer = vmx_set_efer,
3680         .get_idt = vmx_get_idt,
3681         .set_idt = vmx_set_idt,
3682         .get_gdt = vmx_get_gdt,
3683         .set_gdt = vmx_set_gdt,
3684         .cache_reg = vmx_cache_reg,
3685         .get_rflags = vmx_get_rflags,
3686         .set_rflags = vmx_set_rflags,
3687
3688         .tlb_flush = vmx_flush_tlb,
3689
3690         .run = vmx_vcpu_run,
3691         .handle_exit = vmx_handle_exit,
3692         .skip_emulated_instruction = skip_emulated_instruction,
3693         .patch_hypercall = vmx_patch_hypercall,
3694         .get_irq = vmx_get_irq,
3695         .set_irq = vmx_inject_irq,
3696         .queue_exception = vmx_queue_exception,
3697         .exception_injected = vmx_exception_injected,
3698         .inject_pending_irq = vmx_intr_assist,
3699         .inject_pending_vectors = do_interrupt_requests,
3700         .interrupt_allowed = vmx_interrupt_allowed,
3701         .set_tss_addr = vmx_set_tss_addr,
3702         .get_tdp_level = get_ept_level,
3703         .get_mt_mask_shift = vmx_get_mt_mask_shift,
3704 };
3705
3706 static int __init vmx_init(void)
3707 {
3708         int r;
3709
3710         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3711         if (!vmx_io_bitmap_a)
3712                 return -ENOMEM;
3713
3714         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3715         if (!vmx_io_bitmap_b) {
3716                 r = -ENOMEM;
3717                 goto out;
3718         }
3719
3720         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3721         if (!vmx_msr_bitmap_legacy) {
3722                 r = -ENOMEM;
3723                 goto out1;
3724         }
3725
3726         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3727         if (!vmx_msr_bitmap_longmode) {
3728                 r = -ENOMEM;
3729                 goto out2;
3730         }
3731
3732         /*
3733          * Allow direct access to the PC debug port (it is often used for I/O
3734          * delays, but the vmexits simply slow things down).
3735          */
3736         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3737         clear_bit(0x80, vmx_io_bitmap_a);
3738
3739         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3740
3741         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3742         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3743
3744         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3745
3746         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3747         if (r)
3748                 goto out3;
3749
3750         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3751         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3752         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3753         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3754         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3755         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3756
3757         if (enable_ept) {
3758                 bypass_guest_pf = 0;
3759                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3760                         VMX_EPT_WRITABLE_MASK);
3761                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3762                                 VMX_EPT_EXECUTABLE_MASK,
3763                                 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3764                 kvm_enable_tdp();
3765         } else
3766                 kvm_disable_tdp();
3767
3768         if (bypass_guest_pf)
3769                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3770
3771         ept_sync_global();
3772
3773         return 0;
3774
3775 out3:
3776         free_page((unsigned long)vmx_msr_bitmap_longmode);
3777 out2:
3778         free_page((unsigned long)vmx_msr_bitmap_legacy);
3779 out1:
3780         free_page((unsigned long)vmx_io_bitmap_b);
3781 out:
3782         free_page((unsigned long)vmx_io_bitmap_a);
3783         return r;
3784 }
3785
3786 static void __exit vmx_exit(void)
3787 {
3788         free_page((unsigned long)vmx_msr_bitmap_legacy);
3789         free_page((unsigned long)vmx_msr_bitmap_longmode);
3790         free_page((unsigned long)vmx_io_bitmap_b);
3791         free_page((unsigned long)vmx_io_bitmap_a);
3792
3793         kvm_exit();
3794 }
3795
3796 module_init(vmx_init)
3797 module_exit(vmx_exit)