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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "vmx.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/desc.h>
  32
  33 MODULE_AUTHOR("Qumranet");
  34 MODULE_LICENSE("GPL");
  35
  36 static int bypass_guest_pf = 1;
  37 module_param(bypass_guest_pf, bool, 0);
  38
  39 static int enable_vpid = 1;
  40 module_param(enable_vpid, bool, 0);
  41
  42 static int flexpriority_enabled = 1;
  43 module_param(flexpriority_enabled, bool, 0);
  44
  45 struct vmcs {
  46         u32 revision_id;
  47         u32 abort;
  48         char data[0];
  49 };
  50
  51 struct vcpu_vmx {
  52         struct kvm_vcpu       vcpu;
  53         int                   launched;
  54         u8                    fail;
  55         u32                   idt_vectoring_info;
  56         struct kvm_msr_entry *guest_msrs;
  57         struct kvm_msr_entry *host_msrs;
  58         int                   nmsrs;
  59         int                   save_nmsrs;
  60         int                   msr_offset_efer;
  61 #ifdef CONFIG_X86_64
  62         int                   msr_offset_kernel_gs_base;
  63 #endif
  64         struct vmcs          *vmcs;
  65         struct {
  66                 int           loaded;
  67                 u16           fs_sel, gs_sel, ldt_sel;
  68                 int           gs_ldt_reload_needed;
  69                 int           fs_reload_needed;
  70                 int           guest_efer_loaded;
  71         } host_state;
  72         struct {
  73                 struct {
  74                         bool pending;
  75                         u8 vector;
  76                         unsigned rip;
  77                 } irq;
  78         } rmode;
  79         int vpid;
  80 };
  81
  82 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_vmx, vcpu);
  85 }
  86
  87 static int init_rmode_tss(struct kvm *kvm);
  88
  89 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  90 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  91
  92 static struct page *vmx_io_bitmap_a;
  93 static struct page *vmx_io_bitmap_b;
  94
  95 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
  96 static DEFINE_SPINLOCK(vmx_vpid_lock);
  97
  98 static struct vmcs_config {
  99         int size;
 100         int order;
 101         u32 revision_id;
 102         u32 pin_based_exec_ctrl;
 103         u32 cpu_based_exec_ctrl;
 104         u32 cpu_based_2nd_exec_ctrl;
 105         u32 vmexit_ctrl;
 106         u32 vmentry_ctrl;
 107 } vmcs_config;
 108
 109 #define VMX_SEGMENT_FIELD(seg)                                  \
 110         [VCPU_SREG_##seg] = {                                   \
 111                 .selector = GUEST_##seg##_SELECTOR,             \
 112                 .base = GUEST_##seg##_BASE,                     \
 113                 .limit = GUEST_##seg##_LIMIT,                   \
 114                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 115         }
 116
 117 static struct kvm_vmx_segment_field {
 118         unsigned selector;
 119         unsigned base;
 120         unsigned limit;
 121         unsigned ar_bytes;
 122 } kvm_vmx_segment_fields[] = {
 123         VMX_SEGMENT_FIELD(CS),
 124         VMX_SEGMENT_FIELD(DS),
 125         VMX_SEGMENT_FIELD(ES),
 126         VMX_SEGMENT_FIELD(FS),
 127         VMX_SEGMENT_FIELD(GS),
 128         VMX_SEGMENT_FIELD(SS),
 129         VMX_SEGMENT_FIELD(TR),
 130         VMX_SEGMENT_FIELD(LDTR),
 131 };
 132
 133 /*
 134  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 135  * away by decrementing the array size.
 136  */
 137 static const u32 vmx_msr_index[] = {
 138 #ifdef CONFIG_X86_64
 139         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 140 #endif
 141         MSR_EFER, MSR_K6_STAR,
 142 };
 143 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 144
 145 static void load_msrs(struct kvm_msr_entry *e, int n)
 146 {
 147         int i;
 148
 149         for (i = 0; i < n; ++i)
 150                 wrmsrl(e[i].index, e[i].data);
 151 }
 152
 153 static void save_msrs(struct kvm_msr_entry *e, int n)
 154 {
 155         int i;
 156
 157         for (i = 0; i < n; ++i)
 158                 rdmsrl(e[i].index, e[i].data);
 159 }
 160
 161 static inline int is_page_fault(u32 intr_info)
 162 {
 163         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 164                              INTR_INFO_VALID_MASK)) ==
 165                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 166 }
 167
 168 static inline int is_no_device(u32 intr_info)
 169 {
 170         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 171                              INTR_INFO_VALID_MASK)) ==
 172                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 173 }
 174
 175 static inline int is_invalid_opcode(u32 intr_info)
 176 {
 177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 178                              INTR_INFO_VALID_MASK)) ==
 179                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 180 }
 181
 182 static inline int is_external_interrupt(u32 intr_info)
 183 {
 184         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 185                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 186 }
 187
 188 static inline int cpu_has_vmx_tpr_shadow(void)
 189 {
 190         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 191 }
 192
 193 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 194 {
 195         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 196 }
 197
 198 static inline int cpu_has_secondary_exec_ctrls(void)
 199 {
 200         return (vmcs_config.cpu_based_exec_ctrl &
 201                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 202 }
 203
 204 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 205 {
 206         return flexpriority_enabled
 207                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 208                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 209 }
 210
 211 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 212 {
 213         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 214                 (irqchip_in_kernel(kvm)));
 215 }
 216
 217 static inline int cpu_has_vmx_vpid(void)
 218 {
 219         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 220                 SECONDARY_EXEC_ENABLE_VPID);
 221 }
 222
 223 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 224 {
 225         int i;
 226
 227         for (i = 0; i < vmx->nmsrs; ++i)
 228                 if (vmx->guest_msrs[i].index == msr)
 229                         return i;
 230         return -1;
 231 }
 232
 233 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 234 {
 235     struct {
 236         u64 vpid : 16;
 237         u64 rsvd : 48;
 238         u64 gva;
 239     } operand = { vpid, 0, gva };
 240
 241     asm volatile (ASM_VMX_INVVPID
 242                   /* CF==1 or ZF==1 --> rc = -1 */
 243                   "; ja 1f ; ud2 ; 1:"
 244                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 245 }
 246
 247 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 248 {
 249         int i;
 250
 251         i = __find_msr_index(vmx, msr);
 252         if (i >= 0)
 253                 return &vmx->guest_msrs[i];
 254         return NULL;
 255 }
 256
 257 static void vmcs_clear(struct vmcs *vmcs)
 258 {
 259         u64 phys_addr = __pa(vmcs);
 260         u8 error;
 261
 262         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
 263                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 264                       : "cc", "memory");
 265         if (error)
 266                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 267                        vmcs, phys_addr);
 268 }
 269
 270 static void __vcpu_clear(void *arg)
 271 {
 272         struct vcpu_vmx *vmx = arg;
 273         int cpu = raw_smp_processor_id();
 274
 275         if (vmx->vcpu.cpu == cpu)
 276                 vmcs_clear(vmx->vmcs);
 277         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 278                 per_cpu(current_vmcs, cpu) = NULL;
 279         rdtscll(vmx->vcpu.arch.host_tsc);
 280 }
 281
 282 static void vcpu_clear(struct vcpu_vmx *vmx)
 283 {
 284         if (vmx->vcpu.cpu == -1)
 285                 return;
 286         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
 287         vmx->launched = 0;
 288 }
 289
 290 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 291 {
 292         if (vmx->vpid == 0)
 293                 return;
 294
 295         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 296 }
 297
 298 static unsigned long vmcs_readl(unsigned long field)
 299 {
 300         unsigned long value;
 301
 302         asm volatile (ASM_VMX_VMREAD_RDX_RAX
 303                       : "=a"(value) : "d"(field) : "cc");
 304         return value;
 305 }
 306
 307 static u16 vmcs_read16(unsigned long field)
 308 {
 309         return vmcs_readl(field);
 310 }
 311
 312 static u32 vmcs_read32(unsigned long field)
 313 {
 314         return vmcs_readl(field);
 315 }
 316
 317 static u64 vmcs_read64(unsigned long field)
 318 {
 319 #ifdef CONFIG_X86_64
 320         return vmcs_readl(field);
 321 #else
 322         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 323 #endif
 324 }
 325
 326 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 327 {
 328         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 329                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 330         dump_stack();
 331 }
 332
 333 static void vmcs_writel(unsigned long field, unsigned long value)
 334 {
 335         u8 error;
 336
 337         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
 338                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 339         if (unlikely(error))
 340                 vmwrite_error(field, value);
 341 }
 342
 343 static void vmcs_write16(unsigned long field, u16 value)
 344 {
 345         vmcs_writel(field, value);
 346 }
 347
 348 static void vmcs_write32(unsigned long field, u32 value)
 349 {
 350         vmcs_writel(field, value);
 351 }
 352
 353 static void vmcs_write64(unsigned long field, u64 value)
 354 {
 355 #ifdef CONFIG_X86_64
 356         vmcs_writel(field, value);
 357 #else
 358         vmcs_writel(field, value);
 359         asm volatile ("");
 360         vmcs_writel(field+1, value >> 32);
 361 #endif
 362 }
 363
 364 static void vmcs_clear_bits(unsigned long field, u32 mask)
 365 {
 366         vmcs_writel(field, vmcs_readl(field) & ~mask);
 367 }
 368
 369 static void vmcs_set_bits(unsigned long field, u32 mask)
 370 {
 371         vmcs_writel(field, vmcs_readl(field) | mask);
 372 }
 373
 374 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 375 {
 376         u32 eb;
 377
 378         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 379         if (!vcpu->fpu_active)
 380                 eb |= 1u << NM_VECTOR;
 381         if (vcpu->guest_debug.enabled)
 382                 eb |= 1u << 1;
 383         if (vcpu->arch.rmode.active)
 384                 eb = ~0;
 385         vmcs_write32(EXCEPTION_BITMAP, eb);
 386 }
 387
 388 static void reload_tss(void)
 389 {
 390         /*
 391          * VT restores TR but not its size.  Useless.
 392          */
 393         struct descriptor_table gdt;
 394         struct desc_struct *descs;
 395
 396         get_gdt(&gdt);
 397         descs = (void *)gdt.base;
 398         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 399         load_TR_desc();
 400 }
 401
 402 static void load_transition_efer(struct vcpu_vmx *vmx)
 403 {
 404         int efer_offset = vmx->msr_offset_efer;
 405         u64 host_efer = vmx->host_msrs[efer_offset].data;
 406         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 407         u64 ignore_bits;
 408
 409         if (efer_offset < 0)
 410                 return;
 411         /*
 412          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 413          * outside long mode
 414          */
 415         ignore_bits = EFER_NX | EFER_SCE;
 416 #ifdef CONFIG_X86_64
 417         ignore_bits |= EFER_LMA | EFER_LME;
 418         /* SCE is meaningful only in long mode on Intel */
 419         if (guest_efer & EFER_LMA)
 420                 ignore_bits &= ~(u64)EFER_SCE;
 421 #endif
 422         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 423                 return;
 424
 425         vmx->host_state.guest_efer_loaded = 1;
 426         guest_efer &= ~ignore_bits;
 427         guest_efer |= host_efer & ignore_bits;
 428         wrmsrl(MSR_EFER, guest_efer);
 429         vmx->vcpu.stat.efer_reload++;
 430 }
 431
 432 static void reload_host_efer(struct vcpu_vmx *vmx)
 433 {
 434         if (vmx->host_state.guest_efer_loaded) {
 435                 vmx->host_state.guest_efer_loaded = 0;
 436                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 437         }
 438 }
 439
 440 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 441 {
 442         struct vcpu_vmx *vmx = to_vmx(vcpu);
 443
 444         if (vmx->host_state.loaded)
 445                 return;
 446
 447         vmx->host_state.loaded = 1;
 448         /*
 449          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 450          * allow segment selectors with cpl > 0 or ti == 1.
 451          */
 452         vmx->host_state.ldt_sel = read_ldt();
 453         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 454         vmx->host_state.fs_sel = read_fs();
 455         if (!(vmx->host_state.fs_sel & 7)) {
 456                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 457                 vmx->host_state.fs_reload_needed = 0;
 458         } else {
 459                 vmcs_write16(HOST_FS_SELECTOR, 0);
 460                 vmx->host_state.fs_reload_needed = 1;
 461         }
 462         vmx->host_state.gs_sel = read_gs();
 463         if (!(vmx->host_state.gs_sel & 7))
 464                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 465         else {
 466                 vmcs_write16(HOST_GS_SELECTOR, 0);
 467                 vmx->host_state.gs_ldt_reload_needed = 1;
 468         }
 469
 470 #ifdef CONFIG_X86_64
 471         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 472         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 473 #else
 474         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 475         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 476 #endif
 477
 478 #ifdef CONFIG_X86_64
 479         if (is_long_mode(&vmx->vcpu))
 480                 save_msrs(vmx->host_msrs +
 481                           vmx->msr_offset_kernel_gs_base, 1);
 482
 483 #endif
 484         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 485         load_transition_efer(vmx);
 486 }
 487
 488 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 489 {
 490         unsigned long flags;
 491
 492         if (!vmx->host_state.loaded)
 493                 return;
 494
 495         ++vmx->vcpu.stat.host_state_reload;
 496         vmx->host_state.loaded = 0;
 497         if (vmx->host_state.fs_reload_needed)
 498                 load_fs(vmx->host_state.fs_sel);
 499         if (vmx->host_state.gs_ldt_reload_needed) {
 500                 load_ldt(vmx->host_state.ldt_sel);
 501                 /*
 502                  * If we have to reload gs, we must take care to
 503                  * preserve our gs base.
 504                  */
 505                 local_irq_save(flags);
 506                 load_gs(vmx->host_state.gs_sel);
 507 #ifdef CONFIG_X86_64
 508                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 509 #endif
 510                 local_irq_restore(flags);
 511         }
 512         reload_tss();
 513         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 514         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 515         reload_host_efer(vmx);
 516 }
 517
 518 /*
 519  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 520  * vcpu mutex is already taken.
 521  */
 522 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 523 {
 524         struct vcpu_vmx *vmx = to_vmx(vcpu);
 525         u64 phys_addr = __pa(vmx->vmcs);
 526         u64 tsc_this, delta, new_offset;
 527
 528         if (vcpu->cpu != cpu) {
 529                 vcpu_clear(vmx);
 530                 kvm_migrate_apic_timer(vcpu);
 531                 vpid_sync_vcpu_all(vmx);
 532         }
 533
 534         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 535                 u8 error;
 536
 537                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 538                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
 539                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 540                               : "cc");
 541                 if (error)
 542                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 543                                vmx->vmcs, phys_addr);
 544         }
 545
 546         if (vcpu->cpu != cpu) {
 547                 struct descriptor_table dt;
 548                 unsigned long sysenter_esp;
 549
 550                 vcpu->cpu = cpu;
 551                 /*
 552                  * Linux uses per-cpu TSS and GDT, so set these when switching
 553                  * processors.
 554                  */
 555                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 556                 get_gdt(&dt);
 557                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 558
 559                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 560                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 561
 562                 /*
 563                  * Make sure the time stamp counter is monotonous.
 564                  */
 565                 rdtscll(tsc_this);
 566                 if (tsc_this < vcpu->arch.host_tsc) {
 567                         delta = vcpu->arch.host_tsc - tsc_this;
 568                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 569                         vmcs_write64(TSC_OFFSET, new_offset);
 570                 }
 571         }
 572 }
 573
 574 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 575 {
 576         vmx_load_host_state(to_vmx(vcpu));
 577 }
 578
 579 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 580 {
 581         if (vcpu->fpu_active)
 582                 return;
 583         vcpu->fpu_active = 1;
 584         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 585         if (vcpu->arch.cr0 & X86_CR0_TS)
 586                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 587         update_exception_bitmap(vcpu);
 588 }
 589
 590 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 591 {
 592         if (!vcpu->fpu_active)
 593                 return;
 594         vcpu->fpu_active = 0;
 595         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 596         update_exception_bitmap(vcpu);
 597 }
 598
 599 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 600 {
 601         vcpu_clear(to_vmx(vcpu));
 602 }
 603
 604 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 605 {
 606         return vmcs_readl(GUEST_RFLAGS);
 607 }
 608
 609 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 610 {
 611         if (vcpu->arch.rmode.active)
 612                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 613         vmcs_writel(GUEST_RFLAGS, rflags);
 614 }
 615
 616 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 617 {
 618         unsigned long rip;
 619         u32 interruptibility;
 620
 621         rip = vmcs_readl(GUEST_RIP);
 622         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 623         vmcs_writel(GUEST_RIP, rip);
 624
 625         /*
 626          * We emulated an instruction, so temporary interrupt blocking
 627          * should be removed, if set.
 628          */
 629         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 630         if (interruptibility & 3)
 631                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 632                              interruptibility & ~3);
 633         vcpu->arch.interrupt_window_open = 1;
 634 }
 635
 636 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 637                                 bool has_error_code, u32 error_code)
 638 {
 639         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 640                      nr | INTR_TYPE_EXCEPTION
 641                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 642                      | INTR_INFO_VALID_MASK);
 643         if (has_error_code)
 644                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 645 }
 646
 647 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 648 {
 649         struct vcpu_vmx *vmx = to_vmx(vcpu);
 650
 651         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
 652 }
 653
 654 /*
 655  * Swap MSR entry in host/guest MSR entry array.
 656  */
 657 #ifdef CONFIG_X86_64
 658 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 659 {
 660         struct kvm_msr_entry tmp;
 661
 662         tmp = vmx->guest_msrs[to];
 663         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 664         vmx->guest_msrs[from] = tmp;
 665         tmp = vmx->host_msrs[to];
 666         vmx->host_msrs[to] = vmx->host_msrs[from];
 667         vmx->host_msrs[from] = tmp;
 668 }
 669 #endif
 670
 671 /*
 672  * Set up the vmcs to automatically save and restore system
 673  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 674  * mode, as fiddling with msrs is very expensive.
 675  */
 676 static void setup_msrs(struct vcpu_vmx *vmx)
 677 {
 678         int save_nmsrs;
 679
 680         vmx_load_host_state(vmx);
 681         save_nmsrs = 0;
 682 #ifdef CONFIG_X86_64
 683         if (is_long_mode(&vmx->vcpu)) {
 684                 int index;
 685
 686                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 687                 if (index >= 0)
 688                         move_msr_up(vmx, index, save_nmsrs++);
 689                 index = __find_msr_index(vmx, MSR_LSTAR);
 690                 if (index >= 0)
 691                         move_msr_up(vmx, index, save_nmsrs++);
 692                 index = __find_msr_index(vmx, MSR_CSTAR);
 693                 if (index >= 0)
 694                         move_msr_up(vmx, index, save_nmsrs++);
 695                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 696                 if (index >= 0)
 697                         move_msr_up(vmx, index, save_nmsrs++);
 698                 /*
 699                  * MSR_K6_STAR is only needed on long mode guests, and only
 700                  * if efer.sce is enabled.
 701                  */
 702                 index = __find_msr_index(vmx, MSR_K6_STAR);
 703                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 704                         move_msr_up(vmx, index, save_nmsrs++);
 705         }
 706 #endif
 707         vmx->save_nmsrs = save_nmsrs;
 708
 709 #ifdef CONFIG_X86_64
 710         vmx->msr_offset_kernel_gs_base =
 711                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 712 #endif
 713         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 714 }
 715
 716 /*
 717  * reads and returns guest's timestamp counter "register"
 718  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 719  */
 720 static u64 guest_read_tsc(void)
 721 {
 722         u64 host_tsc, tsc_offset;
 723
 724         rdtscll(host_tsc);
 725         tsc_offset = vmcs_read64(TSC_OFFSET);
 726         return host_tsc + tsc_offset;
 727 }
 728
 729 /*
 730  * writes 'guest_tsc' into guest's timestamp counter "register"
 731  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 732  */
 733 static void guest_write_tsc(u64 guest_tsc)
 734 {
 735         u64 host_tsc;
 736
 737         rdtscll(host_tsc);
 738         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 739 }
 740
 741 /*
 742  * Reads an msr value (of 'msr_index') into 'pdata'.
 743  * Returns 0 on success, non-0 otherwise.
 744  * Assumes vcpu_load() was already called.
 745  */
 746 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 747 {
 748         u64 data;
 749         struct kvm_msr_entry *msr;
 750
 751         if (!pdata) {
 752                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 753                 return -EINVAL;
 754         }
 755
 756         switch (msr_index) {
 757 #ifdef CONFIG_X86_64
 758         case MSR_FS_BASE:
 759                 data = vmcs_readl(GUEST_FS_BASE);
 760                 break;
 761         case MSR_GS_BASE:
 762                 data = vmcs_readl(GUEST_GS_BASE);
 763                 break;
 764         case MSR_EFER:
 765                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 766 #endif
 767         case MSR_IA32_TIME_STAMP_COUNTER:
 768                 data = guest_read_tsc();
 769                 break;
 770         case MSR_IA32_SYSENTER_CS:
 771                 data = vmcs_read32(GUEST_SYSENTER_CS);
 772                 break;
 773         case MSR_IA32_SYSENTER_EIP:
 774                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 775                 break;
 776         case MSR_IA32_SYSENTER_ESP:
 777                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 778                 break;
 779         default:
 780                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 781                 if (msr) {
 782                         data = msr->data;
 783                         break;
 784                 }
 785                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 786         }
 787
 788         *pdata = data;
 789         return 0;
 790 }
 791
 792 /*
 793  * Writes msr value into into the appropriate "register".
 794  * Returns 0 on success, non-0 otherwise.
 795  * Assumes vcpu_load() was already called.
 796  */
 797 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 798 {
 799         struct vcpu_vmx *vmx = to_vmx(vcpu);
 800         struct kvm_msr_entry *msr;
 801         int ret = 0;
 802
 803         switch (msr_index) {
 804 #ifdef CONFIG_X86_64
 805         case MSR_EFER:
 806                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 807                 if (vmx->host_state.loaded) {
 808                         reload_host_efer(vmx);
 809                         load_transition_efer(vmx);
 810                 }
 811                 break;
 812         case MSR_FS_BASE:
 813                 vmcs_writel(GUEST_FS_BASE, data);
 814                 break;
 815         case MSR_GS_BASE:
 816                 vmcs_writel(GUEST_GS_BASE, data);
 817                 break;
 818 #endif
 819         case MSR_IA32_SYSENTER_CS:
 820                 vmcs_write32(GUEST_SYSENTER_CS, data);
 821                 break;
 822         case MSR_IA32_SYSENTER_EIP:
 823                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 824                 break;
 825         case MSR_IA32_SYSENTER_ESP:
 826                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 827                 break;
 828         case MSR_IA32_TIME_STAMP_COUNTER:
 829                 guest_write_tsc(data);
 830                 break;
 831         default:
 832                 msr = find_msr_entry(vmx, msr_index);
 833                 if (msr) {
 834                         msr->data = data;
 835                         if (vmx->host_state.loaded)
 836                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 837                         break;
 838                 }
 839                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 840         }
 841
 842         return ret;
 843 }
 844
 845 /*
 846  * Sync the rsp and rip registers into the vcpu structure.  This allows
 847  * registers to be accessed by indexing vcpu->arch.regs.
 848  */
 849 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 850 {
 851         vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 852         vcpu->arch.rip = vmcs_readl(GUEST_RIP);
 853 }
 854
 855 /*
 856  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 857  * modification.
 858  */
 859 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 860 {
 861         vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
 862         vmcs_writel(GUEST_RIP, vcpu->arch.rip);
 863 }
 864
 865 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 866 {
 867         unsigned long dr7 = 0x400;
 868         int old_singlestep;
 869
 870         old_singlestep = vcpu->guest_debug.singlestep;
 871
 872         vcpu->guest_debug.enabled = dbg->enabled;
 873         if (vcpu->guest_debug.enabled) {
 874                 int i;
 875
 876                 dr7 |= 0x200;  /* exact */
 877                 for (i = 0; i < 4; ++i) {
 878                         if (!dbg->breakpoints[i].enabled)
 879                                 continue;
 880                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 881                         dr7 |= 2 << (i*2);    /* global enable */
 882                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 883                 }
 884
 885                 vcpu->guest_debug.singlestep = dbg->singlestep;
 886         } else
 887                 vcpu->guest_debug.singlestep = 0;
 888
 889         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 890                 unsigned long flags;
 891
 892                 flags = vmcs_readl(GUEST_RFLAGS);
 893                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 894                 vmcs_writel(GUEST_RFLAGS, flags);
 895         }
 896
 897         update_exception_bitmap(vcpu);
 898         vmcs_writel(GUEST_DR7, dr7);
 899
 900         return 0;
 901 }
 902
 903 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 904 {
 905         struct vcpu_vmx *vmx = to_vmx(vcpu);
 906         u32 idtv_info_field;
 907
 908         idtv_info_field = vmx->idt_vectoring_info;
 909         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 910                 if (is_external_interrupt(idtv_info_field))
 911                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 912                 else
 913                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 914         }
 915         return -1;
 916 }
 917
 918 static __init int cpu_has_kvm_support(void)
 919 {
 920         unsigned long ecx = cpuid_ecx(1);
 921         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
 922 }
 923
 924 static __init int vmx_disabled_by_bios(void)
 925 {
 926         u64 msr;
 927
 928         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 929         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 930                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 931             == MSR_IA32_FEATURE_CONTROL_LOCKED;
 932         /* locked but not enabled */
 933 }
 934
 935 static void hardware_enable(void *garbage)
 936 {
 937         int cpu = raw_smp_processor_id();
 938         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 939         u64 old;
 940
 941         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
 942         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 943                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 944             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
 945                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 946                 /* enable and lock */
 947                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
 948                        MSR_IA32_FEATURE_CONTROL_LOCKED |
 949                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
 950         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
 951         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
 952                       : "memory", "cc");
 953 }
 954
 955 static void hardware_disable(void *garbage)
 956 {
 957         asm volatile (ASM_VMX_VMXOFF : : : "cc");
 958 }
 959
 960 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 961                                       u32 msr, u32 *result)
 962 {
 963         u32 vmx_msr_low, vmx_msr_high;
 964         u32 ctl = ctl_min | ctl_opt;
 965
 966         rdmsr(msr, vmx_msr_low, vmx_msr_high);
 967
 968         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
 969         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
 970
 971         /* Ensure minimum (required) set of control bits are supported. */
 972         if (ctl_min & ~ctl)
 973                 return -EIO;
 974
 975         *result = ctl;
 976         return 0;
 977 }
 978
 979 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 980 {
 981         u32 vmx_msr_low, vmx_msr_high;
 982         u32 min, opt;
 983         u32 _pin_based_exec_control = 0;
 984         u32 _cpu_based_exec_control = 0;
 985         u32 _cpu_based_2nd_exec_control = 0;
 986         u32 _vmexit_control = 0;
 987         u32 _vmentry_control = 0;
 988
 989         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
 990         opt = 0;
 991         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
 992                                 &_pin_based_exec_control) < 0)
 993                 return -EIO;
 994
 995         min = CPU_BASED_HLT_EXITING |
 996 #ifdef CONFIG_X86_64
 997               CPU_BASED_CR8_LOAD_EXITING |
 998               CPU_BASED_CR8_STORE_EXITING |
 999 #endif
1000               CPU_BASED_USE_IO_BITMAPS |
1001               CPU_BASED_MOV_DR_EXITING |
1002               CPU_BASED_USE_TSC_OFFSETING;
1003         opt = CPU_BASED_TPR_SHADOW |
1004               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1005         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1006                                 &_cpu_based_exec_control) < 0)
1007                 return -EIO;
1008 #ifdef CONFIG_X86_64
1009         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1010                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1011                                            ~CPU_BASED_CR8_STORE_EXITING;
1012 #endif
1013         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1014                 min = 0;
1015                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1016                         SECONDARY_EXEC_WBINVD_EXITING |
1017                         SECONDARY_EXEC_ENABLE_VPID;
1018                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
1019                                         &_cpu_based_2nd_exec_control) < 0)
1020                         return -EIO;
1021         }
1022 #ifndef CONFIG_X86_64
1023         if (!(_cpu_based_2nd_exec_control &
1024                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1025                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1026 #endif
1027
1028         min = 0;
1029 #ifdef CONFIG_X86_64
1030         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1031 #endif
1032         opt = 0;
1033         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1034                                 &_vmexit_control) < 0)
1035                 return -EIO;
1036
1037         min = opt = 0;
1038         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1039                                 &_vmentry_control) < 0)
1040                 return -EIO;
1041
1042         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1043
1044         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1045         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1046                 return -EIO;
1047
1048 #ifdef CONFIG_X86_64
1049         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1050         if (vmx_msr_high & (1u<<16))
1051                 return -EIO;
1052 #endif
1053
1054         /* Require Write-Back (WB) memory type for VMCS accesses. */
1055         if (((vmx_msr_high >> 18) & 15) != 6)
1056                 return -EIO;
1057
1058         vmcs_conf->size = vmx_msr_high & 0x1fff;
1059         vmcs_conf->order = get_order(vmcs_config.size);
1060         vmcs_conf->revision_id = vmx_msr_low;
1061
1062         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1063         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1064         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1065         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1066         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1067
1068         return 0;
1069 }
1070
1071 static struct vmcs *alloc_vmcs_cpu(int cpu)
1072 {
1073         int node = cpu_to_node(cpu);
1074         struct page *pages;
1075         struct vmcs *vmcs;
1076
1077         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1078         if (!pages)
1079                 return NULL;
1080         vmcs = page_address(pages);
1081         memset(vmcs, 0, vmcs_config.size);
1082         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1083         return vmcs;
1084 }
1085
1086 static struct vmcs *alloc_vmcs(void)
1087 {
1088         return alloc_vmcs_cpu(raw_smp_processor_id());
1089 }
1090
1091 static void free_vmcs(struct vmcs *vmcs)
1092 {
1093         free_pages((unsigned long)vmcs, vmcs_config.order);
1094 }
1095
1096 static void free_kvm_area(void)
1097 {
1098         int cpu;
1099
1100         for_each_online_cpu(cpu)
1101                 free_vmcs(per_cpu(vmxarea, cpu));
1102 }
1103
1104 static __init int alloc_kvm_area(void)
1105 {
1106         int cpu;
1107
1108         for_each_online_cpu(cpu) {
1109                 struct vmcs *vmcs;
1110
1111                 vmcs = alloc_vmcs_cpu(cpu);
1112                 if (!vmcs) {
1113                         free_kvm_area();
1114                         return -ENOMEM;
1115                 }
1116
1117                 per_cpu(vmxarea, cpu) = vmcs;
1118         }
1119         return 0;
1120 }
1121
1122 static __init int hardware_setup(void)
1123 {
1124         if (setup_vmcs_config(&vmcs_config) < 0)
1125                 return -EIO;
1126
1127         if (boot_cpu_has(X86_FEATURE_NX))
1128                 kvm_enable_efer_bits(EFER_NX);
1129
1130         return alloc_kvm_area();
1131 }
1132
1133 static __exit void hardware_unsetup(void)
1134 {
1135         free_kvm_area();
1136 }
1137
1138 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1139 {
1140         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1141
1142         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1143                 vmcs_write16(sf->selector, save->selector);
1144                 vmcs_writel(sf->base, save->base);
1145                 vmcs_write32(sf->limit, save->limit);
1146                 vmcs_write32(sf->ar_bytes, save->ar);
1147         } else {
1148                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1149                         << AR_DPL_SHIFT;
1150                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1151         }
1152 }
1153
1154 static void enter_pmode(struct kvm_vcpu *vcpu)
1155 {
1156         unsigned long flags;
1157
1158         vcpu->arch.rmode.active = 0;
1159
1160         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1161         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1162         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1163
1164         flags = vmcs_readl(GUEST_RFLAGS);
1165         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1166         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1167         vmcs_writel(GUEST_RFLAGS, flags);
1168
1169         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1170                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1171
1172         update_exception_bitmap(vcpu);
1173
1174         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1175         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1176         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1177         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1178
1179         vmcs_write16(GUEST_SS_SELECTOR, 0);
1180         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1181
1182         vmcs_write16(GUEST_CS_SELECTOR,
1183                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1184         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1185 }
1186
1187 static gva_t rmode_tss_base(struct kvm *kvm)
1188 {
1189         if (!kvm->arch.tss_addr) {
1190                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1191                                  kvm->memslots[0].npages - 3;
1192                 return base_gfn << PAGE_SHIFT;
1193         }
1194         return kvm->arch.tss_addr;
1195 }
1196
1197 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1198 {
1199         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1200
1201         save->selector = vmcs_read16(sf->selector);
1202         save->base = vmcs_readl(sf->base);
1203         save->limit = vmcs_read32(sf->limit);
1204         save->ar = vmcs_read32(sf->ar_bytes);
1205         vmcs_write16(sf->selector, save->base >> 4);
1206         vmcs_write32(sf->base, save->base & 0xfffff);
1207         vmcs_write32(sf->limit, 0xffff);
1208         vmcs_write32(sf->ar_bytes, 0xf3);
1209 }
1210
1211 static void enter_rmode(struct kvm_vcpu *vcpu)
1212 {
1213         unsigned long flags;
1214
1215         vcpu->arch.rmode.active = 1;
1216
1217         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1218         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1219
1220         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1221         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1222
1223         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1224         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1225
1226         flags = vmcs_readl(GUEST_RFLAGS);
1227         vcpu->arch.rmode.save_iopl
1228                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1229
1230         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1231
1232         vmcs_writel(GUEST_RFLAGS, flags);
1233         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1234         update_exception_bitmap(vcpu);
1235
1236         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1237         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1238         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1239
1240         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1241         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1242         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1243                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1244         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1245
1246         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1247         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1248         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1249         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1250
1251         kvm_mmu_reset_context(vcpu);
1252         init_rmode_tss(vcpu->kvm);
1253 }
1254
1255 #ifdef CONFIG_X86_64
1256
1257 static void enter_lmode(struct kvm_vcpu *vcpu)
1258 {
1259         u32 guest_tr_ar;
1260
1261         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1262         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1263                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1264                        __func__);
1265                 vmcs_write32(GUEST_TR_AR_BYTES,
1266                              (guest_tr_ar & ~AR_TYPE_MASK)
1267                              | AR_TYPE_BUSY_64_TSS);
1268         }
1269
1270         vcpu->arch.shadow_efer |= EFER_LMA;
1271
1272         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1273         vmcs_write32(VM_ENTRY_CONTROLS,
1274                      vmcs_read32(VM_ENTRY_CONTROLS)
1275                      | VM_ENTRY_IA32E_MODE);
1276 }
1277
1278 static void exit_lmode(struct kvm_vcpu *vcpu)
1279 {
1280         vcpu->arch.shadow_efer &= ~EFER_LMA;
1281
1282         vmcs_write32(VM_ENTRY_CONTROLS,
1283                      vmcs_read32(VM_ENTRY_CONTROLS)
1284                      & ~VM_ENTRY_IA32E_MODE);
1285 }
1286
1287 #endif
1288
1289 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1290 {
1291         vpid_sync_vcpu_all(to_vmx(vcpu));
1292 }
1293
1294 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1295 {
1296         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1297         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1298 }
1299
1300 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1301 {
1302         vmx_fpu_deactivate(vcpu);
1303
1304         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1305                 enter_pmode(vcpu);
1306
1307         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1308                 enter_rmode(vcpu);
1309
1310 #ifdef CONFIG_X86_64
1311         if (vcpu->arch.shadow_efer & EFER_LME) {
1312                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1313                         enter_lmode(vcpu);
1314                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1315                         exit_lmode(vcpu);
1316         }
1317 #endif
1318
1319         vmcs_writel(CR0_READ_SHADOW, cr0);
1320         vmcs_writel(GUEST_CR0,
1321                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1322         vcpu->arch.cr0 = cr0;
1323
1324         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1325                 vmx_fpu_activate(vcpu);
1326 }
1327
1328 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1329 {
1330         vmx_flush_tlb(vcpu);
1331         vmcs_writel(GUEST_CR3, cr3);
1332         if (vcpu->arch.cr0 & X86_CR0_PE)
1333                 vmx_fpu_deactivate(vcpu);
1334 }
1335
1336 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1337 {
1338         vmcs_writel(CR4_READ_SHADOW, cr4);
1339         vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
1340                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1341         vcpu->arch.cr4 = cr4;
1342 }
1343
1344 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1345 {
1346         struct vcpu_vmx *vmx = to_vmx(vcpu);
1347         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1348
1349         vcpu->arch.shadow_efer = efer;
1350         if (!msr)
1351                 return;
1352         if (efer & EFER_LMA) {
1353                 vmcs_write32(VM_ENTRY_CONTROLS,
1354                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1355                                      VM_ENTRY_IA32E_MODE);
1356                 msr->data = efer;
1357
1358         } else {
1359                 vmcs_write32(VM_ENTRY_CONTROLS,
1360                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1361                                      ~VM_ENTRY_IA32E_MODE);
1362
1363                 msr->data = efer & ~EFER_LME;
1364         }
1365         setup_msrs(vmx);
1366 }
1367
1368 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1369 {
1370         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1371
1372         return vmcs_readl(sf->base);
1373 }
1374
1375 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1376                             struct kvm_segment *var, int seg)
1377 {
1378         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1379         u32 ar;
1380
1381         var->base = vmcs_readl(sf->base);
1382         var->limit = vmcs_read32(sf->limit);
1383         var->selector = vmcs_read16(sf->selector);
1384         ar = vmcs_read32(sf->ar_bytes);
1385         if (ar & AR_UNUSABLE_MASK)
1386                 ar = 0;
1387         var->type = ar & 15;
1388         var->s = (ar >> 4) & 1;
1389         var->dpl = (ar >> 5) & 3;
1390         var->present = (ar >> 7) & 1;
1391         var->avl = (ar >> 12) & 1;
1392         var->l = (ar >> 13) & 1;
1393         var->db = (ar >> 14) & 1;
1394         var->g = (ar >> 15) & 1;
1395         var->unusable = (ar >> 16) & 1;
1396 }
1397
1398 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1399 {
1400         u32 ar;
1401
1402         if (var->unusable)
1403                 ar = 1 << 16;
1404         else {
1405                 ar = var->type & 15;
1406                 ar |= (var->s & 1) << 4;
1407                 ar |= (var->dpl & 3) << 5;
1408                 ar |= (var->present & 1) << 7;
1409                 ar |= (var->avl & 1) << 12;
1410                 ar |= (var->l & 1) << 13;
1411                 ar |= (var->db & 1) << 14;
1412                 ar |= (var->g & 1) << 15;
1413         }
1414         if (ar == 0) /* a 0 value means unusable */
1415                 ar = AR_UNUSABLE_MASK;
1416
1417         return ar;
1418 }
1419
1420 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1421                             struct kvm_segment *var, int seg)
1422 {
1423         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1424         u32 ar;
1425
1426         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1427                 vcpu->arch.rmode.tr.selector = var->selector;
1428                 vcpu->arch.rmode.tr.base = var->base;
1429                 vcpu->arch.rmode.tr.limit = var->limit;
1430                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1431                 return;
1432         }
1433         vmcs_writel(sf->base, var->base);
1434         vmcs_write32(sf->limit, var->limit);
1435         vmcs_write16(sf->selector, var->selector);
1436         if (vcpu->arch.rmode.active && var->s) {
1437                 /*
1438                  * Hack real-mode segments into vm86 compatibility.
1439                  */
1440                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1441                         vmcs_writel(sf->base, 0xf0000);
1442                 ar = 0xf3;
1443         } else
1444                 ar = vmx_segment_access_rights(var);
1445         vmcs_write32(sf->ar_bytes, ar);
1446 }
1447
1448 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1449 {
1450         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1451
1452         *db = (ar >> 14) & 1;
1453         *l = (ar >> 13) & 1;
1454 }
1455
1456 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1457 {
1458         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1459         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1460 }
1461
1462 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1463 {
1464         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1465         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1466 }
1467
1468 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1469 {
1470         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1471         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1472 }
1473
1474 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1475 {
1476         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1477         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1478 }
1479
1480 static int init_rmode_tss(struct kvm *kvm)
1481 {
1482         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1483         u16 data = 0;
1484         int ret = 0;
1485         int r;
1486
1487         down_read(&kvm->slots_lock);
1488         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1489         if (r < 0)
1490                 goto out;
1491         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1492         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1493         if (r < 0)
1494                 goto out;
1495         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1496         if (r < 0)
1497                 goto out;
1498         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1499         if (r < 0)
1500                 goto out;
1501         data = ~0;
1502         r = kvm_write_guest_page(kvm, fn, &data,
1503                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1504                                  sizeof(u8));
1505         if (r < 0)
1506                 goto out;
1507
1508         ret = 1;
1509 out:
1510         up_read(&kvm->slots_lock);
1511         return ret;
1512 }
1513
1514 static void seg_setup(int seg)
1515 {
1516         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1517
1518         vmcs_write16(sf->selector, 0);
1519         vmcs_writel(sf->base, 0);
1520         vmcs_write32(sf->limit, 0xffff);
1521         vmcs_write32(sf->ar_bytes, 0x93);
1522 }
1523
1524 static int alloc_apic_access_page(struct kvm *kvm)
1525 {
1526         struct kvm_userspace_memory_region kvm_userspace_mem;
1527         int r = 0;
1528
1529         down_write(&kvm->slots_lock);
1530         if (kvm->arch.apic_access_page)
1531                 goto out;
1532         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1533         kvm_userspace_mem.flags = 0;
1534         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1535         kvm_userspace_mem.memory_size = PAGE_SIZE;
1536         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1537         if (r)
1538                 goto out;
1539
1540         down_read(&current->mm->mmap_sem);
1541         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1542         up_read(&current->mm->mmap_sem);
1543 out:
1544         up_write(&kvm->slots_lock);
1545         return r;
1546 }
1547
1548 static void allocate_vpid(struct vcpu_vmx *vmx)
1549 {
1550         int vpid;
1551
1552         vmx->vpid = 0;
1553         if (!enable_vpid || !cpu_has_vmx_vpid())
1554                 return;
1555         spin_lock(&vmx_vpid_lock);
1556         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1557         if (vpid < VMX_NR_VPIDS) {
1558                 vmx->vpid = vpid;
1559                 __set_bit(vpid, vmx_vpid_bitmap);
1560         }
1561         spin_unlock(&vmx_vpid_lock);
1562 }
1563
1564 /*
1565  * Sets up the vmcs for emulated real mode.
1566  */
1567 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1568 {
1569         u32 host_sysenter_cs;
1570         u32 junk;
1571         unsigned long a;
1572         struct descriptor_table dt;
1573         int i;
1574         unsigned long kvm_vmx_return;
1575         u32 exec_control;
1576
1577         /* I/O */
1578         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1579         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1580
1581         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1582
1583         /* Control */
1584         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1585                 vmcs_config.pin_based_exec_ctrl);
1586
1587         exec_control = vmcs_config.cpu_based_exec_ctrl;
1588         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1589                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1590 #ifdef CONFIG_X86_64
1591                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1592                                 CPU_BASED_CR8_LOAD_EXITING;
1593 #endif
1594         }
1595         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1596
1597         if (cpu_has_secondary_exec_ctrls()) {
1598                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1599                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1600                         exec_control &=
1601                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1602                 if (vmx->vpid == 0)
1603                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1604                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1605         }
1606
1607         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1608         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1609         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1610
1611         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1612         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1613         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1614
1615         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1616         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1617         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1618         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1619         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1620         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1621 #ifdef CONFIG_X86_64
1622         rdmsrl(MSR_FS_BASE, a);
1623         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1624         rdmsrl(MSR_GS_BASE, a);
1625         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1626 #else
1627         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1628         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1629 #endif
1630
1631         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1632
1633         get_idt(&dt);
1634         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1635
1636         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1637         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1638         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1639         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1640         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1641
1642         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1643         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1644         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1645         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1646         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1647         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1648
1649         for (i = 0; i < NR_VMX_MSR; ++i) {
1650                 u32 index = vmx_msr_index[i];
1651                 u32 data_low, data_high;
1652                 u64 data;
1653                 int j = vmx->nmsrs;
1654
1655                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1656                         continue;
1657                 if (wrmsr_safe(index, data_low, data_high) < 0)
1658                         continue;
1659                 data = data_low | ((u64)data_high << 32);
1660                 vmx->host_msrs[j].index = index;
1661                 vmx->host_msrs[j].reserved = 0;
1662                 vmx->host_msrs[j].data = data;
1663                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1664                 ++vmx->nmsrs;
1665         }
1666
1667         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1668
1669         /* 22.2.1, 20.8.1 */
1670         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1671
1672         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1673         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1674
1675
1676         return 0;
1677 }
1678
1679 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1680 {
1681         struct vcpu_vmx *vmx = to_vmx(vcpu);
1682         u64 msr;
1683         int ret;
1684
1685         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1686                 ret = -ENOMEM;
1687                 goto out;
1688         }
1689
1690         vmx->vcpu.arch.rmode.active = 0;
1691
1692         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1693         kvm_set_cr8(&vmx->vcpu, 0);
1694         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1695         if (vmx->vcpu.vcpu_id == 0)
1696                 msr |= MSR_IA32_APICBASE_BSP;
1697         kvm_set_apic_base(&vmx->vcpu, msr);
1698
1699         fx_init(&vmx->vcpu);
1700
1701         /*
1702          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1703          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1704          */
1705         if (vmx->vcpu.vcpu_id == 0) {
1706                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1707                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1708         } else {
1709                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1710                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
1711         }
1712         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1713         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1714
1715         seg_setup(VCPU_SREG_DS);
1716         seg_setup(VCPU_SREG_ES);
1717         seg_setup(VCPU_SREG_FS);
1718         seg_setup(VCPU_SREG_GS);
1719         seg_setup(VCPU_SREG_SS);
1720
1721         vmcs_write16(GUEST_TR_SELECTOR, 0);
1722         vmcs_writel(GUEST_TR_BASE, 0);
1723         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1724         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1725
1726         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1727         vmcs_writel(GUEST_LDTR_BASE, 0);
1728         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1729         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1730
1731         vmcs_write32(GUEST_SYSENTER_CS, 0);
1732         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1733         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1734
1735         vmcs_writel(GUEST_RFLAGS, 0x02);
1736         if (vmx->vcpu.vcpu_id == 0)
1737                 vmcs_writel(GUEST_RIP, 0xfff0);
1738         else
1739                 vmcs_writel(GUEST_RIP, 0);
1740         vmcs_writel(GUEST_RSP, 0);
1741
1742         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1743         vmcs_writel(GUEST_DR7, 0x400);
1744
1745         vmcs_writel(GUEST_GDTR_BASE, 0);
1746         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1747
1748         vmcs_writel(GUEST_IDTR_BASE, 0);
1749         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1750
1751         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1752         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1753         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1754
1755         guest_write_tsc(0);
1756
1757         /* Special registers */
1758         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1759
1760         setup_msrs(vmx);
1761
1762         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1763
1764         if (cpu_has_vmx_tpr_shadow()) {
1765                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1766                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1767                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1768                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
1769                 vmcs_write32(TPR_THRESHOLD, 0);
1770         }
1771
1772         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1773                 vmcs_write64(APIC_ACCESS_ADDR,
1774                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
1775
1776         if (vmx->vpid != 0)
1777                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
1778
1779         vmx->vcpu.arch.cr0 = 0x60000010;
1780         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
1781         vmx_set_cr4(&vmx->vcpu, 0);
1782         vmx_set_efer(&vmx->vcpu, 0);
1783         vmx_fpu_activate(&vmx->vcpu);
1784         update_exception_bitmap(&vmx->vcpu);
1785
1786         vpid_sync_vcpu_all(vmx);
1787
1788         return 0;
1789
1790 out:
1791         return ret;
1792 }
1793
1794 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1795 {
1796         struct vcpu_vmx *vmx = to_vmx(vcpu);
1797
1798         if (vcpu->arch.rmode.active) {
1799                 vmx->rmode.irq.pending = true;
1800                 vmx->rmode.irq.vector = irq;
1801                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1802                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1803                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1804                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1805                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1806                 return;
1807         }
1808         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1809                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1810 }
1811
1812 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1813 {
1814         int word_index = __ffs(vcpu->arch.irq_summary);
1815         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1816         int irq = word_index * BITS_PER_LONG + bit_index;
1817
1818         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1819         if (!vcpu->arch.irq_pending[word_index])
1820                 clear_bit(word_index, &vcpu->arch.irq_summary);
1821         vmx_inject_irq(vcpu, irq);
1822 }
1823
1824
1825 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1826                                        struct kvm_run *kvm_run)
1827 {
1828         u32 cpu_based_vm_exec_control;
1829
1830         vcpu->arch.interrupt_window_open =
1831                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1832                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1833
1834         if (vcpu->arch.interrupt_window_open &&
1835             vcpu->arch.irq_summary &&
1836             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1837                 /*
1838                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1839                  */
1840                 kvm_do_inject_irq(vcpu);
1841
1842         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1843         if (!vcpu->arch.interrupt_window_open &&
1844             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
1845                 /*
1846                  * Interrupts blocked.  Wait for unblock.
1847                  */
1848                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1849         else
1850                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1851         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1852 }
1853
1854 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1855 {
1856         int ret;
1857         struct kvm_userspace_memory_region tss_mem = {
1858                 .slot = 8,
1859                 .guest_phys_addr = addr,
1860                 .memory_size = PAGE_SIZE * 3,
1861                 .flags = 0,
1862         };
1863
1864         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1865         if (ret)
1866                 return ret;
1867         kvm->arch.tss_addr = addr;
1868         return 0;
1869 }
1870
1871 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1872 {
1873         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1874
1875         set_debugreg(dbg->bp[0], 0);
1876         set_debugreg(dbg->bp[1], 1);
1877         set_debugreg(dbg->bp[2], 2);
1878         set_debugreg(dbg->bp[3], 3);
1879
1880         if (dbg->singlestep) {
1881                 unsigned long flags;
1882
1883                 flags = vmcs_readl(GUEST_RFLAGS);
1884                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1885                 vmcs_writel(GUEST_RFLAGS, flags);
1886         }
1887 }
1888
1889 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1890                                   int vec, u32 err_code)
1891 {
1892         if (!vcpu->arch.rmode.active)
1893                 return 0;
1894
1895         /*
1896          * Instruction with address size override prefix opcode 0x67
1897          * Cause the #SS fault with 0 error code in VM86 mode.
1898          */
1899         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1900                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1901                         return 1;
1902         return 0;
1903 }
1904
1905 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1906 {
1907         struct vcpu_vmx *vmx = to_vmx(vcpu);
1908         u32 intr_info, error_code;
1909         unsigned long cr2, rip;
1910         u32 vect_info;
1911         enum emulation_result er;
1912
1913         vect_info = vmx->idt_vectoring_info;
1914         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1915
1916         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1917                                                 !is_page_fault(intr_info))
1918                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1919                        "intr info 0x%x\n", __func__, vect_info, intr_info);
1920
1921         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1922                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1923                 set_bit(irq, vcpu->arch.irq_pending);
1924                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
1925         }
1926
1927         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1928                 return 1;  /* already handled by vmx_vcpu_run() */
1929
1930         if (is_no_device(intr_info)) {
1931                 vmx_fpu_activate(vcpu);
1932                 return 1;
1933         }
1934
1935         if (is_invalid_opcode(intr_info)) {
1936                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1937                 if (er != EMULATE_DONE)
1938                         kvm_queue_exception(vcpu, UD_VECTOR);
1939                 return 1;
1940         }
1941
1942         error_code = 0;
1943         rip = vmcs_readl(GUEST_RIP);
1944         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
1945                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1946         if (is_page_fault(intr_info)) {
1947                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1948                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1949         }
1950
1951         if (vcpu->arch.rmode.active &&
1952             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1953                                                                 error_code)) {
1954                 if (vcpu->arch.halt_request) {
1955                         vcpu->arch.halt_request = 0;
1956                         return kvm_emulate_halt(vcpu);
1957                 }
1958                 return 1;
1959         }
1960
1961         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1962             (INTR_TYPE_EXCEPTION | 1)) {
1963                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1964                 return 0;
1965         }
1966         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1967         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1968         kvm_run->ex.error_code = error_code;
1969         return 0;
1970 }
1971
1972 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1973                                      struct kvm_run *kvm_run)
1974 {
1975         ++vcpu->stat.irq_exits;
1976         return 1;
1977 }
1978
1979 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1980 {
1981         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1982         return 0;
1983 }
1984
1985 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1986 {
1987         unsigned long exit_qualification;
1988         int size, down, in, string, rep;
1989         unsigned port;
1990
1991         ++vcpu->stat.io_exits;
1992         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1993         string = (exit_qualification & 16) != 0;
1994
1995         if (string) {
1996                 if (emulate_instruction(vcpu,
1997                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1998                         return 0;
1999                 return 1;
2000         }
2001
2002         size = (exit_qualification & 7) + 1;
2003         in = (exit_qualification & 8) != 0;
2004         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2005         rep = (exit_qualification & 32) != 0;
2006         port = exit_qualification >> 16;
2007
2008         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2009 }
2010
2011 static void
2012 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2013 {
2014         /*
2015          * Patch in the VMCALL instruction:
2016          */
2017         hypercall[0] = 0x0f;
2018         hypercall[1] = 0x01;
2019         hypercall[2] = 0xc1;
2020 }
2021
2022 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2023 {
2024         unsigned long exit_qualification;
2025         int cr;
2026         int reg;
2027
2028         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2029         cr = exit_qualification & 15;
2030         reg = (exit_qualification >> 8) & 15;
2031         switch ((exit_qualification >> 4) & 3) {
2032         case 0: /* mov to cr */
2033                 switch (cr) {
2034                 case 0:
2035                         vcpu_load_rsp_rip(vcpu);
2036                         kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2037                         skip_emulated_instruction(vcpu);
2038                         return 1;
2039                 case 3:
2040                         vcpu_load_rsp_rip(vcpu);
2041                         kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2042                         skip_emulated_instruction(vcpu);
2043                         return 1;
2044                 case 4:
2045                         vcpu_load_rsp_rip(vcpu);
2046                         kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2047                         skip_emulated_instruction(vcpu);
2048                         return 1;
2049                 case 8:
2050                         vcpu_load_rsp_rip(vcpu);
2051                         kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2052                         skip_emulated_instruction(vcpu);
2053                         if (irqchip_in_kernel(vcpu->kvm))
2054                                 return 1;
2055                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2056                         return 0;
2057                 };
2058                 break;
2059         case 2: /* clts */
2060                 vcpu_load_rsp_rip(vcpu);
2061                 vmx_fpu_deactivate(vcpu);
2062                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2063                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2064                 vmx_fpu_activate(vcpu);
2065                 skip_emulated_instruction(vcpu);
2066                 return 1;
2067         case 1: /*mov from cr*/
2068                 switch (cr) {
2069                 case 3:
2070                         vcpu_load_rsp_rip(vcpu);
2071                         vcpu->arch.regs[reg] = vcpu->arch.cr3;
2072                         vcpu_put_rsp_rip(vcpu);
2073                         skip_emulated_instruction(vcpu);
2074                         return 1;
2075                 case 8:
2076                         vcpu_load_rsp_rip(vcpu);
2077                         vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2078                         vcpu_put_rsp_rip(vcpu);
2079                         skip_emulated_instruction(vcpu);
2080                         return 1;
2081                 }
2082                 break;
2083         case 3: /* lmsw */
2084                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2085
2086                 skip_emulated_instruction(vcpu);
2087                 return 1;
2088         default:
2089                 break;
2090         }
2091         kvm_run->exit_reason = 0;
2092         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2093                (int)(exit_qualification >> 4) & 3, cr);
2094         return 0;
2095 }
2096
2097 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2098 {
2099         unsigned long exit_qualification;
2100         unsigned long val;
2101         int dr, reg;
2102
2103         /*
2104          * FIXME: this code assumes the host is debugging the guest.
2105          *        need to deal with guest debugging itself too.
2106          */
2107         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2108         dr = exit_qualification & 7;
2109         reg = (exit_qualification >> 8) & 15;
2110         vcpu_load_rsp_rip(vcpu);
2111         if (exit_qualification & 16) {
2112                 /* mov from dr */
2113                 switch (dr) {
2114                 case 6:
2115                         val = 0xffff0ff0;
2116                         break;
2117                 case 7:
2118                         val = 0x400;
2119                         break;
2120                 default:
2121                         val = 0;
2122                 }
2123                 vcpu->arch.regs[reg] = val;
2124         } else {
2125                 /* mov to dr */
2126         }
2127         vcpu_put_rsp_rip(vcpu);
2128         skip_emulated_instruction(vcpu);
2129         return 1;
2130 }
2131
2132 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2133 {
2134         kvm_emulate_cpuid(vcpu);
2135         return 1;
2136 }
2137
2138 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2139 {
2140         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2141         u64 data;
2142
2143         if (vmx_get_msr(vcpu, ecx, &data)) {
2144                 kvm_inject_gp(vcpu, 0);
2145                 return 1;
2146         }
2147
2148         /* FIXME: handling of bits 32:63 of rax, rdx */
2149         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2150         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2151         skip_emulated_instruction(vcpu);
2152         return 1;
2153 }
2154
2155 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2156 {
2157         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2158         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2159                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2160
2161         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2162                 kvm_inject_gp(vcpu, 0);
2163                 return 1;
2164         }
2165
2166         skip_emulated_instruction(vcpu);
2167         return 1;
2168 }
2169
2170 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2171                                       struct kvm_run *kvm_run)
2172 {
2173         return 1;
2174 }
2175
2176 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2177                                    struct kvm_run *kvm_run)
2178 {
2179         u32 cpu_based_vm_exec_control;
2180
2181         /* clear pending irq */
2182         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2183         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2184         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2185         /*
2186          * If the user space waits to inject interrupts, exit as soon as
2187          * possible
2188          */
2189         if (kvm_run->request_interrupt_window &&
2190             !vcpu->arch.irq_summary) {
2191                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2192                 ++vcpu->stat.irq_window_exits;
2193                 return 0;
2194         }
2195         return 1;
2196 }
2197
2198 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2199 {
2200         skip_emulated_instruction(vcpu);
2201         return kvm_emulate_halt(vcpu);
2202 }
2203
2204 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2205 {
2206         skip_emulated_instruction(vcpu);
2207         kvm_emulate_hypercall(vcpu);
2208         return 1;
2209 }
2210
2211 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2212 {
2213         skip_emulated_instruction(vcpu);
2214         /* TODO: Add support for VT-d/pass-through device */
2215         return 1;
2216 }
2217
2218 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2219 {
2220         u64 exit_qualification;
2221         enum emulation_result er;
2222         unsigned long offset;
2223
2224         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2225         offset = exit_qualification & 0xffful;
2226
2227         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2228
2229         if (er !=  EMULATE_DONE) {
2230                 printk(KERN_ERR
2231                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2232                        offset);
2233                 return -ENOTSUPP;
2234         }
2235         return 1;
2236 }
2237
2238 /*
2239  * The exit handlers return 1 if the exit was handled fully and guest execution
2240  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2241  * to be done to userspace and return 0.
2242  */
2243 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2244                                       struct kvm_run *kvm_run) = {
2245         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2246         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2247         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2248         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2249         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2250         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2251         [EXIT_REASON_CPUID]                   = handle_cpuid,
2252         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2253         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2254         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2255         [EXIT_REASON_HLT]                     = handle_halt,
2256         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2257         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2258         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2259         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2260 };
2261
2262 static const int kvm_vmx_max_exit_handlers =
2263         ARRAY_SIZE(kvm_vmx_exit_handlers);
2264
2265 /*
2266  * The guest has exited.  See if we can fix it or if we need userspace
2267  * assistance.
2268  */
2269 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2270 {
2271         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2272         struct vcpu_vmx *vmx = to_vmx(vcpu);
2273         u32 vectoring_info = vmx->idt_vectoring_info;
2274
2275         if (unlikely(vmx->fail)) {
2276                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2277                 kvm_run->fail_entry.hardware_entry_failure_reason
2278                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2279                 return 0;
2280         }
2281
2282         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2283                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2284                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2285                        "exit reason is 0x%x\n", __func__, exit_reason);
2286         if (exit_reason < kvm_vmx_max_exit_handlers
2287             && kvm_vmx_exit_handlers[exit_reason])
2288                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2289         else {
2290                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2291                 kvm_run->hw.hardware_exit_reason = exit_reason;
2292         }
2293         return 0;
2294 }
2295
2296 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2297 {
2298         int max_irr, tpr;
2299
2300         if (!vm_need_tpr_shadow(vcpu->kvm))
2301                 return;
2302
2303         if (!kvm_lapic_enabled(vcpu) ||
2304             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2305                 vmcs_write32(TPR_THRESHOLD, 0);
2306                 return;
2307         }
2308
2309         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2310         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2311 }
2312
2313 static void enable_irq_window(struct kvm_vcpu *vcpu)
2314 {
2315         u32 cpu_based_vm_exec_control;
2316
2317         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2318         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2319         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2320 }
2321
2322 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2323 {
2324         struct vcpu_vmx *vmx = to_vmx(vcpu);
2325         u32 idtv_info_field, intr_info_field;
2326         int has_ext_irq, interrupt_window_open;
2327         int vector;
2328
2329         update_tpr_threshold(vcpu);
2330
2331         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2332         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2333         idtv_info_field = vmx->idt_vectoring_info;
2334         if (intr_info_field & INTR_INFO_VALID_MASK) {
2335                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2336                         /* TODO: fault when IDT_Vectoring */
2337                         if (printk_ratelimit())
2338                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2339                 }
2340                 if (has_ext_irq)
2341                         enable_irq_window(vcpu);
2342                 return;
2343         }
2344         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2345                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2346                     == INTR_TYPE_EXT_INTR
2347                     && vcpu->arch.rmode.active) {
2348                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2349
2350                         vmx_inject_irq(vcpu, vect);
2351                         if (unlikely(has_ext_irq))
2352                                 enable_irq_window(vcpu);
2353                         return;
2354                 }
2355
2356                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2357                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2358                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2359
2360                 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2361                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2362                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2363                 if (unlikely(has_ext_irq))
2364                         enable_irq_window(vcpu);
2365                 return;
2366         }
2367         if (!has_ext_irq)
2368                 return;
2369         interrupt_window_open =
2370                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2371                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2372         if (interrupt_window_open) {
2373                 vector = kvm_cpu_get_interrupt(vcpu);
2374                 vmx_inject_irq(vcpu, vector);
2375                 kvm_timer_intr_post(vcpu, vector);
2376         } else
2377                 enable_irq_window(vcpu);
2378 }
2379
2380 /*
2381  * Failure to inject an interrupt should give us the information
2382  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2383  * when fetching the interrupt redirection bitmap in the real-mode
2384  * tss, this doesn't happen.  So we do it ourselves.
2385  */
2386 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2387 {
2388         vmx->rmode.irq.pending = 0;
2389         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2390                 return;
2391         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2392         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2393                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2394                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2395                 return;
2396         }
2397         vmx->idt_vectoring_info =
2398                 VECTORING_INFO_VALID_MASK
2399                 | INTR_TYPE_EXT_INTR
2400                 | vmx->rmode.irq.vector;
2401 }
2402
2403 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2404 {
2405         struct vcpu_vmx *vmx = to_vmx(vcpu);
2406         u32 intr_info;
2407
2408         /*
2409          * Loading guest fpu may have cleared host cr0.ts
2410          */
2411         vmcs_writel(HOST_CR0, read_cr0());
2412
2413         asm(
2414                 /* Store host registers */
2415 #ifdef CONFIG_X86_64
2416                 "push %%rdx; push %%rbp;"
2417                 "push %%rcx \n\t"
2418 #else
2419                 "push %%edx; push %%ebp;"
2420                 "push %%ecx \n\t"
2421 #endif
2422                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2423                 /* Check if vmlaunch of vmresume is needed */
2424                 "cmpl $0, %c[launched](%0) \n\t"
2425                 /* Load guest registers.  Don't clobber flags. */
2426 #ifdef CONFIG_X86_64
2427                 "mov %c[cr2](%0), %%rax \n\t"
2428                 "mov %%rax, %%cr2 \n\t"
2429                 "mov %c[rax](%0), %%rax \n\t"
2430                 "mov %c[rbx](%0), %%rbx \n\t"
2431                 "mov %c[rdx](%0), %%rdx \n\t"
2432                 "mov %c[rsi](%0), %%rsi \n\t"
2433                 "mov %c[rdi](%0), %%rdi \n\t"
2434                 "mov %c[rbp](%0), %%rbp \n\t"
2435                 "mov %c[r8](%0),  %%r8  \n\t"
2436                 "mov %c[r9](%0),  %%r9  \n\t"
2437                 "mov %c[r10](%0), %%r10 \n\t"
2438                 "mov %c[r11](%0), %%r11 \n\t"
2439                 "mov %c[r12](%0), %%r12 \n\t"
2440                 "mov %c[r13](%0), %%r13 \n\t"
2441                 "mov %c[r14](%0), %%r14 \n\t"
2442                 "mov %c[r15](%0), %%r15 \n\t"
2443                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2444 #else
2445                 "mov %c[cr2](%0), %%eax \n\t"
2446                 "mov %%eax,   %%cr2 \n\t"
2447                 "mov %c[rax](%0), %%eax \n\t"
2448                 "mov %c[rbx](%0), %%ebx \n\t"
2449                 "mov %c[rdx](%0), %%edx \n\t"
2450                 "mov %c[rsi](%0), %%esi \n\t"
2451                 "mov %c[rdi](%0), %%edi \n\t"
2452                 "mov %c[rbp](%0), %%ebp \n\t"
2453                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2454 #endif
2455                 /* Enter guest mode */
2456                 "jne .Llaunched \n\t"
2457                 ASM_VMX_VMLAUNCH "\n\t"
2458                 "jmp .Lkvm_vmx_return \n\t"
2459                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2460                 ".Lkvm_vmx_return: "
2461                 /* Save guest registers, load host registers, keep flags */
2462 #ifdef CONFIG_X86_64
2463                 "xchg %0,     (%%rsp) \n\t"
2464                 "mov %%rax, %c[rax](%0) \n\t"
2465                 "mov %%rbx, %c[rbx](%0) \n\t"
2466                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2467                 "mov %%rdx, %c[rdx](%0) \n\t"
2468                 "mov %%rsi, %c[rsi](%0) \n\t"
2469                 "mov %%rdi, %c[rdi](%0) \n\t"
2470                 "mov %%rbp, %c[rbp](%0) \n\t"
2471                 "mov %%r8,  %c[r8](%0) \n\t"
2472                 "mov %%r9,  %c[r9](%0) \n\t"
2473                 "mov %%r10, %c[r10](%0) \n\t"
2474                 "mov %%r11, %c[r11](%0) \n\t"
2475                 "mov %%r12, %c[r12](%0) \n\t"
2476                 "mov %%r13, %c[r13](%0) \n\t"
2477                 "mov %%r14, %c[r14](%0) \n\t"
2478                 "mov %%r15, %c[r15](%0) \n\t"
2479                 "mov %%cr2, %%rax   \n\t"
2480                 "mov %%rax, %c[cr2](%0) \n\t"
2481
2482                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2483 #else
2484                 "xchg %0, (%%esp) \n\t"
2485                 "mov %%eax, %c[rax](%0) \n\t"
2486                 "mov %%ebx, %c[rbx](%0) \n\t"
2487                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2488                 "mov %%edx, %c[rdx](%0) \n\t"
2489                 "mov %%esi, %c[rsi](%0) \n\t"
2490                 "mov %%edi, %c[rdi](%0) \n\t"
2491                 "mov %%ebp, %c[rbp](%0) \n\t"
2492                 "mov %%cr2, %%eax  \n\t"
2493                 "mov %%eax, %c[cr2](%0) \n\t"
2494
2495                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2496 #endif
2497                 "setbe %c[fail](%0) \n\t"
2498               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2499                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2500                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2501                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2502                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2503                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2504                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2505                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2506                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2507                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2508 #ifdef CONFIG_X86_64
2509                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2510                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2511                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2512                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2513                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2514                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2515                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2516                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2517 #endif
2518                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2519               : "cc", "memory"
2520 #ifdef CONFIG_X86_64
2521                 , "rbx", "rdi", "rsi"
2522                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2523 #else
2524                 , "ebx", "edi", "rsi"
2525 #endif
2526               );
2527
2528         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2529         if (vmx->rmode.irq.pending)
2530                 fixup_rmode_irq(vmx);
2531
2532         vcpu->arch.interrupt_window_open =
2533                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2534
2535         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2536         vmx->launched = 1;
2537
2538         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2539
2540         /* We need to handle NMIs before interrupts are enabled */
2541         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2542                 asm("int $2");
2543 }
2544
2545 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2546 {
2547         struct vcpu_vmx *vmx = to_vmx(vcpu);
2548
2549         if (vmx->vmcs) {
2550                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2551                 free_vmcs(vmx->vmcs);
2552                 vmx->vmcs = NULL;
2553         }
2554 }
2555
2556 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2557 {
2558         struct vcpu_vmx *vmx = to_vmx(vcpu);
2559
2560         spin_lock(&vmx_vpid_lock);
2561         if (vmx->vpid != 0)
2562                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2563         spin_unlock(&vmx_vpid_lock);
2564         vmx_free_vmcs(vcpu);
2565         kfree(vmx->host_msrs);
2566         kfree(vmx->guest_msrs);
2567         kvm_vcpu_uninit(vcpu);
2568         kmem_cache_free(kvm_vcpu_cache, vmx);
2569 }
2570
2571 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2572 {
2573         int err;
2574         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2575         int cpu;
2576
2577         if (!vmx)
2578                 return ERR_PTR(-ENOMEM);
2579
2580         allocate_vpid(vmx);
2581
2582         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2583         if (err)
2584                 goto free_vcpu;
2585
2586         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2587         if (!vmx->guest_msrs) {
2588                 err = -ENOMEM;
2589                 goto uninit_vcpu;
2590         }
2591
2592         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2593         if (!vmx->host_msrs)
2594                 goto free_guest_msrs;
2595
2596         vmx->vmcs = alloc_vmcs();
2597         if (!vmx->vmcs)
2598                 goto free_msrs;
2599
2600         vmcs_clear(vmx->vmcs);
2601
2602         cpu = get_cpu();
2603         vmx_vcpu_load(&vmx->vcpu, cpu);
2604         err = vmx_vcpu_setup(vmx);
2605         vmx_vcpu_put(&vmx->vcpu);
2606         put_cpu();
2607         if (err)
2608                 goto free_vmcs;
2609         if (vm_need_virtualize_apic_accesses(kvm))
2610                 if (alloc_apic_access_page(kvm) != 0)
2611                         goto free_vmcs;
2612
2613         return &vmx->vcpu;
2614
2615 free_vmcs:
2616         free_vmcs(vmx->vmcs);
2617 free_msrs:
2618         kfree(vmx->host_msrs);
2619 free_guest_msrs:
2620         kfree(vmx->guest_msrs);
2621 uninit_vcpu:
2622         kvm_vcpu_uninit(&vmx->vcpu);
2623 free_vcpu:
2624         kmem_cache_free(kvm_vcpu_cache, vmx);
2625         return ERR_PTR(err);
2626 }
2627
2628 static void __init vmx_check_processor_compat(void *rtn)
2629 {
2630         struct vmcs_config vmcs_conf;
2631
2632         *(int *)rtn = 0;
2633         if (setup_vmcs_config(&vmcs_conf) < 0)
2634                 *(int *)rtn = -EIO;
2635         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2636                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2637                                 smp_processor_id());
2638                 *(int *)rtn = -EIO;
2639         }
2640 }
2641
2642 static struct kvm_x86_ops vmx_x86_ops = {
2643         .cpu_has_kvm_support = cpu_has_kvm_support,
2644         .disabled_by_bios = vmx_disabled_by_bios,
2645         .hardware_setup = hardware_setup,
2646         .hardware_unsetup = hardware_unsetup,
2647         .check_processor_compatibility = vmx_check_processor_compat,
2648         .hardware_enable = hardware_enable,
2649         .hardware_disable = hardware_disable,
2650         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
2651
2652         .vcpu_create = vmx_create_vcpu,
2653         .vcpu_free = vmx_free_vcpu,
2654         .vcpu_reset = vmx_vcpu_reset,
2655
2656         .prepare_guest_switch = vmx_save_host_state,
2657         .vcpu_load = vmx_vcpu_load,
2658         .vcpu_put = vmx_vcpu_put,
2659         .vcpu_decache = vmx_vcpu_decache,
2660
2661         .set_guest_debug = set_guest_debug,
2662         .guest_debug_pre = kvm_guest_debug_pre,
2663         .get_msr = vmx_get_msr,
2664         .set_msr = vmx_set_msr,
2665         .get_segment_base = vmx_get_segment_base,
2666         .get_segment = vmx_get_segment,
2667         .set_segment = vmx_set_segment,
2668         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2669         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2670         .set_cr0 = vmx_set_cr0,
2671         .set_cr3 = vmx_set_cr3,
2672         .set_cr4 = vmx_set_cr4,
2673         .set_efer = vmx_set_efer,
2674         .get_idt = vmx_get_idt,
2675         .set_idt = vmx_set_idt,
2676         .get_gdt = vmx_get_gdt,
2677         .set_gdt = vmx_set_gdt,
2678         .cache_regs = vcpu_load_rsp_rip,
2679         .decache_regs = vcpu_put_rsp_rip,
2680         .get_rflags = vmx_get_rflags,
2681         .set_rflags = vmx_set_rflags,
2682
2683         .tlb_flush = vmx_flush_tlb,
2684
2685         .run = vmx_vcpu_run,
2686         .handle_exit = kvm_handle_exit,
2687         .skip_emulated_instruction = skip_emulated_instruction,
2688         .patch_hypercall = vmx_patch_hypercall,
2689         .get_irq = vmx_get_irq,
2690         .set_irq = vmx_inject_irq,
2691         .queue_exception = vmx_queue_exception,
2692         .exception_injected = vmx_exception_injected,
2693         .inject_pending_irq = vmx_intr_assist,
2694         .inject_pending_vectors = do_interrupt_requests,
2695
2696         .set_tss_addr = vmx_set_tss_addr,
2697 };
2698
2699 static int __init vmx_init(void)
2700 {
2701         void *iova;
2702         int r;
2703
2704         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2705         if (!vmx_io_bitmap_a)
2706                 return -ENOMEM;
2707
2708         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2709         if (!vmx_io_bitmap_b) {
2710                 r = -ENOMEM;
2711                 goto out;
2712         }
2713
2714         /*
2715          * Allow direct access to the PC debug port (it is often used for I/O
2716          * delays, but the vmexits simply slow things down).
2717          */
2718         iova = kmap(vmx_io_bitmap_a);
2719         memset(iova, 0xff, PAGE_SIZE);
2720         clear_bit(0x80, iova);
2721         kunmap(vmx_io_bitmap_a);
2722
2723         iova = kmap(vmx_io_bitmap_b);
2724         memset(iova, 0xff, PAGE_SIZE);
2725         kunmap(vmx_io_bitmap_b);
2726
2727         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
2728
2729         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2730         if (r)
2731                 goto out1;
2732
2733         if (bypass_guest_pf)
2734                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2735
2736         return 0;
2737
2738 out1:
2739         __free_page(vmx_io_bitmap_b);
2740 out:
2741         __free_page(vmx_io_bitmap_a);
2742         return r;
2743 }
2744
2745 static void __exit vmx_exit(void)
2746 {
2747         __free_page(vmx_io_bitmap_b);
2748         __free_page(vmx_io_bitmap_a);
2749
2750         kvm_exit();
2751 }
2752
2753 module_init(vmx_init)
2754 module_exit(vmx_exit)