2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include "kvm_cache_regs.h"
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
40 static int bypass_guest_pf = 1;
41 module_param(bypass_guest_pf, bool, 0);
43 static int enable_vpid = 1;
44 module_param(enable_vpid, bool, 0);
46 static int flexpriority_enabled = 1;
47 module_param(flexpriority_enabled, bool, 0);
49 static int enable_ept = 1;
50 module_param(enable_ept, bool, 0);
52 static int emulate_invalid_guest_state = 0;
53 module_param(emulate_invalid_guest_state, bool, 0);
63 struct list_head local_vcpus_link;
64 unsigned long host_rsp;
67 u32 idt_vectoring_info;
68 struct kvm_msr_entry *guest_msrs;
69 struct kvm_msr_entry *host_msrs;
74 int msr_offset_kernel_gs_base;
79 u16 fs_sel, gs_sel, ldt_sel;
80 int gs_ldt_reload_needed;
82 int guest_efer_loaded;
92 bool emulation_required;
95 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
97 return container_of(vcpu, struct vcpu_vmx, vcpu);
100 static int init_rmode(struct kvm *kvm);
101 static u64 construct_eptp(unsigned long root_hpa);
103 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
104 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
105 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
107 static struct page *vmx_io_bitmap_a;
108 static struct page *vmx_io_bitmap_b;
109 static struct page *vmx_msr_bitmap;
111 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
112 static DEFINE_SPINLOCK(vmx_vpid_lock);
114 static struct vmcs_config {
118 u32 pin_based_exec_ctrl;
119 u32 cpu_based_exec_ctrl;
120 u32 cpu_based_2nd_exec_ctrl;
125 struct vmx_capability {
130 #define VMX_SEGMENT_FIELD(seg) \
131 [VCPU_SREG_##seg] = { \
132 .selector = GUEST_##seg##_SELECTOR, \
133 .base = GUEST_##seg##_BASE, \
134 .limit = GUEST_##seg##_LIMIT, \
135 .ar_bytes = GUEST_##seg##_AR_BYTES, \
138 static struct kvm_vmx_segment_field {
143 } kvm_vmx_segment_fields[] = {
144 VMX_SEGMENT_FIELD(CS),
145 VMX_SEGMENT_FIELD(DS),
146 VMX_SEGMENT_FIELD(ES),
147 VMX_SEGMENT_FIELD(FS),
148 VMX_SEGMENT_FIELD(GS),
149 VMX_SEGMENT_FIELD(SS),
150 VMX_SEGMENT_FIELD(TR),
151 VMX_SEGMENT_FIELD(LDTR),
155 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
156 * away by decrementing the array size.
158 static const u32 vmx_msr_index[] = {
160 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
162 MSR_EFER, MSR_K6_STAR,
164 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
166 static void load_msrs(struct kvm_msr_entry *e, int n)
170 for (i = 0; i < n; ++i)
171 wrmsrl(e[i].index, e[i].data);
174 static void save_msrs(struct kvm_msr_entry *e, int n)
178 for (i = 0; i < n; ++i)
179 rdmsrl(e[i].index, e[i].data);
182 static inline int is_page_fault(u32 intr_info)
184 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
185 INTR_INFO_VALID_MASK)) ==
186 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
189 static inline int is_no_device(u32 intr_info)
191 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
192 INTR_INFO_VALID_MASK)) ==
193 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
196 static inline int is_invalid_opcode(u32 intr_info)
198 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
199 INTR_INFO_VALID_MASK)) ==
200 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
203 static inline int is_external_interrupt(u32 intr_info)
205 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
206 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
209 static inline int cpu_has_vmx_msr_bitmap(void)
211 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
214 static inline int cpu_has_vmx_tpr_shadow(void)
216 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
219 static inline int vm_need_tpr_shadow(struct kvm *kvm)
221 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
224 static inline int cpu_has_secondary_exec_ctrls(void)
226 return (vmcs_config.cpu_based_exec_ctrl &
227 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
230 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
232 return flexpriority_enabled
233 && (vmcs_config.cpu_based_2nd_exec_ctrl &
234 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
237 static inline int cpu_has_vmx_invept_individual_addr(void)
239 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
242 static inline int cpu_has_vmx_invept_context(void)
244 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
247 static inline int cpu_has_vmx_invept_global(void)
249 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
252 static inline int cpu_has_vmx_ept(void)
254 return (vmcs_config.cpu_based_2nd_exec_ctrl &
255 SECONDARY_EXEC_ENABLE_EPT);
258 static inline int vm_need_ept(void)
260 return (cpu_has_vmx_ept() && enable_ept);
263 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
265 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
266 (irqchip_in_kernel(kvm)));
269 static inline int cpu_has_vmx_vpid(void)
271 return (vmcs_config.cpu_based_2nd_exec_ctrl &
272 SECONDARY_EXEC_ENABLE_VPID);
275 static inline int cpu_has_virtual_nmis(void)
277 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
280 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
284 for (i = 0; i < vmx->nmsrs; ++i)
285 if (vmx->guest_msrs[i].index == msr)
290 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
296 } operand = { vpid, 0, gva };
298 asm volatile (__ex(ASM_VMX_INVVPID)
299 /* CF==1 or ZF==1 --> rc = -1 */
301 : : "a"(&operand), "c"(ext) : "cc", "memory");
304 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
308 } operand = {eptp, gpa};
310 asm volatile (__ex(ASM_VMX_INVEPT)
311 /* CF==1 or ZF==1 --> rc = -1 */
312 "; ja 1f ; ud2 ; 1:\n"
313 : : "a" (&operand), "c" (ext) : "cc", "memory");
316 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
320 i = __find_msr_index(vmx, msr);
322 return &vmx->guest_msrs[i];
326 static void vmcs_clear(struct vmcs *vmcs)
328 u64 phys_addr = __pa(vmcs);
331 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
332 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
335 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
339 static void __vcpu_clear(void *arg)
341 struct vcpu_vmx *vmx = arg;
342 int cpu = raw_smp_processor_id();
344 if (vmx->vcpu.cpu == cpu)
345 vmcs_clear(vmx->vmcs);
346 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
347 per_cpu(current_vmcs, cpu) = NULL;
348 rdtscll(vmx->vcpu.arch.host_tsc);
349 list_del(&vmx->local_vcpus_link);
354 static void vcpu_clear(struct vcpu_vmx *vmx)
356 if (vmx->vcpu.cpu == -1)
358 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
361 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
366 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
369 static inline void ept_sync_global(void)
371 if (cpu_has_vmx_invept_global())
372 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
375 static inline void ept_sync_context(u64 eptp)
378 if (cpu_has_vmx_invept_context())
379 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
385 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
388 if (cpu_has_vmx_invept_individual_addr())
389 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
392 ept_sync_context(eptp);
396 static unsigned long vmcs_readl(unsigned long field)
400 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
401 : "=a"(value) : "d"(field) : "cc");
405 static u16 vmcs_read16(unsigned long field)
407 return vmcs_readl(field);
410 static u32 vmcs_read32(unsigned long field)
412 return vmcs_readl(field);
415 static u64 vmcs_read64(unsigned long field)
418 return vmcs_readl(field);
420 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
424 static noinline void vmwrite_error(unsigned long field, unsigned long value)
426 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
427 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
431 static void vmcs_writel(unsigned long field, unsigned long value)
435 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
436 : "=q"(error) : "a"(value), "d"(field) : "cc");
438 vmwrite_error(field, value);
441 static void vmcs_write16(unsigned long field, u16 value)
443 vmcs_writel(field, value);
446 static void vmcs_write32(unsigned long field, u32 value)
448 vmcs_writel(field, value);
451 static void vmcs_write64(unsigned long field, u64 value)
453 vmcs_writel(field, value);
454 #ifndef CONFIG_X86_64
456 vmcs_writel(field+1, value >> 32);
460 static void vmcs_clear_bits(unsigned long field, u32 mask)
462 vmcs_writel(field, vmcs_readl(field) & ~mask);
465 static void vmcs_set_bits(unsigned long field, u32 mask)
467 vmcs_writel(field, vmcs_readl(field) | mask);
470 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
474 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
475 if (!vcpu->fpu_active)
476 eb |= 1u << NM_VECTOR;
477 if (vcpu->guest_debug.enabled)
478 eb |= 1u << DB_VECTOR;
479 if (vcpu->arch.rmode.active)
482 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
483 vmcs_write32(EXCEPTION_BITMAP, eb);
486 static void reload_tss(void)
489 * VT restores TR but not its size. Useless.
491 struct descriptor_table gdt;
492 struct desc_struct *descs;
495 descs = (void *)gdt.base;
496 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
500 static void load_transition_efer(struct vcpu_vmx *vmx)
502 int efer_offset = vmx->msr_offset_efer;
503 u64 host_efer = vmx->host_msrs[efer_offset].data;
504 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
510 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
513 ignore_bits = EFER_NX | EFER_SCE;
515 ignore_bits |= EFER_LMA | EFER_LME;
516 /* SCE is meaningful only in long mode on Intel */
517 if (guest_efer & EFER_LMA)
518 ignore_bits &= ~(u64)EFER_SCE;
520 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
523 vmx->host_state.guest_efer_loaded = 1;
524 guest_efer &= ~ignore_bits;
525 guest_efer |= host_efer & ignore_bits;
526 wrmsrl(MSR_EFER, guest_efer);
527 vmx->vcpu.stat.efer_reload++;
530 static void reload_host_efer(struct vcpu_vmx *vmx)
532 if (vmx->host_state.guest_efer_loaded) {
533 vmx->host_state.guest_efer_loaded = 0;
534 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
538 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
540 struct vcpu_vmx *vmx = to_vmx(vcpu);
542 if (vmx->host_state.loaded)
545 vmx->host_state.loaded = 1;
547 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
548 * allow segment selectors with cpl > 0 or ti == 1.
550 vmx->host_state.ldt_sel = kvm_read_ldt();
551 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
552 vmx->host_state.fs_sel = kvm_read_fs();
553 if (!(vmx->host_state.fs_sel & 7)) {
554 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
555 vmx->host_state.fs_reload_needed = 0;
557 vmcs_write16(HOST_FS_SELECTOR, 0);
558 vmx->host_state.fs_reload_needed = 1;
560 vmx->host_state.gs_sel = kvm_read_gs();
561 if (!(vmx->host_state.gs_sel & 7))
562 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
564 vmcs_write16(HOST_GS_SELECTOR, 0);
565 vmx->host_state.gs_ldt_reload_needed = 1;
569 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
570 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
572 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
573 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
577 if (is_long_mode(&vmx->vcpu))
578 save_msrs(vmx->host_msrs +
579 vmx->msr_offset_kernel_gs_base, 1);
582 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
583 load_transition_efer(vmx);
586 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
590 if (!vmx->host_state.loaded)
593 ++vmx->vcpu.stat.host_state_reload;
594 vmx->host_state.loaded = 0;
595 if (vmx->host_state.fs_reload_needed)
596 kvm_load_fs(vmx->host_state.fs_sel);
597 if (vmx->host_state.gs_ldt_reload_needed) {
598 kvm_load_ldt(vmx->host_state.ldt_sel);
600 * If we have to reload gs, we must take care to
601 * preserve our gs base.
603 local_irq_save(flags);
604 kvm_load_gs(vmx->host_state.gs_sel);
606 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
608 local_irq_restore(flags);
611 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
612 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
613 reload_host_efer(vmx);
616 static void vmx_load_host_state(struct vcpu_vmx *vmx)
619 __vmx_load_host_state(vmx);
624 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
625 * vcpu mutex is already taken.
627 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
629 struct vcpu_vmx *vmx = to_vmx(vcpu);
630 u64 phys_addr = __pa(vmx->vmcs);
631 u64 tsc_this, delta, new_offset;
633 if (vcpu->cpu != cpu) {
635 kvm_migrate_timers(vcpu);
636 vpid_sync_vcpu_all(vmx);
638 list_add(&vmx->local_vcpus_link,
639 &per_cpu(vcpus_on_cpu, cpu));
643 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
646 per_cpu(current_vmcs, cpu) = vmx->vmcs;
647 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
648 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
651 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
652 vmx->vmcs, phys_addr);
655 if (vcpu->cpu != cpu) {
656 struct descriptor_table dt;
657 unsigned long sysenter_esp;
661 * Linux uses per-cpu TSS and GDT, so set these when switching
664 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
666 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
668 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
669 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
672 * Make sure the time stamp counter is monotonous.
675 if (tsc_this < vcpu->arch.host_tsc) {
676 delta = vcpu->arch.host_tsc - tsc_this;
677 new_offset = vmcs_read64(TSC_OFFSET) + delta;
678 vmcs_write64(TSC_OFFSET, new_offset);
683 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
685 __vmx_load_host_state(to_vmx(vcpu));
688 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
690 if (vcpu->fpu_active)
692 vcpu->fpu_active = 1;
693 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
694 if (vcpu->arch.cr0 & X86_CR0_TS)
695 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
696 update_exception_bitmap(vcpu);
699 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
701 if (!vcpu->fpu_active)
703 vcpu->fpu_active = 0;
704 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
705 update_exception_bitmap(vcpu);
708 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
710 return vmcs_readl(GUEST_RFLAGS);
713 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
715 if (vcpu->arch.rmode.active)
716 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
717 vmcs_writel(GUEST_RFLAGS, rflags);
720 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
723 u32 interruptibility;
725 rip = kvm_rip_read(vcpu);
726 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
727 kvm_rip_write(vcpu, rip);
730 * We emulated an instruction, so temporary interrupt blocking
731 * should be removed, if set.
733 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
734 if (interruptibility & 3)
735 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
736 interruptibility & ~3);
737 vcpu->arch.interrupt_window_open = 1;
740 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
741 bool has_error_code, u32 error_code)
743 struct vcpu_vmx *vmx = to_vmx(vcpu);
746 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
748 if (vcpu->arch.rmode.active) {
749 vmx->rmode.irq.pending = true;
750 vmx->rmode.irq.vector = nr;
751 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
753 vmx->rmode.irq.rip++;
754 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
755 nr | INTR_TYPE_SOFT_INTR
756 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
757 | INTR_INFO_VALID_MASK);
758 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
759 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
763 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
764 nr | INTR_TYPE_EXCEPTION
765 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
766 | INTR_INFO_VALID_MASK);
769 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
775 * Swap MSR entry in host/guest MSR entry array.
778 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
780 struct kvm_msr_entry tmp;
782 tmp = vmx->guest_msrs[to];
783 vmx->guest_msrs[to] = vmx->guest_msrs[from];
784 vmx->guest_msrs[from] = tmp;
785 tmp = vmx->host_msrs[to];
786 vmx->host_msrs[to] = vmx->host_msrs[from];
787 vmx->host_msrs[from] = tmp;
792 * Set up the vmcs to automatically save and restore system
793 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
794 * mode, as fiddling with msrs is very expensive.
796 static void setup_msrs(struct vcpu_vmx *vmx)
800 vmx_load_host_state(vmx);
803 if (is_long_mode(&vmx->vcpu)) {
806 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
808 move_msr_up(vmx, index, save_nmsrs++);
809 index = __find_msr_index(vmx, MSR_LSTAR);
811 move_msr_up(vmx, index, save_nmsrs++);
812 index = __find_msr_index(vmx, MSR_CSTAR);
814 move_msr_up(vmx, index, save_nmsrs++);
815 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
817 move_msr_up(vmx, index, save_nmsrs++);
819 * MSR_K6_STAR is only needed on long mode guests, and only
820 * if efer.sce is enabled.
822 index = __find_msr_index(vmx, MSR_K6_STAR);
823 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
824 move_msr_up(vmx, index, save_nmsrs++);
827 vmx->save_nmsrs = save_nmsrs;
830 vmx->msr_offset_kernel_gs_base =
831 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
833 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
837 * reads and returns guest's timestamp counter "register"
838 * guest_tsc = host_tsc + tsc_offset -- 21.3
840 static u64 guest_read_tsc(void)
842 u64 host_tsc, tsc_offset;
845 tsc_offset = vmcs_read64(TSC_OFFSET);
846 return host_tsc + tsc_offset;
850 * writes 'guest_tsc' into guest's timestamp counter "register"
851 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
853 static void guest_write_tsc(u64 guest_tsc)
858 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
862 * Reads an msr value (of 'msr_index') into 'pdata'.
863 * Returns 0 on success, non-0 otherwise.
864 * Assumes vcpu_load() was already called.
866 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
869 struct kvm_msr_entry *msr;
872 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
879 data = vmcs_readl(GUEST_FS_BASE);
882 data = vmcs_readl(GUEST_GS_BASE);
885 return kvm_get_msr_common(vcpu, msr_index, pdata);
887 case MSR_IA32_TIME_STAMP_COUNTER:
888 data = guest_read_tsc();
890 case MSR_IA32_SYSENTER_CS:
891 data = vmcs_read32(GUEST_SYSENTER_CS);
893 case MSR_IA32_SYSENTER_EIP:
894 data = vmcs_readl(GUEST_SYSENTER_EIP);
896 case MSR_IA32_SYSENTER_ESP:
897 data = vmcs_readl(GUEST_SYSENTER_ESP);
900 msr = find_msr_entry(to_vmx(vcpu), msr_index);
905 return kvm_get_msr_common(vcpu, msr_index, pdata);
913 * Writes msr value into into the appropriate "register".
914 * Returns 0 on success, non-0 otherwise.
915 * Assumes vcpu_load() was already called.
917 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
919 struct vcpu_vmx *vmx = to_vmx(vcpu);
920 struct kvm_msr_entry *msr;
926 vmx_load_host_state(vmx);
927 ret = kvm_set_msr_common(vcpu, msr_index, data);
930 vmcs_writel(GUEST_FS_BASE, data);
933 vmcs_writel(GUEST_GS_BASE, data);
936 case MSR_IA32_SYSENTER_CS:
937 vmcs_write32(GUEST_SYSENTER_CS, data);
939 case MSR_IA32_SYSENTER_EIP:
940 vmcs_writel(GUEST_SYSENTER_EIP, data);
942 case MSR_IA32_SYSENTER_ESP:
943 vmcs_writel(GUEST_SYSENTER_ESP, data);
945 case MSR_IA32_TIME_STAMP_COUNTER:
946 guest_write_tsc(data);
948 case MSR_P6_PERFCTR0:
949 case MSR_P6_PERFCTR1:
950 case MSR_P6_EVNTSEL0:
951 case MSR_P6_EVNTSEL1:
953 * Just discard all writes to the performance counters; this
954 * should keep both older linux and windows 64-bit guests
957 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
961 vmx_load_host_state(vmx);
962 msr = find_msr_entry(vmx, msr_index);
967 ret = kvm_set_msr_common(vcpu, msr_index, data);
973 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
975 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
978 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
981 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
988 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
990 unsigned long dr7 = 0x400;
993 old_singlestep = vcpu->guest_debug.singlestep;
995 vcpu->guest_debug.enabled = dbg->enabled;
996 if (vcpu->guest_debug.enabled) {
999 dr7 |= 0x200; /* exact */
1000 for (i = 0; i < 4; ++i) {
1001 if (!dbg->breakpoints[i].enabled)
1003 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1004 dr7 |= 2 << (i*2); /* global enable */
1005 dr7 |= 0 << (i*4+16); /* execution breakpoint */
1008 vcpu->guest_debug.singlestep = dbg->singlestep;
1010 vcpu->guest_debug.singlestep = 0;
1012 if (old_singlestep && !vcpu->guest_debug.singlestep) {
1013 unsigned long flags;
1015 flags = vmcs_readl(GUEST_RFLAGS);
1016 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1017 vmcs_writel(GUEST_RFLAGS, flags);
1020 update_exception_bitmap(vcpu);
1021 vmcs_writel(GUEST_DR7, dr7);
1026 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1028 if (!vcpu->arch.interrupt.pending)
1030 return vcpu->arch.interrupt.nr;
1033 static __init int cpu_has_kvm_support(void)
1035 unsigned long ecx = cpuid_ecx(1);
1036 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1039 static __init int vmx_disabled_by_bios(void)
1043 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1044 return (msr & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1045 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1046 == IA32_FEATURE_CONTROL_LOCKED_BIT;
1047 /* locked but not enabled */
1050 static void hardware_enable(void *garbage)
1052 int cpu = raw_smp_processor_id();
1053 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1056 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1057 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1058 if ((old & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1059 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1060 != (IA32_FEATURE_CONTROL_LOCKED_BIT |
1061 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1062 /* enable and lock */
1063 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1064 IA32_FEATURE_CONTROL_LOCKED_BIT |
1065 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT);
1066 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1067 asm volatile (ASM_VMX_VMXON_RAX
1068 : : "a"(&phys_addr), "m"(phys_addr)
1072 static void vmclear_local_vcpus(void)
1074 int cpu = raw_smp_processor_id();
1075 struct vcpu_vmx *vmx, *n;
1077 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1082 static void hardware_disable(void *garbage)
1084 vmclear_local_vcpus();
1085 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1086 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1089 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1090 u32 msr, u32 *result)
1092 u32 vmx_msr_low, vmx_msr_high;
1093 u32 ctl = ctl_min | ctl_opt;
1095 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1097 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1098 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1100 /* Ensure minimum (required) set of control bits are supported. */
1108 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1110 u32 vmx_msr_low, vmx_msr_high;
1111 u32 min, opt, min2, opt2;
1112 u32 _pin_based_exec_control = 0;
1113 u32 _cpu_based_exec_control = 0;
1114 u32 _cpu_based_2nd_exec_control = 0;
1115 u32 _vmexit_control = 0;
1116 u32 _vmentry_control = 0;
1118 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1119 opt = PIN_BASED_VIRTUAL_NMIS;
1120 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1121 &_pin_based_exec_control) < 0)
1124 min = CPU_BASED_HLT_EXITING |
1125 #ifdef CONFIG_X86_64
1126 CPU_BASED_CR8_LOAD_EXITING |
1127 CPU_BASED_CR8_STORE_EXITING |
1129 CPU_BASED_CR3_LOAD_EXITING |
1130 CPU_BASED_CR3_STORE_EXITING |
1131 CPU_BASED_USE_IO_BITMAPS |
1132 CPU_BASED_MOV_DR_EXITING |
1133 CPU_BASED_USE_TSC_OFFSETING;
1134 opt = CPU_BASED_TPR_SHADOW |
1135 CPU_BASED_USE_MSR_BITMAPS |
1136 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1137 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1138 &_cpu_based_exec_control) < 0)
1140 #ifdef CONFIG_X86_64
1141 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1142 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1143 ~CPU_BASED_CR8_STORE_EXITING;
1145 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1147 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1148 SECONDARY_EXEC_WBINVD_EXITING |
1149 SECONDARY_EXEC_ENABLE_VPID |
1150 SECONDARY_EXEC_ENABLE_EPT;
1151 if (adjust_vmx_controls(min2, opt2,
1152 MSR_IA32_VMX_PROCBASED_CTLS2,
1153 &_cpu_based_2nd_exec_control) < 0)
1156 #ifndef CONFIG_X86_64
1157 if (!(_cpu_based_2nd_exec_control &
1158 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1159 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1161 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1162 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1163 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1164 CPU_BASED_CR3_STORE_EXITING);
1165 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1166 &_cpu_based_exec_control) < 0)
1168 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1169 vmx_capability.ept, vmx_capability.vpid);
1173 #ifdef CONFIG_X86_64
1174 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1177 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1178 &_vmexit_control) < 0)
1182 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1183 &_vmentry_control) < 0)
1186 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1188 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1189 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1192 #ifdef CONFIG_X86_64
1193 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1194 if (vmx_msr_high & (1u<<16))
1198 /* Require Write-Back (WB) memory type for VMCS accesses. */
1199 if (((vmx_msr_high >> 18) & 15) != 6)
1202 vmcs_conf->size = vmx_msr_high & 0x1fff;
1203 vmcs_conf->order = get_order(vmcs_config.size);
1204 vmcs_conf->revision_id = vmx_msr_low;
1206 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1207 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1208 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1209 vmcs_conf->vmexit_ctrl = _vmexit_control;
1210 vmcs_conf->vmentry_ctrl = _vmentry_control;
1215 static struct vmcs *alloc_vmcs_cpu(int cpu)
1217 int node = cpu_to_node(cpu);
1221 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1224 vmcs = page_address(pages);
1225 memset(vmcs, 0, vmcs_config.size);
1226 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1230 static struct vmcs *alloc_vmcs(void)
1232 return alloc_vmcs_cpu(raw_smp_processor_id());
1235 static void free_vmcs(struct vmcs *vmcs)
1237 free_pages((unsigned long)vmcs, vmcs_config.order);
1240 static void free_kvm_area(void)
1244 for_each_online_cpu(cpu)
1245 free_vmcs(per_cpu(vmxarea, cpu));
1248 static __init int alloc_kvm_area(void)
1252 for_each_online_cpu(cpu) {
1255 vmcs = alloc_vmcs_cpu(cpu);
1261 per_cpu(vmxarea, cpu) = vmcs;
1266 static __init int hardware_setup(void)
1268 if (setup_vmcs_config(&vmcs_config) < 0)
1271 if (boot_cpu_has(X86_FEATURE_NX))
1272 kvm_enable_efer_bits(EFER_NX);
1274 return alloc_kvm_area();
1277 static __exit void hardware_unsetup(void)
1282 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1284 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1286 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1287 vmcs_write16(sf->selector, save->selector);
1288 vmcs_writel(sf->base, save->base);
1289 vmcs_write32(sf->limit, save->limit);
1290 vmcs_write32(sf->ar_bytes, save->ar);
1292 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1294 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1298 static void enter_pmode(struct kvm_vcpu *vcpu)
1300 unsigned long flags;
1301 struct vcpu_vmx *vmx = to_vmx(vcpu);
1303 vmx->emulation_required = 1;
1304 vcpu->arch.rmode.active = 0;
1306 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1307 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1308 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1310 flags = vmcs_readl(GUEST_RFLAGS);
1311 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1312 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1313 vmcs_writel(GUEST_RFLAGS, flags);
1315 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1316 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1318 update_exception_bitmap(vcpu);
1320 if (emulate_invalid_guest_state)
1323 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1324 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1325 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1326 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1328 vmcs_write16(GUEST_SS_SELECTOR, 0);
1329 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1331 vmcs_write16(GUEST_CS_SELECTOR,
1332 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1333 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1336 static gva_t rmode_tss_base(struct kvm *kvm)
1338 if (!kvm->arch.tss_addr) {
1339 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1340 kvm->memslots[0].npages - 3;
1341 return base_gfn << PAGE_SHIFT;
1343 return kvm->arch.tss_addr;
1346 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1348 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1350 save->selector = vmcs_read16(sf->selector);
1351 save->base = vmcs_readl(sf->base);
1352 save->limit = vmcs_read32(sf->limit);
1353 save->ar = vmcs_read32(sf->ar_bytes);
1354 vmcs_write16(sf->selector, save->base >> 4);
1355 vmcs_write32(sf->base, save->base & 0xfffff);
1356 vmcs_write32(sf->limit, 0xffff);
1357 vmcs_write32(sf->ar_bytes, 0xf3);
1360 static void enter_rmode(struct kvm_vcpu *vcpu)
1362 unsigned long flags;
1363 struct vcpu_vmx *vmx = to_vmx(vcpu);
1365 vmx->emulation_required = 1;
1366 vcpu->arch.rmode.active = 1;
1368 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1369 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1371 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1372 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1374 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1375 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1377 flags = vmcs_readl(GUEST_RFLAGS);
1378 vcpu->arch.rmode.save_iopl
1379 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1381 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1383 vmcs_writel(GUEST_RFLAGS, flags);
1384 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1385 update_exception_bitmap(vcpu);
1387 if (emulate_invalid_guest_state)
1388 goto continue_rmode;
1390 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1391 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1392 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1394 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1395 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1396 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1397 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1398 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1400 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1401 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1402 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1403 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1406 kvm_mmu_reset_context(vcpu);
1407 init_rmode(vcpu->kvm);
1410 #ifdef CONFIG_X86_64
1412 static void enter_lmode(struct kvm_vcpu *vcpu)
1416 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1417 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1418 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1420 vmcs_write32(GUEST_TR_AR_BYTES,
1421 (guest_tr_ar & ~AR_TYPE_MASK)
1422 | AR_TYPE_BUSY_64_TSS);
1425 vcpu->arch.shadow_efer |= EFER_LMA;
1427 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1428 vmcs_write32(VM_ENTRY_CONTROLS,
1429 vmcs_read32(VM_ENTRY_CONTROLS)
1430 | VM_ENTRY_IA32E_MODE);
1433 static void exit_lmode(struct kvm_vcpu *vcpu)
1435 vcpu->arch.shadow_efer &= ~EFER_LMA;
1437 vmcs_write32(VM_ENTRY_CONTROLS,
1438 vmcs_read32(VM_ENTRY_CONTROLS)
1439 & ~VM_ENTRY_IA32E_MODE);
1444 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1446 vpid_sync_vcpu_all(to_vmx(vcpu));
1448 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1451 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1453 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1454 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1457 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1459 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1460 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1461 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1464 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1465 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1466 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1467 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1471 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1473 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1475 struct kvm_vcpu *vcpu)
1477 if (!(cr0 & X86_CR0_PG)) {
1478 /* From paging/starting to nonpaging */
1479 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1480 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1481 (CPU_BASED_CR3_LOAD_EXITING |
1482 CPU_BASED_CR3_STORE_EXITING));
1483 vcpu->arch.cr0 = cr0;
1484 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1485 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1486 *hw_cr0 &= ~X86_CR0_WP;
1487 } else if (!is_paging(vcpu)) {
1488 /* From nonpaging to paging */
1489 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1490 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1491 ~(CPU_BASED_CR3_LOAD_EXITING |
1492 CPU_BASED_CR3_STORE_EXITING));
1493 vcpu->arch.cr0 = cr0;
1494 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1495 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1496 *hw_cr0 &= ~X86_CR0_WP;
1500 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1501 struct kvm_vcpu *vcpu)
1503 if (!is_paging(vcpu)) {
1504 *hw_cr4 &= ~X86_CR4_PAE;
1505 *hw_cr4 |= X86_CR4_PSE;
1506 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1507 *hw_cr4 &= ~X86_CR4_PAE;
1510 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1512 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1513 KVM_VM_CR0_ALWAYS_ON;
1515 vmx_fpu_deactivate(vcpu);
1517 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1520 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1523 #ifdef CONFIG_X86_64
1524 if (vcpu->arch.shadow_efer & EFER_LME) {
1525 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1527 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1533 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1535 vmcs_writel(CR0_READ_SHADOW, cr0);
1536 vmcs_writel(GUEST_CR0, hw_cr0);
1537 vcpu->arch.cr0 = cr0;
1539 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1540 vmx_fpu_activate(vcpu);
1543 static u64 construct_eptp(unsigned long root_hpa)
1547 /* TODO write the value reading from MSR */
1548 eptp = VMX_EPT_DEFAULT_MT |
1549 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1550 eptp |= (root_hpa & PAGE_MASK);
1555 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1557 unsigned long guest_cr3;
1561 if (vm_need_ept()) {
1562 eptp = construct_eptp(cr3);
1563 vmcs_write64(EPT_POINTER, eptp);
1564 ept_sync_context(eptp);
1565 ept_load_pdptrs(vcpu);
1566 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1567 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1570 vmx_flush_tlb(vcpu);
1571 vmcs_writel(GUEST_CR3, guest_cr3);
1572 if (vcpu->arch.cr0 & X86_CR0_PE)
1573 vmx_fpu_deactivate(vcpu);
1576 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1578 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1579 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1581 vcpu->arch.cr4 = cr4;
1583 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1585 vmcs_writel(CR4_READ_SHADOW, cr4);
1586 vmcs_writel(GUEST_CR4, hw_cr4);
1589 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1591 struct vcpu_vmx *vmx = to_vmx(vcpu);
1592 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1594 vcpu->arch.shadow_efer = efer;
1597 if (efer & EFER_LMA) {
1598 vmcs_write32(VM_ENTRY_CONTROLS,
1599 vmcs_read32(VM_ENTRY_CONTROLS) |
1600 VM_ENTRY_IA32E_MODE);
1604 vmcs_write32(VM_ENTRY_CONTROLS,
1605 vmcs_read32(VM_ENTRY_CONTROLS) &
1606 ~VM_ENTRY_IA32E_MODE);
1608 msr->data = efer & ~EFER_LME;
1613 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1615 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1617 return vmcs_readl(sf->base);
1620 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1621 struct kvm_segment *var, int seg)
1623 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1626 var->base = vmcs_readl(sf->base);
1627 var->limit = vmcs_read32(sf->limit);
1628 var->selector = vmcs_read16(sf->selector);
1629 ar = vmcs_read32(sf->ar_bytes);
1630 if (ar & AR_UNUSABLE_MASK)
1632 var->type = ar & 15;
1633 var->s = (ar >> 4) & 1;
1634 var->dpl = (ar >> 5) & 3;
1635 var->present = (ar >> 7) & 1;
1636 var->avl = (ar >> 12) & 1;
1637 var->l = (ar >> 13) & 1;
1638 var->db = (ar >> 14) & 1;
1639 var->g = (ar >> 15) & 1;
1640 var->unusable = (ar >> 16) & 1;
1643 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1645 struct kvm_segment kvm_seg;
1647 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1650 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1653 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1654 return kvm_seg.selector & 3;
1657 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1664 ar = var->type & 15;
1665 ar |= (var->s & 1) << 4;
1666 ar |= (var->dpl & 3) << 5;
1667 ar |= (var->present & 1) << 7;
1668 ar |= (var->avl & 1) << 12;
1669 ar |= (var->l & 1) << 13;
1670 ar |= (var->db & 1) << 14;
1671 ar |= (var->g & 1) << 15;
1673 if (ar == 0) /* a 0 value means unusable */
1674 ar = AR_UNUSABLE_MASK;
1679 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1680 struct kvm_segment *var, int seg)
1682 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1685 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1686 vcpu->arch.rmode.tr.selector = var->selector;
1687 vcpu->arch.rmode.tr.base = var->base;
1688 vcpu->arch.rmode.tr.limit = var->limit;
1689 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1692 vmcs_writel(sf->base, var->base);
1693 vmcs_write32(sf->limit, var->limit);
1694 vmcs_write16(sf->selector, var->selector);
1695 if (vcpu->arch.rmode.active && var->s) {
1697 * Hack real-mode segments into vm86 compatibility.
1699 if (var->base == 0xffff0000 && var->selector == 0xf000)
1700 vmcs_writel(sf->base, 0xf0000);
1703 ar = vmx_segment_access_rights(var);
1704 vmcs_write32(sf->ar_bytes, ar);
1707 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1709 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1711 *db = (ar >> 14) & 1;
1712 *l = (ar >> 13) & 1;
1715 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1717 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1718 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1721 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1723 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1724 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1727 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1729 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1730 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1733 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1735 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1736 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1739 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1741 struct kvm_segment var;
1744 vmx_get_segment(vcpu, &var, seg);
1745 ar = vmx_segment_access_rights(&var);
1747 if (var.base != (var.selector << 4))
1749 if (var.limit != 0xffff)
1757 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1759 struct kvm_segment cs;
1760 unsigned int cs_rpl;
1762 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1763 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1765 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1769 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1770 if (cs.dpl > cs_rpl)
1772 } else if (cs.type & AR_TYPE_CODE_MASK) {
1773 if (cs.dpl != cs_rpl)
1779 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1783 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1785 struct kvm_segment ss;
1786 unsigned int ss_rpl;
1788 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1789 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1791 if ((ss.type != 3) || (ss.type != 7))
1795 if (ss.dpl != ss_rpl) /* DPL != RPL */
1803 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1805 struct kvm_segment var;
1808 vmx_get_segment(vcpu, &var, seg);
1809 rpl = var.selector & SELECTOR_RPL_MASK;
1815 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1816 if (var.dpl < rpl) /* DPL < RPL */
1820 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1826 static bool tr_valid(struct kvm_vcpu *vcpu)
1828 struct kvm_segment tr;
1830 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1832 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1834 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1842 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1844 struct kvm_segment ldtr;
1846 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1848 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1858 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1860 struct kvm_segment cs, ss;
1862 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1863 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1865 return ((cs.selector & SELECTOR_RPL_MASK) ==
1866 (ss.selector & SELECTOR_RPL_MASK));
1870 * Check if guest state is valid. Returns true if valid, false if
1872 * We assume that registers are always usable
1874 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1876 /* real mode guest state checks */
1877 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1878 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1880 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1882 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1884 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1886 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1888 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1891 /* protected mode guest state checks */
1892 if (!cs_ss_rpl_check(vcpu))
1894 if (!code_segment_valid(vcpu))
1896 if (!stack_segment_valid(vcpu))
1898 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1900 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1902 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1904 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1906 if (!tr_valid(vcpu))
1908 if (!ldtr_valid(vcpu))
1912 * - Add checks on RIP
1913 * - Add checks on RFLAGS
1919 static int init_rmode_tss(struct kvm *kvm)
1921 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1926 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1929 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1930 r = kvm_write_guest_page(kvm, fn++, &data,
1931 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1934 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1937 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1941 r = kvm_write_guest_page(kvm, fn, &data,
1942 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1952 static int init_rmode_identity_map(struct kvm *kvm)
1955 pfn_t identity_map_pfn;
1960 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1961 printk(KERN_ERR "EPT: identity-mapping pagetable "
1962 "haven't been allocated!\n");
1965 if (likely(kvm->arch.ept_identity_pagetable_done))
1968 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1969 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1972 /* Set up identity-mapping pagetable for EPT in real mode */
1973 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1974 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1975 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1976 r = kvm_write_guest_page(kvm, identity_map_pfn,
1977 &tmp, i * sizeof(tmp), sizeof(tmp));
1981 kvm->arch.ept_identity_pagetable_done = true;
1987 static void seg_setup(int seg)
1989 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1991 vmcs_write16(sf->selector, 0);
1992 vmcs_writel(sf->base, 0);
1993 vmcs_write32(sf->limit, 0xffff);
1994 vmcs_write32(sf->ar_bytes, 0xf3);
1997 static int alloc_apic_access_page(struct kvm *kvm)
1999 struct kvm_userspace_memory_region kvm_userspace_mem;
2002 down_write(&kvm->slots_lock);
2003 if (kvm->arch.apic_access_page)
2005 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2006 kvm_userspace_mem.flags = 0;
2007 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2008 kvm_userspace_mem.memory_size = PAGE_SIZE;
2009 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2013 down_read(¤t->mm->mmap_sem);
2014 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2015 up_read(¤t->mm->mmap_sem);
2017 up_write(&kvm->slots_lock);
2021 static int alloc_identity_pagetable(struct kvm *kvm)
2023 struct kvm_userspace_memory_region kvm_userspace_mem;
2026 down_write(&kvm->slots_lock);
2027 if (kvm->arch.ept_identity_pagetable)
2029 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2030 kvm_userspace_mem.flags = 0;
2031 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2032 kvm_userspace_mem.memory_size = PAGE_SIZE;
2033 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2037 down_read(¤t->mm->mmap_sem);
2038 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2039 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2040 up_read(¤t->mm->mmap_sem);
2042 up_write(&kvm->slots_lock);
2046 static void allocate_vpid(struct vcpu_vmx *vmx)
2051 if (!enable_vpid || !cpu_has_vmx_vpid())
2053 spin_lock(&vmx_vpid_lock);
2054 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2055 if (vpid < VMX_NR_VPIDS) {
2057 __set_bit(vpid, vmx_vpid_bitmap);
2059 spin_unlock(&vmx_vpid_lock);
2062 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2066 if (!cpu_has_vmx_msr_bitmap())
2070 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2071 * have the write-low and read-high bitmap offsets the wrong way round.
2072 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2074 va = kmap(msr_bitmap);
2075 if (msr <= 0x1fff) {
2076 __clear_bit(msr, va + 0x000); /* read-low */
2077 __clear_bit(msr, va + 0x800); /* write-low */
2078 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2080 __clear_bit(msr, va + 0x400); /* read-high */
2081 __clear_bit(msr, va + 0xc00); /* write-high */
2087 * Sets up the vmcs for emulated real mode.
2089 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2091 u32 host_sysenter_cs;
2094 struct descriptor_table dt;
2096 unsigned long kvm_vmx_return;
2100 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2101 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2103 if (cpu_has_vmx_msr_bitmap())
2104 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2106 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2109 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2110 vmcs_config.pin_based_exec_ctrl);
2112 exec_control = vmcs_config.cpu_based_exec_ctrl;
2113 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2114 exec_control &= ~CPU_BASED_TPR_SHADOW;
2115 #ifdef CONFIG_X86_64
2116 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2117 CPU_BASED_CR8_LOAD_EXITING;
2121 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2122 CPU_BASED_CR3_LOAD_EXITING;
2123 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2125 if (cpu_has_secondary_exec_ctrls()) {
2126 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2127 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2129 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2131 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2133 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2134 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2137 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2138 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2139 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2141 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2142 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2143 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2145 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2146 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2147 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2148 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2149 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2150 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2151 #ifdef CONFIG_X86_64
2152 rdmsrl(MSR_FS_BASE, a);
2153 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2154 rdmsrl(MSR_GS_BASE, a);
2155 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2157 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2158 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2161 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2164 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2166 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2167 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2168 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2169 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2170 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2172 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2173 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2174 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2175 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2176 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2177 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2179 for (i = 0; i < NR_VMX_MSR; ++i) {
2180 u32 index = vmx_msr_index[i];
2181 u32 data_low, data_high;
2185 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2187 if (wrmsr_safe(index, data_low, data_high) < 0)
2189 data = data_low | ((u64)data_high << 32);
2190 vmx->host_msrs[j].index = index;
2191 vmx->host_msrs[j].reserved = 0;
2192 vmx->host_msrs[j].data = data;
2193 vmx->guest_msrs[j] = vmx->host_msrs[j];
2197 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2199 /* 22.2.1, 20.8.1 */
2200 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2202 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2203 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2209 static int init_rmode(struct kvm *kvm)
2211 if (!init_rmode_tss(kvm))
2213 if (!init_rmode_identity_map(kvm))
2218 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2220 struct vcpu_vmx *vmx = to_vmx(vcpu);
2224 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2225 down_read(&vcpu->kvm->slots_lock);
2226 if (!init_rmode(vmx->vcpu.kvm)) {
2231 vmx->vcpu.arch.rmode.active = 0;
2233 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2234 kvm_set_cr8(&vmx->vcpu, 0);
2235 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2236 if (vmx->vcpu.vcpu_id == 0)
2237 msr |= MSR_IA32_APICBASE_BSP;
2238 kvm_set_apic_base(&vmx->vcpu, msr);
2240 fx_init(&vmx->vcpu);
2242 seg_setup(VCPU_SREG_CS);
2244 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2245 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2247 if (vmx->vcpu.vcpu_id == 0) {
2248 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2249 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2251 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2252 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2255 seg_setup(VCPU_SREG_DS);
2256 seg_setup(VCPU_SREG_ES);
2257 seg_setup(VCPU_SREG_FS);
2258 seg_setup(VCPU_SREG_GS);
2259 seg_setup(VCPU_SREG_SS);
2261 vmcs_write16(GUEST_TR_SELECTOR, 0);
2262 vmcs_writel(GUEST_TR_BASE, 0);
2263 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2264 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2266 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2267 vmcs_writel(GUEST_LDTR_BASE, 0);
2268 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2269 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2271 vmcs_write32(GUEST_SYSENTER_CS, 0);
2272 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2273 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2275 vmcs_writel(GUEST_RFLAGS, 0x02);
2276 if (vmx->vcpu.vcpu_id == 0)
2277 kvm_rip_write(vcpu, 0xfff0);
2279 kvm_rip_write(vcpu, 0);
2280 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2282 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2283 vmcs_writel(GUEST_DR7, 0x400);
2285 vmcs_writel(GUEST_GDTR_BASE, 0);
2286 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2288 vmcs_writel(GUEST_IDTR_BASE, 0);
2289 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2291 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2292 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2293 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2297 /* Special registers */
2298 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2302 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2304 if (cpu_has_vmx_tpr_shadow()) {
2305 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2306 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2307 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2308 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2309 vmcs_write32(TPR_THRESHOLD, 0);
2312 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2313 vmcs_write64(APIC_ACCESS_ADDR,
2314 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2317 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2319 vmx->vcpu.arch.cr0 = 0x60000010;
2320 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2321 vmx_set_cr4(&vmx->vcpu, 0);
2322 vmx_set_efer(&vmx->vcpu, 0);
2323 vmx_fpu_activate(&vmx->vcpu);
2324 update_exception_bitmap(&vmx->vcpu);
2326 vpid_sync_vcpu_all(vmx);
2330 /* HACK: Don't enable emulation on guest boot/reset */
2331 vmx->emulation_required = 0;
2334 up_read(&vcpu->kvm->slots_lock);
2338 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2340 struct vcpu_vmx *vmx = to_vmx(vcpu);
2342 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2344 ++vcpu->stat.irq_injections;
2345 if (vcpu->arch.rmode.active) {
2346 vmx->rmode.irq.pending = true;
2347 vmx->rmode.irq.vector = irq;
2348 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2349 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2350 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2351 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2352 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2355 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2356 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2359 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2361 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2362 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2365 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2367 int word_index = __ffs(vcpu->arch.irq_summary);
2368 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2369 int irq = word_index * BITS_PER_LONG + bit_index;
2371 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2372 if (!vcpu->arch.irq_pending[word_index])
2373 clear_bit(word_index, &vcpu->arch.irq_summary);
2374 kvm_queue_interrupt(vcpu, irq);
2378 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2379 struct kvm_run *kvm_run)
2381 u32 cpu_based_vm_exec_control;
2383 vcpu->arch.interrupt_window_open =
2384 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2385 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2387 if (vcpu->arch.interrupt_window_open &&
2388 vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2389 kvm_do_inject_irq(vcpu);
2391 if (vcpu->arch.interrupt_window_open && vcpu->arch.interrupt.pending)
2392 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2394 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2395 if (!vcpu->arch.interrupt_window_open &&
2396 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2398 * Interrupts blocked. Wait for unblock.
2400 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2402 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2403 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2406 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2409 struct kvm_userspace_memory_region tss_mem = {
2411 .guest_phys_addr = addr,
2412 .memory_size = PAGE_SIZE * 3,
2416 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2419 kvm->arch.tss_addr = addr;
2423 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2425 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2427 set_debugreg(dbg->bp[0], 0);
2428 set_debugreg(dbg->bp[1], 1);
2429 set_debugreg(dbg->bp[2], 2);
2430 set_debugreg(dbg->bp[3], 3);
2432 if (dbg->singlestep) {
2433 unsigned long flags;
2435 flags = vmcs_readl(GUEST_RFLAGS);
2436 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2437 vmcs_writel(GUEST_RFLAGS, flags);
2441 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2442 int vec, u32 err_code)
2445 * Instruction with address size override prefix opcode 0x67
2446 * Cause the #SS fault with 0 error code in VM86 mode.
2448 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2449 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2452 * Forward all other exceptions that are valid in real mode.
2453 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2454 * the required debugging infrastructure rework.
2467 kvm_queue_exception(vcpu, vec);
2473 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2475 struct vcpu_vmx *vmx = to_vmx(vcpu);
2476 u32 intr_info, error_code;
2477 unsigned long cr2, rip;
2479 enum emulation_result er;
2481 vect_info = vmx->idt_vectoring_info;
2482 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2484 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2485 !is_page_fault(intr_info))
2486 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2487 "intr info 0x%x\n", __func__, vect_info, intr_info);
2489 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2490 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2491 set_bit(irq, vcpu->arch.irq_pending);
2492 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2495 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2496 return 1; /* already handled by vmx_vcpu_run() */
2498 if (is_no_device(intr_info)) {
2499 vmx_fpu_activate(vcpu);
2503 if (is_invalid_opcode(intr_info)) {
2504 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2505 if (er != EMULATE_DONE)
2506 kvm_queue_exception(vcpu, UD_VECTOR);
2511 rip = kvm_rip_read(vcpu);
2512 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2513 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2514 if (is_page_fault(intr_info)) {
2515 /* EPT won't cause page fault directly */
2518 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2519 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2520 (u32)((u64)cr2 >> 32), handler);
2521 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2522 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2523 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2526 if (vcpu->arch.rmode.active &&
2527 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2529 if (vcpu->arch.halt_request) {
2530 vcpu->arch.halt_request = 0;
2531 return kvm_emulate_halt(vcpu);
2536 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2537 (INTR_TYPE_EXCEPTION | 1)) {
2538 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2541 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2542 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2543 kvm_run->ex.error_code = error_code;
2547 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2548 struct kvm_run *kvm_run)
2550 ++vcpu->stat.irq_exits;
2551 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2555 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2557 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2561 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2563 unsigned long exit_qualification;
2564 int size, down, in, string, rep;
2567 ++vcpu->stat.io_exits;
2568 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2569 string = (exit_qualification & 16) != 0;
2572 if (emulate_instruction(vcpu,
2573 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2578 size = (exit_qualification & 7) + 1;
2579 in = (exit_qualification & 8) != 0;
2580 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2581 rep = (exit_qualification & 32) != 0;
2582 port = exit_qualification >> 16;
2584 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2588 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2591 * Patch in the VMCALL instruction:
2593 hypercall[0] = 0x0f;
2594 hypercall[1] = 0x01;
2595 hypercall[2] = 0xc1;
2598 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2600 unsigned long exit_qualification;
2604 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2605 cr = exit_qualification & 15;
2606 reg = (exit_qualification >> 8) & 15;
2607 switch ((exit_qualification >> 4) & 3) {
2608 case 0: /* mov to cr */
2609 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2610 (u32)kvm_register_read(vcpu, reg),
2611 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2615 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2616 skip_emulated_instruction(vcpu);
2619 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2620 skip_emulated_instruction(vcpu);
2623 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2624 skip_emulated_instruction(vcpu);
2627 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2628 skip_emulated_instruction(vcpu);
2629 if (irqchip_in_kernel(vcpu->kvm))
2631 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2636 vmx_fpu_deactivate(vcpu);
2637 vcpu->arch.cr0 &= ~X86_CR0_TS;
2638 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2639 vmx_fpu_activate(vcpu);
2640 KVMTRACE_0D(CLTS, vcpu, handler);
2641 skip_emulated_instruction(vcpu);
2643 case 1: /*mov from cr*/
2646 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2647 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2648 (u32)kvm_register_read(vcpu, reg),
2649 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2651 skip_emulated_instruction(vcpu);
2654 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2655 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2656 (u32)kvm_register_read(vcpu, reg), handler);
2657 skip_emulated_instruction(vcpu);
2662 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2664 skip_emulated_instruction(vcpu);
2669 kvm_run->exit_reason = 0;
2670 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2671 (int)(exit_qualification >> 4) & 3, cr);
2675 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2677 unsigned long exit_qualification;
2682 * FIXME: this code assumes the host is debugging the guest.
2683 * need to deal with guest debugging itself too.
2685 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2686 dr = exit_qualification & 7;
2687 reg = (exit_qualification >> 8) & 15;
2688 if (exit_qualification & 16) {
2700 kvm_register_write(vcpu, reg, val);
2701 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2705 skip_emulated_instruction(vcpu);
2709 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2711 kvm_emulate_cpuid(vcpu);
2715 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2717 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2720 if (vmx_get_msr(vcpu, ecx, &data)) {
2721 kvm_inject_gp(vcpu, 0);
2725 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2728 /* FIXME: handling of bits 32:63 of rax, rdx */
2729 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2730 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2731 skip_emulated_instruction(vcpu);
2735 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2737 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2738 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2739 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2741 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2744 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2745 kvm_inject_gp(vcpu, 0);
2749 skip_emulated_instruction(vcpu);
2753 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2754 struct kvm_run *kvm_run)
2759 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2760 struct kvm_run *kvm_run)
2762 u32 cpu_based_vm_exec_control;
2764 /* clear pending irq */
2765 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2766 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2767 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2769 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2772 * If the user space waits to inject interrupts, exit as soon as
2775 if (kvm_run->request_interrupt_window &&
2776 !vcpu->arch.irq_summary) {
2777 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2778 ++vcpu->stat.irq_window_exits;
2784 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2786 skip_emulated_instruction(vcpu);
2787 return kvm_emulate_halt(vcpu);
2790 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2792 skip_emulated_instruction(vcpu);
2793 kvm_emulate_hypercall(vcpu);
2797 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2799 skip_emulated_instruction(vcpu);
2800 /* TODO: Add support for VT-d/pass-through device */
2804 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2806 u64 exit_qualification;
2807 enum emulation_result er;
2808 unsigned long offset;
2810 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2811 offset = exit_qualification & 0xffful;
2813 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2815 if (er != EMULATE_DONE) {
2817 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2824 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2826 unsigned long exit_qualification;
2830 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2832 reason = (u32)exit_qualification >> 30;
2833 tss_selector = exit_qualification;
2835 return kvm_task_switch(vcpu, tss_selector, reason);
2838 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2840 u64 exit_qualification;
2841 enum emulation_result er;
2847 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2849 if (exit_qualification & (1 << 6)) {
2850 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2854 gla_validity = (exit_qualification >> 7) & 0x3;
2855 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2856 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2857 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2858 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2859 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2860 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2861 (long unsigned int)exit_qualification);
2862 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2863 kvm_run->hw.hardware_exit_reason = 0;
2867 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2868 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2869 if (!kvm_is_error_hva(hva)) {
2870 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2872 printk(KERN_ERR "EPT: Not enough memory!\n");
2878 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2880 if (er == EMULATE_FAIL) {
2882 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2884 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2885 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2886 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2887 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2888 (long unsigned int)exit_qualification);
2890 } else if (er == EMULATE_DO_MMIO)
2896 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2898 u32 cpu_based_vm_exec_control;
2900 /* clear pending NMI */
2901 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2902 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2903 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2904 ++vcpu->stat.nmi_window_exits;
2909 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
2910 struct kvm_run *kvm_run)
2912 struct vcpu_vmx *vmx = to_vmx(vcpu);
2918 while (!guest_state_valid(vcpu)) {
2919 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2924 case EMULATE_DO_MMIO:
2925 kvm_report_emulation_failure(vcpu, "mmio");
2926 /* TODO: Handle MMIO */
2929 kvm_report_emulation_failure(vcpu, "emulation failure");
2933 if (signal_pending(current))
2939 local_irq_disable();
2942 /* Guest state should be valid now, no more emulation should be needed */
2943 vmx->emulation_required = 0;
2947 * The exit handlers return 1 if the exit was handled fully and guest execution
2948 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2949 * to be done to userspace and return 0.
2951 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2952 struct kvm_run *kvm_run) = {
2953 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2954 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2955 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2956 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
2957 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2958 [EXIT_REASON_CR_ACCESS] = handle_cr,
2959 [EXIT_REASON_DR_ACCESS] = handle_dr,
2960 [EXIT_REASON_CPUID] = handle_cpuid,
2961 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2962 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2963 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2964 [EXIT_REASON_HLT] = handle_halt,
2965 [EXIT_REASON_VMCALL] = handle_vmcall,
2966 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2967 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
2968 [EXIT_REASON_WBINVD] = handle_wbinvd,
2969 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
2970 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
2973 static const int kvm_vmx_max_exit_handlers =
2974 ARRAY_SIZE(kvm_vmx_exit_handlers);
2977 * The guest has exited. See if we can fix it or if we need userspace
2980 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2982 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2983 struct vcpu_vmx *vmx = to_vmx(vcpu);
2984 u32 vectoring_info = vmx->idt_vectoring_info;
2986 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
2987 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2989 /* Access CR3 don't cause VMExit in paging mode, so we need
2990 * to sync with guest real CR3. */
2991 if (vm_need_ept() && is_paging(vcpu)) {
2992 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2993 ept_load_pdptrs(vcpu);
2996 if (unlikely(vmx->fail)) {
2997 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2998 kvm_run->fail_entry.hardware_entry_failure_reason
2999 = vmcs_read32(VM_INSTRUCTION_ERROR);
3003 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3004 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3005 exit_reason != EXIT_REASON_EPT_VIOLATION))
3006 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
3007 "exit reason is 0x%x\n", __func__, exit_reason);
3008 if (exit_reason < kvm_vmx_max_exit_handlers
3009 && kvm_vmx_exit_handlers[exit_reason])
3010 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3012 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3013 kvm_run->hw.hardware_exit_reason = exit_reason;
3018 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3022 if (!vm_need_tpr_shadow(vcpu->kvm))
3025 if (!kvm_lapic_enabled(vcpu) ||
3026 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3027 vmcs_write32(TPR_THRESHOLD, 0);
3031 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3032 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3035 static void enable_irq_window(struct kvm_vcpu *vcpu)
3037 u32 cpu_based_vm_exec_control;
3039 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3040 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3041 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3044 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3046 u32 cpu_based_vm_exec_control;
3048 if (!cpu_has_virtual_nmis())
3051 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3052 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3053 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3056 static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
3058 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3059 return !(guest_intr & (GUEST_INTR_STATE_NMI |
3060 GUEST_INTR_STATE_MOV_SS |
3061 GUEST_INTR_STATE_STI));
3064 static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
3066 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3067 return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
3068 GUEST_INTR_STATE_STI)) &&
3069 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
3072 static void enable_intr_window(struct kvm_vcpu *vcpu)
3074 if (vcpu->arch.nmi_pending)
3075 enable_nmi_window(vcpu);
3076 else if (kvm_cpu_has_interrupt(vcpu))
3077 enable_irq_window(vcpu);
3080 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3083 u32 idt_vectoring_info;
3087 bool idtv_info_valid;
3090 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3091 if (cpu_has_virtual_nmis()) {
3092 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3093 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3096 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3097 * a guest IRET fault.
3099 if (unblock_nmi && vector != DF_VECTOR)
3100 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3101 GUEST_INTR_STATE_NMI);
3104 idt_vectoring_info = vmx->idt_vectoring_info;
3105 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3106 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3107 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3108 if (vmx->vcpu.arch.nmi_injected) {
3111 * Clear bit "block by NMI" before VM entry if a NMI delivery
3114 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3115 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3116 GUEST_INTR_STATE_NMI);
3118 vmx->vcpu.arch.nmi_injected = false;
3120 kvm_clear_exception_queue(&vmx->vcpu);
3121 if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
3122 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3123 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3124 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3126 kvm_queue_exception(&vmx->vcpu, vector);
3127 vmx->idt_vectoring_info = 0;
3129 kvm_clear_interrupt_queue(&vmx->vcpu);
3130 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3131 kvm_queue_interrupt(&vmx->vcpu, vector);
3132 vmx->idt_vectoring_info = 0;
3136 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3138 update_tpr_threshold(vcpu);
3140 if (cpu_has_virtual_nmis()) {
3141 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3142 if (vmx_nmi_enabled(vcpu)) {
3143 vcpu->arch.nmi_pending = false;
3144 vcpu->arch.nmi_injected = true;
3146 enable_intr_window(vcpu);
3150 if (vcpu->arch.nmi_injected) {
3151 vmx_inject_nmi(vcpu);
3152 enable_intr_window(vcpu);
3156 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3157 if (vmx_irq_enabled(vcpu))
3158 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3160 enable_irq_window(vcpu);
3162 if (vcpu->arch.interrupt.pending) {
3163 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3164 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
3169 * Failure to inject an interrupt should give us the information
3170 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3171 * when fetching the interrupt redirection bitmap in the real-mode
3172 * tss, this doesn't happen. So we do it ourselves.
3174 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3176 vmx->rmode.irq.pending = 0;
3177 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3179 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3180 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3181 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3182 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3185 vmx->idt_vectoring_info =
3186 VECTORING_INFO_VALID_MASK
3187 | INTR_TYPE_EXT_INTR
3188 | vmx->rmode.irq.vector;
3191 #ifdef CONFIG_X86_64
3199 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3201 struct vcpu_vmx *vmx = to_vmx(vcpu);
3204 /* Handle invalid guest state instead of entering VMX */
3205 if (vmx->emulation_required && emulate_invalid_guest_state) {
3206 handle_invalid_guest_state(vcpu, kvm_run);
3210 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3211 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3212 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3213 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3216 * Loading guest fpu may have cleared host cr0.ts
3218 vmcs_writel(HOST_CR0, read_cr0());
3221 /* Store host registers */
3222 "push %%"R"dx; push %%"R"bp;"
3224 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3226 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3227 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3229 /* Check if vmlaunch of vmresume is needed */
3230 "cmpl $0, %c[launched](%0) \n\t"
3231 /* Load guest registers. Don't clobber flags. */
3232 "mov %c[cr2](%0), %%"R"ax \n\t"
3233 "mov %%"R"ax, %%cr2 \n\t"
3234 "mov %c[rax](%0), %%"R"ax \n\t"
3235 "mov %c[rbx](%0), %%"R"bx \n\t"
3236 "mov %c[rdx](%0), %%"R"dx \n\t"
3237 "mov %c[rsi](%0), %%"R"si \n\t"
3238 "mov %c[rdi](%0), %%"R"di \n\t"
3239 "mov %c[rbp](%0), %%"R"bp \n\t"
3240 #ifdef CONFIG_X86_64
3241 "mov %c[r8](%0), %%r8 \n\t"
3242 "mov %c[r9](%0), %%r9 \n\t"
3243 "mov %c[r10](%0), %%r10 \n\t"
3244 "mov %c[r11](%0), %%r11 \n\t"
3245 "mov %c[r12](%0), %%r12 \n\t"
3246 "mov %c[r13](%0), %%r13 \n\t"
3247 "mov %c[r14](%0), %%r14 \n\t"
3248 "mov %c[r15](%0), %%r15 \n\t"
3250 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3252 /* Enter guest mode */
3253 "jne .Llaunched \n\t"
3254 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3255 "jmp .Lkvm_vmx_return \n\t"
3256 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3257 ".Lkvm_vmx_return: "
3258 /* Save guest registers, load host registers, keep flags */
3259 "xchg %0, (%%"R"sp) \n\t"
3260 "mov %%"R"ax, %c[rax](%0) \n\t"
3261 "mov %%"R"bx, %c[rbx](%0) \n\t"
3262 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3263 "mov %%"R"dx, %c[rdx](%0) \n\t"
3264 "mov %%"R"si, %c[rsi](%0) \n\t"
3265 "mov %%"R"di, %c[rdi](%0) \n\t"
3266 "mov %%"R"bp, %c[rbp](%0) \n\t"
3267 #ifdef CONFIG_X86_64
3268 "mov %%r8, %c[r8](%0) \n\t"
3269 "mov %%r9, %c[r9](%0) \n\t"
3270 "mov %%r10, %c[r10](%0) \n\t"
3271 "mov %%r11, %c[r11](%0) \n\t"
3272 "mov %%r12, %c[r12](%0) \n\t"
3273 "mov %%r13, %c[r13](%0) \n\t"
3274 "mov %%r14, %c[r14](%0) \n\t"
3275 "mov %%r15, %c[r15](%0) \n\t"
3277 "mov %%cr2, %%"R"ax \n\t"
3278 "mov %%"R"ax, %c[cr2](%0) \n\t"
3280 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3281 "setbe %c[fail](%0) \n\t"
3282 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3283 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3284 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3285 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3286 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3287 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3288 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3289 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3290 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3291 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3292 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3293 #ifdef CONFIG_X86_64
3294 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3295 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3296 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3297 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3298 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3299 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3300 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3301 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3303 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3305 , R"bx", R"di", R"si"
3306 #ifdef CONFIG_X86_64
3307 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3311 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3312 vcpu->arch.regs_dirty = 0;
3314 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3315 if (vmx->rmode.irq.pending)
3316 fixup_rmode_irq(vmx);
3318 vcpu->arch.interrupt_window_open =
3319 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3320 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
3322 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3325 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3327 /* We need to handle NMIs before interrupts are enabled */
3328 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3329 (intr_info & INTR_INFO_VALID_MASK)) {
3330 KVMTRACE_0D(NMI, vcpu, handler);
3334 vmx_complete_interrupts(vmx);
3340 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3342 struct vcpu_vmx *vmx = to_vmx(vcpu);
3346 free_vmcs(vmx->vmcs);
3351 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3353 struct vcpu_vmx *vmx = to_vmx(vcpu);
3355 spin_lock(&vmx_vpid_lock);
3357 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3358 spin_unlock(&vmx_vpid_lock);
3359 vmx_free_vmcs(vcpu);
3360 kfree(vmx->host_msrs);
3361 kfree(vmx->guest_msrs);
3362 kvm_vcpu_uninit(vcpu);
3363 kmem_cache_free(kvm_vcpu_cache, vmx);
3366 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3369 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3373 return ERR_PTR(-ENOMEM);
3377 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3381 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3382 if (!vmx->guest_msrs) {
3387 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3388 if (!vmx->host_msrs)
3389 goto free_guest_msrs;
3391 vmx->vmcs = alloc_vmcs();
3395 vmcs_clear(vmx->vmcs);
3398 vmx_vcpu_load(&vmx->vcpu, cpu);
3399 err = vmx_vcpu_setup(vmx);
3400 vmx_vcpu_put(&vmx->vcpu);
3404 if (vm_need_virtualize_apic_accesses(kvm))
3405 if (alloc_apic_access_page(kvm) != 0)
3409 if (alloc_identity_pagetable(kvm) != 0)
3415 free_vmcs(vmx->vmcs);
3417 kfree(vmx->host_msrs);
3419 kfree(vmx->guest_msrs);
3421 kvm_vcpu_uninit(&vmx->vcpu);
3423 kmem_cache_free(kvm_vcpu_cache, vmx);
3424 return ERR_PTR(err);
3427 static void __init vmx_check_processor_compat(void *rtn)
3429 struct vmcs_config vmcs_conf;
3432 if (setup_vmcs_config(&vmcs_conf) < 0)
3434 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3435 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3436 smp_processor_id());
3441 static int get_ept_level(void)
3443 return VMX_EPT_DEFAULT_GAW + 1;
3446 static struct kvm_x86_ops vmx_x86_ops = {
3447 .cpu_has_kvm_support = cpu_has_kvm_support,
3448 .disabled_by_bios = vmx_disabled_by_bios,
3449 .hardware_setup = hardware_setup,
3450 .hardware_unsetup = hardware_unsetup,
3451 .check_processor_compatibility = vmx_check_processor_compat,
3452 .hardware_enable = hardware_enable,
3453 .hardware_disable = hardware_disable,
3454 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3456 .vcpu_create = vmx_create_vcpu,
3457 .vcpu_free = vmx_free_vcpu,
3458 .vcpu_reset = vmx_vcpu_reset,
3460 .prepare_guest_switch = vmx_save_host_state,
3461 .vcpu_load = vmx_vcpu_load,
3462 .vcpu_put = vmx_vcpu_put,
3464 .set_guest_debug = set_guest_debug,
3465 .guest_debug_pre = kvm_guest_debug_pre,
3466 .get_msr = vmx_get_msr,
3467 .set_msr = vmx_set_msr,
3468 .get_segment_base = vmx_get_segment_base,
3469 .get_segment = vmx_get_segment,
3470 .set_segment = vmx_set_segment,
3471 .get_cpl = vmx_get_cpl,
3472 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3473 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3474 .set_cr0 = vmx_set_cr0,
3475 .set_cr3 = vmx_set_cr3,
3476 .set_cr4 = vmx_set_cr4,
3477 .set_efer = vmx_set_efer,
3478 .get_idt = vmx_get_idt,
3479 .set_idt = vmx_set_idt,
3480 .get_gdt = vmx_get_gdt,
3481 .set_gdt = vmx_set_gdt,
3482 .cache_reg = vmx_cache_reg,
3483 .get_rflags = vmx_get_rflags,
3484 .set_rflags = vmx_set_rflags,
3486 .tlb_flush = vmx_flush_tlb,
3488 .run = vmx_vcpu_run,
3489 .handle_exit = kvm_handle_exit,
3490 .skip_emulated_instruction = skip_emulated_instruction,
3491 .patch_hypercall = vmx_patch_hypercall,
3492 .get_irq = vmx_get_irq,
3493 .set_irq = vmx_inject_irq,
3494 .queue_exception = vmx_queue_exception,
3495 .exception_injected = vmx_exception_injected,
3496 .inject_pending_irq = vmx_intr_assist,
3497 .inject_pending_vectors = do_interrupt_requests,
3499 .set_tss_addr = vmx_set_tss_addr,
3500 .get_tdp_level = get_ept_level,
3503 static int __init vmx_init(void)
3508 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3509 if (!vmx_io_bitmap_a)
3512 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3513 if (!vmx_io_bitmap_b) {
3518 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3519 if (!vmx_msr_bitmap) {
3525 * Allow direct access to the PC debug port (it is often used for I/O
3526 * delays, but the vmexits simply slow things down).
3528 va = kmap(vmx_io_bitmap_a);
3529 memset(va, 0xff, PAGE_SIZE);
3530 clear_bit(0x80, va);
3531 kunmap(vmx_io_bitmap_a);
3533 va = kmap(vmx_io_bitmap_b);
3534 memset(va, 0xff, PAGE_SIZE);
3535 kunmap(vmx_io_bitmap_b);
3537 va = kmap(vmx_msr_bitmap);
3538 memset(va, 0xff, PAGE_SIZE);
3539 kunmap(vmx_msr_bitmap);
3541 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3543 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3547 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3548 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3549 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3550 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3551 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3553 if (vm_need_ept()) {
3554 bypass_guest_pf = 0;
3555 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3556 VMX_EPT_WRITABLE_MASK |
3557 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3558 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3559 VMX_EPT_EXECUTABLE_MASK);
3564 if (bypass_guest_pf)
3565 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3572 __free_page(vmx_msr_bitmap);
3574 __free_page(vmx_io_bitmap_b);
3576 __free_page(vmx_io_bitmap_a);
3580 static void __exit vmx_exit(void)
3582 __free_page(vmx_msr_bitmap);
3583 __free_page(vmx_io_bitmap_b);
3584 __free_page(vmx_io_bitmap_a);
3589 module_init(vmx_init)
3590 module_exit(vmx_exit)