SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 struct vmcs {
  65         u32 revision_id;
  66         u32 abort;
  67         char data[0];
  68 };
  69
  70 struct vcpu_vmx {
  71         struct kvm_vcpu       vcpu;
  72         struct list_head      local_vcpus_link;
  73         unsigned long         host_rsp;
  74         int                   launched;
  75         u8                    fail;
  76         u32                   idt_vectoring_info;
  77         struct kvm_msr_entry *guest_msrs;
  78         struct kvm_msr_entry *host_msrs;
  79         int                   nmsrs;
  80         int                   save_nmsrs;
  81         int                   msr_offset_efer;
  82 #ifdef CONFIG_X86_64
  83         int                   msr_offset_kernel_gs_base;
  84 #endif
  85         struct vmcs          *vmcs;
  86         struct {
  87                 int           loaded;
  88                 u16           fs_sel, gs_sel, ldt_sel;
  89                 int           gs_ldt_reload_needed;
  90                 int           fs_reload_needed;
  91                 int           guest_efer_loaded;
  92         } host_state;
  93         struct {
  94                 int vm86_active;
  95                 u8 save_iopl;
  96                 struct kvm_save_segment {
  97                         u16 selector;
  98                         unsigned long base;
  99                         u32 limit;
 100                         u32 ar;
 101                 } tr, es, ds, fs, gs;
 102                 struct {
 103                         bool pending;
 104                         u8 vector;
 105                         unsigned rip;
 106                 } irq;
 107         } rmode;
 108         int vpid;
 109         bool emulation_required;
 110
 111         /* Support for vnmi-less CPUs */
 112         int soft_vnmi_blocked;
 113         ktime_t entry_time;
 114         s64 vnmi_blocked_time;
 115         u32 exit_reason;
 116 };
 117
 118 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 119 {
 120         return container_of(vcpu, struct vcpu_vmx, vcpu);
 121 }
 122
 123 static int init_rmode(struct kvm *kvm);
 124 static u64 construct_eptp(unsigned long root_hpa);
 125
 126 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 127 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 128 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 129
 130 static unsigned long *vmx_io_bitmap_a;
 131 static unsigned long *vmx_io_bitmap_b;
 132 static unsigned long *vmx_msr_bitmap_legacy;
 133 static unsigned long *vmx_msr_bitmap_longmode;
 134
 135 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 136 static DEFINE_SPINLOCK(vmx_vpid_lock);
 137
 138 static struct vmcs_config {
 139         int size;
 140         int order;
 141         u32 revision_id;
 142         u32 pin_based_exec_ctrl;
 143         u32 cpu_based_exec_ctrl;
 144         u32 cpu_based_2nd_exec_ctrl;
 145         u32 vmexit_ctrl;
 146         u32 vmentry_ctrl;
 147 } vmcs_config;
 148
 149 static struct vmx_capability {
 150         u32 ept;
 151         u32 vpid;
 152 } vmx_capability;
 153
 154 #define VMX_SEGMENT_FIELD(seg)                                  \
 155         [VCPU_SREG_##seg] = {                                   \
 156                 .selector = GUEST_##seg##_SELECTOR,             \
 157                 .base = GUEST_##seg##_BASE,                     \
 158                 .limit = GUEST_##seg##_LIMIT,                   \
 159                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 160         }
 161
 162 static struct kvm_vmx_segment_field {
 163         unsigned selector;
 164         unsigned base;
 165         unsigned limit;
 166         unsigned ar_bytes;
 167 } kvm_vmx_segment_fields[] = {
 168         VMX_SEGMENT_FIELD(CS),
 169         VMX_SEGMENT_FIELD(DS),
 170         VMX_SEGMENT_FIELD(ES),
 171         VMX_SEGMENT_FIELD(FS),
 172         VMX_SEGMENT_FIELD(GS),
 173         VMX_SEGMENT_FIELD(SS),
 174         VMX_SEGMENT_FIELD(TR),
 175         VMX_SEGMENT_FIELD(LDTR),
 176 };
 177
 178 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 179
 180 /*
 181  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 182  * away by decrementing the array size.
 183  */
 184 static const u32 vmx_msr_index[] = {
 185 #ifdef CONFIG_X86_64
 186         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 187 #endif
 188         MSR_EFER, MSR_K6_STAR,
 189 };
 190 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 191
 192 static void load_msrs(struct kvm_msr_entry *e, int n)
 193 {
 194         int i;
 195
 196         for (i = 0; i < n; ++i)
 197                 wrmsrl(e[i].index, e[i].data);
 198 }
 199
 200 static void save_msrs(struct kvm_msr_entry *e, int n)
 201 {
 202         int i;
 203
 204         for (i = 0; i < n; ++i)
 205                 rdmsrl(e[i].index, e[i].data);
 206 }
 207
 208 static inline int is_page_fault(u32 intr_info)
 209 {
 210         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 211                              INTR_INFO_VALID_MASK)) ==
 212                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 213 }
 214
 215 static inline int is_no_device(u32 intr_info)
 216 {
 217         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 218                              INTR_INFO_VALID_MASK)) ==
 219                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 220 }
 221
 222 static inline int is_invalid_opcode(u32 intr_info)
 223 {
 224         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 225                              INTR_INFO_VALID_MASK)) ==
 226                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 227 }
 228
 229 static inline int is_external_interrupt(u32 intr_info)
 230 {
 231         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 232                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 233 }
 234
 235 static inline int is_machine_check(u32 intr_info)
 236 {
 237         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 238                              INTR_INFO_VALID_MASK)) ==
 239                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 240 }
 241
 242 static inline int cpu_has_vmx_msr_bitmap(void)
 243 {
 244         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 245 }
 246
 247 static inline int cpu_has_vmx_tpr_shadow(void)
 248 {
 249         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 250 }
 251
 252 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 253 {
 254         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 255 }
 256
 257 static inline int cpu_has_secondary_exec_ctrls(void)
 258 {
 259         return vmcs_config.cpu_based_exec_ctrl &
 260                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 261 }
 262
 263 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 264 {
 265         return vmcs_config.cpu_based_2nd_exec_ctrl &
 266                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 267 }
 268
 269 static inline bool cpu_has_vmx_flexpriority(void)
 270 {
 271         return cpu_has_vmx_tpr_shadow() &&
 272                 cpu_has_vmx_virtualize_apic_accesses();
 273 }
 274
 275 static inline bool cpu_has_vmx_ept_execute_only(void)
 276 {
 277         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 278 }
 279
 280 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 281 {
 282         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 283 }
 284
 285 static inline bool cpu_has_vmx_eptp_writeback(void)
 286 {
 287         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 288 }
 289
 290 static inline bool cpu_has_vmx_ept_2m_page(void)
 291 {
 292         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 293 }
 294
 295 static inline int cpu_has_vmx_invept_individual_addr(void)
 296 {
 297         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 298 }
 299
 300 static inline int cpu_has_vmx_invept_context(void)
 301 {
 302         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 303 }
 304
 305 static inline int cpu_has_vmx_invept_global(void)
 306 {
 307         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 308 }
 309
 310 static inline int cpu_has_vmx_ept(void)
 311 {
 312         return vmcs_config.cpu_based_2nd_exec_ctrl &
 313                 SECONDARY_EXEC_ENABLE_EPT;
 314 }
 315
 316 static inline int cpu_has_vmx_unrestricted_guest(void)
 317 {
 318         return vmcs_config.cpu_based_2nd_exec_ctrl &
 319                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 320 }
 321
 322 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 323 {
 324         return flexpriority_enabled &&
 325                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 326                 (irqchip_in_kernel(kvm));
 327 }
 328
 329 static inline int cpu_has_vmx_vpid(void)
 330 {
 331         return vmcs_config.cpu_based_2nd_exec_ctrl &
 332                 SECONDARY_EXEC_ENABLE_VPID;
 333 }
 334
 335 static inline int cpu_has_virtual_nmis(void)
 336 {
 337         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 338 }
 339
 340 static inline bool report_flexpriority(void)
 341 {
 342         return flexpriority_enabled;
 343 }
 344
 345 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 346 {
 347         int i;
 348
 349         for (i = 0; i < vmx->nmsrs; ++i)
 350                 if (vmx->guest_msrs[i].index == msr)
 351                         return i;
 352         return -1;
 353 }
 354
 355 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 356 {
 357     struct {
 358         u64 vpid : 16;
 359         u64 rsvd : 48;
 360         u64 gva;
 361     } operand = { vpid, 0, gva };
 362
 363     asm volatile (__ex(ASM_VMX_INVVPID)
 364                   /* CF==1 or ZF==1 --> rc = -1 */
 365                   "; ja 1f ; ud2 ; 1:"
 366                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 367 }
 368
 369 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 370 {
 371         struct {
 372                 u64 eptp, gpa;
 373         } operand = {eptp, gpa};
 374
 375         asm volatile (__ex(ASM_VMX_INVEPT)
 376                         /* CF==1 or ZF==1 --> rc = -1 */
 377                         "; ja 1f ; ud2 ; 1:\n"
 378                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 379 }
 380
 381 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 382 {
 383         int i;
 384
 385         i = __find_msr_index(vmx, msr);
 386         if (i >= 0)
 387                 return &vmx->guest_msrs[i];
 388         return NULL;
 389 }
 390
 391 static void vmcs_clear(struct vmcs *vmcs)
 392 {
 393         u64 phys_addr = __pa(vmcs);
 394         u8 error;
 395
 396         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 397                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 398                       : "cc", "memory");
 399         if (error)
 400                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 401                        vmcs, phys_addr);
 402 }
 403
 404 static void __vcpu_clear(void *arg)
 405 {
 406         struct vcpu_vmx *vmx = arg;
 407         int cpu = raw_smp_processor_id();
 408
 409         if (vmx->vcpu.cpu == cpu)
 410                 vmcs_clear(vmx->vmcs);
 411         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 412                 per_cpu(current_vmcs, cpu) = NULL;
 413         rdtscll(vmx->vcpu.arch.host_tsc);
 414         list_del(&vmx->local_vcpus_link);
 415         vmx->vcpu.cpu = -1;
 416         vmx->launched = 0;
 417 }
 418
 419 static void vcpu_clear(struct vcpu_vmx *vmx)
 420 {
 421         if (vmx->vcpu.cpu == -1)
 422                 return;
 423         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 424 }
 425
 426 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 427 {
 428         if (vmx->vpid == 0)
 429                 return;
 430
 431         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 432 }
 433
 434 static inline void ept_sync_global(void)
 435 {
 436         if (cpu_has_vmx_invept_global())
 437                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 438 }
 439
 440 static inline void ept_sync_context(u64 eptp)
 441 {
 442         if (enable_ept) {
 443                 if (cpu_has_vmx_invept_context())
 444                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 445                 else
 446                         ept_sync_global();
 447         }
 448 }
 449
 450 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 451 {
 452         if (enable_ept) {
 453                 if (cpu_has_vmx_invept_individual_addr())
 454                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 455                                         eptp, gpa);
 456                 else
 457                         ept_sync_context(eptp);
 458         }
 459 }
 460
 461 static unsigned long vmcs_readl(unsigned long field)
 462 {
 463         unsigned long value;
 464
 465         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 466                       : "=a"(value) : "d"(field) : "cc");
 467         return value;
 468 }
 469
 470 static u16 vmcs_read16(unsigned long field)
 471 {
 472         return vmcs_readl(field);
 473 }
 474
 475 static u32 vmcs_read32(unsigned long field)
 476 {
 477         return vmcs_readl(field);
 478 }
 479
 480 static u64 vmcs_read64(unsigned long field)
 481 {
 482 #ifdef CONFIG_X86_64
 483         return vmcs_readl(field);
 484 #else
 485         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 486 #endif
 487 }
 488
 489 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 490 {
 491         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 492                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 493         dump_stack();
 494 }
 495
 496 static void vmcs_writel(unsigned long field, unsigned long value)
 497 {
 498         u8 error;
 499
 500         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 501                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 502         if (unlikely(error))
 503                 vmwrite_error(field, value);
 504 }
 505
 506 static void vmcs_write16(unsigned long field, u16 value)
 507 {
 508         vmcs_writel(field, value);
 509 }
 510
 511 static void vmcs_write32(unsigned long field, u32 value)
 512 {
 513         vmcs_writel(field, value);
 514 }
 515
 516 static void vmcs_write64(unsigned long field, u64 value)
 517 {
 518         vmcs_writel(field, value);
 519 #ifndef CONFIG_X86_64
 520         asm volatile ("");
 521         vmcs_writel(field+1, value >> 32);
 522 #endif
 523 }
 524
 525 static void vmcs_clear_bits(unsigned long field, u32 mask)
 526 {
 527         vmcs_writel(field, vmcs_readl(field) & ~mask);
 528 }
 529
 530 static void vmcs_set_bits(unsigned long field, u32 mask)
 531 {
 532         vmcs_writel(field, vmcs_readl(field) | mask);
 533 }
 534
 535 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 536 {
 537         u32 eb;
 538
 539         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 540         if (!vcpu->fpu_active)
 541                 eb |= 1u << NM_VECTOR;
 542         /*
 543          * Unconditionally intercept #DB so we can maintain dr6 without
 544          * reading it every exit.
 545          */
 546         eb |= 1u << DB_VECTOR;
 547         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 548                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 549                         eb |= 1u << BP_VECTOR;
 550         }
 551         if (to_vmx(vcpu)->rmode.vm86_active)
 552                 eb = ~0;
 553         if (enable_ept)
 554                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 555         vmcs_write32(EXCEPTION_BITMAP, eb);
 556 }
 557
 558 static void reload_tss(void)
 559 {
 560         /*
 561          * VT restores TR but not its size.  Useless.
 562          */
 563         struct descriptor_table gdt;
 564         struct desc_struct *descs;
 565
 566         kvm_get_gdt(&gdt);
 567         descs = (void *)gdt.base;
 568         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 569         load_TR_desc();
 570 }
 571
 572 static void load_transition_efer(struct vcpu_vmx *vmx)
 573 {
 574         int efer_offset = vmx->msr_offset_efer;
 575         u64 host_efer;
 576         u64 guest_efer;
 577         u64 ignore_bits;
 578
 579         if (efer_offset < 0)
 580                 return;
 581         host_efer = vmx->host_msrs[efer_offset].data;
 582         guest_efer = vmx->guest_msrs[efer_offset].data;
 583
 584         /*
 585          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 586          * outside long mode
 587          */
 588         ignore_bits = EFER_NX | EFER_SCE;
 589 #ifdef CONFIG_X86_64
 590         ignore_bits |= EFER_LMA | EFER_LME;
 591         /* SCE is meaningful only in long mode on Intel */
 592         if (guest_efer & EFER_LMA)
 593                 ignore_bits &= ~(u64)EFER_SCE;
 594 #endif
 595         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 596                 return;
 597
 598         vmx->host_state.guest_efer_loaded = 1;
 599         guest_efer &= ~ignore_bits;
 600         guest_efer |= host_efer & ignore_bits;
 601         wrmsrl(MSR_EFER, guest_efer);
 602         vmx->vcpu.stat.efer_reload++;
 603 }
 604
 605 static void reload_host_efer(struct vcpu_vmx *vmx)
 606 {
 607         if (vmx->host_state.guest_efer_loaded) {
 608                 vmx->host_state.guest_efer_loaded = 0;
 609                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 610         }
 611 }
 612
 613 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 614 {
 615         struct vcpu_vmx *vmx = to_vmx(vcpu);
 616
 617         if (vmx->host_state.loaded)
 618                 return;
 619
 620         vmx->host_state.loaded = 1;
 621         /*
 622          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 623          * allow segment selectors with cpl > 0 or ti == 1.
 624          */
 625         vmx->host_state.ldt_sel = kvm_read_ldt();
 626         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 627         vmx->host_state.fs_sel = kvm_read_fs();
 628         if (!(vmx->host_state.fs_sel & 7)) {
 629                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 630                 vmx->host_state.fs_reload_needed = 0;
 631         } else {
 632                 vmcs_write16(HOST_FS_SELECTOR, 0);
 633                 vmx->host_state.fs_reload_needed = 1;
 634         }
 635         vmx->host_state.gs_sel = kvm_read_gs();
 636         if (!(vmx->host_state.gs_sel & 7))
 637                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 638         else {
 639                 vmcs_write16(HOST_GS_SELECTOR, 0);
 640                 vmx->host_state.gs_ldt_reload_needed = 1;
 641         }
 642
 643 #ifdef CONFIG_X86_64
 644         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 645         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 646 #else
 647         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 648         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 649 #endif
 650
 651 #ifdef CONFIG_X86_64
 652         if (is_long_mode(&vmx->vcpu))
 653                 save_msrs(vmx->host_msrs +
 654                           vmx->msr_offset_kernel_gs_base, 1);
 655
 656 #endif
 657         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 658         load_transition_efer(vmx);
 659 }
 660
 661 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 662 {
 663         unsigned long flags;
 664
 665         if (!vmx->host_state.loaded)
 666                 return;
 667
 668         ++vmx->vcpu.stat.host_state_reload;
 669         vmx->host_state.loaded = 0;
 670         if (vmx->host_state.fs_reload_needed)
 671                 kvm_load_fs(vmx->host_state.fs_sel);
 672         if (vmx->host_state.gs_ldt_reload_needed) {
 673                 kvm_load_ldt(vmx->host_state.ldt_sel);
 674                 /*
 675                  * If we have to reload gs, we must take care to
 676                  * preserve our gs base.
 677                  */
 678                 local_irq_save(flags);
 679                 kvm_load_gs(vmx->host_state.gs_sel);
 680 #ifdef CONFIG_X86_64
 681                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 682 #endif
 683                 local_irq_restore(flags);
 684         }
 685         reload_tss();
 686         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 687         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 688         reload_host_efer(vmx);
 689 }
 690
 691 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 692 {
 693         preempt_disable();
 694         __vmx_load_host_state(vmx);
 695         preempt_enable();
 696 }
 697
 698 /*
 699  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 700  * vcpu mutex is already taken.
 701  */
 702 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 703 {
 704         struct vcpu_vmx *vmx = to_vmx(vcpu);
 705         u64 phys_addr = __pa(vmx->vmcs);
 706         u64 tsc_this, delta, new_offset;
 707
 708         if (vcpu->cpu != cpu) {
 709                 vcpu_clear(vmx);
 710                 kvm_migrate_timers(vcpu);
 711                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 712                 local_irq_disable();
 713                 list_add(&vmx->local_vcpus_link,
 714                          &per_cpu(vcpus_on_cpu, cpu));
 715                 local_irq_enable();
 716         }
 717
 718         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 719                 u8 error;
 720
 721                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 722                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 723                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 724                               : "cc");
 725                 if (error)
 726                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 727                                vmx->vmcs, phys_addr);
 728         }
 729
 730         if (vcpu->cpu != cpu) {
 731                 struct descriptor_table dt;
 732                 unsigned long sysenter_esp;
 733
 734                 vcpu->cpu = cpu;
 735                 /*
 736                  * Linux uses per-cpu TSS and GDT, so set these when switching
 737                  * processors.
 738                  */
 739                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 740                 kvm_get_gdt(&dt);
 741                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 742
 743                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 744                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 745
 746                 /*
 747                  * Make sure the time stamp counter is monotonous.
 748                  */
 749                 rdtscll(tsc_this);
 750                 if (tsc_this < vcpu->arch.host_tsc) {
 751                         delta = vcpu->arch.host_tsc - tsc_this;
 752                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 753                         vmcs_write64(TSC_OFFSET, new_offset);
 754                 }
 755         }
 756 }
 757
 758 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 759 {
 760         __vmx_load_host_state(to_vmx(vcpu));
 761 }
 762
 763 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 764 {
 765         if (vcpu->fpu_active)
 766                 return;
 767         vcpu->fpu_active = 1;
 768         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 769         if (vcpu->arch.cr0 & X86_CR0_TS)
 770                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 771         update_exception_bitmap(vcpu);
 772 }
 773
 774 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 775 {
 776         if (!vcpu->fpu_active)
 777                 return;
 778         vcpu->fpu_active = 0;
 779         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 780         update_exception_bitmap(vcpu);
 781 }
 782
 783 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 784 {
 785         unsigned long rflags;
 786
 787         rflags = vmcs_readl(GUEST_RFLAGS);
 788         if (to_vmx(vcpu)->rmode.vm86_active)
 789                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 790         return rflags;
 791 }
 792
 793 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 794 {
 795         if (to_vmx(vcpu)->rmode.vm86_active)
 796                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 797         vmcs_writel(GUEST_RFLAGS, rflags);
 798 }
 799
 800 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 801 {
 802         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 803         int ret = 0;
 804
 805         if (interruptibility & GUEST_INTR_STATE_STI)
 806                 ret |= X86_SHADOW_INT_STI;
 807         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 808                 ret |= X86_SHADOW_INT_MOV_SS;
 809
 810         return ret & mask;
 811 }
 812
 813 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 814 {
 815         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 816         u32 interruptibility = interruptibility_old;
 817
 818         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 819
 820         if (mask & X86_SHADOW_INT_MOV_SS)
 821                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 822         if (mask & X86_SHADOW_INT_STI)
 823                 interruptibility |= GUEST_INTR_STATE_STI;
 824
 825         if ((interruptibility != interruptibility_old))
 826                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 827 }
 828
 829 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 830 {
 831         unsigned long rip;
 832
 833         rip = kvm_rip_read(vcpu);
 834         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 835         kvm_rip_write(vcpu, rip);
 836
 837         /* skipping an emulated instruction also counts */
 838         vmx_set_interrupt_shadow(vcpu, 0);
 839 }
 840
 841 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 842                                 bool has_error_code, u32 error_code)
 843 {
 844         struct vcpu_vmx *vmx = to_vmx(vcpu);
 845         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 846
 847         if (has_error_code) {
 848                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 849                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 850         }
 851
 852         if (vmx->rmode.vm86_active) {
 853                 vmx->rmode.irq.pending = true;
 854                 vmx->rmode.irq.vector = nr;
 855                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 856                 if (kvm_exception_is_soft(nr))
 857                         vmx->rmode.irq.rip +=
 858                                 vmx->vcpu.arch.event_exit_inst_len;
 859                 intr_info |= INTR_TYPE_SOFT_INTR;
 860                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 861                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 862                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 863                 return;
 864         }
 865
 866         if (kvm_exception_is_soft(nr)) {
 867                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 868                              vmx->vcpu.arch.event_exit_inst_len);
 869                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 870         } else
 871                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 872
 873         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 874 }
 875
 876 /*
 877  * Swap MSR entry in host/guest MSR entry array.
 878  */
 879 #ifdef CONFIG_X86_64
 880 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 881 {
 882         struct kvm_msr_entry tmp;
 883
 884         tmp = vmx->guest_msrs[to];
 885         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 886         vmx->guest_msrs[from] = tmp;
 887         tmp = vmx->host_msrs[to];
 888         vmx->host_msrs[to] = vmx->host_msrs[from];
 889         vmx->host_msrs[from] = tmp;
 890 }
 891 #endif
 892
 893 /*
 894  * Set up the vmcs to automatically save and restore system
 895  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 896  * mode, as fiddling with msrs is very expensive.
 897  */
 898 static void setup_msrs(struct vcpu_vmx *vmx)
 899 {
 900         int save_nmsrs;
 901         unsigned long *msr_bitmap;
 902
 903         vmx_load_host_state(vmx);
 904         save_nmsrs = 0;
 905 #ifdef CONFIG_X86_64
 906         if (is_long_mode(&vmx->vcpu)) {
 907                 int index;
 908
 909                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 910                 if (index >= 0)
 911                         move_msr_up(vmx, index, save_nmsrs++);
 912                 index = __find_msr_index(vmx, MSR_LSTAR);
 913                 if (index >= 0)
 914                         move_msr_up(vmx, index, save_nmsrs++);
 915                 index = __find_msr_index(vmx, MSR_CSTAR);
 916                 if (index >= 0)
 917                         move_msr_up(vmx, index, save_nmsrs++);
 918                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 919                 if (index >= 0)
 920                         move_msr_up(vmx, index, save_nmsrs++);
 921                 /*
 922                  * MSR_K6_STAR is only needed on long mode guests, and only
 923                  * if efer.sce is enabled.
 924                  */
 925                 index = __find_msr_index(vmx, MSR_K6_STAR);
 926                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 927                         move_msr_up(vmx, index, save_nmsrs++);
 928         }
 929 #endif
 930         vmx->save_nmsrs = save_nmsrs;
 931
 932 #ifdef CONFIG_X86_64
 933         vmx->msr_offset_kernel_gs_base =
 934                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 935 #endif
 936         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 937
 938         if (cpu_has_vmx_msr_bitmap()) {
 939                 if (is_long_mode(&vmx->vcpu))
 940                         msr_bitmap = vmx_msr_bitmap_longmode;
 941                 else
 942                         msr_bitmap = vmx_msr_bitmap_legacy;
 943
 944                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 945         }
 946 }
 947
 948 /*
 949  * reads and returns guest's timestamp counter "register"
 950  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 951  */
 952 static u64 guest_read_tsc(void)
 953 {
 954         u64 host_tsc, tsc_offset;
 955
 956         rdtscll(host_tsc);
 957         tsc_offset = vmcs_read64(TSC_OFFSET);
 958         return host_tsc + tsc_offset;
 959 }
 960
 961 /*
 962  * writes 'guest_tsc' into guest's timestamp counter "register"
 963  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 964  */
 965 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 966 {
 967         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 968 }
 969
 970 /*
 971  * Reads an msr value (of 'msr_index') into 'pdata'.
 972  * Returns 0 on success, non-0 otherwise.
 973  * Assumes vcpu_load() was already called.
 974  */
 975 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 976 {
 977         u64 data;
 978         struct kvm_msr_entry *msr;
 979
 980         if (!pdata) {
 981                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 982                 return -EINVAL;
 983         }
 984
 985         switch (msr_index) {
 986 #ifdef CONFIG_X86_64
 987         case MSR_FS_BASE:
 988                 data = vmcs_readl(GUEST_FS_BASE);
 989                 break;
 990         case MSR_GS_BASE:
 991                 data = vmcs_readl(GUEST_GS_BASE);
 992                 break;
 993         case MSR_EFER:
 994                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 995 #endif
 996         case MSR_IA32_TSC:
 997                 data = guest_read_tsc();
 998                 break;
 999         case MSR_IA32_SYSENTER_CS:
1000                 data = vmcs_read32(GUEST_SYSENTER_CS);
1001                 break;
1002         case MSR_IA32_SYSENTER_EIP:
1003                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1004                 break;
1005         case MSR_IA32_SYSENTER_ESP:
1006                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1007                 break;
1008         default:
1009                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1010                 if (msr) {
1011                         vmx_load_host_state(to_vmx(vcpu));
1012                         data = msr->data;
1013                         break;
1014                 }
1015                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1016         }
1017
1018         *pdata = data;
1019         return 0;
1020 }
1021
1022 /*
1023  * Writes msr value into into the appropriate "register".
1024  * Returns 0 on success, non-0 otherwise.
1025  * Assumes vcpu_load() was already called.
1026  */
1027 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1028 {
1029         struct vcpu_vmx *vmx = to_vmx(vcpu);
1030         struct kvm_msr_entry *msr;
1031         u64 host_tsc;
1032         int ret = 0;
1033
1034         switch (msr_index) {
1035         case MSR_EFER:
1036                 vmx_load_host_state(vmx);
1037                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1038                 break;
1039 #ifdef CONFIG_X86_64
1040         case MSR_FS_BASE:
1041                 vmcs_writel(GUEST_FS_BASE, data);
1042                 break;
1043         case MSR_GS_BASE:
1044                 vmcs_writel(GUEST_GS_BASE, data);
1045                 break;
1046 #endif
1047         case MSR_IA32_SYSENTER_CS:
1048                 vmcs_write32(GUEST_SYSENTER_CS, data);
1049                 break;
1050         case MSR_IA32_SYSENTER_EIP:
1051                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1052                 break;
1053         case MSR_IA32_SYSENTER_ESP:
1054                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1055                 break;
1056         case MSR_IA32_TSC:
1057                 rdtscll(host_tsc);
1058                 guest_write_tsc(data, host_tsc);
1059                 break;
1060         case MSR_IA32_CR_PAT:
1061                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1062                         vmcs_write64(GUEST_IA32_PAT, data);
1063                         vcpu->arch.pat = data;
1064                         break;
1065                 }
1066                 /* Otherwise falls through to kvm_set_msr_common */
1067         default:
1068                 msr = find_msr_entry(vmx, msr_index);
1069                 if (msr) {
1070                         vmx_load_host_state(vmx);
1071                         msr->data = data;
1072                         break;
1073                 }
1074                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1075         }
1076
1077         return ret;
1078 }
1079
1080 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1081 {
1082         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1083         switch (reg) {
1084         case VCPU_REGS_RSP:
1085                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1086                 break;
1087         case VCPU_REGS_RIP:
1088                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1089                 break;
1090         case VCPU_EXREG_PDPTR:
1091                 if (enable_ept)
1092                         ept_save_pdptrs(vcpu);
1093                 break;
1094         default:
1095                 break;
1096         }
1097 }
1098
1099 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1100 {
1101         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1102                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1103         else
1104                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1105
1106         update_exception_bitmap(vcpu);
1107 }
1108
1109 static __init int cpu_has_kvm_support(void)
1110 {
1111         return cpu_has_vmx();
1112 }
1113
1114 static __init int vmx_disabled_by_bios(void)
1115 {
1116         u64 msr;
1117
1118         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1119         return (msr & (FEATURE_CONTROL_LOCKED |
1120                        FEATURE_CONTROL_VMXON_ENABLED))
1121             == FEATURE_CONTROL_LOCKED;
1122         /* locked but not enabled */
1123 }
1124
1125 static int hardware_enable(void *garbage)
1126 {
1127         int cpu = raw_smp_processor_id();
1128         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1129         u64 old;
1130
1131         if (read_cr4() & X86_CR4_VMXE)
1132                 return -EBUSY;
1133
1134         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1135         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1136         if ((old & (FEATURE_CONTROL_LOCKED |
1137                     FEATURE_CONTROL_VMXON_ENABLED))
1138             != (FEATURE_CONTROL_LOCKED |
1139                 FEATURE_CONTROL_VMXON_ENABLED))
1140                 /* enable and lock */
1141                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1142                        FEATURE_CONTROL_LOCKED |
1143                        FEATURE_CONTROL_VMXON_ENABLED);
1144         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1145         asm volatile (ASM_VMX_VMXON_RAX
1146                       : : "a"(&phys_addr), "m"(phys_addr)
1147                       : "memory", "cc");
1148
1149         ept_sync_global();
1150
1151         return 0;
1152 }
1153
1154 static void vmclear_local_vcpus(void)
1155 {
1156         int cpu = raw_smp_processor_id();
1157         struct vcpu_vmx *vmx, *n;
1158
1159         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1160                                  local_vcpus_link)
1161                 __vcpu_clear(vmx);
1162 }
1163
1164
1165 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1166  * tricks.
1167  */
1168 static void kvm_cpu_vmxoff(void)
1169 {
1170         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1171         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1172 }
1173
1174 static void hardware_disable(void *garbage)
1175 {
1176         vmclear_local_vcpus();
1177         kvm_cpu_vmxoff();
1178 }
1179
1180 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1181                                       u32 msr, u32 *result)
1182 {
1183         u32 vmx_msr_low, vmx_msr_high;
1184         u32 ctl = ctl_min | ctl_opt;
1185
1186         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1187
1188         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1189         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1190
1191         /* Ensure minimum (required) set of control bits are supported. */
1192         if (ctl_min & ~ctl)
1193                 return -EIO;
1194
1195         *result = ctl;
1196         return 0;
1197 }
1198
1199 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1200 {
1201         u32 vmx_msr_low, vmx_msr_high;
1202         u32 min, opt, min2, opt2;
1203         u32 _pin_based_exec_control = 0;
1204         u32 _cpu_based_exec_control = 0;
1205         u32 _cpu_based_2nd_exec_control = 0;
1206         u32 _vmexit_control = 0;
1207         u32 _vmentry_control = 0;
1208
1209         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1210         opt = PIN_BASED_VIRTUAL_NMIS;
1211         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1212                                 &_pin_based_exec_control) < 0)
1213                 return -EIO;
1214
1215         min = CPU_BASED_HLT_EXITING |
1216 #ifdef CONFIG_X86_64
1217               CPU_BASED_CR8_LOAD_EXITING |
1218               CPU_BASED_CR8_STORE_EXITING |
1219 #endif
1220               CPU_BASED_CR3_LOAD_EXITING |
1221               CPU_BASED_CR3_STORE_EXITING |
1222               CPU_BASED_USE_IO_BITMAPS |
1223               CPU_BASED_MOV_DR_EXITING |
1224               CPU_BASED_USE_TSC_OFFSETING |
1225               CPU_BASED_INVLPG_EXITING;
1226         opt = CPU_BASED_TPR_SHADOW |
1227               CPU_BASED_USE_MSR_BITMAPS |
1228               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1229         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1230                                 &_cpu_based_exec_control) < 0)
1231                 return -EIO;
1232 #ifdef CONFIG_X86_64
1233         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1234                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1235                                            ~CPU_BASED_CR8_STORE_EXITING;
1236 #endif
1237         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1238                 min2 = 0;
1239                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1240                         SECONDARY_EXEC_WBINVD_EXITING |
1241                         SECONDARY_EXEC_ENABLE_VPID |
1242                         SECONDARY_EXEC_ENABLE_EPT |
1243                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
1244                 if (adjust_vmx_controls(min2, opt2,
1245                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1246                                         &_cpu_based_2nd_exec_control) < 0)
1247                         return -EIO;
1248         }
1249 #ifndef CONFIG_X86_64
1250         if (!(_cpu_based_2nd_exec_control &
1251                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1252                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1253 #endif
1254         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1255                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1256                    enabled */
1257                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1258                                              CPU_BASED_CR3_STORE_EXITING |
1259                                              CPU_BASED_INVLPG_EXITING);
1260                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1261                       vmx_capability.ept, vmx_capability.vpid);
1262         }
1263
1264         min = 0;
1265 #ifdef CONFIG_X86_64
1266         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1267 #endif
1268         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1269         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1270                                 &_vmexit_control) < 0)
1271                 return -EIO;
1272
1273         min = 0;
1274         opt = VM_ENTRY_LOAD_IA32_PAT;
1275         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1276                                 &_vmentry_control) < 0)
1277                 return -EIO;
1278
1279         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1280
1281         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1282         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1283                 return -EIO;
1284
1285 #ifdef CONFIG_X86_64
1286         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1287         if (vmx_msr_high & (1u<<16))
1288                 return -EIO;
1289 #endif
1290
1291         /* Require Write-Back (WB) memory type for VMCS accesses. */
1292         if (((vmx_msr_high >> 18) & 15) != 6)
1293                 return -EIO;
1294
1295         vmcs_conf->size = vmx_msr_high & 0x1fff;
1296         vmcs_conf->order = get_order(vmcs_config.size);
1297         vmcs_conf->revision_id = vmx_msr_low;
1298
1299         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1300         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1301         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1302         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1303         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1304
1305         return 0;
1306 }
1307
1308 static struct vmcs *alloc_vmcs_cpu(int cpu)
1309 {
1310         int node = cpu_to_node(cpu);
1311         struct page *pages;
1312         struct vmcs *vmcs;
1313
1314         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1315         if (!pages)
1316                 return NULL;
1317         vmcs = page_address(pages);
1318         memset(vmcs, 0, vmcs_config.size);
1319         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1320         return vmcs;
1321 }
1322
1323 static struct vmcs *alloc_vmcs(void)
1324 {
1325         return alloc_vmcs_cpu(raw_smp_processor_id());
1326 }
1327
1328 static void free_vmcs(struct vmcs *vmcs)
1329 {
1330         free_pages((unsigned long)vmcs, vmcs_config.order);
1331 }
1332
1333 static void free_kvm_area(void)
1334 {
1335         int cpu;
1336
1337         for_each_possible_cpu(cpu) {
1338                 free_vmcs(per_cpu(vmxarea, cpu));
1339                 per_cpu(vmxarea, cpu) = NULL;
1340         }
1341 }
1342
1343 static __init int alloc_kvm_area(void)
1344 {
1345         int cpu;
1346
1347         for_each_possible_cpu(cpu) {
1348                 struct vmcs *vmcs;
1349
1350                 vmcs = alloc_vmcs_cpu(cpu);
1351                 if (!vmcs) {
1352                         free_kvm_area();
1353                         return -ENOMEM;
1354                 }
1355
1356                 per_cpu(vmxarea, cpu) = vmcs;
1357         }
1358         return 0;
1359 }
1360
1361 static __init int hardware_setup(void)
1362 {
1363         if (setup_vmcs_config(&vmcs_config) < 0)
1364                 return -EIO;
1365
1366         if (boot_cpu_has(X86_FEATURE_NX))
1367                 kvm_enable_efer_bits(EFER_NX);
1368
1369         if (!cpu_has_vmx_vpid())
1370                 enable_vpid = 0;
1371
1372         if (!cpu_has_vmx_ept()) {
1373                 enable_ept = 0;
1374                 enable_unrestricted_guest = 0;
1375         }
1376
1377         if (!cpu_has_vmx_unrestricted_guest())
1378                 enable_unrestricted_guest = 0;
1379
1380         if (!cpu_has_vmx_flexpriority())
1381                 flexpriority_enabled = 0;
1382
1383         if (!cpu_has_vmx_tpr_shadow())
1384                 kvm_x86_ops->update_cr8_intercept = NULL;
1385
1386         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1387                 kvm_disable_largepages();
1388
1389         return alloc_kvm_area();
1390 }
1391
1392 static __exit void hardware_unsetup(void)
1393 {
1394         free_kvm_area();
1395 }
1396
1397 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1398 {
1399         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1400
1401         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1402                 vmcs_write16(sf->selector, save->selector);
1403                 vmcs_writel(sf->base, save->base);
1404                 vmcs_write32(sf->limit, save->limit);
1405                 vmcs_write32(sf->ar_bytes, save->ar);
1406         } else {
1407                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1408                         << AR_DPL_SHIFT;
1409                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1410         }
1411 }
1412
1413 static void enter_pmode(struct kvm_vcpu *vcpu)
1414 {
1415         unsigned long flags;
1416         struct vcpu_vmx *vmx = to_vmx(vcpu);
1417
1418         vmx->emulation_required = 1;
1419         vmx->rmode.vm86_active = 0;
1420
1421         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1422         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1423         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1424
1425         flags = vmcs_readl(GUEST_RFLAGS);
1426         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1427         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1428         vmcs_writel(GUEST_RFLAGS, flags);
1429
1430         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1431                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1432
1433         update_exception_bitmap(vcpu);
1434
1435         if (emulate_invalid_guest_state)
1436                 return;
1437
1438         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1439         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1440         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1441         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1442
1443         vmcs_write16(GUEST_SS_SELECTOR, 0);
1444         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1445
1446         vmcs_write16(GUEST_CS_SELECTOR,
1447                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1448         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1449 }
1450
1451 static gva_t rmode_tss_base(struct kvm *kvm)
1452 {
1453         if (!kvm->arch.tss_addr) {
1454                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1455                                  kvm->memslots[0].npages - 3;
1456                 return base_gfn << PAGE_SHIFT;
1457         }
1458         return kvm->arch.tss_addr;
1459 }
1460
1461 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1462 {
1463         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1464
1465         save->selector = vmcs_read16(sf->selector);
1466         save->base = vmcs_readl(sf->base);
1467         save->limit = vmcs_read32(sf->limit);
1468         save->ar = vmcs_read32(sf->ar_bytes);
1469         vmcs_write16(sf->selector, save->base >> 4);
1470         vmcs_write32(sf->base, save->base & 0xfffff);
1471         vmcs_write32(sf->limit, 0xffff);
1472         vmcs_write32(sf->ar_bytes, 0xf3);
1473 }
1474
1475 static void enter_rmode(struct kvm_vcpu *vcpu)
1476 {
1477         unsigned long flags;
1478         struct vcpu_vmx *vmx = to_vmx(vcpu);
1479
1480         if (enable_unrestricted_guest)
1481                 return;
1482
1483         vmx->emulation_required = 1;
1484         vmx->rmode.vm86_active = 1;
1485
1486         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1487         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1488
1489         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1490         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1491
1492         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1493         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1494
1495         flags = vmcs_readl(GUEST_RFLAGS);
1496         vmx->rmode.save_iopl
1497                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1498
1499         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1500
1501         vmcs_writel(GUEST_RFLAGS, flags);
1502         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1503         update_exception_bitmap(vcpu);
1504
1505         if (emulate_invalid_guest_state)
1506                 goto continue_rmode;
1507
1508         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1509         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1510         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1511
1512         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1513         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1514         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1515                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1516         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1517
1518         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1519         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1520         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1521         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1522
1523 continue_rmode:
1524         kvm_mmu_reset_context(vcpu);
1525         init_rmode(vcpu->kvm);
1526 }
1527
1528 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1529 {
1530         struct vcpu_vmx *vmx = to_vmx(vcpu);
1531         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1532
1533         vcpu->arch.shadow_efer = efer;
1534         if (!msr)
1535                 return;
1536         if (efer & EFER_LMA) {
1537                 vmcs_write32(VM_ENTRY_CONTROLS,
1538                              vmcs_read32(VM_ENTRY_CONTROLS) |
1539                              VM_ENTRY_IA32E_MODE);
1540                 msr->data = efer;
1541         } else {
1542                 vmcs_write32(VM_ENTRY_CONTROLS,
1543                              vmcs_read32(VM_ENTRY_CONTROLS) &
1544                              ~VM_ENTRY_IA32E_MODE);
1545
1546                 msr->data = efer & ~EFER_LME;
1547         }
1548         setup_msrs(vmx);
1549 }
1550
1551 #ifdef CONFIG_X86_64
1552
1553 static void enter_lmode(struct kvm_vcpu *vcpu)
1554 {
1555         u32 guest_tr_ar;
1556
1557         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1558         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1559                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1560                        __func__);
1561                 vmcs_write32(GUEST_TR_AR_BYTES,
1562                              (guest_tr_ar & ~AR_TYPE_MASK)
1563                              | AR_TYPE_BUSY_64_TSS);
1564         }
1565         vcpu->arch.shadow_efer |= EFER_LMA;
1566         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1567 }
1568
1569 static void exit_lmode(struct kvm_vcpu *vcpu)
1570 {
1571         vcpu->arch.shadow_efer &= ~EFER_LMA;
1572
1573         vmcs_write32(VM_ENTRY_CONTROLS,
1574                      vmcs_read32(VM_ENTRY_CONTROLS)
1575                      & ~VM_ENTRY_IA32E_MODE);
1576 }
1577
1578 #endif
1579
1580 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1581 {
1582         vpid_sync_vcpu_all(to_vmx(vcpu));
1583         if (enable_ept)
1584                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1585 }
1586
1587 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1588 {
1589         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1590         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1591 }
1592
1593 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1594 {
1595         if (!test_bit(VCPU_EXREG_PDPTR,
1596                       (unsigned long *)&vcpu->arch.regs_dirty))
1597                 return;
1598
1599         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1600                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1601                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1602                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1603                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1604         }
1605 }
1606
1607 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1608 {
1609         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1610                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1611                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1612                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1613                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1614         }
1615
1616         __set_bit(VCPU_EXREG_PDPTR,
1617                   (unsigned long *)&vcpu->arch.regs_avail);
1618         __set_bit(VCPU_EXREG_PDPTR,
1619                   (unsigned long *)&vcpu->arch.regs_dirty);
1620 }
1621
1622 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1623
1624 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1625                                         unsigned long cr0,
1626                                         struct kvm_vcpu *vcpu)
1627 {
1628         if (!(cr0 & X86_CR0_PG)) {
1629                 /* From paging/starting to nonpaging */
1630                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1631                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1632                              (CPU_BASED_CR3_LOAD_EXITING |
1633                               CPU_BASED_CR3_STORE_EXITING));
1634                 vcpu->arch.cr0 = cr0;
1635                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1636         } else if (!is_paging(vcpu)) {
1637                 /* From nonpaging to paging */
1638                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1639                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1640                              ~(CPU_BASED_CR3_LOAD_EXITING |
1641                                CPU_BASED_CR3_STORE_EXITING));
1642                 vcpu->arch.cr0 = cr0;
1643                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1644         }
1645
1646         if (!(cr0 & X86_CR0_WP))
1647                 *hw_cr0 &= ~X86_CR0_WP;
1648 }
1649
1650 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1651                                         struct kvm_vcpu *vcpu)
1652 {
1653         if (!is_paging(vcpu)) {
1654                 *hw_cr4 &= ~X86_CR4_PAE;
1655                 *hw_cr4 |= X86_CR4_PSE;
1656         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1657                 *hw_cr4 &= ~X86_CR4_PAE;
1658 }
1659
1660 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1661 {
1662         struct vcpu_vmx *vmx = to_vmx(vcpu);
1663         unsigned long hw_cr0;
1664
1665         if (enable_unrestricted_guest)
1666                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1667                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1668         else
1669                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1670
1671         vmx_fpu_deactivate(vcpu);
1672
1673         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1674                 enter_pmode(vcpu);
1675
1676         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1677                 enter_rmode(vcpu);
1678
1679 #ifdef CONFIG_X86_64
1680         if (vcpu->arch.shadow_efer & EFER_LME) {
1681                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1682                         enter_lmode(vcpu);
1683                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1684                         exit_lmode(vcpu);
1685         }
1686 #endif
1687
1688         if (enable_ept)
1689                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1690
1691         vmcs_writel(CR0_READ_SHADOW, cr0);
1692         vmcs_writel(GUEST_CR0, hw_cr0);
1693         vcpu->arch.cr0 = cr0;
1694
1695         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1696                 vmx_fpu_activate(vcpu);
1697 }
1698
1699 static u64 construct_eptp(unsigned long root_hpa)
1700 {
1701         u64 eptp;
1702
1703         /* TODO write the value reading from MSR */
1704         eptp = VMX_EPT_DEFAULT_MT |
1705                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1706         eptp |= (root_hpa & PAGE_MASK);
1707
1708         return eptp;
1709 }
1710
1711 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1712 {
1713         unsigned long guest_cr3;
1714         u64 eptp;
1715
1716         guest_cr3 = cr3;
1717         if (enable_ept) {
1718                 eptp = construct_eptp(cr3);
1719                 vmcs_write64(EPT_POINTER, eptp);
1720                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1721                         vcpu->kvm->arch.ept_identity_map_addr;
1722         }
1723
1724         vmx_flush_tlb(vcpu);
1725         vmcs_writel(GUEST_CR3, guest_cr3);
1726         if (vcpu->arch.cr0 & X86_CR0_PE)
1727                 vmx_fpu_deactivate(vcpu);
1728 }
1729
1730 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1731 {
1732         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1733                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1734
1735         vcpu->arch.cr4 = cr4;
1736         if (enable_ept)
1737                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1738
1739         vmcs_writel(CR4_READ_SHADOW, cr4);
1740         vmcs_writel(GUEST_CR4, hw_cr4);
1741 }
1742
1743 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1744 {
1745         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1746
1747         return vmcs_readl(sf->base);
1748 }
1749
1750 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1751                             struct kvm_segment *var, int seg)
1752 {
1753         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1754         u32 ar;
1755
1756         var->base = vmcs_readl(sf->base);
1757         var->limit = vmcs_read32(sf->limit);
1758         var->selector = vmcs_read16(sf->selector);
1759         ar = vmcs_read32(sf->ar_bytes);
1760         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1761                 ar = 0;
1762         var->type = ar & 15;
1763         var->s = (ar >> 4) & 1;
1764         var->dpl = (ar >> 5) & 3;
1765         var->present = (ar >> 7) & 1;
1766         var->avl = (ar >> 12) & 1;
1767         var->l = (ar >> 13) & 1;
1768         var->db = (ar >> 14) & 1;
1769         var->g = (ar >> 15) & 1;
1770         var->unusable = (ar >> 16) & 1;
1771 }
1772
1773 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1774 {
1775         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1776                 return 0;
1777
1778         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1779                 return 3;
1780
1781         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1782 }
1783
1784 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1785 {
1786         u32 ar;
1787
1788         if (var->unusable)
1789                 ar = 1 << 16;
1790         else {
1791                 ar = var->type & 15;
1792                 ar |= (var->s & 1) << 4;
1793                 ar |= (var->dpl & 3) << 5;
1794                 ar |= (var->present & 1) << 7;
1795                 ar |= (var->avl & 1) << 12;
1796                 ar |= (var->l & 1) << 13;
1797                 ar |= (var->db & 1) << 14;
1798                 ar |= (var->g & 1) << 15;
1799         }
1800         if (ar == 0) /* a 0 value means unusable */
1801                 ar = AR_UNUSABLE_MASK;
1802
1803         return ar;
1804 }
1805
1806 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1807                             struct kvm_segment *var, int seg)
1808 {
1809         struct vcpu_vmx *vmx = to_vmx(vcpu);
1810         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1811         u32 ar;
1812
1813         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1814                 vmx->rmode.tr.selector = var->selector;
1815                 vmx->rmode.tr.base = var->base;
1816                 vmx->rmode.tr.limit = var->limit;
1817                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1818                 return;
1819         }
1820         vmcs_writel(sf->base, var->base);
1821         vmcs_write32(sf->limit, var->limit);
1822         vmcs_write16(sf->selector, var->selector);
1823         if (vmx->rmode.vm86_active && var->s) {
1824                 /*
1825                  * Hack real-mode segments into vm86 compatibility.
1826                  */
1827                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1828                         vmcs_writel(sf->base, 0xf0000);
1829                 ar = 0xf3;
1830         } else
1831                 ar = vmx_segment_access_rights(var);
1832
1833         /*
1834          *   Fix the "Accessed" bit in AR field of segment registers for older
1835          * qemu binaries.
1836          *   IA32 arch specifies that at the time of processor reset the
1837          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1838          * is setting it to 0 in the usedland code. This causes invalid guest
1839          * state vmexit when "unrestricted guest" mode is turned on.
1840          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1841          * tree. Newer qemu binaries with that qemu fix would not need this
1842          * kvm hack.
1843          */
1844         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1845                 ar |= 0x1; /* Accessed */
1846
1847         vmcs_write32(sf->ar_bytes, ar);
1848 }
1849
1850 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1851 {
1852         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1853
1854         *db = (ar >> 14) & 1;
1855         *l = (ar >> 13) & 1;
1856 }
1857
1858 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1859 {
1860         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1861         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1862 }
1863
1864 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1865 {
1866         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1867         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1868 }
1869
1870 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1871 {
1872         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1873         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1874 }
1875
1876 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1877 {
1878         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1879         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1880 }
1881
1882 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1883 {
1884         struct kvm_segment var;
1885         u32 ar;
1886
1887         vmx_get_segment(vcpu, &var, seg);
1888         ar = vmx_segment_access_rights(&var);
1889
1890         if (var.base != (var.selector << 4))
1891                 return false;
1892         if (var.limit != 0xffff)
1893                 return false;
1894         if (ar != 0xf3)
1895                 return false;
1896
1897         return true;
1898 }
1899
1900 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1901 {
1902         struct kvm_segment cs;
1903         unsigned int cs_rpl;
1904
1905         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1906         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1907
1908         if (cs.unusable)
1909                 return false;
1910         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1911                 return false;
1912         if (!cs.s)
1913                 return false;
1914         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1915                 if (cs.dpl > cs_rpl)
1916                         return false;
1917         } else {
1918                 if (cs.dpl != cs_rpl)
1919                         return false;
1920         }
1921         if (!cs.present)
1922                 return false;
1923
1924         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1925         return true;
1926 }
1927
1928 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1929 {
1930         struct kvm_segment ss;
1931         unsigned int ss_rpl;
1932
1933         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1934         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1935
1936         if (ss.unusable)
1937                 return true;
1938         if (ss.type != 3 && ss.type != 7)
1939                 return false;
1940         if (!ss.s)
1941                 return false;
1942         if (ss.dpl != ss_rpl) /* DPL != RPL */
1943                 return false;
1944         if (!ss.present)
1945                 return false;
1946
1947         return true;
1948 }
1949
1950 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1951 {
1952         struct kvm_segment var;
1953         unsigned int rpl;
1954
1955         vmx_get_segment(vcpu, &var, seg);
1956         rpl = var.selector & SELECTOR_RPL_MASK;
1957
1958         if (var.unusable)
1959                 return true;
1960         if (!var.s)
1961                 return false;
1962         if (!var.present)
1963                 return false;
1964         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1965                 if (var.dpl < rpl) /* DPL < RPL */
1966                         return false;
1967         }
1968
1969         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1970          * rights flags
1971          */
1972         return true;
1973 }
1974
1975 static bool tr_valid(struct kvm_vcpu *vcpu)
1976 {
1977         struct kvm_segment tr;
1978
1979         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1980
1981         if (tr.unusable)
1982                 return false;
1983         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1984                 return false;
1985         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1986                 return false;
1987         if (!tr.present)
1988                 return false;
1989
1990         return true;
1991 }
1992
1993 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1994 {
1995         struct kvm_segment ldtr;
1996
1997         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1998
1999         if (ldtr.unusable)
2000                 return true;
2001         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2002                 return false;
2003         if (ldtr.type != 2)
2004                 return false;
2005         if (!ldtr.present)
2006                 return false;
2007
2008         return true;
2009 }
2010
2011 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2012 {
2013         struct kvm_segment cs, ss;
2014
2015         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2016         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2017
2018         return ((cs.selector & SELECTOR_RPL_MASK) ==
2019                  (ss.selector & SELECTOR_RPL_MASK));
2020 }
2021
2022 /*
2023  * Check if guest state is valid. Returns true if valid, false if
2024  * not.
2025  * We assume that registers are always usable
2026  */
2027 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2028 {
2029         /* real mode guest state checks */
2030         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2031                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2032                         return false;
2033                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2034                         return false;
2035                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2036                         return false;
2037                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2038                         return false;
2039                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2040                         return false;
2041                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2042                         return false;
2043         } else {
2044         /* protected mode guest state checks */
2045                 if (!cs_ss_rpl_check(vcpu))
2046                         return false;
2047                 if (!code_segment_valid(vcpu))
2048                         return false;
2049                 if (!stack_segment_valid(vcpu))
2050                         return false;
2051                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2052                         return false;
2053                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2054                         return false;
2055                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2056                         return false;
2057                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2058                         return false;
2059                 if (!tr_valid(vcpu))
2060                         return false;
2061                 if (!ldtr_valid(vcpu))
2062                         return false;
2063         }
2064         /* TODO:
2065          * - Add checks on RIP
2066          * - Add checks on RFLAGS
2067          */
2068
2069         return true;
2070 }
2071
2072 static int init_rmode_tss(struct kvm *kvm)
2073 {
2074         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2075         u16 data = 0;
2076         int ret = 0;
2077         int r;
2078
2079         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2080         if (r < 0)
2081                 goto out;
2082         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2083         r = kvm_write_guest_page(kvm, fn++, &data,
2084                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2085         if (r < 0)
2086                 goto out;
2087         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2088         if (r < 0)
2089                 goto out;
2090         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2091         if (r < 0)
2092                 goto out;
2093         data = ~0;
2094         r = kvm_write_guest_page(kvm, fn, &data,
2095                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2096                                  sizeof(u8));
2097         if (r < 0)
2098                 goto out;
2099
2100         ret = 1;
2101 out:
2102         return ret;
2103 }
2104
2105 static int init_rmode_identity_map(struct kvm *kvm)
2106 {
2107         int i, r, ret;
2108         pfn_t identity_map_pfn;
2109         u32 tmp;
2110
2111         if (!enable_ept)
2112                 return 1;
2113         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2114                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2115                         "haven't been allocated!\n");
2116                 return 0;
2117         }
2118         if (likely(kvm->arch.ept_identity_pagetable_done))
2119                 return 1;
2120         ret = 0;
2121         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2122         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2123         if (r < 0)
2124                 goto out;
2125         /* Set up identity-mapping pagetable for EPT in real mode */
2126         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2127                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2128                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2129                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2130                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2131                 if (r < 0)
2132                         goto out;
2133         }
2134         kvm->arch.ept_identity_pagetable_done = true;
2135         ret = 1;
2136 out:
2137         return ret;
2138 }
2139
2140 static void seg_setup(int seg)
2141 {
2142         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2143         unsigned int ar;
2144
2145         vmcs_write16(sf->selector, 0);
2146         vmcs_writel(sf->base, 0);
2147         vmcs_write32(sf->limit, 0xffff);
2148         if (enable_unrestricted_guest) {
2149                 ar = 0x93;
2150                 if (seg == VCPU_SREG_CS)
2151                         ar |= 0x08; /* code segment */
2152         } else
2153                 ar = 0xf3;
2154
2155         vmcs_write32(sf->ar_bytes, ar);
2156 }
2157
2158 static int alloc_apic_access_page(struct kvm *kvm)
2159 {
2160         struct kvm_userspace_memory_region kvm_userspace_mem;
2161         int r = 0;
2162
2163         down_write(&kvm->slots_lock);
2164         if (kvm->arch.apic_access_page)
2165                 goto out;
2166         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2167         kvm_userspace_mem.flags = 0;
2168         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2169         kvm_userspace_mem.memory_size = PAGE_SIZE;
2170         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2171         if (r)
2172                 goto out;
2173
2174         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2175 out:
2176         up_write(&kvm->slots_lock);
2177         return r;
2178 }
2179
2180 static int alloc_identity_pagetable(struct kvm *kvm)
2181 {
2182         struct kvm_userspace_memory_region kvm_userspace_mem;
2183         int r = 0;
2184
2185         down_write(&kvm->slots_lock);
2186         if (kvm->arch.ept_identity_pagetable)
2187                 goto out;
2188         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2189         kvm_userspace_mem.flags = 0;
2190         kvm_userspace_mem.guest_phys_addr =
2191                 kvm->arch.ept_identity_map_addr;
2192         kvm_userspace_mem.memory_size = PAGE_SIZE;
2193         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2194         if (r)
2195                 goto out;
2196
2197         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2198                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2199 out:
2200         up_write(&kvm->slots_lock);
2201         return r;
2202 }
2203
2204 static void allocate_vpid(struct vcpu_vmx *vmx)
2205 {
2206         int vpid;
2207
2208         vmx->vpid = 0;
2209         if (!enable_vpid)
2210                 return;
2211         spin_lock(&vmx_vpid_lock);
2212         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2213         if (vpid < VMX_NR_VPIDS) {
2214                 vmx->vpid = vpid;
2215                 __set_bit(vpid, vmx_vpid_bitmap);
2216         }
2217         spin_unlock(&vmx_vpid_lock);
2218 }
2219
2220 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2221 {
2222         int f = sizeof(unsigned long);
2223
2224         if (!cpu_has_vmx_msr_bitmap())
2225                 return;
2226
2227         /*
2228          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2229          * have the write-low and read-high bitmap offsets the wrong way round.
2230          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2231          */
2232         if (msr <= 0x1fff) {
2233                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2234                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2235         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2236                 msr &= 0x1fff;
2237                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2238                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2239         }
2240 }
2241
2242 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2243 {
2244         if (!longmode_only)
2245                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2246         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2247 }
2248
2249 /*
2250  * Sets up the vmcs for emulated real mode.
2251  */
2252 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2253 {
2254         u32 host_sysenter_cs, msr_low, msr_high;
2255         u32 junk;
2256         u64 host_pat, tsc_this, tsc_base;
2257         unsigned long a;
2258         struct descriptor_table dt;
2259         int i;
2260         unsigned long kvm_vmx_return;
2261         u32 exec_control;
2262
2263         /* I/O */
2264         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2265         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2266
2267         if (cpu_has_vmx_msr_bitmap())
2268                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2269
2270         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2271
2272         /* Control */
2273         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2274                 vmcs_config.pin_based_exec_ctrl);
2275
2276         exec_control = vmcs_config.cpu_based_exec_ctrl;
2277         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2278                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2279 #ifdef CONFIG_X86_64
2280                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2281                                 CPU_BASED_CR8_LOAD_EXITING;
2282 #endif
2283         }
2284         if (!enable_ept)
2285                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2286                                 CPU_BASED_CR3_LOAD_EXITING  |
2287                                 CPU_BASED_INVLPG_EXITING;
2288         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2289
2290         if (cpu_has_secondary_exec_ctrls()) {
2291                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2292                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2293                         exec_control &=
2294                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2295                 if (vmx->vpid == 0)
2296                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2297                 if (!enable_ept)
2298                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2299                 if (!enable_unrestricted_guest)
2300                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2301                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2302         }
2303
2304         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2305         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2306         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2307
2308         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2309         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2310         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2311
2312         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2313         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2314         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2315         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2316         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2317         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2318 #ifdef CONFIG_X86_64
2319         rdmsrl(MSR_FS_BASE, a);
2320         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2321         rdmsrl(MSR_GS_BASE, a);
2322         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2323 #else
2324         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2325         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2326 #endif
2327
2328         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2329
2330         kvm_get_idt(&dt);
2331         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2332
2333         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2334         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2335         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2336         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2337         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2338
2339         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2340         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2341         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2342         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2343         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2344         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2345
2346         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2347                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2348                 host_pat = msr_low | ((u64) msr_high << 32);
2349                 vmcs_write64(HOST_IA32_PAT, host_pat);
2350         }
2351         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2352                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2353                 host_pat = msr_low | ((u64) msr_high << 32);
2354                 /* Write the default value follow host pat */
2355                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2356                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2357                 vmx->vcpu.arch.pat = host_pat;
2358         }
2359
2360         for (i = 0; i < NR_VMX_MSR; ++i) {
2361                 u32 index = vmx_msr_index[i];
2362                 u32 data_low, data_high;
2363                 u64 data;
2364                 int j = vmx->nmsrs;
2365
2366                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2367                         continue;
2368                 if (wrmsr_safe(index, data_low, data_high) < 0)
2369                         continue;
2370                 data = data_low | ((u64)data_high << 32);
2371                 vmx->host_msrs[j].index = index;
2372                 vmx->host_msrs[j].reserved = 0;
2373                 vmx->host_msrs[j].data = data;
2374                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2375                 ++vmx->nmsrs;
2376         }
2377
2378         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2379
2380         /* 22.2.1, 20.8.1 */
2381         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2382
2383         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2384         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2385
2386         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2387         rdtscll(tsc_this);
2388         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2389                 tsc_base = tsc_this;
2390
2391         guest_write_tsc(0, tsc_base);
2392
2393         return 0;
2394 }
2395
2396 static int init_rmode(struct kvm *kvm)
2397 {
2398         if (!init_rmode_tss(kvm))
2399                 return 0;
2400         if (!init_rmode_identity_map(kvm))
2401                 return 0;
2402         return 1;
2403 }
2404
2405 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2406 {
2407         struct vcpu_vmx *vmx = to_vmx(vcpu);
2408         u64 msr;
2409         int ret;
2410
2411         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2412         down_read(&vcpu->kvm->slots_lock);
2413         if (!init_rmode(vmx->vcpu.kvm)) {
2414                 ret = -ENOMEM;
2415                 goto out;
2416         }
2417
2418         vmx->rmode.vm86_active = 0;
2419
2420         vmx->soft_vnmi_blocked = 0;
2421
2422         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2423         kvm_set_cr8(&vmx->vcpu, 0);
2424         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2425         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2426                 msr |= MSR_IA32_APICBASE_BSP;
2427         kvm_set_apic_base(&vmx->vcpu, msr);
2428
2429         fx_init(&vmx->vcpu);
2430
2431         seg_setup(VCPU_SREG_CS);
2432         /*
2433          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2434          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2435          */
2436         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2437                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2438                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2439         } else {
2440                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2441                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2442         }
2443
2444         seg_setup(VCPU_SREG_DS);
2445         seg_setup(VCPU_SREG_ES);
2446         seg_setup(VCPU_SREG_FS);
2447         seg_setup(VCPU_SREG_GS);
2448         seg_setup(VCPU_SREG_SS);
2449
2450         vmcs_write16(GUEST_TR_SELECTOR, 0);
2451         vmcs_writel(GUEST_TR_BASE, 0);
2452         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2453         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2454
2455         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2456         vmcs_writel(GUEST_LDTR_BASE, 0);
2457         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2458         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2459
2460         vmcs_write32(GUEST_SYSENTER_CS, 0);
2461         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2462         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2463
2464         vmcs_writel(GUEST_RFLAGS, 0x02);
2465         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2466                 kvm_rip_write(vcpu, 0xfff0);
2467         else
2468                 kvm_rip_write(vcpu, 0);
2469         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2470
2471         vmcs_writel(GUEST_DR7, 0x400);
2472
2473         vmcs_writel(GUEST_GDTR_BASE, 0);
2474         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2475
2476         vmcs_writel(GUEST_IDTR_BASE, 0);
2477         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2478
2479         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2480         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2481         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2482
2483         /* Special registers */
2484         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2485
2486         setup_msrs(vmx);
2487
2488         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2489
2490         if (cpu_has_vmx_tpr_shadow()) {
2491                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2492                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2493                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2494                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2495                 vmcs_write32(TPR_THRESHOLD, 0);
2496         }
2497
2498         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2499                 vmcs_write64(APIC_ACCESS_ADDR,
2500                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2501
2502         if (vmx->vpid != 0)
2503                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2504
2505         vmx->vcpu.arch.cr0 = 0x60000010;
2506         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2507         vmx_set_cr4(&vmx->vcpu, 0);
2508         vmx_set_efer(&vmx->vcpu, 0);
2509         vmx_fpu_activate(&vmx->vcpu);
2510         update_exception_bitmap(&vmx->vcpu);
2511
2512         vpid_sync_vcpu_all(vmx);
2513
2514         ret = 0;
2515
2516         /* HACK: Don't enable emulation on guest boot/reset */
2517         vmx->emulation_required = 0;
2518
2519 out:
2520         up_read(&vcpu->kvm->slots_lock);
2521         return ret;
2522 }
2523
2524 static void enable_irq_window(struct kvm_vcpu *vcpu)
2525 {
2526         u32 cpu_based_vm_exec_control;
2527
2528         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2529         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2530         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2531 }
2532
2533 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2534 {
2535         u32 cpu_based_vm_exec_control;
2536
2537         if (!cpu_has_virtual_nmis()) {
2538                 enable_irq_window(vcpu);
2539                 return;
2540         }
2541
2542         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2543         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2544         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2545 }
2546
2547 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2548 {
2549         struct vcpu_vmx *vmx = to_vmx(vcpu);
2550         uint32_t intr;
2551         int irq = vcpu->arch.interrupt.nr;
2552
2553         trace_kvm_inj_virq(irq);
2554
2555         ++vcpu->stat.irq_injections;
2556         if (vmx->rmode.vm86_active) {
2557                 vmx->rmode.irq.pending = true;
2558                 vmx->rmode.irq.vector = irq;
2559                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2560                 if (vcpu->arch.interrupt.soft)
2561                         vmx->rmode.irq.rip +=
2562                                 vmx->vcpu.arch.event_exit_inst_len;
2563                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2564                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2565                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2566                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2567                 return;
2568         }
2569         intr = irq | INTR_INFO_VALID_MASK;
2570         if (vcpu->arch.interrupt.soft) {
2571                 intr |= INTR_TYPE_SOFT_INTR;
2572                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2573                              vmx->vcpu.arch.event_exit_inst_len);
2574         } else
2575                 intr |= INTR_TYPE_EXT_INTR;
2576         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2577 }
2578
2579 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2580 {
2581         struct vcpu_vmx *vmx = to_vmx(vcpu);
2582
2583         if (!cpu_has_virtual_nmis()) {
2584                 /*
2585                  * Tracking the NMI-blocked state in software is built upon
2586                  * finding the next open IRQ window. This, in turn, depends on
2587                  * well-behaving guests: They have to keep IRQs disabled at
2588                  * least as long as the NMI handler runs. Otherwise we may
2589                  * cause NMI nesting, maybe breaking the guest. But as this is
2590                  * highly unlikely, we can live with the residual risk.
2591                  */
2592                 vmx->soft_vnmi_blocked = 1;
2593                 vmx->vnmi_blocked_time = 0;
2594         }
2595
2596         ++vcpu->stat.nmi_injections;
2597         if (vmx->rmode.vm86_active) {
2598                 vmx->rmode.irq.pending = true;
2599                 vmx->rmode.irq.vector = NMI_VECTOR;
2600                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2601                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2602                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2603                              INTR_INFO_VALID_MASK);
2604                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2605                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2606                 return;
2607         }
2608         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2609                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2610 }
2611
2612 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2613 {
2614         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2615                 return 0;
2616
2617         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2618                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2619                                 GUEST_INTR_STATE_NMI));
2620 }
2621
2622 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2623 {
2624         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2625                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2626                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2627 }
2628
2629 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2630 {
2631         int ret;
2632         struct kvm_userspace_memory_region tss_mem = {
2633                 .slot = TSS_PRIVATE_MEMSLOT,
2634                 .guest_phys_addr = addr,
2635                 .memory_size = PAGE_SIZE * 3,
2636                 .flags = 0,
2637         };
2638
2639         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2640         if (ret)
2641                 return ret;
2642         kvm->arch.tss_addr = addr;
2643         return 0;
2644 }
2645
2646 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2647                                   int vec, u32 err_code)
2648 {
2649         /*
2650          * Instruction with address size override prefix opcode 0x67
2651          * Cause the #SS fault with 0 error code in VM86 mode.
2652          */
2653         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2654                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2655                         return 1;
2656         /*
2657          * Forward all other exceptions that are valid in real mode.
2658          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2659          *        the required debugging infrastructure rework.
2660          */
2661         switch (vec) {
2662         case DB_VECTOR:
2663                 if (vcpu->guest_debug &
2664                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2665                         return 0;
2666                 kvm_queue_exception(vcpu, vec);
2667                 return 1;
2668         case BP_VECTOR:
2669                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2670                         return 0;
2671                 /* fall through */
2672         case DE_VECTOR:
2673         case OF_VECTOR:
2674         case BR_VECTOR:
2675         case UD_VECTOR:
2676         case DF_VECTOR:
2677         case SS_VECTOR:
2678         case GP_VECTOR:
2679         case MF_VECTOR:
2680                 kvm_queue_exception(vcpu, vec);
2681                 return 1;
2682         }
2683         return 0;
2684 }
2685
2686 /*
2687  * Trigger machine check on the host. We assume all the MSRs are already set up
2688  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2689  * We pass a fake environment to the machine check handler because we want
2690  * the guest to be always treated like user space, no matter what context
2691  * it used internally.
2692  */
2693 static void kvm_machine_check(void)
2694 {
2695 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2696         struct pt_regs regs = {
2697                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2698                 .flags = X86_EFLAGS_IF,
2699         };
2700
2701         do_machine_check(&regs, 0);
2702 #endif
2703 }
2704
2705 static int handle_machine_check(struct kvm_vcpu *vcpu)
2706 {
2707         /* already handled by vcpu_run */
2708         return 1;
2709 }
2710
2711 static int handle_exception(struct kvm_vcpu *vcpu)
2712 {
2713         struct vcpu_vmx *vmx = to_vmx(vcpu);
2714         struct kvm_run *kvm_run = vcpu->run;
2715         u32 intr_info, ex_no, error_code;
2716         unsigned long cr2, rip, dr6;
2717         u32 vect_info;
2718         enum emulation_result er;
2719
2720         vect_info = vmx->idt_vectoring_info;
2721         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2722
2723         if (is_machine_check(intr_info))
2724                 return handle_machine_check(vcpu);
2725
2726         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2727                                                 !is_page_fault(intr_info))
2728                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2729                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2730
2731         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2732                 return 1;  /* already handled by vmx_vcpu_run() */
2733
2734         if (is_no_device(intr_info)) {
2735                 vmx_fpu_activate(vcpu);
2736                 return 1;
2737         }
2738
2739         if (is_invalid_opcode(intr_info)) {
2740                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2741                 if (er != EMULATE_DONE)
2742                         kvm_queue_exception(vcpu, UD_VECTOR);
2743                 return 1;
2744         }
2745
2746         error_code = 0;
2747         rip = kvm_rip_read(vcpu);
2748         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2749                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2750         if (is_page_fault(intr_info)) {
2751                 /* EPT won't cause page fault directly */
2752                 if (enable_ept)
2753                         BUG();
2754                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2755                 trace_kvm_page_fault(cr2, error_code);
2756
2757                 if (kvm_event_needs_reinjection(vcpu))
2758                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2759                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2760         }
2761
2762         if (vmx->rmode.vm86_active &&
2763             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2764                                                                 error_code)) {
2765                 if (vcpu->arch.halt_request) {
2766                         vcpu->arch.halt_request = 0;
2767                         return kvm_emulate_halt(vcpu);
2768                 }
2769                 return 1;
2770         }
2771
2772         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2773         switch (ex_no) {
2774         case DB_VECTOR:
2775                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2776                 if (!(vcpu->guest_debug &
2777                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2778                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2779                         kvm_queue_exception(vcpu, DB_VECTOR);
2780                         return 1;
2781                 }
2782                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2783                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2784                 /* fall through */
2785         case BP_VECTOR:
2786                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2787                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2788                 kvm_run->debug.arch.exception = ex_no;
2789                 break;
2790         default:
2791                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2792                 kvm_run->ex.exception = ex_no;
2793                 kvm_run->ex.error_code = error_code;
2794                 break;
2795         }
2796         return 0;
2797 }
2798
2799 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2800 {
2801         ++vcpu->stat.irq_exits;
2802         return 1;
2803 }
2804
2805 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2806 {
2807         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2808         return 0;
2809 }
2810
2811 static int handle_io(struct kvm_vcpu *vcpu)
2812 {
2813         unsigned long exit_qualification;
2814         int size, in, string;
2815         unsigned port;
2816
2817         ++vcpu->stat.io_exits;
2818         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2819         string = (exit_qualification & 16) != 0;
2820
2821         if (string) {
2822                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2823                         return 0;
2824                 return 1;
2825         }
2826
2827         size = (exit_qualification & 7) + 1;
2828         in = (exit_qualification & 8) != 0;
2829         port = exit_qualification >> 16;
2830
2831         skip_emulated_instruction(vcpu);
2832         return kvm_emulate_pio(vcpu, in, size, port);
2833 }
2834
2835 static void
2836 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2837 {
2838         /*
2839          * Patch in the VMCALL instruction:
2840          */
2841         hypercall[0] = 0x0f;
2842         hypercall[1] = 0x01;
2843         hypercall[2] = 0xc1;
2844 }
2845
2846 static int handle_cr(struct kvm_vcpu *vcpu)
2847 {
2848         unsigned long exit_qualification, val;
2849         int cr;
2850         int reg;
2851
2852         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2853         cr = exit_qualification & 15;
2854         reg = (exit_qualification >> 8) & 15;
2855         switch ((exit_qualification >> 4) & 3) {
2856         case 0: /* mov to cr */
2857                 val = kvm_register_read(vcpu, reg);
2858                 trace_kvm_cr_write(cr, val);
2859                 switch (cr) {
2860                 case 0:
2861                         kvm_set_cr0(vcpu, val);
2862                         skip_emulated_instruction(vcpu);
2863                         return 1;
2864                 case 3:
2865                         kvm_set_cr3(vcpu, val);
2866                         skip_emulated_instruction(vcpu);
2867                         return 1;
2868                 case 4:
2869                         kvm_set_cr4(vcpu, val);
2870                         skip_emulated_instruction(vcpu);
2871                         return 1;
2872                 case 8: {
2873                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2874                                 u8 cr8 = kvm_register_read(vcpu, reg);
2875                                 kvm_set_cr8(vcpu, cr8);
2876                                 skip_emulated_instruction(vcpu);
2877                                 if (irqchip_in_kernel(vcpu->kvm))
2878                                         return 1;
2879                                 if (cr8_prev <= cr8)
2880                                         return 1;
2881                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2882                                 return 0;
2883                         }
2884                 };
2885                 break;
2886         case 2: /* clts */
2887                 vmx_fpu_deactivate(vcpu);
2888                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2889                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2890                 vmx_fpu_activate(vcpu);
2891                 skip_emulated_instruction(vcpu);
2892                 return 1;
2893         case 1: /*mov from cr*/
2894                 switch (cr) {
2895                 case 3:
2896                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2897                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2898                         skip_emulated_instruction(vcpu);
2899                         return 1;
2900                 case 8:
2901                         val = kvm_get_cr8(vcpu);
2902                         kvm_register_write(vcpu, reg, val);
2903                         trace_kvm_cr_read(cr, val);
2904                         skip_emulated_instruction(vcpu);
2905                         return 1;
2906                 }
2907                 break;
2908         case 3: /* lmsw */
2909                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2910
2911                 skip_emulated_instruction(vcpu);
2912                 return 1;
2913         default:
2914                 break;
2915         }
2916         vcpu->run->exit_reason = 0;
2917         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2918                (int)(exit_qualification >> 4) & 3, cr);
2919         return 0;
2920 }
2921
2922 static int handle_dr(struct kvm_vcpu *vcpu)
2923 {
2924         unsigned long exit_qualification;
2925         unsigned long val;
2926         int dr, reg;
2927
2928         if (!kvm_require_cpl(vcpu, 0))
2929                 return 1;
2930         dr = vmcs_readl(GUEST_DR7);
2931         if (dr & DR7_GD) {
2932                 /*
2933                  * As the vm-exit takes precedence over the debug trap, we
2934                  * need to emulate the latter, either for the host or the
2935                  * guest debugging itself.
2936                  */
2937                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2938                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2939                         vcpu->run->debug.arch.dr7 = dr;
2940                         vcpu->run->debug.arch.pc =
2941                                 vmcs_readl(GUEST_CS_BASE) +
2942                                 vmcs_readl(GUEST_RIP);
2943                         vcpu->run->debug.arch.exception = DB_VECTOR;
2944                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
2945                         return 0;
2946                 } else {
2947                         vcpu->arch.dr7 &= ~DR7_GD;
2948                         vcpu->arch.dr6 |= DR6_BD;
2949                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2950                         kvm_queue_exception(vcpu, DB_VECTOR);
2951                         return 1;
2952                 }
2953         }
2954
2955         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2956         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2957         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2958         if (exit_qualification & TYPE_MOV_FROM_DR) {
2959                 switch (dr) {
2960                 case 0 ... 3:
2961                         val = vcpu->arch.db[dr];
2962                         break;
2963                 case 6:
2964                         val = vcpu->arch.dr6;
2965                         break;
2966                 case 7:
2967                         val = vcpu->arch.dr7;
2968                         break;
2969                 default:
2970                         val = 0;
2971                 }
2972                 kvm_register_write(vcpu, reg, val);
2973         } else {
2974                 val = vcpu->arch.regs[reg];
2975                 switch (dr) {
2976                 case 0 ... 3:
2977                         vcpu->arch.db[dr] = val;
2978                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2979                                 vcpu->arch.eff_db[dr] = val;
2980                         break;
2981                 case 4 ... 5:
2982                         if (vcpu->arch.cr4 & X86_CR4_DE)
2983                                 kvm_queue_exception(vcpu, UD_VECTOR);
2984                         break;
2985                 case 6:
2986                         if (val & 0xffffffff00000000ULL) {
2987                                 kvm_queue_exception(vcpu, GP_VECTOR);
2988                                 break;
2989                         }
2990                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2991                         break;
2992                 case 7:
2993                         if (val & 0xffffffff00000000ULL) {
2994                                 kvm_queue_exception(vcpu, GP_VECTOR);
2995                                 break;
2996                         }
2997                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2998                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2999                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3000                                 vcpu->arch.switch_db_regs =
3001                                         (val & DR7_BP_EN_MASK);
3002                         }
3003                         break;
3004                 }
3005         }
3006         skip_emulated_instruction(vcpu);
3007         return 1;
3008 }
3009
3010 static int handle_cpuid(struct kvm_vcpu *vcpu)
3011 {
3012         kvm_emulate_cpuid(vcpu);
3013         return 1;
3014 }
3015
3016 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3017 {
3018         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3019         u64 data;
3020
3021         if (vmx_get_msr(vcpu, ecx, &data)) {
3022                 kvm_inject_gp(vcpu, 0);
3023                 return 1;
3024         }
3025
3026         trace_kvm_msr_read(ecx, data);
3027
3028         /* FIXME: handling of bits 32:63 of rax, rdx */
3029         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3030         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3031         skip_emulated_instruction(vcpu);
3032         return 1;
3033 }
3034
3035 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3036 {
3037         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3038         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3039                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3040
3041         trace_kvm_msr_write(ecx, data);
3042
3043         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3044                 kvm_inject_gp(vcpu, 0);
3045                 return 1;
3046         }
3047
3048         skip_emulated_instruction(vcpu);
3049         return 1;
3050 }
3051
3052 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3053 {
3054         return 1;
3055 }
3056
3057 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3058 {
3059         u32 cpu_based_vm_exec_control;
3060
3061         /* clear pending irq */
3062         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3063         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3064         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3065
3066         ++vcpu->stat.irq_window_exits;
3067
3068         /*
3069          * If the user space waits to inject interrupts, exit as soon as
3070          * possible
3071          */
3072         if (!irqchip_in_kernel(vcpu->kvm) &&
3073             vcpu->run->request_interrupt_window &&
3074             !kvm_cpu_has_interrupt(vcpu)) {
3075                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3076                 return 0;
3077         }
3078         return 1;
3079 }
3080
3081 static int handle_halt(struct kvm_vcpu *vcpu)
3082 {
3083         skip_emulated_instruction(vcpu);
3084         return kvm_emulate_halt(vcpu);
3085 }
3086
3087 static int handle_vmcall(struct kvm_vcpu *vcpu)
3088 {
3089         skip_emulated_instruction(vcpu);
3090         kvm_emulate_hypercall(vcpu);
3091         return 1;
3092 }
3093
3094 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3095 {
3096         kvm_queue_exception(vcpu, UD_VECTOR);
3097         return 1;
3098 }
3099
3100 static int handle_invlpg(struct kvm_vcpu *vcpu)
3101 {
3102         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3103
3104         kvm_mmu_invlpg(vcpu, exit_qualification);
3105         skip_emulated_instruction(vcpu);
3106         return 1;
3107 }
3108
3109 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3110 {
3111         skip_emulated_instruction(vcpu);
3112         /* TODO: Add support for VT-d/pass-through device */
3113         return 1;
3114 }
3115
3116 static int handle_apic_access(struct kvm_vcpu *vcpu)
3117 {
3118         unsigned long exit_qualification;
3119         enum emulation_result er;
3120         unsigned long offset;
3121
3122         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3123         offset = exit_qualification & 0xffful;
3124
3125         er = emulate_instruction(vcpu, 0, 0, 0);
3126
3127         if (er !=  EMULATE_DONE) {
3128                 printk(KERN_ERR
3129                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3130                        offset);
3131                 return -ENOEXEC;
3132         }
3133         return 1;
3134 }
3135
3136 static int handle_task_switch(struct kvm_vcpu *vcpu)
3137 {
3138         struct vcpu_vmx *vmx = to_vmx(vcpu);
3139         unsigned long exit_qualification;
3140         u16 tss_selector;
3141         int reason, type, idt_v;
3142
3143         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3144         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3145
3146         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3147
3148         reason = (u32)exit_qualification >> 30;
3149         if (reason == TASK_SWITCH_GATE && idt_v) {
3150                 switch (type) {
3151                 case INTR_TYPE_NMI_INTR:
3152                         vcpu->arch.nmi_injected = false;
3153                         if (cpu_has_virtual_nmis())
3154                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3155                                               GUEST_INTR_STATE_NMI);
3156                         break;
3157                 case INTR_TYPE_EXT_INTR:
3158                 case INTR_TYPE_SOFT_INTR:
3159                         kvm_clear_interrupt_queue(vcpu);
3160                         break;
3161                 case INTR_TYPE_HARD_EXCEPTION:
3162                 case INTR_TYPE_SOFT_EXCEPTION:
3163                         kvm_clear_exception_queue(vcpu);
3164                         break;
3165                 default:
3166                         break;
3167                 }
3168         }
3169         tss_selector = exit_qualification;
3170
3171         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3172                        type != INTR_TYPE_EXT_INTR &&
3173                        type != INTR_TYPE_NMI_INTR))
3174                 skip_emulated_instruction(vcpu);
3175
3176         if (!kvm_task_switch(vcpu, tss_selector, reason))
3177                 return 0;
3178
3179         /* clear all local breakpoint enable flags */
3180         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3181
3182         /*
3183          * TODO: What about debug traps on tss switch?
3184          *       Are we supposed to inject them and update dr6?
3185          */
3186
3187         return 1;
3188 }
3189
3190 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3191 {
3192         unsigned long exit_qualification;
3193         gpa_t gpa;
3194         int gla_validity;
3195
3196         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3197
3198         if (exit_qualification & (1 << 6)) {
3199                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3200                 return -EINVAL;
3201         }
3202
3203         gla_validity = (exit_qualification >> 7) & 0x3;
3204         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3205                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3206                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3207                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3208                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3209                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3210                         (long unsigned int)exit_qualification);
3211                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3212                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3213                 return 0;
3214         }
3215
3216         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3217         trace_kvm_page_fault(gpa, exit_qualification);
3218         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3219 }
3220
3221 static u64 ept_rsvd_mask(u64 spte, int level)
3222 {
3223         int i;
3224         u64 mask = 0;
3225
3226         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3227                 mask |= (1ULL << i);
3228
3229         if (level > 2)
3230                 /* bits 7:3 reserved */
3231                 mask |= 0xf8;
3232         else if (level == 2) {
3233                 if (spte & (1ULL << 7))
3234                         /* 2MB ref, bits 20:12 reserved */
3235                         mask |= 0x1ff000;
3236                 else
3237                         /* bits 6:3 reserved */
3238                         mask |= 0x78;
3239         }
3240
3241         return mask;
3242 }
3243
3244 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3245                                        int level)
3246 {
3247         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3248
3249         /* 010b (write-only) */
3250         WARN_ON((spte & 0x7) == 0x2);
3251
3252         /* 110b (write/execute) */
3253         WARN_ON((spte & 0x7) == 0x6);
3254
3255         /* 100b (execute-only) and value not supported by logical processor */
3256         if (!cpu_has_vmx_ept_execute_only())
3257                 WARN_ON((spte & 0x7) == 0x4);
3258
3259         /* not 000b */
3260         if ((spte & 0x7)) {
3261                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3262
3263                 if (rsvd_bits != 0) {
3264                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3265                                          __func__, rsvd_bits);
3266                         WARN_ON(1);
3267                 }
3268
3269                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3270                         u64 ept_mem_type = (spte & 0x38) >> 3;
3271
3272                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3273                             ept_mem_type == 7) {
3274                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3275                                                 __func__, ept_mem_type);
3276                                 WARN_ON(1);
3277                         }
3278                 }
3279         }
3280 }
3281
3282 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3283 {
3284         u64 sptes[4];
3285         int nr_sptes, i;
3286         gpa_t gpa;
3287
3288         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3289
3290         printk(KERN_ERR "EPT: Misconfiguration.\n");
3291         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3292
3293         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3294
3295         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3296                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3297
3298         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3299         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3300
3301         return 0;
3302 }
3303
3304 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3305 {
3306         u32 cpu_based_vm_exec_control;
3307
3308         /* clear pending NMI */
3309         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3310         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3311         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3312         ++vcpu->stat.nmi_window_exits;
3313
3314         return 1;
3315 }
3316
3317 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3318 {
3319         struct vcpu_vmx *vmx = to_vmx(vcpu);
3320         enum emulation_result err = EMULATE_DONE;
3321         int ret = 1;
3322
3323         while (!guest_state_valid(vcpu)) {
3324                 err = emulate_instruction(vcpu, 0, 0, 0);
3325
3326                 if (err == EMULATE_DO_MMIO) {
3327                         ret = 0;
3328                         goto out;
3329                 }
3330
3331                 if (err != EMULATE_DONE) {
3332                         kvm_report_emulation_failure(vcpu, "emulation failure");
3333                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3334                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3335                         ret = 0;
3336                         goto out;
3337                 }
3338
3339                 if (signal_pending(current))
3340                         goto out;
3341                 if (need_resched())
3342                         schedule();
3343         }
3344
3345         vmx->emulation_required = 0;
3346 out:
3347         return ret;
3348 }
3349
3350 /*
3351  * The exit handlers return 1 if the exit was handled fully and guest execution
3352  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3353  * to be done to userspace and return 0.
3354  */
3355 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3356         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3357         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3358         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3359         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3360         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3361         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3362         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3363         [EXIT_REASON_CPUID]                   = handle_cpuid,
3364         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3365         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3366         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3367         [EXIT_REASON_HLT]                     = handle_halt,
3368         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3369         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3370         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3371         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3372         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3373         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3374         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3375         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3376         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3377         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3378         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3379         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3380         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3381         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3382         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3383         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3384         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3385         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3386 };
3387
3388 static const int kvm_vmx_max_exit_handlers =
3389         ARRAY_SIZE(kvm_vmx_exit_handlers);
3390
3391 /*
3392  * The guest has exited.  See if we can fix it or if we need userspace
3393  * assistance.
3394  */
3395 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3396 {
3397         struct vcpu_vmx *vmx = to_vmx(vcpu);
3398         u32 exit_reason = vmx->exit_reason;
3399         u32 vectoring_info = vmx->idt_vectoring_info;
3400
3401         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3402
3403         /* If guest state is invalid, start emulating */
3404         if (vmx->emulation_required && emulate_invalid_guest_state)
3405                 return handle_invalid_guest_state(vcpu);
3406
3407         /* Access CR3 don't cause VMExit in paging mode, so we need
3408          * to sync with guest real CR3. */
3409         if (enable_ept && is_paging(vcpu))
3410                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3411
3412         if (unlikely(vmx->fail)) {
3413                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3414                 vcpu->run->fail_entry.hardware_entry_failure_reason
3415                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3416                 return 0;
3417         }
3418
3419         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3420                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3421                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3422                         exit_reason != EXIT_REASON_TASK_SWITCH))
3423                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3424                        "(0x%x) and exit reason is 0x%x\n",
3425                        __func__, vectoring_info, exit_reason);
3426
3427         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3428                 if (vmx_interrupt_allowed(vcpu)) {
3429                         vmx->soft_vnmi_blocked = 0;
3430                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3431                            vcpu->arch.nmi_pending) {
3432                         /*
3433                          * This CPU don't support us in finding the end of an
3434                          * NMI-blocked window if the guest runs with IRQs
3435                          * disabled. So we pull the trigger after 1 s of
3436                          * futile waiting, but inform the user about this.
3437                          */
3438                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3439                                "state on VCPU %d after 1 s timeout\n",
3440                                __func__, vcpu->vcpu_id);
3441                         vmx->soft_vnmi_blocked = 0;
3442                 }
3443         }
3444
3445         if (exit_reason < kvm_vmx_max_exit_handlers
3446             && kvm_vmx_exit_handlers[exit_reason])
3447                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3448         else {
3449                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3450                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3451         }
3452         return 0;
3453 }
3454
3455 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3456 {
3457         if (irr == -1 || tpr < irr) {
3458                 vmcs_write32(TPR_THRESHOLD, 0);
3459                 return;
3460         }
3461
3462         vmcs_write32(TPR_THRESHOLD, irr);
3463 }
3464
3465 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3466 {
3467         u32 exit_intr_info;
3468         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3469         bool unblock_nmi;
3470         u8 vector;
3471         int type;
3472         bool idtv_info_valid;
3473
3474         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3475
3476         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3477
3478         /* Handle machine checks before interrupts are enabled */
3479         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3480             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3481                 && is_machine_check(exit_intr_info)))
3482                 kvm_machine_check();
3483
3484         /* We need to handle NMIs before interrupts are enabled */
3485         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3486             (exit_intr_info & INTR_INFO_VALID_MASK))
3487                 asm("int $2");
3488
3489         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3490
3491         if (cpu_has_virtual_nmis()) {
3492                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3493                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3494                 /*
3495                  * SDM 3: 27.7.1.2 (September 2008)
3496                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3497                  * a guest IRET fault.
3498                  * SDM 3: 23.2.2 (September 2008)
3499                  * Bit 12 is undefined in any of the following cases:
3500                  *  If the VM exit sets the valid bit in the IDT-vectoring
3501                  *   information field.
3502                  *  If the VM exit is due to a double fault.
3503                  */
3504                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3505                     vector != DF_VECTOR && !idtv_info_valid)
3506                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3507                                       GUEST_INTR_STATE_NMI);
3508         } else if (unlikely(vmx->soft_vnmi_blocked))
3509                 vmx->vnmi_blocked_time +=
3510                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3511
3512         vmx->vcpu.arch.nmi_injected = false;
3513         kvm_clear_exception_queue(&vmx->vcpu);
3514         kvm_clear_interrupt_queue(&vmx->vcpu);
3515
3516         if (!idtv_info_valid)
3517                 return;
3518
3519         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3520         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3521
3522         switch (type) {
3523         case INTR_TYPE_NMI_INTR:
3524                 vmx->vcpu.arch.nmi_injected = true;
3525                 /*
3526                  * SDM 3: 27.7.1.2 (September 2008)
3527                  * Clear bit "block by NMI" before VM entry if a NMI
3528                  * delivery faulted.
3529                  */
3530                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3531                                 GUEST_INTR_STATE_NMI);
3532                 break;
3533         case INTR_TYPE_SOFT_EXCEPTION:
3534                 vmx->vcpu.arch.event_exit_inst_len =
3535                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3536                 /* fall through */
3537         case INTR_TYPE_HARD_EXCEPTION:
3538                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3539                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3540                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3541                 } else
3542                         kvm_queue_exception(&vmx->vcpu, vector);
3543                 break;
3544         case INTR_TYPE_SOFT_INTR:
3545                 vmx->vcpu.arch.event_exit_inst_len =
3546                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3547                 /* fall through */
3548         case INTR_TYPE_EXT_INTR:
3549                 kvm_queue_interrupt(&vmx->vcpu, vector,
3550                         type == INTR_TYPE_SOFT_INTR);
3551                 break;
3552         default:
3553                 break;
3554         }
3555 }
3556
3557 /*
3558  * Failure to inject an interrupt should give us the information
3559  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3560  * when fetching the interrupt redirection bitmap in the real-mode
3561  * tss, this doesn't happen.  So we do it ourselves.
3562  */
3563 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3564 {
3565         vmx->rmode.irq.pending = 0;
3566         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3567                 return;
3568         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3569         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3570                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3571                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3572                 return;
3573         }
3574         vmx->idt_vectoring_info =
3575                 VECTORING_INFO_VALID_MASK
3576                 | INTR_TYPE_EXT_INTR
3577                 | vmx->rmode.irq.vector;
3578 }
3579
3580 #ifdef CONFIG_X86_64
3581 #define R "r"
3582 #define Q "q"
3583 #else
3584 #define R "e"
3585 #define Q "l"
3586 #endif
3587
3588 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3589 {
3590         struct vcpu_vmx *vmx = to_vmx(vcpu);
3591
3592         if (enable_ept && is_paging(vcpu)) {
3593                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3594                 ept_load_pdptrs(vcpu);
3595         }
3596         /* Record the guest's net vcpu time for enforced NMI injections. */
3597         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3598                 vmx->entry_time = ktime_get();
3599
3600         /* Don't enter VMX if guest state is invalid, let the exit handler
3601            start emulation until we arrive back to a valid state */
3602         if (vmx->emulation_required && emulate_invalid_guest_state)
3603                 return;
3604
3605         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3606                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3607         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3608                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3609
3610         /* When single-stepping over STI and MOV SS, we must clear the
3611          * corresponding interruptibility bits in the guest state. Otherwise
3612          * vmentry fails as it then expects bit 14 (BS) in pending debug
3613          * exceptions being set, but that's not correct for the guest debugging
3614          * case. */
3615         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3616                 vmx_set_interrupt_shadow(vcpu, 0);
3617
3618         /*
3619          * Loading guest fpu may have cleared host cr0.ts
3620          */
3621         vmcs_writel(HOST_CR0, read_cr0());
3622
3623         if (vcpu->arch.switch_db_regs)
3624                 set_debugreg(vcpu->arch.dr6, 6);
3625
3626         asm(
3627                 /* Store host registers */
3628                 "push %%"R"dx; push %%"R"bp;"
3629                 "push %%"R"cx \n\t"
3630                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3631                 "je 1f \n\t"
3632                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3633                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3634                 "1: \n\t"
3635                 /* Reload cr2 if changed */
3636                 "mov %c[cr2](%0), %%"R"ax \n\t"
3637                 "mov %%cr2, %%"R"dx \n\t"
3638                 "cmp %%"R"ax, %%"R"dx \n\t"
3639                 "je 2f \n\t"
3640                 "mov %%"R"ax, %%cr2 \n\t"
3641                 "2: \n\t"
3642                 /* Check if vmlaunch of vmresume is needed */
3643                 "cmpl $0, %c[launched](%0) \n\t"
3644                 /* Load guest registers.  Don't clobber flags. */
3645                 "mov %c[rax](%0), %%"R"ax \n\t"
3646                 "mov %c[rbx](%0), %%"R"bx \n\t"
3647                 "mov %c[rdx](%0), %%"R"dx \n\t"
3648                 "mov %c[rsi](%0), %%"R"si \n\t"
3649                 "mov %c[rdi](%0), %%"R"di \n\t"
3650                 "mov %c[rbp](%0), %%"R"bp \n\t"
3651 #ifdef CONFIG_X86_64
3652                 "mov %c[r8](%0),  %%r8  \n\t"
3653                 "mov %c[r9](%0),  %%r9  \n\t"
3654                 "mov %c[r10](%0), %%r10 \n\t"
3655                 "mov %c[r11](%0), %%r11 \n\t"
3656                 "mov %c[r12](%0), %%r12 \n\t"
3657                 "mov %c[r13](%0), %%r13 \n\t"
3658                 "mov %c[r14](%0), %%r14 \n\t"
3659                 "mov %c[r15](%0), %%r15 \n\t"
3660 #endif
3661                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3662
3663                 /* Enter guest mode */
3664                 "jne .Llaunched \n\t"
3665                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3666                 "jmp .Lkvm_vmx_return \n\t"
3667                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3668                 ".Lkvm_vmx_return: "
3669                 /* Save guest registers, load host registers, keep flags */
3670                 "xchg %0,     (%%"R"sp) \n\t"
3671                 "mov %%"R"ax, %c[rax](%0) \n\t"
3672                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3673                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3674                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3675                 "mov %%"R"si, %c[rsi](%0) \n\t"
3676                 "mov %%"R"di, %c[rdi](%0) \n\t"
3677                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3678 #ifdef CONFIG_X86_64
3679                 "mov %%r8,  %c[r8](%0) \n\t"
3680                 "mov %%r9,  %c[r9](%0) \n\t"
3681                 "mov %%r10, %c[r10](%0) \n\t"
3682                 "mov %%r11, %c[r11](%0) \n\t"
3683                 "mov %%r12, %c[r12](%0) \n\t"
3684                 "mov %%r13, %c[r13](%0) \n\t"
3685                 "mov %%r14, %c[r14](%0) \n\t"
3686                 "mov %%r15, %c[r15](%0) \n\t"
3687 #endif
3688                 "mov %%cr2, %%"R"ax   \n\t"
3689                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3690
3691                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3692                 "setbe %c[fail](%0) \n\t"
3693               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3694                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3695                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3696                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3697                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3698                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3699                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3700                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3701                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3702                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3703                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3704 #ifdef CONFIG_X86_64
3705                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3706                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3707                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3708                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3709                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3710                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3711                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3712                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3713 #endif
3714                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3715               : "cc", "memory"
3716                 , R"bx", R"di", R"si"
3717 #ifdef CONFIG_X86_64
3718                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3719 #endif
3720               );
3721
3722         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3723                                   | (1 << VCPU_EXREG_PDPTR));
3724         vcpu->arch.regs_dirty = 0;
3725
3726         if (vcpu->arch.switch_db_regs)
3727                 get_debugreg(vcpu->arch.dr6, 6);
3728
3729         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3730         if (vmx->rmode.irq.pending)
3731                 fixup_rmode_irq(vmx);
3732
3733         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3734         vmx->launched = 1;
3735
3736         vmx_complete_interrupts(vmx);
3737 }
3738
3739 #undef R
3740 #undef Q
3741
3742 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3743 {
3744         struct vcpu_vmx *vmx = to_vmx(vcpu);
3745
3746         if (vmx->vmcs) {
3747                 vcpu_clear(vmx);
3748                 free_vmcs(vmx->vmcs);
3749                 vmx->vmcs = NULL;
3750         }
3751 }
3752
3753 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3754 {
3755         struct vcpu_vmx *vmx = to_vmx(vcpu);
3756
3757         spin_lock(&vmx_vpid_lock);
3758         if (vmx->vpid != 0)
3759                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3760         spin_unlock(&vmx_vpid_lock);
3761         vmx_free_vmcs(vcpu);
3762         kfree(vmx->host_msrs);
3763         kfree(vmx->guest_msrs);
3764         kvm_vcpu_uninit(vcpu);
3765         kmem_cache_free(kvm_vcpu_cache, vmx);
3766 }
3767
3768 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3769 {
3770         int err;
3771         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3772         int cpu;
3773
3774         if (!vmx)
3775                 return ERR_PTR(-ENOMEM);
3776
3777         allocate_vpid(vmx);
3778
3779         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3780         if (err)
3781                 goto free_vcpu;
3782
3783         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3784         if (!vmx->guest_msrs) {
3785                 err = -ENOMEM;
3786                 goto uninit_vcpu;
3787         }
3788
3789         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3790         if (!vmx->host_msrs)
3791                 goto free_guest_msrs;
3792
3793         vmx->vmcs = alloc_vmcs();
3794         if (!vmx->vmcs)
3795                 goto free_msrs;
3796
3797         vmcs_clear(vmx->vmcs);
3798
3799         cpu = get_cpu();
3800         vmx_vcpu_load(&vmx->vcpu, cpu);
3801         err = vmx_vcpu_setup(vmx);
3802         vmx_vcpu_put(&vmx->vcpu);
3803         put_cpu();
3804         if (err)
3805                 goto free_vmcs;
3806         if (vm_need_virtualize_apic_accesses(kvm))
3807                 if (alloc_apic_access_page(kvm) != 0)
3808                         goto free_vmcs;
3809
3810         if (enable_ept) {
3811                 if (!kvm->arch.ept_identity_map_addr)
3812                         kvm->arch.ept_identity_map_addr =
3813                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3814                 if (alloc_identity_pagetable(kvm) != 0)
3815                         goto free_vmcs;
3816         }
3817
3818         return &vmx->vcpu;
3819
3820 free_vmcs:
3821         free_vmcs(vmx->vmcs);
3822 free_msrs:
3823         kfree(vmx->host_msrs);
3824 free_guest_msrs:
3825         kfree(vmx->guest_msrs);
3826 uninit_vcpu:
3827         kvm_vcpu_uninit(&vmx->vcpu);
3828 free_vcpu:
3829         kmem_cache_free(kvm_vcpu_cache, vmx);
3830         return ERR_PTR(err);
3831 }
3832
3833 static void __init vmx_check_processor_compat(void *rtn)
3834 {
3835         struct vmcs_config vmcs_conf;
3836
3837         *(int *)rtn = 0;
3838         if (setup_vmcs_config(&vmcs_conf) < 0)
3839                 *(int *)rtn = -EIO;
3840         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3841                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3842                                 smp_processor_id());
3843                 *(int *)rtn = -EIO;
3844         }
3845 }
3846
3847 static int get_ept_level(void)
3848 {
3849         return VMX_EPT_DEFAULT_GAW + 1;
3850 }
3851
3852 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3853 {
3854         u64 ret;
3855
3856         /* For VT-d and EPT combination
3857          * 1. MMIO: always map as UC
3858          * 2. EPT with VT-d:
3859          *   a. VT-d without snooping control feature: can't guarantee the
3860          *      result, try to trust guest.
3861          *   b. VT-d with snooping control feature: snooping control feature of
3862          *      VT-d engine can guarantee the cache correctness. Just set it
3863          *      to WB to keep consistent with host. So the same as item 3.
3864          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3865          *    consistent with host MTRR
3866          */
3867         if (is_mmio)
3868                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3869         else if (vcpu->kvm->arch.iommu_domain &&
3870                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3871                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3872                       VMX_EPT_MT_EPTE_SHIFT;
3873         else
3874                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3875                         | VMX_EPT_IGMT_BIT;
3876
3877         return ret;
3878 }
3879
3880 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3881         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3882         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3883         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3884         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3885         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3886         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3887         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3888         { EXIT_REASON_CPUID,                   "cpuid" },
3889         { EXIT_REASON_MSR_READ,                "rdmsr" },
3890         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3891         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3892         { EXIT_REASON_HLT,                     "halt" },
3893         { EXIT_REASON_INVLPG,                  "invlpg" },
3894         { EXIT_REASON_VMCALL,                  "hypercall" },
3895         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3896         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3897         { EXIT_REASON_WBINVD,                  "wbinvd" },
3898         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3899         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3900         { -1, NULL }
3901 };
3902
3903 static bool vmx_gb_page_enable(void)
3904 {
3905         return false;
3906 }
3907
3908 static struct kvm_x86_ops vmx_x86_ops = {
3909         .cpu_has_kvm_support = cpu_has_kvm_support,
3910         .disabled_by_bios = vmx_disabled_by_bios,
3911         .hardware_setup = hardware_setup,
3912         .hardware_unsetup = hardware_unsetup,
3913         .check_processor_compatibility = vmx_check_processor_compat,
3914         .hardware_enable = hardware_enable,
3915         .hardware_disable = hardware_disable,
3916         .cpu_has_accelerated_tpr = report_flexpriority,
3917
3918         .vcpu_create = vmx_create_vcpu,
3919         .vcpu_free = vmx_free_vcpu,
3920         .vcpu_reset = vmx_vcpu_reset,
3921
3922         .prepare_guest_switch = vmx_save_host_state,
3923         .vcpu_load = vmx_vcpu_load,
3924         .vcpu_put = vmx_vcpu_put,
3925
3926         .set_guest_debug = set_guest_debug,
3927         .get_msr = vmx_get_msr,
3928         .set_msr = vmx_set_msr,
3929         .get_segment_base = vmx_get_segment_base,
3930         .get_segment = vmx_get_segment,
3931         .set_segment = vmx_set_segment,
3932         .get_cpl = vmx_get_cpl,
3933         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3934         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3935         .set_cr0 = vmx_set_cr0,
3936         .set_cr3 = vmx_set_cr3,
3937         .set_cr4 = vmx_set_cr4,
3938         .set_efer = vmx_set_efer,
3939         .get_idt = vmx_get_idt,
3940         .set_idt = vmx_set_idt,
3941         .get_gdt = vmx_get_gdt,
3942         .set_gdt = vmx_set_gdt,
3943         .cache_reg = vmx_cache_reg,
3944         .get_rflags = vmx_get_rflags,
3945         .set_rflags = vmx_set_rflags,
3946
3947         .tlb_flush = vmx_flush_tlb,
3948
3949         .run = vmx_vcpu_run,
3950         .handle_exit = vmx_handle_exit,
3951         .skip_emulated_instruction = skip_emulated_instruction,
3952         .set_interrupt_shadow = vmx_set_interrupt_shadow,
3953         .get_interrupt_shadow = vmx_get_interrupt_shadow,
3954         .patch_hypercall = vmx_patch_hypercall,
3955         .set_irq = vmx_inject_irq,
3956         .set_nmi = vmx_inject_nmi,
3957         .queue_exception = vmx_queue_exception,
3958         .interrupt_allowed = vmx_interrupt_allowed,
3959         .nmi_allowed = vmx_nmi_allowed,
3960         .enable_nmi_window = enable_nmi_window,
3961         .enable_irq_window = enable_irq_window,
3962         .update_cr8_intercept = update_cr8_intercept,
3963
3964         .set_tss_addr = vmx_set_tss_addr,
3965         .get_tdp_level = get_ept_level,
3966         .get_mt_mask = vmx_get_mt_mask,
3967
3968         .exit_reasons_str = vmx_exit_reasons_str,
3969         .gb_page_enable = vmx_gb_page_enable,
3970 };
3971
3972 static int __init vmx_init(void)
3973 {
3974         int r;
3975
3976         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3977         if (!vmx_io_bitmap_a)
3978                 return -ENOMEM;
3979
3980         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3981         if (!vmx_io_bitmap_b) {
3982                 r = -ENOMEM;
3983                 goto out;
3984         }
3985
3986         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3987         if (!vmx_msr_bitmap_legacy) {
3988                 r = -ENOMEM;
3989                 goto out1;
3990         }
3991
3992         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3993         if (!vmx_msr_bitmap_longmode) {
3994                 r = -ENOMEM;
3995                 goto out2;
3996         }
3997
3998         /*
3999          * Allow direct access to the PC debug port (it is often used for I/O
4000          * delays, but the vmexits simply slow things down).
4001          */
4002         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4003         clear_bit(0x80, vmx_io_bitmap_a);
4004
4005         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4006
4007         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4008         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4009
4010         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4011
4012         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4013         if (r)
4014                 goto out3;
4015
4016         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4017         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4018         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4019         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4020         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4021         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4022
4023         if (enable_ept) {
4024                 bypass_guest_pf = 0;
4025                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4026                         VMX_EPT_WRITABLE_MASK);
4027                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4028                                 VMX_EPT_EXECUTABLE_MASK);
4029                 kvm_enable_tdp();
4030         } else
4031                 kvm_disable_tdp();
4032
4033         if (bypass_guest_pf)
4034                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4035
4036         return 0;
4037
4038 out3:
4039         free_page((unsigned long)vmx_msr_bitmap_longmode);
4040 out2:
4041         free_page((unsigned long)vmx_msr_bitmap_legacy);
4042 out1:
4043         free_page((unsigned long)vmx_io_bitmap_b);
4044 out:
4045         free_page((unsigned long)vmx_io_bitmap_a);
4046         return r;
4047 }
4048
4049 static void __exit vmx_exit(void)
4050 {
4051         free_page((unsigned long)vmx_msr_bitmap_legacy);
4052         free_page((unsigned long)vmx_msr_bitmap_longmode);
4053         free_page((unsigned long)vmx_io_bitmap_b);
4054         free_page((unsigned long)vmx_io_bitmap_a);
4055
4056         kvm_exit();
4057 }
4058
4059 module_init(vmx_init)
4060 module_exit(vmx_exit)