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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "vmx.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/desc.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 static int enable_vpid = 1;
  42 module_param(enable_vpid, bool, 0);
  43
  44 static int flexpriority_enabled = 1;
  45 module_param(flexpriority_enabled, bool, 0);
  46
  47 static int enable_ept = 1;
  48 module_param(enable_ept, bool, 0);
  49
  50 struct vmcs {
  51         u32 revision_id;
  52         u32 abort;
  53         char data[0];
  54 };
  55
  56 struct vcpu_vmx {
  57         struct kvm_vcpu       vcpu;
  58         struct list_head      local_vcpus_link;
  59         int                   launched;
  60         u8                    fail;
  61         u32                   idt_vectoring_info;
  62         struct kvm_msr_entry *guest_msrs;
  63         struct kvm_msr_entry *host_msrs;
  64         int                   nmsrs;
  65         int                   save_nmsrs;
  66         int                   msr_offset_efer;
  67 #ifdef CONFIG_X86_64
  68         int                   msr_offset_kernel_gs_base;
  69 #endif
  70         struct vmcs          *vmcs;
  71         struct {
  72                 int           loaded;
  73                 u16           fs_sel, gs_sel, ldt_sel;
  74                 int           gs_ldt_reload_needed;
  75                 int           fs_reload_needed;
  76                 int           guest_efer_loaded;
  77         } host_state;
  78         struct {
  79                 struct {
  80                         bool pending;
  81                         u8 vector;
  82                         unsigned rip;
  83                 } irq;
  84         } rmode;
  85         int vpid;
  86 };
  87
  88 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  89 {
  90         return container_of(vcpu, struct vcpu_vmx, vcpu);
  91 }
  92
  93 static int init_rmode(struct kvm *kvm);
  94
  95 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  96 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  97 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
  98
  99 static struct page *vmx_io_bitmap_a;
 100 static struct page *vmx_io_bitmap_b;
 101 static struct page *vmx_msr_bitmap;
 102
 103 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 104 static DEFINE_SPINLOCK(vmx_vpid_lock);
 105
 106 static struct vmcs_config {
 107         int size;
 108         int order;
 109         u32 revision_id;
 110         u32 pin_based_exec_ctrl;
 111         u32 cpu_based_exec_ctrl;
 112         u32 cpu_based_2nd_exec_ctrl;
 113         u32 vmexit_ctrl;
 114         u32 vmentry_ctrl;
 115 } vmcs_config;
 116
 117 struct vmx_capability {
 118         u32 ept;
 119         u32 vpid;
 120 } vmx_capability;
 121
 122 #define VMX_SEGMENT_FIELD(seg)                                  \
 123         [VCPU_SREG_##seg] = {                                   \
 124                 .selector = GUEST_##seg##_SELECTOR,             \
 125                 .base = GUEST_##seg##_BASE,                     \
 126                 .limit = GUEST_##seg##_LIMIT,                   \
 127                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 128         }
 129
 130 static struct kvm_vmx_segment_field {
 131         unsigned selector;
 132         unsigned base;
 133         unsigned limit;
 134         unsigned ar_bytes;
 135 } kvm_vmx_segment_fields[] = {
 136         VMX_SEGMENT_FIELD(CS),
 137         VMX_SEGMENT_FIELD(DS),
 138         VMX_SEGMENT_FIELD(ES),
 139         VMX_SEGMENT_FIELD(FS),
 140         VMX_SEGMENT_FIELD(GS),
 141         VMX_SEGMENT_FIELD(SS),
 142         VMX_SEGMENT_FIELD(TR),
 143         VMX_SEGMENT_FIELD(LDTR),
 144 };
 145
 146 /*
 147  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 148  * away by decrementing the array size.
 149  */
 150 static const u32 vmx_msr_index[] = {
 151 #ifdef CONFIG_X86_64
 152         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 153 #endif
 154         MSR_EFER, MSR_K6_STAR,
 155 };
 156 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 157
 158 static void load_msrs(struct kvm_msr_entry *e, int n)
 159 {
 160         int i;
 161
 162         for (i = 0; i < n; ++i)
 163                 wrmsrl(e[i].index, e[i].data);
 164 }
 165
 166 static void save_msrs(struct kvm_msr_entry *e, int n)
 167 {
 168         int i;
 169
 170         for (i = 0; i < n; ++i)
 171                 rdmsrl(e[i].index, e[i].data);
 172 }
 173
 174 static inline int is_page_fault(u32 intr_info)
 175 {
 176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 177                              INTR_INFO_VALID_MASK)) ==
 178                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 179 }
 180
 181 static inline int is_no_device(u32 intr_info)
 182 {
 183         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 184                              INTR_INFO_VALID_MASK)) ==
 185                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 186 }
 187
 188 static inline int is_invalid_opcode(u32 intr_info)
 189 {
 190         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 191                              INTR_INFO_VALID_MASK)) ==
 192                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 193 }
 194
 195 static inline int is_external_interrupt(u32 intr_info)
 196 {
 197         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 198                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 199 }
 200
 201 static inline int cpu_has_vmx_msr_bitmap(void)
 202 {
 203         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 204 }
 205
 206 static inline int cpu_has_vmx_tpr_shadow(void)
 207 {
 208         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 209 }
 210
 211 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 212 {
 213         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 214 }
 215
 216 static inline int cpu_has_secondary_exec_ctrls(void)
 217 {
 218         return (vmcs_config.cpu_based_exec_ctrl &
 219                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 220 }
 221
 222 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 223 {
 224         return flexpriority_enabled
 225                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 226                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 227 }
 228
 229 static inline int cpu_has_vmx_invept_individual_addr(void)
 230 {
 231         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 232 }
 233
 234 static inline int cpu_has_vmx_invept_context(void)
 235 {
 236         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 237 }
 238
 239 static inline int cpu_has_vmx_invept_global(void)
 240 {
 241         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 242 }
 243
 244 static inline int cpu_has_vmx_ept(void)
 245 {
 246         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 247                 SECONDARY_EXEC_ENABLE_EPT);
 248 }
 249
 250 static inline int vm_need_ept(void)
 251 {
 252         return (cpu_has_vmx_ept() && enable_ept);
 253 }
 254
 255 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 256 {
 257         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 258                 (irqchip_in_kernel(kvm)));
 259 }
 260
 261 static inline int cpu_has_vmx_vpid(void)
 262 {
 263         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 264                 SECONDARY_EXEC_ENABLE_VPID);
 265 }
 266
 267 static inline int cpu_has_virtual_nmis(void)
 268 {
 269         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 270 }
 271
 272 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 273 {
 274         int i;
 275
 276         for (i = 0; i < vmx->nmsrs; ++i)
 277                 if (vmx->guest_msrs[i].index == msr)
 278                         return i;
 279         return -1;
 280 }
 281
 282 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 283 {
 284     struct {
 285         u64 vpid : 16;
 286         u64 rsvd : 48;
 287         u64 gva;
 288     } operand = { vpid, 0, gva };
 289
 290     asm volatile (__ex(ASM_VMX_INVVPID)
 291                   /* CF==1 or ZF==1 --> rc = -1 */
 292                   "; ja 1f ; ud2 ; 1:"
 293                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 294 }
 295
 296 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 297 {
 298         struct {
 299                 u64 eptp, gpa;
 300         } operand = {eptp, gpa};
 301
 302         asm volatile (__ex(ASM_VMX_INVEPT)
 303                         /* CF==1 or ZF==1 --> rc = -1 */
 304                         "; ja 1f ; ud2 ; 1:\n"
 305                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 306 }
 307
 308 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 309 {
 310         int i;
 311
 312         i = __find_msr_index(vmx, msr);
 313         if (i >= 0)
 314                 return &vmx->guest_msrs[i];
 315         return NULL;
 316 }
 317
 318 static void vmcs_clear(struct vmcs *vmcs)
 319 {
 320         u64 phys_addr = __pa(vmcs);
 321         u8 error;
 322
 323         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 324                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 325                       : "cc", "memory");
 326         if (error)
 327                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 328                        vmcs, phys_addr);
 329 }
 330
 331 static void __vcpu_clear(void *arg)
 332 {
 333         struct vcpu_vmx *vmx = arg;
 334         int cpu = raw_smp_processor_id();
 335
 336         if (vmx->vcpu.cpu == cpu)
 337                 vmcs_clear(vmx->vmcs);
 338         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 339                 per_cpu(current_vmcs, cpu) = NULL;
 340         rdtscll(vmx->vcpu.arch.host_tsc);
 341         list_del(&vmx->local_vcpus_link);
 342         vmx->vcpu.cpu = -1;
 343         vmx->launched = 0;
 344 }
 345
 346 static void vcpu_clear(struct vcpu_vmx *vmx)
 347 {
 348         if (vmx->vcpu.cpu == -1)
 349                 return;
 350         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 351 }
 352
 353 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 354 {
 355         if (vmx->vpid == 0)
 356                 return;
 357
 358         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 359 }
 360
 361 static inline void ept_sync_global(void)
 362 {
 363         if (cpu_has_vmx_invept_global())
 364                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 365 }
 366
 367 static inline void ept_sync_context(u64 eptp)
 368 {
 369         if (vm_need_ept()) {
 370                 if (cpu_has_vmx_invept_context())
 371                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 372                 else
 373                         ept_sync_global();
 374         }
 375 }
 376
 377 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 378 {
 379         if (vm_need_ept()) {
 380                 if (cpu_has_vmx_invept_individual_addr())
 381                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 382                                         eptp, gpa);
 383                 else
 384                         ept_sync_context(eptp);
 385         }
 386 }
 387
 388 static unsigned long vmcs_readl(unsigned long field)
 389 {
 390         unsigned long value;
 391
 392         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 393                       : "=a"(value) : "d"(field) : "cc");
 394         return value;
 395 }
 396
 397 static u16 vmcs_read16(unsigned long field)
 398 {
 399         return vmcs_readl(field);
 400 }
 401
 402 static u32 vmcs_read32(unsigned long field)
 403 {
 404         return vmcs_readl(field);
 405 }
 406
 407 static u64 vmcs_read64(unsigned long field)
 408 {
 409 #ifdef CONFIG_X86_64
 410         return vmcs_readl(field);
 411 #else
 412         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 413 #endif
 414 }
 415
 416 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 417 {
 418         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 419                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 420         dump_stack();
 421 }
 422
 423 static void vmcs_writel(unsigned long field, unsigned long value)
 424 {
 425         u8 error;
 426
 427         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 428                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 429         if (unlikely(error))
 430                 vmwrite_error(field, value);
 431 }
 432
 433 static void vmcs_write16(unsigned long field, u16 value)
 434 {
 435         vmcs_writel(field, value);
 436 }
 437
 438 static void vmcs_write32(unsigned long field, u32 value)
 439 {
 440         vmcs_writel(field, value);
 441 }
 442
 443 static void vmcs_write64(unsigned long field, u64 value)
 444 {
 445         vmcs_writel(field, value);
 446 #ifndef CONFIG_X86_64
 447         asm volatile ("");
 448         vmcs_writel(field+1, value >> 32);
 449 #endif
 450 }
 451
 452 static void vmcs_clear_bits(unsigned long field, u32 mask)
 453 {
 454         vmcs_writel(field, vmcs_readl(field) & ~mask);
 455 }
 456
 457 static void vmcs_set_bits(unsigned long field, u32 mask)
 458 {
 459         vmcs_writel(field, vmcs_readl(field) | mask);
 460 }
 461
 462 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 463 {
 464         u32 eb;
 465
 466         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 467         if (!vcpu->fpu_active)
 468                 eb |= 1u << NM_VECTOR;
 469         if (vcpu->guest_debug.enabled)
 470                 eb |= 1u << 1;
 471         if (vcpu->arch.rmode.active)
 472                 eb = ~0;
 473         if (vm_need_ept())
 474                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 475         vmcs_write32(EXCEPTION_BITMAP, eb);
 476 }
 477
 478 static void reload_tss(void)
 479 {
 480         /*
 481          * VT restores TR but not its size.  Useless.
 482          */
 483         struct descriptor_table gdt;
 484         struct desc_struct *descs;
 485
 486         get_gdt(&gdt);
 487         descs = (void *)gdt.base;
 488         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 489         load_TR_desc();
 490 }
 491
 492 static void load_transition_efer(struct vcpu_vmx *vmx)
 493 {
 494         int efer_offset = vmx->msr_offset_efer;
 495         u64 host_efer = vmx->host_msrs[efer_offset].data;
 496         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 497         u64 ignore_bits;
 498
 499         if (efer_offset < 0)
 500                 return;
 501         /*
 502          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 503          * outside long mode
 504          */
 505         ignore_bits = EFER_NX | EFER_SCE;
 506 #ifdef CONFIG_X86_64
 507         ignore_bits |= EFER_LMA | EFER_LME;
 508         /* SCE is meaningful only in long mode on Intel */
 509         if (guest_efer & EFER_LMA)
 510                 ignore_bits &= ~(u64)EFER_SCE;
 511 #endif
 512         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 513                 return;
 514
 515         vmx->host_state.guest_efer_loaded = 1;
 516         guest_efer &= ~ignore_bits;
 517         guest_efer |= host_efer & ignore_bits;
 518         wrmsrl(MSR_EFER, guest_efer);
 519         vmx->vcpu.stat.efer_reload++;
 520 }
 521
 522 static void reload_host_efer(struct vcpu_vmx *vmx)
 523 {
 524         if (vmx->host_state.guest_efer_loaded) {
 525                 vmx->host_state.guest_efer_loaded = 0;
 526                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 527         }
 528 }
 529
 530 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 531 {
 532         struct vcpu_vmx *vmx = to_vmx(vcpu);
 533
 534         if (vmx->host_state.loaded)
 535                 return;
 536
 537         vmx->host_state.loaded = 1;
 538         /*
 539          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 540          * allow segment selectors with cpl > 0 or ti == 1.
 541          */
 542         vmx->host_state.ldt_sel = read_ldt();
 543         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 544         vmx->host_state.fs_sel = read_fs();
 545         if (!(vmx->host_state.fs_sel & 7)) {
 546                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 547                 vmx->host_state.fs_reload_needed = 0;
 548         } else {
 549                 vmcs_write16(HOST_FS_SELECTOR, 0);
 550                 vmx->host_state.fs_reload_needed = 1;
 551         }
 552         vmx->host_state.gs_sel = read_gs();
 553         if (!(vmx->host_state.gs_sel & 7))
 554                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 555         else {
 556                 vmcs_write16(HOST_GS_SELECTOR, 0);
 557                 vmx->host_state.gs_ldt_reload_needed = 1;
 558         }
 559
 560 #ifdef CONFIG_X86_64
 561         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 562         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 563 #else
 564         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 565         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 566 #endif
 567
 568 #ifdef CONFIG_X86_64
 569         if (is_long_mode(&vmx->vcpu))
 570                 save_msrs(vmx->host_msrs +
 571                           vmx->msr_offset_kernel_gs_base, 1);
 572
 573 #endif
 574         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 575         load_transition_efer(vmx);
 576 }
 577
 578 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 579 {
 580         unsigned long flags;
 581
 582         if (!vmx->host_state.loaded)
 583                 return;
 584
 585         ++vmx->vcpu.stat.host_state_reload;
 586         vmx->host_state.loaded = 0;
 587         if (vmx->host_state.fs_reload_needed)
 588                 load_fs(vmx->host_state.fs_sel);
 589         if (vmx->host_state.gs_ldt_reload_needed) {
 590                 load_ldt(vmx->host_state.ldt_sel);
 591                 /*
 592                  * If we have to reload gs, we must take care to
 593                  * preserve our gs base.
 594                  */
 595                 local_irq_save(flags);
 596                 load_gs(vmx->host_state.gs_sel);
 597 #ifdef CONFIG_X86_64
 598                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 599 #endif
 600                 local_irq_restore(flags);
 601         }
 602         reload_tss();
 603         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 604         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 605         reload_host_efer(vmx);
 606 }
 607
 608 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 609 {
 610         preempt_disable();
 611         __vmx_load_host_state(vmx);
 612         preempt_enable();
 613 }
 614
 615 /*
 616  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 617  * vcpu mutex is already taken.
 618  */
 619 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 620 {
 621         struct vcpu_vmx *vmx = to_vmx(vcpu);
 622         u64 phys_addr = __pa(vmx->vmcs);
 623         u64 tsc_this, delta, new_offset;
 624
 625         if (vcpu->cpu != cpu) {
 626                 vcpu_clear(vmx);
 627                 kvm_migrate_timers(vcpu);
 628                 vpid_sync_vcpu_all(vmx);
 629                 local_irq_disable();
 630                 list_add(&vmx->local_vcpus_link,
 631                          &per_cpu(vcpus_on_cpu, cpu));
 632                 local_irq_enable();
 633         }
 634
 635         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 636                 u8 error;
 637
 638                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 639                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 640                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 641                               : "cc");
 642                 if (error)
 643                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 644                                vmx->vmcs, phys_addr);
 645         }
 646
 647         if (vcpu->cpu != cpu) {
 648                 struct descriptor_table dt;
 649                 unsigned long sysenter_esp;
 650
 651                 vcpu->cpu = cpu;
 652                 /*
 653                  * Linux uses per-cpu TSS and GDT, so set these when switching
 654                  * processors.
 655                  */
 656                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 657                 get_gdt(&dt);
 658                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 659
 660                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 661                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 662
 663                 /*
 664                  * Make sure the time stamp counter is monotonous.
 665                  */
 666                 rdtscll(tsc_this);
 667                 if (tsc_this < vcpu->arch.host_tsc) {
 668                         delta = vcpu->arch.host_tsc - tsc_this;
 669                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 670                         vmcs_write64(TSC_OFFSET, new_offset);
 671                 }
 672         }
 673 }
 674
 675 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 676 {
 677         __vmx_load_host_state(to_vmx(vcpu));
 678 }
 679
 680 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 681 {
 682         if (vcpu->fpu_active)
 683                 return;
 684         vcpu->fpu_active = 1;
 685         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 686         if (vcpu->arch.cr0 & X86_CR0_TS)
 687                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 688         update_exception_bitmap(vcpu);
 689 }
 690
 691 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 692 {
 693         if (!vcpu->fpu_active)
 694                 return;
 695         vcpu->fpu_active = 0;
 696         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 697         update_exception_bitmap(vcpu);
 698 }
 699
 700 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 701 {
 702         return vmcs_readl(GUEST_RFLAGS);
 703 }
 704
 705 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 706 {
 707         if (vcpu->arch.rmode.active)
 708                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 709         vmcs_writel(GUEST_RFLAGS, rflags);
 710 }
 711
 712 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 713 {
 714         unsigned long rip;
 715         u32 interruptibility;
 716
 717         rip = vmcs_readl(GUEST_RIP);
 718         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 719         vmcs_writel(GUEST_RIP, rip);
 720
 721         /*
 722          * We emulated an instruction, so temporary interrupt blocking
 723          * should be removed, if set.
 724          */
 725         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 726         if (interruptibility & 3)
 727                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 728                              interruptibility & ~3);
 729         vcpu->arch.interrupt_window_open = 1;
 730 }
 731
 732 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 733                                 bool has_error_code, u32 error_code)
 734 {
 735         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 736                      nr | INTR_TYPE_EXCEPTION
 737                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 738                      | INTR_INFO_VALID_MASK);
 739         if (has_error_code)
 740                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 741 }
 742
 743 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 744 {
 745         struct vcpu_vmx *vmx = to_vmx(vcpu);
 746
 747         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
 748 }
 749
 750 /*
 751  * Swap MSR entry in host/guest MSR entry array.
 752  */
 753 #ifdef CONFIG_X86_64
 754 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 755 {
 756         struct kvm_msr_entry tmp;
 757
 758         tmp = vmx->guest_msrs[to];
 759         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 760         vmx->guest_msrs[from] = tmp;
 761         tmp = vmx->host_msrs[to];
 762         vmx->host_msrs[to] = vmx->host_msrs[from];
 763         vmx->host_msrs[from] = tmp;
 764 }
 765 #endif
 766
 767 /*
 768  * Set up the vmcs to automatically save and restore system
 769  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 770  * mode, as fiddling with msrs is very expensive.
 771  */
 772 static void setup_msrs(struct vcpu_vmx *vmx)
 773 {
 774         int save_nmsrs;
 775
 776         vmx_load_host_state(vmx);
 777         save_nmsrs = 0;
 778 #ifdef CONFIG_X86_64
 779         if (is_long_mode(&vmx->vcpu)) {
 780                 int index;
 781
 782                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 783                 if (index >= 0)
 784                         move_msr_up(vmx, index, save_nmsrs++);
 785                 index = __find_msr_index(vmx, MSR_LSTAR);
 786                 if (index >= 0)
 787                         move_msr_up(vmx, index, save_nmsrs++);
 788                 index = __find_msr_index(vmx, MSR_CSTAR);
 789                 if (index >= 0)
 790                         move_msr_up(vmx, index, save_nmsrs++);
 791                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 792                 if (index >= 0)
 793                         move_msr_up(vmx, index, save_nmsrs++);
 794                 /*
 795                  * MSR_K6_STAR is only needed on long mode guests, and only
 796                  * if efer.sce is enabled.
 797                  */
 798                 index = __find_msr_index(vmx, MSR_K6_STAR);
 799                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 800                         move_msr_up(vmx, index, save_nmsrs++);
 801         }
 802 #endif
 803         vmx->save_nmsrs = save_nmsrs;
 804
 805 #ifdef CONFIG_X86_64
 806         vmx->msr_offset_kernel_gs_base =
 807                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 808 #endif
 809         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 810 }
 811
 812 /*
 813  * reads and returns guest's timestamp counter "register"
 814  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 815  */
 816 static u64 guest_read_tsc(void)
 817 {
 818         u64 host_tsc, tsc_offset;
 819
 820         rdtscll(host_tsc);
 821         tsc_offset = vmcs_read64(TSC_OFFSET);
 822         return host_tsc + tsc_offset;
 823 }
 824
 825 /*
 826  * writes 'guest_tsc' into guest's timestamp counter "register"
 827  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 828  */
 829 static void guest_write_tsc(u64 guest_tsc)
 830 {
 831         u64 host_tsc;
 832
 833         rdtscll(host_tsc);
 834         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 835 }
 836
 837 /*
 838  * Reads an msr value (of 'msr_index') into 'pdata'.
 839  * Returns 0 on success, non-0 otherwise.
 840  * Assumes vcpu_load() was already called.
 841  */
 842 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 843 {
 844         u64 data;
 845         struct kvm_msr_entry *msr;
 846
 847         if (!pdata) {
 848                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 849                 return -EINVAL;
 850         }
 851
 852         switch (msr_index) {
 853 #ifdef CONFIG_X86_64
 854         case MSR_FS_BASE:
 855                 data = vmcs_readl(GUEST_FS_BASE);
 856                 break;
 857         case MSR_GS_BASE:
 858                 data = vmcs_readl(GUEST_GS_BASE);
 859                 break;
 860         case MSR_EFER:
 861                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 862 #endif
 863         case MSR_IA32_TIME_STAMP_COUNTER:
 864                 data = guest_read_tsc();
 865                 break;
 866         case MSR_IA32_SYSENTER_CS:
 867                 data = vmcs_read32(GUEST_SYSENTER_CS);
 868                 break;
 869         case MSR_IA32_SYSENTER_EIP:
 870                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 871                 break;
 872         case MSR_IA32_SYSENTER_ESP:
 873                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 874                 break;
 875         default:
 876                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 877                 if (msr) {
 878                         data = msr->data;
 879                         break;
 880                 }
 881                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 882         }
 883
 884         *pdata = data;
 885         return 0;
 886 }
 887
 888 /*
 889  * Writes msr value into into the appropriate "register".
 890  * Returns 0 on success, non-0 otherwise.
 891  * Assumes vcpu_load() was already called.
 892  */
 893 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 894 {
 895         struct vcpu_vmx *vmx = to_vmx(vcpu);
 896         struct kvm_msr_entry *msr;
 897         int ret = 0;
 898
 899         switch (msr_index) {
 900 #ifdef CONFIG_X86_64
 901         case MSR_EFER:
 902                 vmx_load_host_state(vmx);
 903                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 904                 break;
 905         case MSR_FS_BASE:
 906                 vmcs_writel(GUEST_FS_BASE, data);
 907                 break;
 908         case MSR_GS_BASE:
 909                 vmcs_writel(GUEST_GS_BASE, data);
 910                 break;
 911 #endif
 912         case MSR_IA32_SYSENTER_CS:
 913                 vmcs_write32(GUEST_SYSENTER_CS, data);
 914                 break;
 915         case MSR_IA32_SYSENTER_EIP:
 916                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 917                 break;
 918         case MSR_IA32_SYSENTER_ESP:
 919                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 920                 break;
 921         case MSR_IA32_TIME_STAMP_COUNTER:
 922                 guest_write_tsc(data);
 923                 break;
 924         case MSR_P6_PERFCTR0:
 925         case MSR_P6_PERFCTR1:
 926         case MSR_P6_EVNTSEL0:
 927         case MSR_P6_EVNTSEL1:
 928                 /*
 929                  * Just discard all writes to the performance counters; this
 930                  * should keep both older linux and windows 64-bit guests
 931                  * happy
 932                  */
 933                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 934
 935                 break;
 936         default:
 937                 vmx_load_host_state(vmx);
 938                 msr = find_msr_entry(vmx, msr_index);
 939                 if (msr) {
 940                         msr->data = data;
 941                         break;
 942                 }
 943                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 944         }
 945
 946         return ret;
 947 }
 948
 949 /*
 950  * Sync the rsp and rip registers into the vcpu structure.  This allows
 951  * registers to be accessed by indexing vcpu->arch.regs.
 952  */
 953 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 954 {
 955         vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 956         vcpu->arch.rip = vmcs_readl(GUEST_RIP);
 957 }
 958
 959 /*
 960  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 961  * modification.
 962  */
 963 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 964 {
 965         vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
 966         vmcs_writel(GUEST_RIP, vcpu->arch.rip);
 967 }
 968
 969 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 970 {
 971         unsigned long dr7 = 0x400;
 972         int old_singlestep;
 973
 974         old_singlestep = vcpu->guest_debug.singlestep;
 975
 976         vcpu->guest_debug.enabled = dbg->enabled;
 977         if (vcpu->guest_debug.enabled) {
 978                 int i;
 979
 980                 dr7 |= 0x200;  /* exact */
 981                 for (i = 0; i < 4; ++i) {
 982                         if (!dbg->breakpoints[i].enabled)
 983                                 continue;
 984                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 985                         dr7 |= 2 << (i*2);    /* global enable */
 986                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 987                 }
 988
 989                 vcpu->guest_debug.singlestep = dbg->singlestep;
 990         } else
 991                 vcpu->guest_debug.singlestep = 0;
 992
 993         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 994                 unsigned long flags;
 995
 996                 flags = vmcs_readl(GUEST_RFLAGS);
 997                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 998                 vmcs_writel(GUEST_RFLAGS, flags);
 999         }
1000
1001         update_exception_bitmap(vcpu);
1002         vmcs_writel(GUEST_DR7, dr7);
1003
1004         return 0;
1005 }
1006
1007 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1008 {
1009         struct vcpu_vmx *vmx = to_vmx(vcpu);
1010         u32 idtv_info_field;
1011
1012         idtv_info_field = vmx->idt_vectoring_info;
1013         if (idtv_info_field & INTR_INFO_VALID_MASK) {
1014                 if (is_external_interrupt(idtv_info_field))
1015                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
1016                 else
1017                         printk(KERN_DEBUG "pending exception: not handled yet\n");
1018         }
1019         return -1;
1020 }
1021
1022 static __init int cpu_has_kvm_support(void)
1023 {
1024         unsigned long ecx = cpuid_ecx(1);
1025         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1026 }
1027
1028 static __init int vmx_disabled_by_bios(void)
1029 {
1030         u64 msr;
1031
1032         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1033         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1034                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1035             == MSR_IA32_FEATURE_CONTROL_LOCKED;
1036         /* locked but not enabled */
1037 }
1038
1039 static void hardware_enable(void *garbage)
1040 {
1041         int cpu = raw_smp_processor_id();
1042         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1043         u64 old;
1044
1045         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1046         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1047         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1048                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1049             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
1050                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1051                 /* enable and lock */
1052                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1053                        MSR_IA32_FEATURE_CONTROL_LOCKED |
1054                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
1055         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1056         asm volatile (ASM_VMX_VMXON_RAX
1057                       : : "a"(&phys_addr), "m"(phys_addr)
1058                       : "memory", "cc");
1059 }
1060
1061 static void vmclear_local_vcpus(void)
1062 {
1063         int cpu = raw_smp_processor_id();
1064         struct vcpu_vmx *vmx, *n;
1065
1066         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1067                                  local_vcpus_link)
1068                 __vcpu_clear(vmx);
1069 }
1070
1071 static void hardware_disable(void *garbage)
1072 {
1073         vmclear_local_vcpus();
1074         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1075         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1076 }
1077
1078 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1079                                       u32 msr, u32 *result)
1080 {
1081         u32 vmx_msr_low, vmx_msr_high;
1082         u32 ctl = ctl_min | ctl_opt;
1083
1084         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1085
1086         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1087         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1088
1089         /* Ensure minimum (required) set of control bits are supported. */
1090         if (ctl_min & ~ctl)
1091                 return -EIO;
1092
1093         *result = ctl;
1094         return 0;
1095 }
1096
1097 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1098 {
1099         u32 vmx_msr_low, vmx_msr_high;
1100         u32 min, opt, min2, opt2;
1101         u32 _pin_based_exec_control = 0;
1102         u32 _cpu_based_exec_control = 0;
1103         u32 _cpu_based_2nd_exec_control = 0;
1104         u32 _vmexit_control = 0;
1105         u32 _vmentry_control = 0;
1106
1107         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1108         opt = PIN_BASED_VIRTUAL_NMIS;
1109         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1110                                 &_pin_based_exec_control) < 0)
1111                 return -EIO;
1112
1113         min = CPU_BASED_HLT_EXITING |
1114 #ifdef CONFIG_X86_64
1115               CPU_BASED_CR8_LOAD_EXITING |
1116               CPU_BASED_CR8_STORE_EXITING |
1117 #endif
1118               CPU_BASED_CR3_LOAD_EXITING |
1119               CPU_BASED_CR3_STORE_EXITING |
1120               CPU_BASED_USE_IO_BITMAPS |
1121               CPU_BASED_MOV_DR_EXITING |
1122               CPU_BASED_USE_TSC_OFFSETING;
1123         opt = CPU_BASED_TPR_SHADOW |
1124               CPU_BASED_USE_MSR_BITMAPS |
1125               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1126         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1127                                 &_cpu_based_exec_control) < 0)
1128                 return -EIO;
1129 #ifdef CONFIG_X86_64
1130         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1131                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1132                                            ~CPU_BASED_CR8_STORE_EXITING;
1133 #endif
1134         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1135                 min2 = 0;
1136                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1137                         SECONDARY_EXEC_WBINVD_EXITING |
1138                         SECONDARY_EXEC_ENABLE_VPID |
1139                         SECONDARY_EXEC_ENABLE_EPT;
1140                 if (adjust_vmx_controls(min2, opt2,
1141                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1142                                         &_cpu_based_2nd_exec_control) < 0)
1143                         return -EIO;
1144         }
1145 #ifndef CONFIG_X86_64
1146         if (!(_cpu_based_2nd_exec_control &
1147                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1148                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1149 #endif
1150         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1151                 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1152                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1153                          CPU_BASED_CR3_STORE_EXITING);
1154                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1155                                         &_cpu_based_exec_control) < 0)
1156                         return -EIO;
1157                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1158                       vmx_capability.ept, vmx_capability.vpid);
1159         }
1160
1161         min = 0;
1162 #ifdef CONFIG_X86_64
1163         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1164 #endif
1165         opt = 0;
1166         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1167                                 &_vmexit_control) < 0)
1168                 return -EIO;
1169
1170         min = opt = 0;
1171         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1172                                 &_vmentry_control) < 0)
1173                 return -EIO;
1174
1175         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1176
1177         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1178         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1179                 return -EIO;
1180
1181 #ifdef CONFIG_X86_64
1182         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1183         if (vmx_msr_high & (1u<<16))
1184                 return -EIO;
1185 #endif
1186
1187         /* Require Write-Back (WB) memory type for VMCS accesses. */
1188         if (((vmx_msr_high >> 18) & 15) != 6)
1189                 return -EIO;
1190
1191         vmcs_conf->size = vmx_msr_high & 0x1fff;
1192         vmcs_conf->order = get_order(vmcs_config.size);
1193         vmcs_conf->revision_id = vmx_msr_low;
1194
1195         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1196         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1197         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1198         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1199         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1200
1201         return 0;
1202 }
1203
1204 static struct vmcs *alloc_vmcs_cpu(int cpu)
1205 {
1206         int node = cpu_to_node(cpu);
1207         struct page *pages;
1208         struct vmcs *vmcs;
1209
1210         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1211         if (!pages)
1212                 return NULL;
1213         vmcs = page_address(pages);
1214         memset(vmcs, 0, vmcs_config.size);
1215         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1216         return vmcs;
1217 }
1218
1219 static struct vmcs *alloc_vmcs(void)
1220 {
1221         return alloc_vmcs_cpu(raw_smp_processor_id());
1222 }
1223
1224 static void free_vmcs(struct vmcs *vmcs)
1225 {
1226         free_pages((unsigned long)vmcs, vmcs_config.order);
1227 }
1228
1229 static void free_kvm_area(void)
1230 {
1231         int cpu;
1232
1233         for_each_online_cpu(cpu)
1234                 free_vmcs(per_cpu(vmxarea, cpu));
1235 }
1236
1237 static __init int alloc_kvm_area(void)
1238 {
1239         int cpu;
1240
1241         for_each_online_cpu(cpu) {
1242                 struct vmcs *vmcs;
1243
1244                 vmcs = alloc_vmcs_cpu(cpu);
1245                 if (!vmcs) {
1246                         free_kvm_area();
1247                         return -ENOMEM;
1248                 }
1249
1250                 per_cpu(vmxarea, cpu) = vmcs;
1251         }
1252         return 0;
1253 }
1254
1255 static __init int hardware_setup(void)
1256 {
1257         if (setup_vmcs_config(&vmcs_config) < 0)
1258                 return -EIO;
1259
1260         if (boot_cpu_has(X86_FEATURE_NX))
1261                 kvm_enable_efer_bits(EFER_NX);
1262
1263         return alloc_kvm_area();
1264 }
1265
1266 static __exit void hardware_unsetup(void)
1267 {
1268         free_kvm_area();
1269 }
1270
1271 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1272 {
1273         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1274
1275         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1276                 vmcs_write16(sf->selector, save->selector);
1277                 vmcs_writel(sf->base, save->base);
1278                 vmcs_write32(sf->limit, save->limit);
1279                 vmcs_write32(sf->ar_bytes, save->ar);
1280         } else {
1281                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1282                         << AR_DPL_SHIFT;
1283                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1284         }
1285 }
1286
1287 static void enter_pmode(struct kvm_vcpu *vcpu)
1288 {
1289         unsigned long flags;
1290
1291         vcpu->arch.rmode.active = 0;
1292
1293         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1294         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1295         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1296
1297         flags = vmcs_readl(GUEST_RFLAGS);
1298         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1299         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1300         vmcs_writel(GUEST_RFLAGS, flags);
1301
1302         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1303                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1304
1305         update_exception_bitmap(vcpu);
1306
1307         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1308         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1309         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1310         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1311
1312         vmcs_write16(GUEST_SS_SELECTOR, 0);
1313         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1314
1315         vmcs_write16(GUEST_CS_SELECTOR,
1316                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1317         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1318 }
1319
1320 static gva_t rmode_tss_base(struct kvm *kvm)
1321 {
1322         if (!kvm->arch.tss_addr) {
1323                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1324                                  kvm->memslots[0].npages - 3;
1325                 return base_gfn << PAGE_SHIFT;
1326         }
1327         return kvm->arch.tss_addr;
1328 }
1329
1330 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1331 {
1332         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1333
1334         save->selector = vmcs_read16(sf->selector);
1335         save->base = vmcs_readl(sf->base);
1336         save->limit = vmcs_read32(sf->limit);
1337         save->ar = vmcs_read32(sf->ar_bytes);
1338         vmcs_write16(sf->selector, save->base >> 4);
1339         vmcs_write32(sf->base, save->base & 0xfffff);
1340         vmcs_write32(sf->limit, 0xffff);
1341         vmcs_write32(sf->ar_bytes, 0xf3);
1342 }
1343
1344 static void enter_rmode(struct kvm_vcpu *vcpu)
1345 {
1346         unsigned long flags;
1347
1348         vcpu->arch.rmode.active = 1;
1349
1350         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1351         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1352
1353         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1354         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1355
1356         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1357         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1358
1359         flags = vmcs_readl(GUEST_RFLAGS);
1360         vcpu->arch.rmode.save_iopl
1361                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1362
1363         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1364
1365         vmcs_writel(GUEST_RFLAGS, flags);
1366         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1367         update_exception_bitmap(vcpu);
1368
1369         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1370         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1371         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1372
1373         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1374         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1375         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1376                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1377         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1378
1379         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1380         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1381         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1382         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1383
1384         kvm_mmu_reset_context(vcpu);
1385         init_rmode(vcpu->kvm);
1386 }
1387
1388 #ifdef CONFIG_X86_64
1389
1390 static void enter_lmode(struct kvm_vcpu *vcpu)
1391 {
1392         u32 guest_tr_ar;
1393
1394         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1395         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1396                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1397                        __func__);
1398                 vmcs_write32(GUEST_TR_AR_BYTES,
1399                              (guest_tr_ar & ~AR_TYPE_MASK)
1400                              | AR_TYPE_BUSY_64_TSS);
1401         }
1402
1403         vcpu->arch.shadow_efer |= EFER_LMA;
1404
1405         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1406         vmcs_write32(VM_ENTRY_CONTROLS,
1407                      vmcs_read32(VM_ENTRY_CONTROLS)
1408                      | VM_ENTRY_IA32E_MODE);
1409 }
1410
1411 static void exit_lmode(struct kvm_vcpu *vcpu)
1412 {
1413         vcpu->arch.shadow_efer &= ~EFER_LMA;
1414
1415         vmcs_write32(VM_ENTRY_CONTROLS,
1416                      vmcs_read32(VM_ENTRY_CONTROLS)
1417                      & ~VM_ENTRY_IA32E_MODE);
1418 }
1419
1420 #endif
1421
1422 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1423 {
1424         vpid_sync_vcpu_all(to_vmx(vcpu));
1425 }
1426
1427 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1428 {
1429         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1430         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1431 }
1432
1433 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1434 {
1435         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1436                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1437                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1438                         return;
1439                 }
1440                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1441                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1442                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1443                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1444         }
1445 }
1446
1447 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1448
1449 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1450                                         unsigned long cr0,
1451                                         struct kvm_vcpu *vcpu)
1452 {
1453         if (!(cr0 & X86_CR0_PG)) {
1454                 /* From paging/starting to nonpaging */
1455                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1456                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1457                              (CPU_BASED_CR3_LOAD_EXITING |
1458                               CPU_BASED_CR3_STORE_EXITING));
1459                 vcpu->arch.cr0 = cr0;
1460                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1461                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1462                 *hw_cr0 &= ~X86_CR0_WP;
1463         } else if (!is_paging(vcpu)) {
1464                 /* From nonpaging to paging */
1465                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1466                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1467                              ~(CPU_BASED_CR3_LOAD_EXITING |
1468                                CPU_BASED_CR3_STORE_EXITING));
1469                 vcpu->arch.cr0 = cr0;
1470                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1471                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1472                         *hw_cr0 &= ~X86_CR0_WP;
1473         }
1474 }
1475
1476 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1477                                         struct kvm_vcpu *vcpu)
1478 {
1479         if (!is_paging(vcpu)) {
1480                 *hw_cr4 &= ~X86_CR4_PAE;
1481                 *hw_cr4 |= X86_CR4_PSE;
1482         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1483                 *hw_cr4 &= ~X86_CR4_PAE;
1484 }
1485
1486 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1487 {
1488         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1489                                 KVM_VM_CR0_ALWAYS_ON;
1490
1491         vmx_fpu_deactivate(vcpu);
1492
1493         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1494                 enter_pmode(vcpu);
1495
1496         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1497                 enter_rmode(vcpu);
1498
1499 #ifdef CONFIG_X86_64
1500         if (vcpu->arch.shadow_efer & EFER_LME) {
1501                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1502                         enter_lmode(vcpu);
1503                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1504                         exit_lmode(vcpu);
1505         }
1506 #endif
1507
1508         if (vm_need_ept())
1509                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1510
1511         vmcs_writel(CR0_READ_SHADOW, cr0);
1512         vmcs_writel(GUEST_CR0, hw_cr0);
1513         vcpu->arch.cr0 = cr0;
1514
1515         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1516                 vmx_fpu_activate(vcpu);
1517 }
1518
1519 static u64 construct_eptp(unsigned long root_hpa)
1520 {
1521         u64 eptp;
1522
1523         /* TODO write the value reading from MSR */
1524         eptp = VMX_EPT_DEFAULT_MT |
1525                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1526         eptp |= (root_hpa & PAGE_MASK);
1527
1528         return eptp;
1529 }
1530
1531 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1532 {
1533         unsigned long guest_cr3;
1534         u64 eptp;
1535
1536         guest_cr3 = cr3;
1537         if (vm_need_ept()) {
1538                 eptp = construct_eptp(cr3);
1539                 vmcs_write64(EPT_POINTER, eptp);
1540                 ept_sync_context(eptp);
1541                 ept_load_pdptrs(vcpu);
1542                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1543                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1544         }
1545
1546         vmx_flush_tlb(vcpu);
1547         vmcs_writel(GUEST_CR3, guest_cr3);
1548         if (vcpu->arch.cr0 & X86_CR0_PE)
1549                 vmx_fpu_deactivate(vcpu);
1550 }
1551
1552 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1553 {
1554         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1555                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1556
1557         vcpu->arch.cr4 = cr4;
1558         if (vm_need_ept())
1559                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1560
1561         vmcs_writel(CR4_READ_SHADOW, cr4);
1562         vmcs_writel(GUEST_CR4, hw_cr4);
1563 }
1564
1565 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1566 {
1567         struct vcpu_vmx *vmx = to_vmx(vcpu);
1568         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1569
1570         vcpu->arch.shadow_efer = efer;
1571         if (!msr)
1572                 return;
1573         if (efer & EFER_LMA) {
1574                 vmcs_write32(VM_ENTRY_CONTROLS,
1575                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1576                                      VM_ENTRY_IA32E_MODE);
1577                 msr->data = efer;
1578
1579         } else {
1580                 vmcs_write32(VM_ENTRY_CONTROLS,
1581                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1582                                      ~VM_ENTRY_IA32E_MODE);
1583
1584                 msr->data = efer & ~EFER_LME;
1585         }
1586         setup_msrs(vmx);
1587 }
1588
1589 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1590 {
1591         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1592
1593         return vmcs_readl(sf->base);
1594 }
1595
1596 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1597                             struct kvm_segment *var, int seg)
1598 {
1599         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1600         u32 ar;
1601
1602         var->base = vmcs_readl(sf->base);
1603         var->limit = vmcs_read32(sf->limit);
1604         var->selector = vmcs_read16(sf->selector);
1605         ar = vmcs_read32(sf->ar_bytes);
1606         if (ar & AR_UNUSABLE_MASK)
1607                 ar = 0;
1608         var->type = ar & 15;
1609         var->s = (ar >> 4) & 1;
1610         var->dpl = (ar >> 5) & 3;
1611         var->present = (ar >> 7) & 1;
1612         var->avl = (ar >> 12) & 1;
1613         var->l = (ar >> 13) & 1;
1614         var->db = (ar >> 14) & 1;
1615         var->g = (ar >> 15) & 1;
1616         var->unusable = (ar >> 16) & 1;
1617 }
1618
1619 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1620 {
1621         struct kvm_segment kvm_seg;
1622
1623         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1624                 return 0;
1625
1626         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1627                 return 3;
1628
1629         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1630         return kvm_seg.selector & 3;
1631 }
1632
1633 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1634 {
1635         u32 ar;
1636
1637         if (var->unusable)
1638                 ar = 1 << 16;
1639         else {
1640                 ar = var->type & 15;
1641                 ar |= (var->s & 1) << 4;
1642                 ar |= (var->dpl & 3) << 5;
1643                 ar |= (var->present & 1) << 7;
1644                 ar |= (var->avl & 1) << 12;
1645                 ar |= (var->l & 1) << 13;
1646                 ar |= (var->db & 1) << 14;
1647                 ar |= (var->g & 1) << 15;
1648         }
1649         if (ar == 0) /* a 0 value means unusable */
1650                 ar = AR_UNUSABLE_MASK;
1651
1652         return ar;
1653 }
1654
1655 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1656                             struct kvm_segment *var, int seg)
1657 {
1658         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1659         u32 ar;
1660
1661         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1662                 vcpu->arch.rmode.tr.selector = var->selector;
1663                 vcpu->arch.rmode.tr.base = var->base;
1664                 vcpu->arch.rmode.tr.limit = var->limit;
1665                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1666                 return;
1667         }
1668         vmcs_writel(sf->base, var->base);
1669         vmcs_write32(sf->limit, var->limit);
1670         vmcs_write16(sf->selector, var->selector);
1671         if (vcpu->arch.rmode.active && var->s) {
1672                 /*
1673                  * Hack real-mode segments into vm86 compatibility.
1674                  */
1675                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1676                         vmcs_writel(sf->base, 0xf0000);
1677                 ar = 0xf3;
1678         } else
1679                 ar = vmx_segment_access_rights(var);
1680         vmcs_write32(sf->ar_bytes, ar);
1681 }
1682
1683 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1684 {
1685         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1686
1687         *db = (ar >> 14) & 1;
1688         *l = (ar >> 13) & 1;
1689 }
1690
1691 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1692 {
1693         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1694         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1695 }
1696
1697 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1698 {
1699         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1700         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1701 }
1702
1703 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1704 {
1705         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1706         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1707 }
1708
1709 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1710 {
1711         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1712         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1713 }
1714
1715 static int init_rmode_tss(struct kvm *kvm)
1716 {
1717         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1718         u16 data = 0;
1719         int ret = 0;
1720         int r;
1721
1722         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1723         if (r < 0)
1724                 goto out;
1725         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1726         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1727         if (r < 0)
1728                 goto out;
1729         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1730         if (r < 0)
1731                 goto out;
1732         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1733         if (r < 0)
1734                 goto out;
1735         data = ~0;
1736         r = kvm_write_guest_page(kvm, fn, &data,
1737                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1738                                  sizeof(u8));
1739         if (r < 0)
1740                 goto out;
1741
1742         ret = 1;
1743 out:
1744         return ret;
1745 }
1746
1747 static int init_rmode_identity_map(struct kvm *kvm)
1748 {
1749         int i, r, ret;
1750         pfn_t identity_map_pfn;
1751         u32 tmp;
1752
1753         if (!vm_need_ept())
1754                 return 1;
1755         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1756                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1757                         "haven't been allocated!\n");
1758                 return 0;
1759         }
1760         if (likely(kvm->arch.ept_identity_pagetable_done))
1761                 return 1;
1762         ret = 0;
1763         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1764         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1765         if (r < 0)
1766                 goto out;
1767         /* Set up identity-mapping pagetable for EPT in real mode */
1768         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1769                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1770                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1771                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1772                                 &tmp, i * sizeof(tmp), sizeof(tmp));
1773                 if (r < 0)
1774                         goto out;
1775         }
1776         kvm->arch.ept_identity_pagetable_done = true;
1777         ret = 1;
1778 out:
1779         return ret;
1780 }
1781
1782 static void seg_setup(int seg)
1783 {
1784         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1785
1786         vmcs_write16(sf->selector, 0);
1787         vmcs_writel(sf->base, 0);
1788         vmcs_write32(sf->limit, 0xffff);
1789         vmcs_write32(sf->ar_bytes, 0x93);
1790 }
1791
1792 static int alloc_apic_access_page(struct kvm *kvm)
1793 {
1794         struct kvm_userspace_memory_region kvm_userspace_mem;
1795         int r = 0;
1796
1797         down_write(&kvm->slots_lock);
1798         if (kvm->arch.apic_access_page)
1799                 goto out;
1800         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1801         kvm_userspace_mem.flags = 0;
1802         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1803         kvm_userspace_mem.memory_size = PAGE_SIZE;
1804         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1805         if (r)
1806                 goto out;
1807
1808         down_read(&current->mm->mmap_sem);
1809         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1810         up_read(&current->mm->mmap_sem);
1811 out:
1812         up_write(&kvm->slots_lock);
1813         return r;
1814 }
1815
1816 static int alloc_identity_pagetable(struct kvm *kvm)
1817 {
1818         struct kvm_userspace_memory_region kvm_userspace_mem;
1819         int r = 0;
1820
1821         down_write(&kvm->slots_lock);
1822         if (kvm->arch.ept_identity_pagetable)
1823                 goto out;
1824         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1825         kvm_userspace_mem.flags = 0;
1826         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1827         kvm_userspace_mem.memory_size = PAGE_SIZE;
1828         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1829         if (r)
1830                 goto out;
1831
1832         down_read(&current->mm->mmap_sem);
1833         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1834                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1835         up_read(&current->mm->mmap_sem);
1836 out:
1837         up_write(&kvm->slots_lock);
1838         return r;
1839 }
1840
1841 static void allocate_vpid(struct vcpu_vmx *vmx)
1842 {
1843         int vpid;
1844
1845         vmx->vpid = 0;
1846         if (!enable_vpid || !cpu_has_vmx_vpid())
1847                 return;
1848         spin_lock(&vmx_vpid_lock);
1849         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1850         if (vpid < VMX_NR_VPIDS) {
1851                 vmx->vpid = vpid;
1852                 __set_bit(vpid, vmx_vpid_bitmap);
1853         }
1854         spin_unlock(&vmx_vpid_lock);
1855 }
1856
1857 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1858 {
1859         void *va;
1860
1861         if (!cpu_has_vmx_msr_bitmap())
1862                 return;
1863
1864         /*
1865          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1866          * have the write-low and read-high bitmap offsets the wrong way round.
1867          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1868          */
1869         va = kmap(msr_bitmap);
1870         if (msr <= 0x1fff) {
1871                 __clear_bit(msr, va + 0x000); /* read-low */
1872                 __clear_bit(msr, va + 0x800); /* write-low */
1873         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1874                 msr &= 0x1fff;
1875                 __clear_bit(msr, va + 0x400); /* read-high */
1876                 __clear_bit(msr, va + 0xc00); /* write-high */
1877         }
1878         kunmap(msr_bitmap);
1879 }
1880
1881 /*
1882  * Sets up the vmcs for emulated real mode.
1883  */
1884 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1885 {
1886         u32 host_sysenter_cs;
1887         u32 junk;
1888         unsigned long a;
1889         struct descriptor_table dt;
1890         int i;
1891         unsigned long kvm_vmx_return;
1892         u32 exec_control;
1893
1894         /* I/O */
1895         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1896         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1897
1898         if (cpu_has_vmx_msr_bitmap())
1899                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1900
1901         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1902
1903         /* Control */
1904         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1905                 vmcs_config.pin_based_exec_ctrl);
1906
1907         exec_control = vmcs_config.cpu_based_exec_ctrl;
1908         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1909                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1910 #ifdef CONFIG_X86_64
1911                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1912                                 CPU_BASED_CR8_LOAD_EXITING;
1913 #endif
1914         }
1915         if (!vm_need_ept())
1916                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1917                                 CPU_BASED_CR3_LOAD_EXITING;
1918         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1919
1920         if (cpu_has_secondary_exec_ctrls()) {
1921                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1922                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1923                         exec_control &=
1924                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1925                 if (vmx->vpid == 0)
1926                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1927                 if (!vm_need_ept())
1928                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
1929                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1930         }
1931
1932         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1933         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1934         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1935
1936         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1937         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1938         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1939
1940         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1941         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1942         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1943         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1944         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1945         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1946 #ifdef CONFIG_X86_64
1947         rdmsrl(MSR_FS_BASE, a);
1948         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1949         rdmsrl(MSR_GS_BASE, a);
1950         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1951 #else
1952         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1953         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1954 #endif
1955
1956         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1957
1958         get_idt(&dt);
1959         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1960
1961         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1962         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1963         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1964         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1965         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1966
1967         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1968         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1969         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1970         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1971         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1972         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1973
1974         for (i = 0; i < NR_VMX_MSR; ++i) {
1975                 u32 index = vmx_msr_index[i];
1976                 u32 data_low, data_high;
1977                 u64 data;
1978                 int j = vmx->nmsrs;
1979
1980                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1981                         continue;
1982                 if (wrmsr_safe(index, data_low, data_high) < 0)
1983                         continue;
1984                 data = data_low | ((u64)data_high << 32);
1985                 vmx->host_msrs[j].index = index;
1986                 vmx->host_msrs[j].reserved = 0;
1987                 vmx->host_msrs[j].data = data;
1988                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1989                 ++vmx->nmsrs;
1990         }
1991
1992         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1993
1994         /* 22.2.1, 20.8.1 */
1995         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1996
1997         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1998         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1999
2000
2001         return 0;
2002 }
2003
2004 static int init_rmode(struct kvm *kvm)
2005 {
2006         if (!init_rmode_tss(kvm))
2007                 return 0;
2008         if (!init_rmode_identity_map(kvm))
2009                 return 0;
2010         return 1;
2011 }
2012
2013 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2014 {
2015         struct vcpu_vmx *vmx = to_vmx(vcpu);
2016         u64 msr;
2017         int ret;
2018
2019         down_read(&vcpu->kvm->slots_lock);
2020         if (!init_rmode(vmx->vcpu.kvm)) {
2021                 ret = -ENOMEM;
2022                 goto out;
2023         }
2024
2025         vmx->vcpu.arch.rmode.active = 0;
2026
2027         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2028         kvm_set_cr8(&vmx->vcpu, 0);
2029         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2030         if (vmx->vcpu.vcpu_id == 0)
2031                 msr |= MSR_IA32_APICBASE_BSP;
2032         kvm_set_apic_base(&vmx->vcpu, msr);
2033
2034         fx_init(&vmx->vcpu);
2035
2036         /*
2037          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2038          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2039          */
2040         if (vmx->vcpu.vcpu_id == 0) {
2041                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2042                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2043         } else {
2044                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2045                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2046         }
2047         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2048         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2049
2050         seg_setup(VCPU_SREG_DS);
2051         seg_setup(VCPU_SREG_ES);
2052         seg_setup(VCPU_SREG_FS);
2053         seg_setup(VCPU_SREG_GS);
2054         seg_setup(VCPU_SREG_SS);
2055
2056         vmcs_write16(GUEST_TR_SELECTOR, 0);
2057         vmcs_writel(GUEST_TR_BASE, 0);
2058         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2059         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2060
2061         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2062         vmcs_writel(GUEST_LDTR_BASE, 0);
2063         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2064         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2065
2066         vmcs_write32(GUEST_SYSENTER_CS, 0);
2067         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2068         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2069
2070         vmcs_writel(GUEST_RFLAGS, 0x02);
2071         if (vmx->vcpu.vcpu_id == 0)
2072                 vmcs_writel(GUEST_RIP, 0xfff0);
2073         else
2074                 vmcs_writel(GUEST_RIP, 0);
2075         vmcs_writel(GUEST_RSP, 0);
2076
2077         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2078         vmcs_writel(GUEST_DR7, 0x400);
2079
2080         vmcs_writel(GUEST_GDTR_BASE, 0);
2081         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2082
2083         vmcs_writel(GUEST_IDTR_BASE, 0);
2084         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2085
2086         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2087         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2088         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2089
2090         guest_write_tsc(0);
2091
2092         /* Special registers */
2093         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2094
2095         setup_msrs(vmx);
2096
2097         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2098
2099         if (cpu_has_vmx_tpr_shadow()) {
2100                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2101                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2102                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2103                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2104                 vmcs_write32(TPR_THRESHOLD, 0);
2105         }
2106
2107         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2108                 vmcs_write64(APIC_ACCESS_ADDR,
2109                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2110
2111         if (vmx->vpid != 0)
2112                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2113
2114         vmx->vcpu.arch.cr0 = 0x60000010;
2115         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2116         vmx_set_cr4(&vmx->vcpu, 0);
2117         vmx_set_efer(&vmx->vcpu, 0);
2118         vmx_fpu_activate(&vmx->vcpu);
2119         update_exception_bitmap(&vmx->vcpu);
2120
2121         vpid_sync_vcpu_all(vmx);
2122
2123         ret = 0;
2124
2125 out:
2126         up_read(&vcpu->kvm->slots_lock);
2127         return ret;
2128 }
2129
2130 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2131 {
2132         struct vcpu_vmx *vmx = to_vmx(vcpu);
2133
2134         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2135
2136         if (vcpu->arch.rmode.active) {
2137                 vmx->rmode.irq.pending = true;
2138                 vmx->rmode.irq.vector = irq;
2139                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
2140                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2141                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2142                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2143                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
2144                 return;
2145         }
2146         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2147                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2148 }
2149
2150 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2151 {
2152         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2153                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2154         vcpu->arch.nmi_pending = 0;
2155 }
2156
2157 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2158 {
2159         int word_index = __ffs(vcpu->arch.irq_summary);
2160         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2161         int irq = word_index * BITS_PER_LONG + bit_index;
2162
2163         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2164         if (!vcpu->arch.irq_pending[word_index])
2165                 clear_bit(word_index, &vcpu->arch.irq_summary);
2166         vmx_inject_irq(vcpu, irq);
2167 }
2168
2169
2170 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2171                                        struct kvm_run *kvm_run)
2172 {
2173         u32 cpu_based_vm_exec_control;
2174
2175         vcpu->arch.interrupt_window_open =
2176                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2177                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2178
2179         if (vcpu->arch.interrupt_window_open &&
2180             vcpu->arch.irq_summary &&
2181             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
2182                 /*
2183                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2184                  */
2185                 kvm_do_inject_irq(vcpu);
2186
2187         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2188         if (!vcpu->arch.interrupt_window_open &&
2189             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2190                 /*
2191                  * Interrupts blocked.  Wait for unblock.
2192                  */
2193                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2194         else
2195                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2196         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2197 }
2198
2199 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2200 {
2201         int ret;
2202         struct kvm_userspace_memory_region tss_mem = {
2203                 .slot = 8,
2204                 .guest_phys_addr = addr,
2205                 .memory_size = PAGE_SIZE * 3,
2206                 .flags = 0,
2207         };
2208
2209         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2210         if (ret)
2211                 return ret;
2212         kvm->arch.tss_addr = addr;
2213         return 0;
2214 }
2215
2216 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2217 {
2218         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2219
2220         set_debugreg(dbg->bp[0], 0);
2221         set_debugreg(dbg->bp[1], 1);
2222         set_debugreg(dbg->bp[2], 2);
2223         set_debugreg(dbg->bp[3], 3);
2224
2225         if (dbg->singlestep) {
2226                 unsigned long flags;
2227
2228                 flags = vmcs_readl(GUEST_RFLAGS);
2229                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2230                 vmcs_writel(GUEST_RFLAGS, flags);
2231         }
2232 }
2233
2234 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2235                                   int vec, u32 err_code)
2236 {
2237         if (!vcpu->arch.rmode.active)
2238                 return 0;
2239
2240         /*
2241          * Instruction with address size override prefix opcode 0x67
2242          * Cause the #SS fault with 0 error code in VM86 mode.
2243          */
2244         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2245                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2246                         return 1;
2247         return 0;
2248 }
2249
2250 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2251 {
2252         struct vcpu_vmx *vmx = to_vmx(vcpu);
2253         u32 intr_info, error_code;
2254         unsigned long cr2, rip;
2255         u32 vect_info;
2256         enum emulation_result er;
2257
2258         vect_info = vmx->idt_vectoring_info;
2259         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2260
2261         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2262                                                 !is_page_fault(intr_info))
2263                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2264                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2265
2266         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2267                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2268                 set_bit(irq, vcpu->arch.irq_pending);
2269                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2270         }
2271
2272         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2273                 return 1;  /* already handled by vmx_vcpu_run() */
2274
2275         if (is_no_device(intr_info)) {
2276                 vmx_fpu_activate(vcpu);
2277                 return 1;
2278         }
2279
2280         if (is_invalid_opcode(intr_info)) {
2281                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2282                 if (er != EMULATE_DONE)
2283                         kvm_queue_exception(vcpu, UD_VECTOR);
2284                 return 1;
2285         }
2286
2287         error_code = 0;
2288         rip = vmcs_readl(GUEST_RIP);
2289         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2290                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2291         if (is_page_fault(intr_info)) {
2292                 /* EPT won't cause page fault directly */
2293                 if (vm_need_ept())
2294                         BUG();
2295                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2296                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2297                             (u32)((u64)cr2 >> 32), handler);
2298                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2299         }
2300
2301         if (vcpu->arch.rmode.active &&
2302             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2303                                                                 error_code)) {
2304                 if (vcpu->arch.halt_request) {
2305                         vcpu->arch.halt_request = 0;
2306                         return kvm_emulate_halt(vcpu);
2307                 }
2308                 return 1;
2309         }
2310
2311         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2312             (INTR_TYPE_EXCEPTION | 1)) {
2313                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2314                 return 0;
2315         }
2316         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2317         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2318         kvm_run->ex.error_code = error_code;
2319         return 0;
2320 }
2321
2322 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2323                                      struct kvm_run *kvm_run)
2324 {
2325         ++vcpu->stat.irq_exits;
2326         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2327         return 1;
2328 }
2329
2330 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2331 {
2332         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2333         return 0;
2334 }
2335
2336 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2337 {
2338         unsigned long exit_qualification;
2339         int size, down, in, string, rep;
2340         unsigned port;
2341
2342         ++vcpu->stat.io_exits;
2343         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2344         string = (exit_qualification & 16) != 0;
2345
2346         if (string) {
2347                 if (emulate_instruction(vcpu,
2348                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2349                         return 0;
2350                 return 1;
2351         }
2352
2353         size = (exit_qualification & 7) + 1;
2354         in = (exit_qualification & 8) != 0;
2355         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2356         rep = (exit_qualification & 32) != 0;
2357         port = exit_qualification >> 16;
2358
2359         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2360 }
2361
2362 static void
2363 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2364 {
2365         /*
2366          * Patch in the VMCALL instruction:
2367          */
2368         hypercall[0] = 0x0f;
2369         hypercall[1] = 0x01;
2370         hypercall[2] = 0xc1;
2371 }
2372
2373 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2374 {
2375         unsigned long exit_qualification;
2376         int cr;
2377         int reg;
2378
2379         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2380         cr = exit_qualification & 15;
2381         reg = (exit_qualification >> 8) & 15;
2382         switch ((exit_qualification >> 4) & 3) {
2383         case 0: /* mov to cr */
2384                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2385                             (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
2386                 switch (cr) {
2387                 case 0:
2388                         vcpu_load_rsp_rip(vcpu);
2389                         kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2390                         skip_emulated_instruction(vcpu);
2391                         return 1;
2392                 case 3:
2393                         vcpu_load_rsp_rip(vcpu);
2394                         kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2395                         skip_emulated_instruction(vcpu);
2396                         return 1;
2397                 case 4:
2398                         vcpu_load_rsp_rip(vcpu);
2399                         kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2400                         skip_emulated_instruction(vcpu);
2401                         return 1;
2402                 case 8:
2403                         vcpu_load_rsp_rip(vcpu);
2404                         kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2405                         skip_emulated_instruction(vcpu);
2406                         if (irqchip_in_kernel(vcpu->kvm))
2407                                 return 1;
2408                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2409                         return 0;
2410                 };
2411                 break;
2412         case 2: /* clts */
2413                 vcpu_load_rsp_rip(vcpu);
2414                 vmx_fpu_deactivate(vcpu);
2415                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2416                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2417                 vmx_fpu_activate(vcpu);
2418                 KVMTRACE_0D(CLTS, vcpu, handler);
2419                 skip_emulated_instruction(vcpu);
2420                 return 1;
2421         case 1: /*mov from cr*/
2422                 switch (cr) {
2423                 case 3:
2424                         vcpu_load_rsp_rip(vcpu);
2425                         vcpu->arch.regs[reg] = vcpu->arch.cr3;
2426                         vcpu_put_rsp_rip(vcpu);
2427                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2428                                     (u32)vcpu->arch.regs[reg],
2429                                     (u32)((u64)vcpu->arch.regs[reg] >> 32),
2430                                     handler);
2431                         skip_emulated_instruction(vcpu);
2432                         return 1;
2433                 case 8:
2434                         vcpu_load_rsp_rip(vcpu);
2435                         vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2436                         vcpu_put_rsp_rip(vcpu);
2437                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2438                                     (u32)vcpu->arch.regs[reg], handler);
2439                         skip_emulated_instruction(vcpu);
2440                         return 1;
2441                 }
2442                 break;
2443         case 3: /* lmsw */
2444                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2445
2446                 skip_emulated_instruction(vcpu);
2447                 return 1;
2448         default:
2449                 break;
2450         }
2451         kvm_run->exit_reason = 0;
2452         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2453                (int)(exit_qualification >> 4) & 3, cr);
2454         return 0;
2455 }
2456
2457 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2458 {
2459         unsigned long exit_qualification;
2460         unsigned long val;
2461         int dr, reg;
2462
2463         /*
2464          * FIXME: this code assumes the host is debugging the guest.
2465          *        need to deal with guest debugging itself too.
2466          */
2467         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2468         dr = exit_qualification & 7;
2469         reg = (exit_qualification >> 8) & 15;
2470         vcpu_load_rsp_rip(vcpu);
2471         if (exit_qualification & 16) {
2472                 /* mov from dr */
2473                 switch (dr) {
2474                 case 6:
2475                         val = 0xffff0ff0;
2476                         break;
2477                 case 7:
2478                         val = 0x400;
2479                         break;
2480                 default:
2481                         val = 0;
2482                 }
2483                 vcpu->arch.regs[reg] = val;
2484                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2485         } else {
2486                 /* mov to dr */
2487         }
2488         vcpu_put_rsp_rip(vcpu);
2489         skip_emulated_instruction(vcpu);
2490         return 1;
2491 }
2492
2493 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2494 {
2495         kvm_emulate_cpuid(vcpu);
2496         return 1;
2497 }
2498
2499 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2500 {
2501         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2502         u64 data;
2503
2504         if (vmx_get_msr(vcpu, ecx, &data)) {
2505                 kvm_inject_gp(vcpu, 0);
2506                 return 1;
2507         }
2508
2509         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2510                     handler);
2511
2512         /* FIXME: handling of bits 32:63 of rax, rdx */
2513         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2514         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2515         skip_emulated_instruction(vcpu);
2516         return 1;
2517 }
2518
2519 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2520 {
2521         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2522         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2523                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2524
2525         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2526                     handler);
2527
2528         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2529                 kvm_inject_gp(vcpu, 0);
2530                 return 1;
2531         }
2532
2533         skip_emulated_instruction(vcpu);
2534         return 1;
2535 }
2536
2537 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2538                                       struct kvm_run *kvm_run)
2539 {
2540         return 1;
2541 }
2542
2543 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2544                                    struct kvm_run *kvm_run)
2545 {
2546         u32 cpu_based_vm_exec_control;
2547
2548         /* clear pending irq */
2549         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2550         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2551         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2552
2553         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2554
2555         /*
2556          * If the user space waits to inject interrupts, exit as soon as
2557          * possible
2558          */
2559         if (kvm_run->request_interrupt_window &&
2560             !vcpu->arch.irq_summary) {
2561                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2562                 ++vcpu->stat.irq_window_exits;
2563                 return 0;
2564         }
2565         return 1;
2566 }
2567
2568 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2569 {
2570         skip_emulated_instruction(vcpu);
2571         return kvm_emulate_halt(vcpu);
2572 }
2573
2574 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2575 {
2576         skip_emulated_instruction(vcpu);
2577         kvm_emulate_hypercall(vcpu);
2578         return 1;
2579 }
2580
2581 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2582 {
2583         skip_emulated_instruction(vcpu);
2584         /* TODO: Add support for VT-d/pass-through device */
2585         return 1;
2586 }
2587
2588 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2589 {
2590         u64 exit_qualification;
2591         enum emulation_result er;
2592         unsigned long offset;
2593
2594         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2595         offset = exit_qualification & 0xffful;
2596
2597         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2598
2599         if (er !=  EMULATE_DONE) {
2600                 printk(KERN_ERR
2601                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2602                        offset);
2603                 return -ENOTSUPP;
2604         }
2605         return 1;
2606 }
2607
2608 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2609 {
2610         unsigned long exit_qualification;
2611         u16 tss_selector;
2612         int reason;
2613
2614         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2615
2616         reason = (u32)exit_qualification >> 30;
2617         tss_selector = exit_qualification;
2618
2619         return kvm_task_switch(vcpu, tss_selector, reason);
2620 }
2621
2622 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2623 {
2624         u64 exit_qualification;
2625         enum emulation_result er;
2626         gpa_t gpa;
2627         unsigned long hva;
2628         int gla_validity;
2629         int r;
2630
2631         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2632
2633         if (exit_qualification & (1 << 6)) {
2634                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2635                 return -ENOTSUPP;
2636         }
2637
2638         gla_validity = (exit_qualification >> 7) & 0x3;
2639         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2640                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2641                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2642                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2643                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2644                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2645                         (long unsigned int)exit_qualification);
2646                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2647                 kvm_run->hw.hardware_exit_reason = 0;
2648                 return -ENOTSUPP;
2649         }
2650
2651         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2652         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2653         if (!kvm_is_error_hva(hva)) {
2654                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2655                 if (r < 0) {
2656                         printk(KERN_ERR "EPT: Not enough memory!\n");
2657                         return -ENOMEM;
2658                 }
2659                 return 1;
2660         } else {
2661                 /* must be MMIO */
2662                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2663
2664                 if (er == EMULATE_FAIL) {
2665                         printk(KERN_ERR
2666                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2667                          er);
2668                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2669                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2670                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2671                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2672                                 (long unsigned int)exit_qualification);
2673                         return -ENOTSUPP;
2674                 } else if (er == EMULATE_DO_MMIO)
2675                         return 0;
2676         }
2677         return 1;
2678 }
2679
2680 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2681 {
2682         u32 cpu_based_vm_exec_control;
2683
2684         /* clear pending NMI */
2685         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2686         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2687         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2688         ++vcpu->stat.nmi_window_exits;
2689
2690         return 1;
2691 }
2692
2693 /*
2694  * The exit handlers return 1 if the exit was handled fully and guest execution
2695  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2696  * to be done to userspace and return 0.
2697  */
2698 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2699                                       struct kvm_run *kvm_run) = {
2700         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2701         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2702         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2703         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
2704         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2705         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2706         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2707         [EXIT_REASON_CPUID]                   = handle_cpuid,
2708         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2709         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2710         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2711         [EXIT_REASON_HLT]                     = handle_halt,
2712         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2713         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2714         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2715         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2716         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
2717         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
2718 };
2719
2720 static const int kvm_vmx_max_exit_handlers =
2721         ARRAY_SIZE(kvm_vmx_exit_handlers);
2722
2723 /*
2724  * The guest has exited.  See if we can fix it or if we need userspace
2725  * assistance.
2726  */
2727 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2728 {
2729         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2730         struct vcpu_vmx *vmx = to_vmx(vcpu);
2731         u32 vectoring_info = vmx->idt_vectoring_info;
2732
2733         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2734                     (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2735
2736         /* Access CR3 don't cause VMExit in paging mode, so we need
2737          * to sync with guest real CR3. */
2738         if (vm_need_ept() && is_paging(vcpu)) {
2739                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2740                 ept_load_pdptrs(vcpu);
2741         }
2742
2743         if (unlikely(vmx->fail)) {
2744                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2745                 kvm_run->fail_entry.hardware_entry_failure_reason
2746                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2747                 return 0;
2748         }
2749
2750         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2751                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2752                         exit_reason != EXIT_REASON_EPT_VIOLATION))
2753                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2754                        "exit reason is 0x%x\n", __func__, exit_reason);
2755         if (exit_reason < kvm_vmx_max_exit_handlers
2756             && kvm_vmx_exit_handlers[exit_reason])
2757                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2758         else {
2759                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2760                 kvm_run->hw.hardware_exit_reason = exit_reason;
2761         }
2762         return 0;
2763 }
2764
2765 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2766 {
2767         int max_irr, tpr;
2768
2769         if (!vm_need_tpr_shadow(vcpu->kvm))
2770                 return;
2771
2772         if (!kvm_lapic_enabled(vcpu) ||
2773             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2774                 vmcs_write32(TPR_THRESHOLD, 0);
2775                 return;
2776         }
2777
2778         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2779         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2780 }
2781
2782 static void enable_irq_window(struct kvm_vcpu *vcpu)
2783 {
2784         u32 cpu_based_vm_exec_control;
2785
2786         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2787         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2788         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2789 }
2790
2791 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2792 {
2793         u32 cpu_based_vm_exec_control;
2794
2795         if (!cpu_has_virtual_nmis())
2796                 return;
2797
2798         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2799         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2800         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2801 }
2802
2803 static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
2804 {
2805         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2806         return !(guest_intr & (GUEST_INTR_STATE_NMI |
2807                                GUEST_INTR_STATE_MOV_SS |
2808                                GUEST_INTR_STATE_STI));
2809 }
2810
2811 static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
2812 {
2813         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2814         return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
2815                                GUEST_INTR_STATE_STI)) &&
2816                 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2817 }
2818
2819 static void enable_intr_window(struct kvm_vcpu *vcpu)
2820 {
2821         if (vcpu->arch.nmi_pending)
2822                 enable_nmi_window(vcpu);
2823         else if (kvm_cpu_has_interrupt(vcpu))
2824                 enable_irq_window(vcpu);
2825 }
2826
2827 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2828 {
2829         struct vcpu_vmx *vmx = to_vmx(vcpu);
2830         u32 idtv_info_field, intr_info_field, exit_intr_info_field;
2831         int vector;
2832
2833         update_tpr_threshold(vcpu);
2834
2835         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2836         exit_intr_info_field = vmcs_read32(VM_EXIT_INTR_INFO);
2837         idtv_info_field = vmx->idt_vectoring_info;
2838         if (intr_info_field & INTR_INFO_VALID_MASK) {
2839                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2840                         /* TODO: fault when IDT_Vectoring */
2841                         if (printk_ratelimit())
2842                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2843                 }
2844                 enable_intr_window(vcpu);
2845                 return;
2846         }
2847         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2848                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2849                     == INTR_TYPE_EXT_INTR
2850                     && vcpu->arch.rmode.active) {
2851                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2852
2853                         vmx_inject_irq(vcpu, vect);
2854                         enable_intr_window(vcpu);
2855                         return;
2856                 }
2857
2858                 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2859
2860                 /*
2861                  * SDM 3: 25.7.1.2
2862                  * Clear bit "block by NMI" before VM entry if a NMI delivery
2863                  * faulted.
2864                  */
2865                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2866                     == INTR_TYPE_NMI_INTR && cpu_has_virtual_nmis())
2867                         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2868                                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2869                                 ~GUEST_INTR_STATE_NMI);
2870
2871                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field
2872                                 & ~INTR_INFO_RESVD_BITS_MASK);
2873                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2874                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2875
2876                 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2877                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2878                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2879                 enable_intr_window(vcpu);
2880                 return;
2881         }
2882         if (cpu_has_virtual_nmis()) {
2883                 /*
2884                  * SDM 3: 25.7.1.2
2885                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
2886                  * a guest IRET fault.
2887                  */
2888                 if ((exit_intr_info_field & INTR_INFO_UNBLOCK_NMI) &&
2889                     (exit_intr_info_field & INTR_INFO_VECTOR_MASK) != 8)
2890                         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2891                                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) |
2892                                 GUEST_INTR_STATE_NMI);
2893                 else if (vcpu->arch.nmi_pending) {
2894                         if (vmx_nmi_enabled(vcpu))
2895                                 vmx_inject_nmi(vcpu);
2896                         enable_intr_window(vcpu);
2897                         return;
2898                 }
2899
2900         }
2901         if (!kvm_cpu_has_interrupt(vcpu))
2902                 return;
2903         if (vmx_irq_enabled(vcpu)) {
2904                 vector = kvm_cpu_get_interrupt(vcpu);
2905                 vmx_inject_irq(vcpu, vector);
2906                 kvm_timer_intr_post(vcpu, vector);
2907         } else
2908                 enable_irq_window(vcpu);
2909 }
2910
2911 /*
2912  * Failure to inject an interrupt should give us the information
2913  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2914  * when fetching the interrupt redirection bitmap in the real-mode
2915  * tss, this doesn't happen.  So we do it ourselves.
2916  */
2917 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2918 {
2919         vmx->rmode.irq.pending = 0;
2920         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2921                 return;
2922         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2923         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2924                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2925                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2926                 return;
2927         }
2928         vmx->idt_vectoring_info =
2929                 VECTORING_INFO_VALID_MASK
2930                 | INTR_TYPE_EXT_INTR
2931                 | vmx->rmode.irq.vector;
2932 }
2933
2934 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2935 {
2936         struct vcpu_vmx *vmx = to_vmx(vcpu);
2937         u32 intr_info;
2938
2939         /*
2940          * Loading guest fpu may have cleared host cr0.ts
2941          */
2942         vmcs_writel(HOST_CR0, read_cr0());
2943
2944         asm(
2945                 /* Store host registers */
2946 #ifdef CONFIG_X86_64
2947                 "push %%rdx; push %%rbp;"
2948                 "push %%rcx \n\t"
2949 #else
2950                 "push %%edx; push %%ebp;"
2951                 "push %%ecx \n\t"
2952 #endif
2953                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
2954                 /* Check if vmlaunch of vmresume is needed */
2955                 "cmpl $0, %c[launched](%0) \n\t"
2956                 /* Load guest registers.  Don't clobber flags. */
2957 #ifdef CONFIG_X86_64
2958                 "mov %c[cr2](%0), %%rax \n\t"
2959                 "mov %%rax, %%cr2 \n\t"
2960                 "mov %c[rax](%0), %%rax \n\t"
2961                 "mov %c[rbx](%0), %%rbx \n\t"
2962                 "mov %c[rdx](%0), %%rdx \n\t"
2963                 "mov %c[rsi](%0), %%rsi \n\t"
2964                 "mov %c[rdi](%0), %%rdi \n\t"
2965                 "mov %c[rbp](%0), %%rbp \n\t"
2966                 "mov %c[r8](%0),  %%r8  \n\t"
2967                 "mov %c[r9](%0),  %%r9  \n\t"
2968                 "mov %c[r10](%0), %%r10 \n\t"
2969                 "mov %c[r11](%0), %%r11 \n\t"
2970                 "mov %c[r12](%0), %%r12 \n\t"
2971                 "mov %c[r13](%0), %%r13 \n\t"
2972                 "mov %c[r14](%0), %%r14 \n\t"
2973                 "mov %c[r15](%0), %%r15 \n\t"
2974                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2975 #else
2976                 "mov %c[cr2](%0), %%eax \n\t"
2977                 "mov %%eax,   %%cr2 \n\t"
2978                 "mov %c[rax](%0), %%eax \n\t"
2979                 "mov %c[rbx](%0), %%ebx \n\t"
2980                 "mov %c[rdx](%0), %%edx \n\t"
2981                 "mov %c[rsi](%0), %%esi \n\t"
2982                 "mov %c[rdi](%0), %%edi \n\t"
2983                 "mov %c[rbp](%0), %%ebp \n\t"
2984                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2985 #endif
2986                 /* Enter guest mode */
2987                 "jne .Llaunched \n\t"
2988                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
2989                 "jmp .Lkvm_vmx_return \n\t"
2990                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
2991                 ".Lkvm_vmx_return: "
2992                 /* Save guest registers, load host registers, keep flags */
2993 #ifdef CONFIG_X86_64
2994                 "xchg %0,     (%%rsp) \n\t"
2995                 "mov %%rax, %c[rax](%0) \n\t"
2996                 "mov %%rbx, %c[rbx](%0) \n\t"
2997                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2998                 "mov %%rdx, %c[rdx](%0) \n\t"
2999                 "mov %%rsi, %c[rsi](%0) \n\t"
3000                 "mov %%rdi, %c[rdi](%0) \n\t"
3001                 "mov %%rbp, %c[rbp](%0) \n\t"
3002                 "mov %%r8,  %c[r8](%0) \n\t"
3003                 "mov %%r9,  %c[r9](%0) \n\t"
3004                 "mov %%r10, %c[r10](%0) \n\t"
3005                 "mov %%r11, %c[r11](%0) \n\t"
3006                 "mov %%r12, %c[r12](%0) \n\t"
3007                 "mov %%r13, %c[r13](%0) \n\t"
3008                 "mov %%r14, %c[r14](%0) \n\t"
3009                 "mov %%r15, %c[r15](%0) \n\t"
3010                 "mov %%cr2, %%rax   \n\t"
3011                 "mov %%rax, %c[cr2](%0) \n\t"
3012
3013                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
3014 #else
3015                 "xchg %0, (%%esp) \n\t"
3016                 "mov %%eax, %c[rax](%0) \n\t"
3017                 "mov %%ebx, %c[rbx](%0) \n\t"
3018                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
3019                 "mov %%edx, %c[rdx](%0) \n\t"
3020                 "mov %%esi, %c[rsi](%0) \n\t"
3021                 "mov %%edi, %c[rdi](%0) \n\t"
3022                 "mov %%ebp, %c[rbp](%0) \n\t"
3023                 "mov %%cr2, %%eax  \n\t"
3024                 "mov %%eax, %c[cr2](%0) \n\t"
3025
3026                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
3027 #endif
3028                 "setbe %c[fail](%0) \n\t"
3029               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3030                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3031                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3032                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3033                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3034                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3035                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3036                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3037                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3038                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3039 #ifdef CONFIG_X86_64
3040                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3041                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3042                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3043                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3044                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3045                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3046                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3047                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3048 #endif
3049                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3050               : "cc", "memory"
3051 #ifdef CONFIG_X86_64
3052                 , "rbx", "rdi", "rsi"
3053                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3054 #else
3055                 , "ebx", "edi", "rsi"
3056 #endif
3057               );
3058
3059         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3060         if (vmx->rmode.irq.pending)
3061                 fixup_rmode_irq(vmx);
3062
3063         vcpu->arch.interrupt_window_open =
3064                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3065                  (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
3066
3067         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3068         vmx->launched = 1;
3069
3070         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3071
3072         /* We need to handle NMIs before interrupts are enabled */
3073         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3074             (intr_info & INTR_INFO_VALID_MASK)) {
3075                 KVMTRACE_0D(NMI, vcpu, handler);
3076                 asm("int $2");
3077         }
3078 }
3079
3080 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3081 {
3082         struct vcpu_vmx *vmx = to_vmx(vcpu);
3083
3084         if (vmx->vmcs) {
3085                 vcpu_clear(vmx);
3086                 free_vmcs(vmx->vmcs);
3087                 vmx->vmcs = NULL;
3088         }
3089 }
3090
3091 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3092 {
3093         struct vcpu_vmx *vmx = to_vmx(vcpu);
3094
3095         spin_lock(&vmx_vpid_lock);
3096         if (vmx->vpid != 0)
3097                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3098         spin_unlock(&vmx_vpid_lock);
3099         vmx_free_vmcs(vcpu);
3100         kfree(vmx->host_msrs);
3101         kfree(vmx->guest_msrs);
3102         kvm_vcpu_uninit(vcpu);
3103         kmem_cache_free(kvm_vcpu_cache, vmx);
3104 }
3105
3106 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3107 {
3108         int err;
3109         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3110         int cpu;
3111
3112         if (!vmx)
3113                 return ERR_PTR(-ENOMEM);
3114
3115         allocate_vpid(vmx);
3116         if (id == 0 && vm_need_ept()) {
3117                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3118                         VMX_EPT_WRITABLE_MASK |
3119                         VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3120                 kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
3121                                 VMX_EPT_FAKE_DIRTY_MASK, 0ull,
3122                                 VMX_EPT_EXECUTABLE_MASK);
3123                 kvm_enable_tdp();
3124         }
3125
3126         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3127         if (err)
3128                 goto free_vcpu;
3129
3130         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3131         if (!vmx->guest_msrs) {
3132                 err = -ENOMEM;
3133                 goto uninit_vcpu;
3134         }
3135
3136         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3137         if (!vmx->host_msrs)
3138                 goto free_guest_msrs;
3139
3140         vmx->vmcs = alloc_vmcs();
3141         if (!vmx->vmcs)
3142                 goto free_msrs;
3143
3144         vmcs_clear(vmx->vmcs);
3145
3146         cpu = get_cpu();
3147         vmx_vcpu_load(&vmx->vcpu, cpu);
3148         err = vmx_vcpu_setup(vmx);
3149         vmx_vcpu_put(&vmx->vcpu);
3150         put_cpu();
3151         if (err)
3152                 goto free_vmcs;
3153         if (vm_need_virtualize_apic_accesses(kvm))
3154                 if (alloc_apic_access_page(kvm) != 0)
3155                         goto free_vmcs;
3156
3157         if (vm_need_ept())
3158                 if (alloc_identity_pagetable(kvm) != 0)
3159                         goto free_vmcs;
3160
3161         return &vmx->vcpu;
3162
3163 free_vmcs:
3164         free_vmcs(vmx->vmcs);
3165 free_msrs:
3166         kfree(vmx->host_msrs);
3167 free_guest_msrs:
3168         kfree(vmx->guest_msrs);
3169 uninit_vcpu:
3170         kvm_vcpu_uninit(&vmx->vcpu);
3171 free_vcpu:
3172         kmem_cache_free(kvm_vcpu_cache, vmx);
3173         return ERR_PTR(err);
3174 }
3175
3176 static void __init vmx_check_processor_compat(void *rtn)
3177 {
3178         struct vmcs_config vmcs_conf;
3179
3180         *(int *)rtn = 0;
3181         if (setup_vmcs_config(&vmcs_conf) < 0)
3182                 *(int *)rtn = -EIO;
3183         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3184                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3185                                 smp_processor_id());
3186                 *(int *)rtn = -EIO;
3187         }
3188 }
3189
3190 static int get_ept_level(void)
3191 {
3192         return VMX_EPT_DEFAULT_GAW + 1;
3193 }
3194
3195 static struct kvm_x86_ops vmx_x86_ops = {
3196         .cpu_has_kvm_support = cpu_has_kvm_support,
3197         .disabled_by_bios = vmx_disabled_by_bios,
3198         .hardware_setup = hardware_setup,
3199         .hardware_unsetup = hardware_unsetup,
3200         .check_processor_compatibility = vmx_check_processor_compat,
3201         .hardware_enable = hardware_enable,
3202         .hardware_disable = hardware_disable,
3203         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3204
3205         .vcpu_create = vmx_create_vcpu,
3206         .vcpu_free = vmx_free_vcpu,
3207         .vcpu_reset = vmx_vcpu_reset,
3208
3209         .prepare_guest_switch = vmx_save_host_state,
3210         .vcpu_load = vmx_vcpu_load,
3211         .vcpu_put = vmx_vcpu_put,
3212
3213         .set_guest_debug = set_guest_debug,
3214         .guest_debug_pre = kvm_guest_debug_pre,
3215         .get_msr = vmx_get_msr,
3216         .set_msr = vmx_set_msr,
3217         .get_segment_base = vmx_get_segment_base,
3218         .get_segment = vmx_get_segment,
3219         .set_segment = vmx_set_segment,
3220         .get_cpl = vmx_get_cpl,
3221         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3222         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3223         .set_cr0 = vmx_set_cr0,
3224         .set_cr3 = vmx_set_cr3,
3225         .set_cr4 = vmx_set_cr4,
3226         .set_efer = vmx_set_efer,
3227         .get_idt = vmx_get_idt,
3228         .set_idt = vmx_set_idt,
3229         .get_gdt = vmx_get_gdt,
3230         .set_gdt = vmx_set_gdt,
3231         .cache_regs = vcpu_load_rsp_rip,
3232         .decache_regs = vcpu_put_rsp_rip,
3233         .get_rflags = vmx_get_rflags,
3234         .set_rflags = vmx_set_rflags,
3235
3236         .tlb_flush = vmx_flush_tlb,
3237
3238         .run = vmx_vcpu_run,
3239         .handle_exit = kvm_handle_exit,
3240         .skip_emulated_instruction = skip_emulated_instruction,
3241         .patch_hypercall = vmx_patch_hypercall,
3242         .get_irq = vmx_get_irq,
3243         .set_irq = vmx_inject_irq,
3244         .queue_exception = vmx_queue_exception,
3245         .exception_injected = vmx_exception_injected,
3246         .inject_pending_irq = vmx_intr_assist,
3247         .inject_pending_vectors = do_interrupt_requests,
3248
3249         .set_tss_addr = vmx_set_tss_addr,
3250         .get_tdp_level = get_ept_level,
3251 };
3252
3253 static int __init vmx_init(void)
3254 {
3255         void *va;
3256         int r;
3257
3258         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3259         if (!vmx_io_bitmap_a)
3260                 return -ENOMEM;
3261
3262         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3263         if (!vmx_io_bitmap_b) {
3264                 r = -ENOMEM;
3265                 goto out;
3266         }
3267
3268         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3269         if (!vmx_msr_bitmap) {
3270                 r = -ENOMEM;
3271                 goto out1;
3272         }
3273
3274         /*
3275          * Allow direct access to the PC debug port (it is often used for I/O
3276          * delays, but the vmexits simply slow things down).
3277          */
3278         va = kmap(vmx_io_bitmap_a);
3279         memset(va, 0xff, PAGE_SIZE);
3280         clear_bit(0x80, va);
3281         kunmap(vmx_io_bitmap_a);
3282
3283         va = kmap(vmx_io_bitmap_b);
3284         memset(va, 0xff, PAGE_SIZE);
3285         kunmap(vmx_io_bitmap_b);
3286
3287         va = kmap(vmx_msr_bitmap);
3288         memset(va, 0xff, PAGE_SIZE);
3289         kunmap(vmx_msr_bitmap);
3290
3291         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3292
3293         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3294         if (r)
3295                 goto out2;
3296
3297         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3298         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3299         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3300         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3301         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3302
3303         if (cpu_has_vmx_ept())
3304                 bypass_guest_pf = 0;
3305
3306         if (bypass_guest_pf)
3307                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3308
3309         ept_sync_global();
3310
3311         return 0;
3312
3313 out2:
3314         __free_page(vmx_msr_bitmap);
3315 out1:
3316         __free_page(vmx_io_bitmap_b);
3317 out:
3318         __free_page(vmx_io_bitmap_a);
3319         return r;
3320 }
3321
3322 static void __exit vmx_exit(void)
3323 {
3324         __free_page(vmx_msr_bitmap);
3325         __free_page(vmx_io_bitmap_b);
3326         __free_page(vmx_io_bitmap_a);
3327
3328         kvm_exit();
3329 }
3330
3331 module_init(vmx_init)
3332 module_exit(vmx_exit)