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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "vmx.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include "kvm_cache_regs.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 static int bypass_guest_pf = 1;
  40 module_param(bypass_guest_pf, bool, 0);
  41
  42 static int enable_vpid = 1;
  43 module_param(enable_vpid, bool, 0);
  44
  45 static int flexpriority_enabled = 1;
  46 module_param(flexpriority_enabled, bool, 0);
  47
  48 static int enable_ept = 1;
  49 module_param(enable_ept, bool, 0);
  50
  51 struct vmcs {
  52         u32 revision_id;
  53         u32 abort;
  54         char data[0];
  55 };
  56
  57 struct vcpu_vmx {
  58         struct kvm_vcpu       vcpu;
  59         struct list_head      local_vcpus_link;
  60         int                   launched;
  61         u8                    fail;
  62         u32                   idt_vectoring_info;
  63         struct kvm_msr_entry *guest_msrs;
  64         struct kvm_msr_entry *host_msrs;
  65         int                   nmsrs;
  66         int                   save_nmsrs;
  67         int                   msr_offset_efer;
  68 #ifdef CONFIG_X86_64
  69         int                   msr_offset_kernel_gs_base;
  70 #endif
  71         struct vmcs          *vmcs;
  72         struct {
  73                 int           loaded;
  74                 u16           fs_sel, gs_sel, ldt_sel;
  75                 int           gs_ldt_reload_needed;
  76                 int           fs_reload_needed;
  77                 int           guest_efer_loaded;
  78         } host_state;
  79         struct {
  80                 struct {
  81                         bool pending;
  82                         u8 vector;
  83                         unsigned rip;
  84                 } irq;
  85         } rmode;
  86         int vpid;
  87 };
  88
  89 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  90 {
  91         return container_of(vcpu, struct vcpu_vmx, vcpu);
  92 }
  93
  94 static int init_rmode(struct kvm *kvm);
  95 static u64 construct_eptp(unsigned long root_hpa);
  96
  97 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  98 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  99 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 100
 101 static struct page *vmx_io_bitmap_a;
 102 static struct page *vmx_io_bitmap_b;
 103 static struct page *vmx_msr_bitmap;
 104
 105 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 106 static DEFINE_SPINLOCK(vmx_vpid_lock);
 107
 108 static struct vmcs_config {
 109         int size;
 110         int order;
 111         u32 revision_id;
 112         u32 pin_based_exec_ctrl;
 113         u32 cpu_based_exec_ctrl;
 114         u32 cpu_based_2nd_exec_ctrl;
 115         u32 vmexit_ctrl;
 116         u32 vmentry_ctrl;
 117 } vmcs_config;
 118
 119 struct vmx_capability {
 120         u32 ept;
 121         u32 vpid;
 122 } vmx_capability;
 123
 124 #define VMX_SEGMENT_FIELD(seg)                                  \
 125         [VCPU_SREG_##seg] = {                                   \
 126                 .selector = GUEST_##seg##_SELECTOR,             \
 127                 .base = GUEST_##seg##_BASE,                     \
 128                 .limit = GUEST_##seg##_LIMIT,                   \
 129                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 130         }
 131
 132 static struct kvm_vmx_segment_field {
 133         unsigned selector;
 134         unsigned base;
 135         unsigned limit;
 136         unsigned ar_bytes;
 137 } kvm_vmx_segment_fields[] = {
 138         VMX_SEGMENT_FIELD(CS),
 139         VMX_SEGMENT_FIELD(DS),
 140         VMX_SEGMENT_FIELD(ES),
 141         VMX_SEGMENT_FIELD(FS),
 142         VMX_SEGMENT_FIELD(GS),
 143         VMX_SEGMENT_FIELD(SS),
 144         VMX_SEGMENT_FIELD(TR),
 145         VMX_SEGMENT_FIELD(LDTR),
 146 };
 147
 148 /*
 149  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 150  * away by decrementing the array size.
 151  */
 152 static const u32 vmx_msr_index[] = {
 153 #ifdef CONFIG_X86_64
 154         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 155 #endif
 156         MSR_EFER, MSR_K6_STAR,
 157 };
 158 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 159
 160 static void load_msrs(struct kvm_msr_entry *e, int n)
 161 {
 162         int i;
 163
 164         for (i = 0; i < n; ++i)
 165                 wrmsrl(e[i].index, e[i].data);
 166 }
 167
 168 static void save_msrs(struct kvm_msr_entry *e, int n)
 169 {
 170         int i;
 171
 172         for (i = 0; i < n; ++i)
 173                 rdmsrl(e[i].index, e[i].data);
 174 }
 175
 176 static inline int is_page_fault(u32 intr_info)
 177 {
 178         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 179                              INTR_INFO_VALID_MASK)) ==
 180                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 181 }
 182
 183 static inline int is_no_device(u32 intr_info)
 184 {
 185         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 186                              INTR_INFO_VALID_MASK)) ==
 187                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 188 }
 189
 190 static inline int is_invalid_opcode(u32 intr_info)
 191 {
 192         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 193                              INTR_INFO_VALID_MASK)) ==
 194                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 195 }
 196
 197 static inline int is_external_interrupt(u32 intr_info)
 198 {
 199         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 200                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 201 }
 202
 203 static inline int cpu_has_vmx_msr_bitmap(void)
 204 {
 205         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 206 }
 207
 208 static inline int cpu_has_vmx_tpr_shadow(void)
 209 {
 210         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 211 }
 212
 213 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 214 {
 215         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 216 }
 217
 218 static inline int cpu_has_secondary_exec_ctrls(void)
 219 {
 220         return (vmcs_config.cpu_based_exec_ctrl &
 221                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 222 }
 223
 224 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 225 {
 226         return flexpriority_enabled
 227                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 228                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 229 }
 230
 231 static inline int cpu_has_vmx_invept_individual_addr(void)
 232 {
 233         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 234 }
 235
 236 static inline int cpu_has_vmx_invept_context(void)
 237 {
 238         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 239 }
 240
 241 static inline int cpu_has_vmx_invept_global(void)
 242 {
 243         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 244 }
 245
 246 static inline int cpu_has_vmx_ept(void)
 247 {
 248         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 249                 SECONDARY_EXEC_ENABLE_EPT);
 250 }
 251
 252 static inline int vm_need_ept(void)
 253 {
 254         return (cpu_has_vmx_ept() && enable_ept);
 255 }
 256
 257 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 258 {
 259         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 260                 (irqchip_in_kernel(kvm)));
 261 }
 262
 263 static inline int cpu_has_vmx_vpid(void)
 264 {
 265         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 266                 SECONDARY_EXEC_ENABLE_VPID);
 267 }
 268
 269 static inline int cpu_has_virtual_nmis(void)
 270 {
 271         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 272 }
 273
 274 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 275 {
 276         int i;
 277
 278         for (i = 0; i < vmx->nmsrs; ++i)
 279                 if (vmx->guest_msrs[i].index == msr)
 280                         return i;
 281         return -1;
 282 }
 283
 284 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 285 {
 286     struct {
 287         u64 vpid : 16;
 288         u64 rsvd : 48;
 289         u64 gva;
 290     } operand = { vpid, 0, gva };
 291
 292     asm volatile (__ex(ASM_VMX_INVVPID)
 293                   /* CF==1 or ZF==1 --> rc = -1 */
 294                   "; ja 1f ; ud2 ; 1:"
 295                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 296 }
 297
 298 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 299 {
 300         struct {
 301                 u64 eptp, gpa;
 302         } operand = {eptp, gpa};
 303
 304         asm volatile (__ex(ASM_VMX_INVEPT)
 305                         /* CF==1 or ZF==1 --> rc = -1 */
 306                         "; ja 1f ; ud2 ; 1:\n"
 307                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 308 }
 309
 310 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 311 {
 312         int i;
 313
 314         i = __find_msr_index(vmx, msr);
 315         if (i >= 0)
 316                 return &vmx->guest_msrs[i];
 317         return NULL;
 318 }
 319
 320 static void vmcs_clear(struct vmcs *vmcs)
 321 {
 322         u64 phys_addr = __pa(vmcs);
 323         u8 error;
 324
 325         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 326                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 327                       : "cc", "memory");
 328         if (error)
 329                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 330                        vmcs, phys_addr);
 331 }
 332
 333 static void __vcpu_clear(void *arg)
 334 {
 335         struct vcpu_vmx *vmx = arg;
 336         int cpu = raw_smp_processor_id();
 337
 338         if (vmx->vcpu.cpu == cpu)
 339                 vmcs_clear(vmx->vmcs);
 340         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 341                 per_cpu(current_vmcs, cpu) = NULL;
 342         rdtscll(vmx->vcpu.arch.host_tsc);
 343         list_del(&vmx->local_vcpus_link);
 344         vmx->vcpu.cpu = -1;
 345         vmx->launched = 0;
 346 }
 347
 348 static void vcpu_clear(struct vcpu_vmx *vmx)
 349 {
 350         if (vmx->vcpu.cpu == -1)
 351                 return;
 352         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 353 }
 354
 355 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 356 {
 357         if (vmx->vpid == 0)
 358                 return;
 359
 360         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 361 }
 362
 363 static inline void ept_sync_global(void)
 364 {
 365         if (cpu_has_vmx_invept_global())
 366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 367 }
 368
 369 static inline void ept_sync_context(u64 eptp)
 370 {
 371         if (vm_need_ept()) {
 372                 if (cpu_has_vmx_invept_context())
 373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 374                 else
 375                         ept_sync_global();
 376         }
 377 }
 378
 379 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 380 {
 381         if (vm_need_ept()) {
 382                 if (cpu_has_vmx_invept_individual_addr())
 383                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 384                                         eptp, gpa);
 385                 else
 386                         ept_sync_context(eptp);
 387         }
 388 }
 389
 390 static unsigned long vmcs_readl(unsigned long field)
 391 {
 392         unsigned long value;
 393
 394         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 395                       : "=a"(value) : "d"(field) : "cc");
 396         return value;
 397 }
 398
 399 static u16 vmcs_read16(unsigned long field)
 400 {
 401         return vmcs_readl(field);
 402 }
 403
 404 static u32 vmcs_read32(unsigned long field)
 405 {
 406         return vmcs_readl(field);
 407 }
 408
 409 static u64 vmcs_read64(unsigned long field)
 410 {
 411 #ifdef CONFIG_X86_64
 412         return vmcs_readl(field);
 413 #else
 414         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 415 #endif
 416 }
 417
 418 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 419 {
 420         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 421                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 422         dump_stack();
 423 }
 424
 425 static void vmcs_writel(unsigned long field, unsigned long value)
 426 {
 427         u8 error;
 428
 429         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 430                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 431         if (unlikely(error))
 432                 vmwrite_error(field, value);
 433 }
 434
 435 static void vmcs_write16(unsigned long field, u16 value)
 436 {
 437         vmcs_writel(field, value);
 438 }
 439
 440 static void vmcs_write32(unsigned long field, u32 value)
 441 {
 442         vmcs_writel(field, value);
 443 }
 444
 445 static void vmcs_write64(unsigned long field, u64 value)
 446 {
 447         vmcs_writel(field, value);
 448 #ifndef CONFIG_X86_64
 449         asm volatile ("");
 450         vmcs_writel(field+1, value >> 32);
 451 #endif
 452 }
 453
 454 static void vmcs_clear_bits(unsigned long field, u32 mask)
 455 {
 456         vmcs_writel(field, vmcs_readl(field) & ~mask);
 457 }
 458
 459 static void vmcs_set_bits(unsigned long field, u32 mask)
 460 {
 461         vmcs_writel(field, vmcs_readl(field) | mask);
 462 }
 463
 464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 465 {
 466         u32 eb;
 467
 468         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 469         if (!vcpu->fpu_active)
 470                 eb |= 1u << NM_VECTOR;
 471         if (vcpu->guest_debug.enabled)
 472                 eb |= 1u << 1;
 473         if (vcpu->arch.rmode.active)
 474                 eb = ~0;
 475         if (vm_need_ept())
 476                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 477         vmcs_write32(EXCEPTION_BITMAP, eb);
 478 }
 479
 480 static void reload_tss(void)
 481 {
 482         /*
 483          * VT restores TR but not its size.  Useless.
 484          */
 485         struct descriptor_table gdt;
 486         struct desc_struct *descs;
 487
 488         kvm_get_gdt(&gdt);
 489         descs = (void *)gdt.base;
 490         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 491         load_TR_desc();
 492 }
 493
 494 static void load_transition_efer(struct vcpu_vmx *vmx)
 495 {
 496         int efer_offset = vmx->msr_offset_efer;
 497         u64 host_efer = vmx->host_msrs[efer_offset].data;
 498         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 499         u64 ignore_bits;
 500
 501         if (efer_offset < 0)
 502                 return;
 503         /*
 504          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 505          * outside long mode
 506          */
 507         ignore_bits = EFER_NX | EFER_SCE;
 508 #ifdef CONFIG_X86_64
 509         ignore_bits |= EFER_LMA | EFER_LME;
 510         /* SCE is meaningful only in long mode on Intel */
 511         if (guest_efer & EFER_LMA)
 512                 ignore_bits &= ~(u64)EFER_SCE;
 513 #endif
 514         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 515                 return;
 516
 517         vmx->host_state.guest_efer_loaded = 1;
 518         guest_efer &= ~ignore_bits;
 519         guest_efer |= host_efer & ignore_bits;
 520         wrmsrl(MSR_EFER, guest_efer);
 521         vmx->vcpu.stat.efer_reload++;
 522 }
 523
 524 static void reload_host_efer(struct vcpu_vmx *vmx)
 525 {
 526         if (vmx->host_state.guest_efer_loaded) {
 527                 vmx->host_state.guest_efer_loaded = 0;
 528                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 529         }
 530 }
 531
 532 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 533 {
 534         struct vcpu_vmx *vmx = to_vmx(vcpu);
 535
 536         if (vmx->host_state.loaded)
 537                 return;
 538
 539         vmx->host_state.loaded = 1;
 540         /*
 541          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 542          * allow segment selectors with cpl > 0 or ti == 1.
 543          */
 544         vmx->host_state.ldt_sel = kvm_read_ldt();
 545         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 546         vmx->host_state.fs_sel = kvm_read_fs();
 547         if (!(vmx->host_state.fs_sel & 7)) {
 548                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 549                 vmx->host_state.fs_reload_needed = 0;
 550         } else {
 551                 vmcs_write16(HOST_FS_SELECTOR, 0);
 552                 vmx->host_state.fs_reload_needed = 1;
 553         }
 554         vmx->host_state.gs_sel = kvm_read_gs();
 555         if (!(vmx->host_state.gs_sel & 7))
 556                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 557         else {
 558                 vmcs_write16(HOST_GS_SELECTOR, 0);
 559                 vmx->host_state.gs_ldt_reload_needed = 1;
 560         }
 561
 562 #ifdef CONFIG_X86_64
 563         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 564         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 565 #else
 566         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 567         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 568 #endif
 569
 570 #ifdef CONFIG_X86_64
 571         if (is_long_mode(&vmx->vcpu))
 572                 save_msrs(vmx->host_msrs +
 573                           vmx->msr_offset_kernel_gs_base, 1);
 574
 575 #endif
 576         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 577         load_transition_efer(vmx);
 578 }
 579
 580 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 581 {
 582         unsigned long flags;
 583
 584         if (!vmx->host_state.loaded)
 585                 return;
 586
 587         ++vmx->vcpu.stat.host_state_reload;
 588         vmx->host_state.loaded = 0;
 589         if (vmx->host_state.fs_reload_needed)
 590                 kvm_load_fs(vmx->host_state.fs_sel);
 591         if (vmx->host_state.gs_ldt_reload_needed) {
 592                 kvm_load_ldt(vmx->host_state.ldt_sel);
 593                 /*
 594                  * If we have to reload gs, we must take care to
 595                  * preserve our gs base.
 596                  */
 597                 local_irq_save(flags);
 598                 kvm_load_gs(vmx->host_state.gs_sel);
 599 #ifdef CONFIG_X86_64
 600                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 601 #endif
 602                 local_irq_restore(flags);
 603         }
 604         reload_tss();
 605         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 606         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 607         reload_host_efer(vmx);
 608 }
 609
 610 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 611 {
 612         preempt_disable();
 613         __vmx_load_host_state(vmx);
 614         preempt_enable();
 615 }
 616
 617 /*
 618  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 619  * vcpu mutex is already taken.
 620  */
 621 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 622 {
 623         struct vcpu_vmx *vmx = to_vmx(vcpu);
 624         u64 phys_addr = __pa(vmx->vmcs);
 625         u64 tsc_this, delta, new_offset;
 626
 627         if (vcpu->cpu != cpu) {
 628                 vcpu_clear(vmx);
 629                 kvm_migrate_timers(vcpu);
 630                 vpid_sync_vcpu_all(vmx);
 631                 local_irq_disable();
 632                 list_add(&vmx->local_vcpus_link,
 633                          &per_cpu(vcpus_on_cpu, cpu));
 634                 local_irq_enable();
 635         }
 636
 637         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 638                 u8 error;
 639
 640                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 641                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 642                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 643                               : "cc");
 644                 if (error)
 645                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 646                                vmx->vmcs, phys_addr);
 647         }
 648
 649         if (vcpu->cpu != cpu) {
 650                 struct descriptor_table dt;
 651                 unsigned long sysenter_esp;
 652
 653                 vcpu->cpu = cpu;
 654                 /*
 655                  * Linux uses per-cpu TSS and GDT, so set these when switching
 656                  * processors.
 657                  */
 658                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 659                 kvm_get_gdt(&dt);
 660                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 661
 662                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 663                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 664
 665                 /*
 666                  * Make sure the time stamp counter is monotonous.
 667                  */
 668                 rdtscll(tsc_this);
 669                 if (tsc_this < vcpu->arch.host_tsc) {
 670                         delta = vcpu->arch.host_tsc - tsc_this;
 671                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 672                         vmcs_write64(TSC_OFFSET, new_offset);
 673                 }
 674         }
 675 }
 676
 677 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 678 {
 679         __vmx_load_host_state(to_vmx(vcpu));
 680 }
 681
 682 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 683 {
 684         if (vcpu->fpu_active)
 685                 return;
 686         vcpu->fpu_active = 1;
 687         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 688         if (vcpu->arch.cr0 & X86_CR0_TS)
 689                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 690         update_exception_bitmap(vcpu);
 691 }
 692
 693 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 694 {
 695         if (!vcpu->fpu_active)
 696                 return;
 697         vcpu->fpu_active = 0;
 698         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 699         update_exception_bitmap(vcpu);
 700 }
 701
 702 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 703 {
 704         return vmcs_readl(GUEST_RFLAGS);
 705 }
 706
 707 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 708 {
 709         if (vcpu->arch.rmode.active)
 710                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 711         vmcs_writel(GUEST_RFLAGS, rflags);
 712 }
 713
 714 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 715 {
 716         unsigned long rip;
 717         u32 interruptibility;
 718
 719         rip = kvm_rip_read(vcpu);
 720         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 721         kvm_rip_write(vcpu, rip);
 722
 723         /*
 724          * We emulated an instruction, so temporary interrupt blocking
 725          * should be removed, if set.
 726          */
 727         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 728         if (interruptibility & 3)
 729                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 730                              interruptibility & ~3);
 731         vcpu->arch.interrupt_window_open = 1;
 732 }
 733
 734 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 735                                 bool has_error_code, u32 error_code)
 736 {
 737         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 738                      nr | INTR_TYPE_EXCEPTION
 739                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 740                      | INTR_INFO_VALID_MASK);
 741         if (has_error_code)
 742                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 743 }
 744
 745 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 746 {
 747         struct vcpu_vmx *vmx = to_vmx(vcpu);
 748
 749         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
 750 }
 751
 752 /*
 753  * Swap MSR entry in host/guest MSR entry array.
 754  */
 755 #ifdef CONFIG_X86_64
 756 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 757 {
 758         struct kvm_msr_entry tmp;
 759
 760         tmp = vmx->guest_msrs[to];
 761         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 762         vmx->guest_msrs[from] = tmp;
 763         tmp = vmx->host_msrs[to];
 764         vmx->host_msrs[to] = vmx->host_msrs[from];
 765         vmx->host_msrs[from] = tmp;
 766 }
 767 #endif
 768
 769 /*
 770  * Set up the vmcs to automatically save and restore system
 771  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 772  * mode, as fiddling with msrs is very expensive.
 773  */
 774 static void setup_msrs(struct vcpu_vmx *vmx)
 775 {
 776         int save_nmsrs;
 777
 778         vmx_load_host_state(vmx);
 779         save_nmsrs = 0;
 780 #ifdef CONFIG_X86_64
 781         if (is_long_mode(&vmx->vcpu)) {
 782                 int index;
 783
 784                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 785                 if (index >= 0)
 786                         move_msr_up(vmx, index, save_nmsrs++);
 787                 index = __find_msr_index(vmx, MSR_LSTAR);
 788                 if (index >= 0)
 789                         move_msr_up(vmx, index, save_nmsrs++);
 790                 index = __find_msr_index(vmx, MSR_CSTAR);
 791                 if (index >= 0)
 792                         move_msr_up(vmx, index, save_nmsrs++);
 793                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 794                 if (index >= 0)
 795                         move_msr_up(vmx, index, save_nmsrs++);
 796                 /*
 797                  * MSR_K6_STAR is only needed on long mode guests, and only
 798                  * if efer.sce is enabled.
 799                  */
 800                 index = __find_msr_index(vmx, MSR_K6_STAR);
 801                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 802                         move_msr_up(vmx, index, save_nmsrs++);
 803         }
 804 #endif
 805         vmx->save_nmsrs = save_nmsrs;
 806
 807 #ifdef CONFIG_X86_64
 808         vmx->msr_offset_kernel_gs_base =
 809                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 810 #endif
 811         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 812 }
 813
 814 /*
 815  * reads and returns guest's timestamp counter "register"
 816  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 817  */
 818 static u64 guest_read_tsc(void)
 819 {
 820         u64 host_tsc, tsc_offset;
 821
 822         rdtscll(host_tsc);
 823         tsc_offset = vmcs_read64(TSC_OFFSET);
 824         return host_tsc + tsc_offset;
 825 }
 826
 827 /*
 828  * writes 'guest_tsc' into guest's timestamp counter "register"
 829  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 830  */
 831 static void guest_write_tsc(u64 guest_tsc)
 832 {
 833         u64 host_tsc;
 834
 835         rdtscll(host_tsc);
 836         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 837 }
 838
 839 /*
 840  * Reads an msr value (of 'msr_index') into 'pdata'.
 841  * Returns 0 on success, non-0 otherwise.
 842  * Assumes vcpu_load() was already called.
 843  */
 844 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 845 {
 846         u64 data;
 847         struct kvm_msr_entry *msr;
 848
 849         if (!pdata) {
 850                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 851                 return -EINVAL;
 852         }
 853
 854         switch (msr_index) {
 855 #ifdef CONFIG_X86_64
 856         case MSR_FS_BASE:
 857                 data = vmcs_readl(GUEST_FS_BASE);
 858                 break;
 859         case MSR_GS_BASE:
 860                 data = vmcs_readl(GUEST_GS_BASE);
 861                 break;
 862         case MSR_EFER:
 863                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 864 #endif
 865         case MSR_IA32_TIME_STAMP_COUNTER:
 866                 data = guest_read_tsc();
 867                 break;
 868         case MSR_IA32_SYSENTER_CS:
 869                 data = vmcs_read32(GUEST_SYSENTER_CS);
 870                 break;
 871         case MSR_IA32_SYSENTER_EIP:
 872                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 873                 break;
 874         case MSR_IA32_SYSENTER_ESP:
 875                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 876                 break;
 877         default:
 878                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 879                 if (msr) {
 880                         data = msr->data;
 881                         break;
 882                 }
 883                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 884         }
 885
 886         *pdata = data;
 887         return 0;
 888 }
 889
 890 /*
 891  * Writes msr value into into the appropriate "register".
 892  * Returns 0 on success, non-0 otherwise.
 893  * Assumes vcpu_load() was already called.
 894  */
 895 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 896 {
 897         struct vcpu_vmx *vmx = to_vmx(vcpu);
 898         struct kvm_msr_entry *msr;
 899         int ret = 0;
 900
 901         switch (msr_index) {
 902 #ifdef CONFIG_X86_64
 903         case MSR_EFER:
 904                 vmx_load_host_state(vmx);
 905                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 906                 break;
 907         case MSR_FS_BASE:
 908                 vmcs_writel(GUEST_FS_BASE, data);
 909                 break;
 910         case MSR_GS_BASE:
 911                 vmcs_writel(GUEST_GS_BASE, data);
 912                 break;
 913 #endif
 914         case MSR_IA32_SYSENTER_CS:
 915                 vmcs_write32(GUEST_SYSENTER_CS, data);
 916                 break;
 917         case MSR_IA32_SYSENTER_EIP:
 918                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 919                 break;
 920         case MSR_IA32_SYSENTER_ESP:
 921                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 922                 break;
 923         case MSR_IA32_TIME_STAMP_COUNTER:
 924                 guest_write_tsc(data);
 925                 break;
 926         case MSR_P6_PERFCTR0:
 927         case MSR_P6_PERFCTR1:
 928         case MSR_P6_EVNTSEL0:
 929         case MSR_P6_EVNTSEL1:
 930                 /*
 931                  * Just discard all writes to the performance counters; this
 932                  * should keep both older linux and windows 64-bit guests
 933                  * happy
 934                  */
 935                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 936
 937                 break;
 938         default:
 939                 vmx_load_host_state(vmx);
 940                 msr = find_msr_entry(vmx, msr_index);
 941                 if (msr) {
 942                         msr->data = data;
 943                         break;
 944                 }
 945                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 946         }
 947
 948         return ret;
 949 }
 950
 951 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 952 {
 953         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
 954         switch (reg) {
 955         case VCPU_REGS_RSP:
 956                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 957                 break;
 958         case VCPU_REGS_RIP:
 959                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
 960                 break;
 961         default:
 962                 break;
 963         }
 964 }
 965
 966 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 967 {
 968         unsigned long dr7 = 0x400;
 969         int old_singlestep;
 970
 971         old_singlestep = vcpu->guest_debug.singlestep;
 972
 973         vcpu->guest_debug.enabled = dbg->enabled;
 974         if (vcpu->guest_debug.enabled) {
 975                 int i;
 976
 977                 dr7 |= 0x200;  /* exact */
 978                 for (i = 0; i < 4; ++i) {
 979                         if (!dbg->breakpoints[i].enabled)
 980                                 continue;
 981                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 982                         dr7 |= 2 << (i*2);    /* global enable */
 983                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 984                 }
 985
 986                 vcpu->guest_debug.singlestep = dbg->singlestep;
 987         } else
 988                 vcpu->guest_debug.singlestep = 0;
 989
 990         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 991                 unsigned long flags;
 992
 993                 flags = vmcs_readl(GUEST_RFLAGS);
 994                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 995                 vmcs_writel(GUEST_RFLAGS, flags);
 996         }
 997
 998         update_exception_bitmap(vcpu);
 999         vmcs_writel(GUEST_DR7, dr7);
1000
1001         return 0;
1002 }
1003
1004 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1005 {
1006         struct vcpu_vmx *vmx = to_vmx(vcpu);
1007         u32 idtv_info_field;
1008
1009         idtv_info_field = vmx->idt_vectoring_info;
1010         if (idtv_info_field & INTR_INFO_VALID_MASK) {
1011                 if (is_external_interrupt(idtv_info_field))
1012                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
1013                 else
1014                         printk(KERN_DEBUG "pending exception: not handled yet\n");
1015         }
1016         return -1;
1017 }
1018
1019 static __init int cpu_has_kvm_support(void)
1020 {
1021         unsigned long ecx = cpuid_ecx(1);
1022         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1023 }
1024
1025 static __init int vmx_disabled_by_bios(void)
1026 {
1027         u64 msr;
1028
1029         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1030         return (msr & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1031                        IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1032             == IA32_FEATURE_CONTROL_LOCKED_BIT;
1033         /* locked but not enabled */
1034 }
1035
1036 static void hardware_enable(void *garbage)
1037 {
1038         int cpu = raw_smp_processor_id();
1039         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1040         u64 old;
1041
1042         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1043         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1044         if ((old & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1045                     IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1046             != (IA32_FEATURE_CONTROL_LOCKED_BIT |
1047                 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1048                 /* enable and lock */
1049                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1050                        IA32_FEATURE_CONTROL_LOCKED_BIT |
1051                        IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT);
1052         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1053         asm volatile (ASM_VMX_VMXON_RAX
1054                       : : "a"(&phys_addr), "m"(phys_addr)
1055                       : "memory", "cc");
1056 }
1057
1058 static void vmclear_local_vcpus(void)
1059 {
1060         int cpu = raw_smp_processor_id();
1061         struct vcpu_vmx *vmx, *n;
1062
1063         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1064                                  local_vcpus_link)
1065                 __vcpu_clear(vmx);
1066 }
1067
1068 static void hardware_disable(void *garbage)
1069 {
1070         vmclear_local_vcpus();
1071         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1072         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1073 }
1074
1075 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1076                                       u32 msr, u32 *result)
1077 {
1078         u32 vmx_msr_low, vmx_msr_high;
1079         u32 ctl = ctl_min | ctl_opt;
1080
1081         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1082
1083         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1084         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1085
1086         /* Ensure minimum (required) set of control bits are supported. */
1087         if (ctl_min & ~ctl)
1088                 return -EIO;
1089
1090         *result = ctl;
1091         return 0;
1092 }
1093
1094 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1095 {
1096         u32 vmx_msr_low, vmx_msr_high;
1097         u32 min, opt, min2, opt2;
1098         u32 _pin_based_exec_control = 0;
1099         u32 _cpu_based_exec_control = 0;
1100         u32 _cpu_based_2nd_exec_control = 0;
1101         u32 _vmexit_control = 0;
1102         u32 _vmentry_control = 0;
1103
1104         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1105         opt = PIN_BASED_VIRTUAL_NMIS;
1106         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1107                                 &_pin_based_exec_control) < 0)
1108                 return -EIO;
1109
1110         min = CPU_BASED_HLT_EXITING |
1111 #ifdef CONFIG_X86_64
1112               CPU_BASED_CR8_LOAD_EXITING |
1113               CPU_BASED_CR8_STORE_EXITING |
1114 #endif
1115               CPU_BASED_CR3_LOAD_EXITING |
1116               CPU_BASED_CR3_STORE_EXITING |
1117               CPU_BASED_USE_IO_BITMAPS |
1118               CPU_BASED_MOV_DR_EXITING |
1119               CPU_BASED_USE_TSC_OFFSETING;
1120         opt = CPU_BASED_TPR_SHADOW |
1121               CPU_BASED_USE_MSR_BITMAPS |
1122               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1123         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1124                                 &_cpu_based_exec_control) < 0)
1125                 return -EIO;
1126 #ifdef CONFIG_X86_64
1127         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1128                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1129                                            ~CPU_BASED_CR8_STORE_EXITING;
1130 #endif
1131         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1132                 min2 = 0;
1133                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1134                         SECONDARY_EXEC_WBINVD_EXITING |
1135                         SECONDARY_EXEC_ENABLE_VPID |
1136                         SECONDARY_EXEC_ENABLE_EPT;
1137                 if (adjust_vmx_controls(min2, opt2,
1138                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1139                                         &_cpu_based_2nd_exec_control) < 0)
1140                         return -EIO;
1141         }
1142 #ifndef CONFIG_X86_64
1143         if (!(_cpu_based_2nd_exec_control &
1144                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1145                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1146 #endif
1147         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1148                 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1149                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1150                          CPU_BASED_CR3_STORE_EXITING);
1151                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1152                                         &_cpu_based_exec_control) < 0)
1153                         return -EIO;
1154                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1155                       vmx_capability.ept, vmx_capability.vpid);
1156         }
1157
1158         min = 0;
1159 #ifdef CONFIG_X86_64
1160         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1161 #endif
1162         opt = 0;
1163         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1164                                 &_vmexit_control) < 0)
1165                 return -EIO;
1166
1167         min = opt = 0;
1168         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1169                                 &_vmentry_control) < 0)
1170                 return -EIO;
1171
1172         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1173
1174         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1175         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1176                 return -EIO;
1177
1178 #ifdef CONFIG_X86_64
1179         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1180         if (vmx_msr_high & (1u<<16))
1181                 return -EIO;
1182 #endif
1183
1184         /* Require Write-Back (WB) memory type for VMCS accesses. */
1185         if (((vmx_msr_high >> 18) & 15) != 6)
1186                 return -EIO;
1187
1188         vmcs_conf->size = vmx_msr_high & 0x1fff;
1189         vmcs_conf->order = get_order(vmcs_config.size);
1190         vmcs_conf->revision_id = vmx_msr_low;
1191
1192         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1193         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1194         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1195         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1196         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1197
1198         return 0;
1199 }
1200
1201 static struct vmcs *alloc_vmcs_cpu(int cpu)
1202 {
1203         int node = cpu_to_node(cpu);
1204         struct page *pages;
1205         struct vmcs *vmcs;
1206
1207         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1208         if (!pages)
1209                 return NULL;
1210         vmcs = page_address(pages);
1211         memset(vmcs, 0, vmcs_config.size);
1212         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1213         return vmcs;
1214 }
1215
1216 static struct vmcs *alloc_vmcs(void)
1217 {
1218         return alloc_vmcs_cpu(raw_smp_processor_id());
1219 }
1220
1221 static void free_vmcs(struct vmcs *vmcs)
1222 {
1223         free_pages((unsigned long)vmcs, vmcs_config.order);
1224 }
1225
1226 static void free_kvm_area(void)
1227 {
1228         int cpu;
1229
1230         for_each_online_cpu(cpu)
1231                 free_vmcs(per_cpu(vmxarea, cpu));
1232 }
1233
1234 static __init int alloc_kvm_area(void)
1235 {
1236         int cpu;
1237
1238         for_each_online_cpu(cpu) {
1239                 struct vmcs *vmcs;
1240
1241                 vmcs = alloc_vmcs_cpu(cpu);
1242                 if (!vmcs) {
1243                         free_kvm_area();
1244                         return -ENOMEM;
1245                 }
1246
1247                 per_cpu(vmxarea, cpu) = vmcs;
1248         }
1249         return 0;
1250 }
1251
1252 static __init int hardware_setup(void)
1253 {
1254         if (setup_vmcs_config(&vmcs_config) < 0)
1255                 return -EIO;
1256
1257         if (boot_cpu_has(X86_FEATURE_NX))
1258                 kvm_enable_efer_bits(EFER_NX);
1259
1260         return alloc_kvm_area();
1261 }
1262
1263 static __exit void hardware_unsetup(void)
1264 {
1265         free_kvm_area();
1266 }
1267
1268 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1269 {
1270         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1271
1272         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1273                 vmcs_write16(sf->selector, save->selector);
1274                 vmcs_writel(sf->base, save->base);
1275                 vmcs_write32(sf->limit, save->limit);
1276                 vmcs_write32(sf->ar_bytes, save->ar);
1277         } else {
1278                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1279                         << AR_DPL_SHIFT;
1280                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1281         }
1282 }
1283
1284 static void enter_pmode(struct kvm_vcpu *vcpu)
1285 {
1286         unsigned long flags;
1287
1288         vcpu->arch.rmode.active = 0;
1289
1290         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1291         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1292         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1293
1294         flags = vmcs_readl(GUEST_RFLAGS);
1295         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1296         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1297         vmcs_writel(GUEST_RFLAGS, flags);
1298
1299         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1300                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1301
1302         update_exception_bitmap(vcpu);
1303
1304         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1305         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1306         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1307         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1308
1309         vmcs_write16(GUEST_SS_SELECTOR, 0);
1310         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1311
1312         vmcs_write16(GUEST_CS_SELECTOR,
1313                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1314         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1315 }
1316
1317 static gva_t rmode_tss_base(struct kvm *kvm)
1318 {
1319         if (!kvm->arch.tss_addr) {
1320                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1321                                  kvm->memslots[0].npages - 3;
1322                 return base_gfn << PAGE_SHIFT;
1323         }
1324         return kvm->arch.tss_addr;
1325 }
1326
1327 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1328 {
1329         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1330
1331         save->selector = vmcs_read16(sf->selector);
1332         save->base = vmcs_readl(sf->base);
1333         save->limit = vmcs_read32(sf->limit);
1334         save->ar = vmcs_read32(sf->ar_bytes);
1335         vmcs_write16(sf->selector, save->base >> 4);
1336         vmcs_write32(sf->base, save->base & 0xfffff);
1337         vmcs_write32(sf->limit, 0xffff);
1338         vmcs_write32(sf->ar_bytes, 0xf3);
1339 }
1340
1341 static void enter_rmode(struct kvm_vcpu *vcpu)
1342 {
1343         unsigned long flags;
1344
1345         vcpu->arch.rmode.active = 1;
1346
1347         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1348         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1349
1350         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1351         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1352
1353         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1354         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1355
1356         flags = vmcs_readl(GUEST_RFLAGS);
1357         vcpu->arch.rmode.save_iopl
1358                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1359
1360         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1361
1362         vmcs_writel(GUEST_RFLAGS, flags);
1363         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1364         update_exception_bitmap(vcpu);
1365
1366         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1367         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1368         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1369
1370         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1371         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1372         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1373                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1374         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1375
1376         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1377         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1378         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1379         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1380
1381         kvm_mmu_reset_context(vcpu);
1382         init_rmode(vcpu->kvm);
1383 }
1384
1385 #ifdef CONFIG_X86_64
1386
1387 static void enter_lmode(struct kvm_vcpu *vcpu)
1388 {
1389         u32 guest_tr_ar;
1390
1391         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1392         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1393                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1394                        __func__);
1395                 vmcs_write32(GUEST_TR_AR_BYTES,
1396                              (guest_tr_ar & ~AR_TYPE_MASK)
1397                              | AR_TYPE_BUSY_64_TSS);
1398         }
1399
1400         vcpu->arch.shadow_efer |= EFER_LMA;
1401
1402         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1403         vmcs_write32(VM_ENTRY_CONTROLS,
1404                      vmcs_read32(VM_ENTRY_CONTROLS)
1405                      | VM_ENTRY_IA32E_MODE);
1406 }
1407
1408 static void exit_lmode(struct kvm_vcpu *vcpu)
1409 {
1410         vcpu->arch.shadow_efer &= ~EFER_LMA;
1411
1412         vmcs_write32(VM_ENTRY_CONTROLS,
1413                      vmcs_read32(VM_ENTRY_CONTROLS)
1414                      & ~VM_ENTRY_IA32E_MODE);
1415 }
1416
1417 #endif
1418
1419 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1420 {
1421         vpid_sync_vcpu_all(to_vmx(vcpu));
1422         if (vm_need_ept())
1423                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1424 }
1425
1426 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1427 {
1428         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1429         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1430 }
1431
1432 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1433 {
1434         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1435                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1436                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1437                         return;
1438                 }
1439                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1440                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1441                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1442                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1443         }
1444 }
1445
1446 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1447
1448 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1449                                         unsigned long cr0,
1450                                         struct kvm_vcpu *vcpu)
1451 {
1452         if (!(cr0 & X86_CR0_PG)) {
1453                 /* From paging/starting to nonpaging */
1454                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1455                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1456                              (CPU_BASED_CR3_LOAD_EXITING |
1457                               CPU_BASED_CR3_STORE_EXITING));
1458                 vcpu->arch.cr0 = cr0;
1459                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1460                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1461                 *hw_cr0 &= ~X86_CR0_WP;
1462         } else if (!is_paging(vcpu)) {
1463                 /* From nonpaging to paging */
1464                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1465                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1466                              ~(CPU_BASED_CR3_LOAD_EXITING |
1467                                CPU_BASED_CR3_STORE_EXITING));
1468                 vcpu->arch.cr0 = cr0;
1469                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1470                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1471                         *hw_cr0 &= ~X86_CR0_WP;
1472         }
1473 }
1474
1475 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1476                                         struct kvm_vcpu *vcpu)
1477 {
1478         if (!is_paging(vcpu)) {
1479                 *hw_cr4 &= ~X86_CR4_PAE;
1480                 *hw_cr4 |= X86_CR4_PSE;
1481         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1482                 *hw_cr4 &= ~X86_CR4_PAE;
1483 }
1484
1485 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1486 {
1487         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1488                                 KVM_VM_CR0_ALWAYS_ON;
1489
1490         vmx_fpu_deactivate(vcpu);
1491
1492         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1493                 enter_pmode(vcpu);
1494
1495         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1496                 enter_rmode(vcpu);
1497
1498 #ifdef CONFIG_X86_64
1499         if (vcpu->arch.shadow_efer & EFER_LME) {
1500                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1501                         enter_lmode(vcpu);
1502                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1503                         exit_lmode(vcpu);
1504         }
1505 #endif
1506
1507         if (vm_need_ept())
1508                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1509
1510         vmcs_writel(CR0_READ_SHADOW, cr0);
1511         vmcs_writel(GUEST_CR0, hw_cr0);
1512         vcpu->arch.cr0 = cr0;
1513
1514         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1515                 vmx_fpu_activate(vcpu);
1516 }
1517
1518 static u64 construct_eptp(unsigned long root_hpa)
1519 {
1520         u64 eptp;
1521
1522         /* TODO write the value reading from MSR */
1523         eptp = VMX_EPT_DEFAULT_MT |
1524                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1525         eptp |= (root_hpa & PAGE_MASK);
1526
1527         return eptp;
1528 }
1529
1530 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1531 {
1532         unsigned long guest_cr3;
1533         u64 eptp;
1534
1535         guest_cr3 = cr3;
1536         if (vm_need_ept()) {
1537                 eptp = construct_eptp(cr3);
1538                 vmcs_write64(EPT_POINTER, eptp);
1539                 ept_sync_context(eptp);
1540                 ept_load_pdptrs(vcpu);
1541                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1542                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1543         }
1544
1545         vmx_flush_tlb(vcpu);
1546         vmcs_writel(GUEST_CR3, guest_cr3);
1547         if (vcpu->arch.cr0 & X86_CR0_PE)
1548                 vmx_fpu_deactivate(vcpu);
1549 }
1550
1551 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1552 {
1553         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1554                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1555
1556         vcpu->arch.cr4 = cr4;
1557         if (vm_need_ept())
1558                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1559
1560         vmcs_writel(CR4_READ_SHADOW, cr4);
1561         vmcs_writel(GUEST_CR4, hw_cr4);
1562 }
1563
1564 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1565 {
1566         struct vcpu_vmx *vmx = to_vmx(vcpu);
1567         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1568
1569         vcpu->arch.shadow_efer = efer;
1570         if (!msr)
1571                 return;
1572         if (efer & EFER_LMA) {
1573                 vmcs_write32(VM_ENTRY_CONTROLS,
1574                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1575                                      VM_ENTRY_IA32E_MODE);
1576                 msr->data = efer;
1577
1578         } else {
1579                 vmcs_write32(VM_ENTRY_CONTROLS,
1580                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1581                                      ~VM_ENTRY_IA32E_MODE);
1582
1583                 msr->data = efer & ~EFER_LME;
1584         }
1585         setup_msrs(vmx);
1586 }
1587
1588 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1589 {
1590         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1591
1592         return vmcs_readl(sf->base);
1593 }
1594
1595 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1596                             struct kvm_segment *var, int seg)
1597 {
1598         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1599         u32 ar;
1600
1601         var->base = vmcs_readl(sf->base);
1602         var->limit = vmcs_read32(sf->limit);
1603         var->selector = vmcs_read16(sf->selector);
1604         ar = vmcs_read32(sf->ar_bytes);
1605         if (ar & AR_UNUSABLE_MASK)
1606                 ar = 0;
1607         var->type = ar & 15;
1608         var->s = (ar >> 4) & 1;
1609         var->dpl = (ar >> 5) & 3;
1610         var->present = (ar >> 7) & 1;
1611         var->avl = (ar >> 12) & 1;
1612         var->l = (ar >> 13) & 1;
1613         var->db = (ar >> 14) & 1;
1614         var->g = (ar >> 15) & 1;
1615         var->unusable = (ar >> 16) & 1;
1616 }
1617
1618 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1619 {
1620         struct kvm_segment kvm_seg;
1621
1622         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1623                 return 0;
1624
1625         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1626                 return 3;
1627
1628         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1629         return kvm_seg.selector & 3;
1630 }
1631
1632 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1633 {
1634         u32 ar;
1635
1636         if (var->unusable)
1637                 ar = 1 << 16;
1638         else {
1639                 ar = var->type & 15;
1640                 ar |= (var->s & 1) << 4;
1641                 ar |= (var->dpl & 3) << 5;
1642                 ar |= (var->present & 1) << 7;
1643                 ar |= (var->avl & 1) << 12;
1644                 ar |= (var->l & 1) << 13;
1645                 ar |= (var->db & 1) << 14;
1646                 ar |= (var->g & 1) << 15;
1647         }
1648         if (ar == 0) /* a 0 value means unusable */
1649                 ar = AR_UNUSABLE_MASK;
1650
1651         return ar;
1652 }
1653
1654 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1655                             struct kvm_segment *var, int seg)
1656 {
1657         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1658         u32 ar;
1659
1660         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1661                 vcpu->arch.rmode.tr.selector = var->selector;
1662                 vcpu->arch.rmode.tr.base = var->base;
1663                 vcpu->arch.rmode.tr.limit = var->limit;
1664                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1665                 return;
1666         }
1667         vmcs_writel(sf->base, var->base);
1668         vmcs_write32(sf->limit, var->limit);
1669         vmcs_write16(sf->selector, var->selector);
1670         if (vcpu->arch.rmode.active && var->s) {
1671                 /*
1672                  * Hack real-mode segments into vm86 compatibility.
1673                  */
1674                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1675                         vmcs_writel(sf->base, 0xf0000);
1676                 ar = 0xf3;
1677         } else
1678                 ar = vmx_segment_access_rights(var);
1679         vmcs_write32(sf->ar_bytes, ar);
1680 }
1681
1682 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1683 {
1684         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1685
1686         *db = (ar >> 14) & 1;
1687         *l = (ar >> 13) & 1;
1688 }
1689
1690 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1691 {
1692         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1693         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1694 }
1695
1696 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1697 {
1698         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1699         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1700 }
1701
1702 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1703 {
1704         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1705         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1706 }
1707
1708 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1709 {
1710         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1711         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1712 }
1713
1714 static int init_rmode_tss(struct kvm *kvm)
1715 {
1716         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1717         u16 data = 0;
1718         int ret = 0;
1719         int r;
1720
1721         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1722         if (r < 0)
1723                 goto out;
1724         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1725         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1726         if (r < 0)
1727                 goto out;
1728         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1729         if (r < 0)
1730                 goto out;
1731         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1732         if (r < 0)
1733                 goto out;
1734         data = ~0;
1735         r = kvm_write_guest_page(kvm, fn, &data,
1736                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1737                                  sizeof(u8));
1738         if (r < 0)
1739                 goto out;
1740
1741         ret = 1;
1742 out:
1743         return ret;
1744 }
1745
1746 static int init_rmode_identity_map(struct kvm *kvm)
1747 {
1748         int i, r, ret;
1749         pfn_t identity_map_pfn;
1750         u32 tmp;
1751
1752         if (!vm_need_ept())
1753                 return 1;
1754         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1755                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1756                         "haven't been allocated!\n");
1757                 return 0;
1758         }
1759         if (likely(kvm->arch.ept_identity_pagetable_done))
1760                 return 1;
1761         ret = 0;
1762         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1763         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1764         if (r < 0)
1765                 goto out;
1766         /* Set up identity-mapping pagetable for EPT in real mode */
1767         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1768                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1769                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1770                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1771                                 &tmp, i * sizeof(tmp), sizeof(tmp));
1772                 if (r < 0)
1773                         goto out;
1774         }
1775         kvm->arch.ept_identity_pagetable_done = true;
1776         ret = 1;
1777 out:
1778         return ret;
1779 }
1780
1781 static void seg_setup(int seg)
1782 {
1783         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1784
1785         vmcs_write16(sf->selector, 0);
1786         vmcs_writel(sf->base, 0);
1787         vmcs_write32(sf->limit, 0xffff);
1788         vmcs_write32(sf->ar_bytes, 0x93);
1789 }
1790
1791 static int alloc_apic_access_page(struct kvm *kvm)
1792 {
1793         struct kvm_userspace_memory_region kvm_userspace_mem;
1794         int r = 0;
1795
1796         down_write(&kvm->slots_lock);
1797         if (kvm->arch.apic_access_page)
1798                 goto out;
1799         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1800         kvm_userspace_mem.flags = 0;
1801         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1802         kvm_userspace_mem.memory_size = PAGE_SIZE;
1803         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1804         if (r)
1805                 goto out;
1806
1807         down_read(&current->mm->mmap_sem);
1808         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1809         up_read(&current->mm->mmap_sem);
1810 out:
1811         up_write(&kvm->slots_lock);
1812         return r;
1813 }
1814
1815 static int alloc_identity_pagetable(struct kvm *kvm)
1816 {
1817         struct kvm_userspace_memory_region kvm_userspace_mem;
1818         int r = 0;
1819
1820         down_write(&kvm->slots_lock);
1821         if (kvm->arch.ept_identity_pagetable)
1822                 goto out;
1823         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1824         kvm_userspace_mem.flags = 0;
1825         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1826         kvm_userspace_mem.memory_size = PAGE_SIZE;
1827         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1828         if (r)
1829                 goto out;
1830
1831         down_read(&current->mm->mmap_sem);
1832         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1833                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1834         up_read(&current->mm->mmap_sem);
1835 out:
1836         up_write(&kvm->slots_lock);
1837         return r;
1838 }
1839
1840 static void allocate_vpid(struct vcpu_vmx *vmx)
1841 {
1842         int vpid;
1843
1844         vmx->vpid = 0;
1845         if (!enable_vpid || !cpu_has_vmx_vpid())
1846                 return;
1847         spin_lock(&vmx_vpid_lock);
1848         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1849         if (vpid < VMX_NR_VPIDS) {
1850                 vmx->vpid = vpid;
1851                 __set_bit(vpid, vmx_vpid_bitmap);
1852         }
1853         spin_unlock(&vmx_vpid_lock);
1854 }
1855
1856 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1857 {
1858         void *va;
1859
1860         if (!cpu_has_vmx_msr_bitmap())
1861                 return;
1862
1863         /*
1864          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1865          * have the write-low and read-high bitmap offsets the wrong way round.
1866          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1867          */
1868         va = kmap(msr_bitmap);
1869         if (msr <= 0x1fff) {
1870                 __clear_bit(msr, va + 0x000); /* read-low */
1871                 __clear_bit(msr, va + 0x800); /* write-low */
1872         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1873                 msr &= 0x1fff;
1874                 __clear_bit(msr, va + 0x400); /* read-high */
1875                 __clear_bit(msr, va + 0xc00); /* write-high */
1876         }
1877         kunmap(msr_bitmap);
1878 }
1879
1880 /*
1881  * Sets up the vmcs for emulated real mode.
1882  */
1883 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1884 {
1885         u32 host_sysenter_cs;
1886         u32 junk;
1887         unsigned long a;
1888         struct descriptor_table dt;
1889         int i;
1890         unsigned long kvm_vmx_return;
1891         u32 exec_control;
1892
1893         /* I/O */
1894         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1895         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1896
1897         if (cpu_has_vmx_msr_bitmap())
1898                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1899
1900         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1901
1902         /* Control */
1903         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1904                 vmcs_config.pin_based_exec_ctrl);
1905
1906         exec_control = vmcs_config.cpu_based_exec_ctrl;
1907         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1908                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1909 #ifdef CONFIG_X86_64
1910                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1911                                 CPU_BASED_CR8_LOAD_EXITING;
1912 #endif
1913         }
1914         if (!vm_need_ept())
1915                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1916                                 CPU_BASED_CR3_LOAD_EXITING;
1917         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1918
1919         if (cpu_has_secondary_exec_ctrls()) {
1920                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1921                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1922                         exec_control &=
1923                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1924                 if (vmx->vpid == 0)
1925                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1926                 if (!vm_need_ept())
1927                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
1928                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1929         }
1930
1931         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1932         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1933         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1934
1935         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1936         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1937         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1938
1939         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1940         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1941         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1942         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
1943         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
1944         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1945 #ifdef CONFIG_X86_64
1946         rdmsrl(MSR_FS_BASE, a);
1947         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1948         rdmsrl(MSR_GS_BASE, a);
1949         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1950 #else
1951         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1952         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1953 #endif
1954
1955         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1956
1957         kvm_get_idt(&dt);
1958         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1959
1960         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1961         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1962         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1963         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1964         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1965
1966         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1967         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1968         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1969         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1970         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1971         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1972
1973         for (i = 0; i < NR_VMX_MSR; ++i) {
1974                 u32 index = vmx_msr_index[i];
1975                 u32 data_low, data_high;
1976                 u64 data;
1977                 int j = vmx->nmsrs;
1978
1979                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1980                         continue;
1981                 if (wrmsr_safe(index, data_low, data_high) < 0)
1982                         continue;
1983                 data = data_low | ((u64)data_high << 32);
1984                 vmx->host_msrs[j].index = index;
1985                 vmx->host_msrs[j].reserved = 0;
1986                 vmx->host_msrs[j].data = data;
1987                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1988                 ++vmx->nmsrs;
1989         }
1990
1991         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1992
1993         /* 22.2.1, 20.8.1 */
1994         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1995
1996         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1997         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1998
1999
2000         return 0;
2001 }
2002
2003 static int init_rmode(struct kvm *kvm)
2004 {
2005         if (!init_rmode_tss(kvm))
2006                 return 0;
2007         if (!init_rmode_identity_map(kvm))
2008                 return 0;
2009         return 1;
2010 }
2011
2012 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2013 {
2014         struct vcpu_vmx *vmx = to_vmx(vcpu);
2015         u64 msr;
2016         int ret;
2017
2018         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2019         down_read(&vcpu->kvm->slots_lock);
2020         if (!init_rmode(vmx->vcpu.kvm)) {
2021                 ret = -ENOMEM;
2022                 goto out;
2023         }
2024
2025         vmx->vcpu.arch.rmode.active = 0;
2026
2027         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2028         kvm_set_cr8(&vmx->vcpu, 0);
2029         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2030         if (vmx->vcpu.vcpu_id == 0)
2031                 msr |= MSR_IA32_APICBASE_BSP;
2032         kvm_set_apic_base(&vmx->vcpu, msr);
2033
2034         fx_init(&vmx->vcpu);
2035
2036         /*
2037          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2038          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2039          */
2040         if (vmx->vcpu.vcpu_id == 0) {
2041                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2042                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2043         } else {
2044                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2045                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2046         }
2047         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2048         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2049
2050         seg_setup(VCPU_SREG_DS);
2051         seg_setup(VCPU_SREG_ES);
2052         seg_setup(VCPU_SREG_FS);
2053         seg_setup(VCPU_SREG_GS);
2054         seg_setup(VCPU_SREG_SS);
2055
2056         vmcs_write16(GUEST_TR_SELECTOR, 0);
2057         vmcs_writel(GUEST_TR_BASE, 0);
2058         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2059         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2060
2061         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2062         vmcs_writel(GUEST_LDTR_BASE, 0);
2063         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2064         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2065
2066         vmcs_write32(GUEST_SYSENTER_CS, 0);
2067         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2068         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2069
2070         vmcs_writel(GUEST_RFLAGS, 0x02);
2071         if (vmx->vcpu.vcpu_id == 0)
2072                 kvm_rip_write(vcpu, 0xfff0);
2073         else
2074                 kvm_rip_write(vcpu, 0);
2075         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2076
2077         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2078         vmcs_writel(GUEST_DR7, 0x400);
2079
2080         vmcs_writel(GUEST_GDTR_BASE, 0);
2081         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2082
2083         vmcs_writel(GUEST_IDTR_BASE, 0);
2084         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2085
2086         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2087         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2088         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2089
2090         guest_write_tsc(0);
2091
2092         /* Special registers */
2093         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2094
2095         setup_msrs(vmx);
2096
2097         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2098
2099         if (cpu_has_vmx_tpr_shadow()) {
2100                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2101                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2102                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2103                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2104                 vmcs_write32(TPR_THRESHOLD, 0);
2105         }
2106
2107         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2108                 vmcs_write64(APIC_ACCESS_ADDR,
2109                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2110
2111         if (vmx->vpid != 0)
2112                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2113
2114         vmx->vcpu.arch.cr0 = 0x60000010;
2115         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2116         vmx_set_cr4(&vmx->vcpu, 0);
2117         vmx_set_efer(&vmx->vcpu, 0);
2118         vmx_fpu_activate(&vmx->vcpu);
2119         update_exception_bitmap(&vmx->vcpu);
2120
2121         vpid_sync_vcpu_all(vmx);
2122
2123         ret = 0;
2124
2125 out:
2126         up_read(&vcpu->kvm->slots_lock);
2127         return ret;
2128 }
2129
2130 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2131 {
2132         struct vcpu_vmx *vmx = to_vmx(vcpu);
2133
2134         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2135
2136         if (vcpu->arch.rmode.active) {
2137                 vmx->rmode.irq.pending = true;
2138                 vmx->rmode.irq.vector = irq;
2139                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2140                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2141                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2142                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2143                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2144                 return;
2145         }
2146         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2147                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2148 }
2149
2150 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2151 {
2152         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2153                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2154 }
2155
2156 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2157 {
2158         int word_index = __ffs(vcpu->arch.irq_summary);
2159         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2160         int irq = word_index * BITS_PER_LONG + bit_index;
2161
2162         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2163         if (!vcpu->arch.irq_pending[word_index])
2164                 clear_bit(word_index, &vcpu->arch.irq_summary);
2165         vmx_inject_irq(vcpu, irq);
2166 }
2167
2168
2169 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2170                                        struct kvm_run *kvm_run)
2171 {
2172         u32 cpu_based_vm_exec_control;
2173
2174         vcpu->arch.interrupt_window_open =
2175                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2176                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2177
2178         if (vcpu->arch.interrupt_window_open &&
2179             vcpu->arch.irq_summary &&
2180             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
2181                 /*
2182                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2183                  */
2184                 kvm_do_inject_irq(vcpu);
2185
2186         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2187         if (!vcpu->arch.interrupt_window_open &&
2188             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2189                 /*
2190                  * Interrupts blocked.  Wait for unblock.
2191                  */
2192                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2193         else
2194                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2195         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2196 }
2197
2198 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2199 {
2200         int ret;
2201         struct kvm_userspace_memory_region tss_mem = {
2202                 .slot = 8,
2203                 .guest_phys_addr = addr,
2204                 .memory_size = PAGE_SIZE * 3,
2205                 .flags = 0,
2206         };
2207
2208         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2209         if (ret)
2210                 return ret;
2211         kvm->arch.tss_addr = addr;
2212         return 0;
2213 }
2214
2215 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2216 {
2217         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2218
2219         set_debugreg(dbg->bp[0], 0);
2220         set_debugreg(dbg->bp[1], 1);
2221         set_debugreg(dbg->bp[2], 2);
2222         set_debugreg(dbg->bp[3], 3);
2223
2224         if (dbg->singlestep) {
2225                 unsigned long flags;
2226
2227                 flags = vmcs_readl(GUEST_RFLAGS);
2228                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2229                 vmcs_writel(GUEST_RFLAGS, flags);
2230         }
2231 }
2232
2233 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2234                                   int vec, u32 err_code)
2235 {
2236         if (!vcpu->arch.rmode.active)
2237                 return 0;
2238
2239         /*
2240          * Instruction with address size override prefix opcode 0x67
2241          * Cause the #SS fault with 0 error code in VM86 mode.
2242          */
2243         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2244                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2245                         return 1;
2246         return 0;
2247 }
2248
2249 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2250 {
2251         struct vcpu_vmx *vmx = to_vmx(vcpu);
2252         u32 intr_info, error_code;
2253         unsigned long cr2, rip;
2254         u32 vect_info;
2255         enum emulation_result er;
2256
2257         vect_info = vmx->idt_vectoring_info;
2258         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2259
2260         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2261                                                 !is_page_fault(intr_info))
2262                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2263                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2264
2265         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2266                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2267                 set_bit(irq, vcpu->arch.irq_pending);
2268                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2269         }
2270
2271         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2272                 return 1;  /* already handled by vmx_vcpu_run() */
2273
2274         if (is_no_device(intr_info)) {
2275                 vmx_fpu_activate(vcpu);
2276                 return 1;
2277         }
2278
2279         if (is_invalid_opcode(intr_info)) {
2280                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2281                 if (er != EMULATE_DONE)
2282                         kvm_queue_exception(vcpu, UD_VECTOR);
2283                 return 1;
2284         }
2285
2286         error_code = 0;
2287         rip = kvm_rip_read(vcpu);
2288         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2289                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2290         if (is_page_fault(intr_info)) {
2291                 /* EPT won't cause page fault directly */
2292                 if (vm_need_ept())
2293                         BUG();
2294                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2295                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2296                             (u32)((u64)cr2 >> 32), handler);
2297                 if (vect_info & VECTORING_INFO_VALID_MASK)
2298                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2299                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2300         }
2301
2302         if (vcpu->arch.rmode.active &&
2303             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2304                                                                 error_code)) {
2305                 if (vcpu->arch.halt_request) {
2306                         vcpu->arch.halt_request = 0;
2307                         return kvm_emulate_halt(vcpu);
2308                 }
2309                 return 1;
2310         }
2311
2312         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2313             (INTR_TYPE_EXCEPTION | 1)) {
2314                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2315                 return 0;
2316         }
2317         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2318         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2319         kvm_run->ex.error_code = error_code;
2320         return 0;
2321 }
2322
2323 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2324                                      struct kvm_run *kvm_run)
2325 {
2326         ++vcpu->stat.irq_exits;
2327         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2328         return 1;
2329 }
2330
2331 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2332 {
2333         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2334         return 0;
2335 }
2336
2337 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2338 {
2339         unsigned long exit_qualification;
2340         int size, down, in, string, rep;
2341         unsigned port;
2342
2343         ++vcpu->stat.io_exits;
2344         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2345         string = (exit_qualification & 16) != 0;
2346
2347         if (string) {
2348                 if (emulate_instruction(vcpu,
2349                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2350                         return 0;
2351                 return 1;
2352         }
2353
2354         size = (exit_qualification & 7) + 1;
2355         in = (exit_qualification & 8) != 0;
2356         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2357         rep = (exit_qualification & 32) != 0;
2358         port = exit_qualification >> 16;
2359
2360         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2361 }
2362
2363 static void
2364 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2365 {
2366         /*
2367          * Patch in the VMCALL instruction:
2368          */
2369         hypercall[0] = 0x0f;
2370         hypercall[1] = 0x01;
2371         hypercall[2] = 0xc1;
2372 }
2373
2374 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2375 {
2376         unsigned long exit_qualification;
2377         int cr;
2378         int reg;
2379
2380         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2381         cr = exit_qualification & 15;
2382         reg = (exit_qualification >> 8) & 15;
2383         switch ((exit_qualification >> 4) & 3) {
2384         case 0: /* mov to cr */
2385                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2386                             (u32)kvm_register_read(vcpu, reg),
2387                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2388                             handler);
2389                 switch (cr) {
2390                 case 0:
2391                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2392                         skip_emulated_instruction(vcpu);
2393                         return 1;
2394                 case 3:
2395                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2396                         skip_emulated_instruction(vcpu);
2397                         return 1;
2398                 case 4:
2399                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2400                         skip_emulated_instruction(vcpu);
2401                         return 1;
2402                 case 8:
2403                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2404                         skip_emulated_instruction(vcpu);
2405                         if (irqchip_in_kernel(vcpu->kvm))
2406                                 return 1;
2407                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2408                         return 0;
2409                 };
2410                 break;
2411         case 2: /* clts */
2412                 vmx_fpu_deactivate(vcpu);
2413                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2414                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2415                 vmx_fpu_activate(vcpu);
2416                 KVMTRACE_0D(CLTS, vcpu, handler);
2417                 skip_emulated_instruction(vcpu);
2418                 return 1;
2419         case 1: /*mov from cr*/
2420                 switch (cr) {
2421                 case 3:
2422                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2423                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2424                                     (u32)kvm_register_read(vcpu, reg),
2425                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2426                                     handler);
2427                         skip_emulated_instruction(vcpu);
2428                         return 1;
2429                 case 8:
2430                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2431                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2432                                     (u32)kvm_register_read(vcpu, reg), handler);
2433                         skip_emulated_instruction(vcpu);
2434                         return 1;
2435                 }
2436                 break;
2437         case 3: /* lmsw */
2438                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2439
2440                 skip_emulated_instruction(vcpu);
2441                 return 1;
2442         default:
2443                 break;
2444         }
2445         kvm_run->exit_reason = 0;
2446         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2447                (int)(exit_qualification >> 4) & 3, cr);
2448         return 0;
2449 }
2450
2451 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2452 {
2453         unsigned long exit_qualification;
2454         unsigned long val;
2455         int dr, reg;
2456
2457         /*
2458          * FIXME: this code assumes the host is debugging the guest.
2459          *        need to deal with guest debugging itself too.
2460          */
2461         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2462         dr = exit_qualification & 7;
2463         reg = (exit_qualification >> 8) & 15;
2464         if (exit_qualification & 16) {
2465                 /* mov from dr */
2466                 switch (dr) {
2467                 case 6:
2468                         val = 0xffff0ff0;
2469                         break;
2470                 case 7:
2471                         val = 0x400;
2472                         break;
2473                 default:
2474                         val = 0;
2475                 }
2476                 kvm_register_write(vcpu, reg, val);
2477                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2478         } else {
2479                 /* mov to dr */
2480         }
2481         skip_emulated_instruction(vcpu);
2482         return 1;
2483 }
2484
2485 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2486 {
2487         kvm_emulate_cpuid(vcpu);
2488         return 1;
2489 }
2490
2491 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2492 {
2493         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2494         u64 data;
2495
2496         if (vmx_get_msr(vcpu, ecx, &data)) {
2497                 kvm_inject_gp(vcpu, 0);
2498                 return 1;
2499         }
2500
2501         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2502                     handler);
2503
2504         /* FIXME: handling of bits 32:63 of rax, rdx */
2505         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2506         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2507         skip_emulated_instruction(vcpu);
2508         return 1;
2509 }
2510
2511 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2512 {
2513         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2514         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2515                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2516
2517         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2518                     handler);
2519
2520         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2521                 kvm_inject_gp(vcpu, 0);
2522                 return 1;
2523         }
2524
2525         skip_emulated_instruction(vcpu);
2526         return 1;
2527 }
2528
2529 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2530                                       struct kvm_run *kvm_run)
2531 {
2532         return 1;
2533 }
2534
2535 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2536                                    struct kvm_run *kvm_run)
2537 {
2538         u32 cpu_based_vm_exec_control;
2539
2540         /* clear pending irq */
2541         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2542         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2543         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2544
2545         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2546
2547         /*
2548          * If the user space waits to inject interrupts, exit as soon as
2549          * possible
2550          */
2551         if (kvm_run->request_interrupt_window &&
2552             !vcpu->arch.irq_summary) {
2553                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2554                 ++vcpu->stat.irq_window_exits;
2555                 return 0;
2556         }
2557         return 1;
2558 }
2559
2560 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2561 {
2562         skip_emulated_instruction(vcpu);
2563         return kvm_emulate_halt(vcpu);
2564 }
2565
2566 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2567 {
2568         skip_emulated_instruction(vcpu);
2569         kvm_emulate_hypercall(vcpu);
2570         return 1;
2571 }
2572
2573 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2574 {
2575         skip_emulated_instruction(vcpu);
2576         /* TODO: Add support for VT-d/pass-through device */
2577         return 1;
2578 }
2579
2580 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2581 {
2582         u64 exit_qualification;
2583         enum emulation_result er;
2584         unsigned long offset;
2585
2586         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2587         offset = exit_qualification & 0xffful;
2588
2589         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2590
2591         if (er !=  EMULATE_DONE) {
2592                 printk(KERN_ERR
2593                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2594                        offset);
2595                 return -ENOTSUPP;
2596         }
2597         return 1;
2598 }
2599
2600 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2601 {
2602         unsigned long exit_qualification;
2603         u16 tss_selector;
2604         int reason;
2605
2606         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2607
2608         reason = (u32)exit_qualification >> 30;
2609         tss_selector = exit_qualification;
2610
2611         return kvm_task_switch(vcpu, tss_selector, reason);
2612 }
2613
2614 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2615 {
2616         u64 exit_qualification;
2617         enum emulation_result er;
2618         gpa_t gpa;
2619         unsigned long hva;
2620         int gla_validity;
2621         int r;
2622
2623         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2624
2625         if (exit_qualification & (1 << 6)) {
2626                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2627                 return -ENOTSUPP;
2628         }
2629
2630         gla_validity = (exit_qualification >> 7) & 0x3;
2631         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2632                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2633                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2634                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2635                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2636                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2637                         (long unsigned int)exit_qualification);
2638                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2639                 kvm_run->hw.hardware_exit_reason = 0;
2640                 return -ENOTSUPP;
2641         }
2642
2643         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2644         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2645         if (!kvm_is_error_hva(hva)) {
2646                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2647                 if (r < 0) {
2648                         printk(KERN_ERR "EPT: Not enough memory!\n");
2649                         return -ENOMEM;
2650                 }
2651                 return 1;
2652         } else {
2653                 /* must be MMIO */
2654                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2655
2656                 if (er == EMULATE_FAIL) {
2657                         printk(KERN_ERR
2658                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2659                          er);
2660                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2661                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2662                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2663                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2664                                 (long unsigned int)exit_qualification);
2665                         return -ENOTSUPP;
2666                 } else if (er == EMULATE_DO_MMIO)
2667                         return 0;
2668         }
2669         return 1;
2670 }
2671
2672 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2673 {
2674         u32 cpu_based_vm_exec_control;
2675
2676         /* clear pending NMI */
2677         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2678         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2679         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2680         ++vcpu->stat.nmi_window_exits;
2681
2682         return 1;
2683 }
2684
2685 /*
2686  * The exit handlers return 1 if the exit was handled fully and guest execution
2687  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2688  * to be done to userspace and return 0.
2689  */
2690 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2691                                       struct kvm_run *kvm_run) = {
2692         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2693         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2694         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2695         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
2696         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2697         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2698         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2699         [EXIT_REASON_CPUID]                   = handle_cpuid,
2700         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2701         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2702         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2703         [EXIT_REASON_HLT]                     = handle_halt,
2704         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2705         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2706         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2707         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2708         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
2709         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
2710 };
2711
2712 static const int kvm_vmx_max_exit_handlers =
2713         ARRAY_SIZE(kvm_vmx_exit_handlers);
2714
2715 /*
2716  * The guest has exited.  See if we can fix it or if we need userspace
2717  * assistance.
2718  */
2719 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2720 {
2721         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2722         struct vcpu_vmx *vmx = to_vmx(vcpu);
2723         u32 vectoring_info = vmx->idt_vectoring_info;
2724
2725         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
2726                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2727
2728         /* Access CR3 don't cause VMExit in paging mode, so we need
2729          * to sync with guest real CR3. */
2730         if (vm_need_ept() && is_paging(vcpu)) {
2731                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2732                 ept_load_pdptrs(vcpu);
2733         }
2734
2735         if (unlikely(vmx->fail)) {
2736                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2737                 kvm_run->fail_entry.hardware_entry_failure_reason
2738                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2739                 return 0;
2740         }
2741
2742         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2743                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2744                         exit_reason != EXIT_REASON_EPT_VIOLATION))
2745                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2746                        "exit reason is 0x%x\n", __func__, exit_reason);
2747         if (exit_reason < kvm_vmx_max_exit_handlers
2748             && kvm_vmx_exit_handlers[exit_reason])
2749                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2750         else {
2751                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2752                 kvm_run->hw.hardware_exit_reason = exit_reason;
2753         }
2754         return 0;
2755 }
2756
2757 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2758 {
2759         int max_irr, tpr;
2760
2761         if (!vm_need_tpr_shadow(vcpu->kvm))
2762                 return;
2763
2764         if (!kvm_lapic_enabled(vcpu) ||
2765             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2766                 vmcs_write32(TPR_THRESHOLD, 0);
2767                 return;
2768         }
2769
2770         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2771         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2772 }
2773
2774 static void enable_irq_window(struct kvm_vcpu *vcpu)
2775 {
2776         u32 cpu_based_vm_exec_control;
2777
2778         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2779         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2780         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2781 }
2782
2783 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2784 {
2785         u32 cpu_based_vm_exec_control;
2786
2787         if (!cpu_has_virtual_nmis())
2788                 return;
2789
2790         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2791         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2792         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2793 }
2794
2795 static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
2796 {
2797         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2798         return !(guest_intr & (GUEST_INTR_STATE_NMI |
2799                                GUEST_INTR_STATE_MOV_SS |
2800                                GUEST_INTR_STATE_STI));
2801 }
2802
2803 static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
2804 {
2805         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2806         return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
2807                                GUEST_INTR_STATE_STI)) &&
2808                 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2809 }
2810
2811 static void enable_intr_window(struct kvm_vcpu *vcpu)
2812 {
2813         if (vcpu->arch.nmi_pending)
2814                 enable_nmi_window(vcpu);
2815         else if (kvm_cpu_has_interrupt(vcpu))
2816                 enable_irq_window(vcpu);
2817 }
2818
2819 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
2820 {
2821         u32 exit_intr_info;
2822         u32 idt_vectoring_info;
2823         bool unblock_nmi;
2824         u8 vector;
2825         int type;
2826         bool idtv_info_valid;
2827
2828         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2829         if (cpu_has_virtual_nmis()) {
2830                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
2831                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
2832                 /*
2833                  * SDM 3: 25.7.1.2
2834                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
2835                  * a guest IRET fault.
2836                  */
2837                 if (unblock_nmi && vector != DF_VECTOR)
2838                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2839                                       GUEST_INTR_STATE_NMI);
2840         }
2841
2842         idt_vectoring_info = vmx->idt_vectoring_info;
2843         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
2844         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
2845         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
2846         if (vmx->vcpu.arch.nmi_injected) {
2847                 /*
2848                  * SDM 3: 25.7.1.2
2849                  * Clear bit "block by NMI" before VM entry if a NMI delivery
2850                  * faulted.
2851                  */
2852                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
2853                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2854                                         GUEST_INTR_STATE_NMI);
2855                 else
2856                         vmx->vcpu.arch.nmi_injected = false;
2857         }
2858 }
2859
2860 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2861 {
2862         struct vcpu_vmx *vmx = to_vmx(vcpu);
2863         u32 idtv_info_field, intr_info_field;
2864         int vector;
2865
2866         update_tpr_threshold(vcpu);
2867
2868         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2869         idtv_info_field = vmx->idt_vectoring_info;
2870         if (intr_info_field & INTR_INFO_VALID_MASK) {
2871                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2872                         /* TODO: fault when IDT_Vectoring */
2873                         if (printk_ratelimit())
2874                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2875                 }
2876                 enable_intr_window(vcpu);
2877                 return;
2878         }
2879         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2880                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2881                     == INTR_TYPE_EXT_INTR
2882                     && vcpu->arch.rmode.active) {
2883                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2884
2885                         vmx_inject_irq(vcpu, vect);
2886                         enable_intr_window(vcpu);
2887                         return;
2888                 }
2889
2890                 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2891
2892                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field
2893                                 & ~INTR_INFO_RESVD_BITS_MASK);
2894                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2895                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2896
2897                 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2898                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2899                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2900                 enable_intr_window(vcpu);
2901                 return;
2902         }
2903         if (cpu_has_virtual_nmis()) {
2904                 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2905                         if (vmx_nmi_enabled(vcpu)) {
2906                                 vcpu->arch.nmi_pending = false;
2907                                 vcpu->arch.nmi_injected = true;
2908                         } else {
2909                                 enable_intr_window(vcpu);
2910                                 return;
2911                         }
2912                 }
2913                 if (vcpu->arch.nmi_injected) {
2914                         vmx_inject_nmi(vcpu);
2915                         enable_intr_window(vcpu);
2916                         return;
2917                 }
2918         }
2919         if (!kvm_cpu_has_interrupt(vcpu))
2920                 return;
2921         if (vmx_irq_enabled(vcpu)) {
2922                 vector = kvm_cpu_get_interrupt(vcpu);
2923                 vmx_inject_irq(vcpu, vector);
2924                 kvm_timer_intr_post(vcpu, vector);
2925         } else
2926                 enable_irq_window(vcpu);
2927 }
2928
2929 /*
2930  * Failure to inject an interrupt should give us the information
2931  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2932  * when fetching the interrupt redirection bitmap in the real-mode
2933  * tss, this doesn't happen.  So we do it ourselves.
2934  */
2935 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2936 {
2937         vmx->rmode.irq.pending = 0;
2938         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
2939                 return;
2940         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
2941         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2942                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2943                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2944                 return;
2945         }
2946         vmx->idt_vectoring_info =
2947                 VECTORING_INFO_VALID_MASK
2948                 | INTR_TYPE_EXT_INTR
2949                 | vmx->rmode.irq.vector;
2950 }
2951
2952 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2953 {
2954         struct vcpu_vmx *vmx = to_vmx(vcpu);
2955         u32 intr_info;
2956
2957         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
2958                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
2959         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
2960                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
2961
2962         /*
2963          * Loading guest fpu may have cleared host cr0.ts
2964          */
2965         vmcs_writel(HOST_CR0, read_cr0());
2966
2967         asm(
2968                 /* Store host registers */
2969 #ifdef CONFIG_X86_64
2970                 "push %%rdx; push %%rbp;"
2971                 "push %%rcx \n\t"
2972 #else
2973                 "push %%edx; push %%ebp;"
2974                 "push %%ecx \n\t"
2975 #endif
2976                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
2977                 /* Check if vmlaunch of vmresume is needed */
2978                 "cmpl $0, %c[launched](%0) \n\t"
2979                 /* Load guest registers.  Don't clobber flags. */
2980 #ifdef CONFIG_X86_64
2981                 "mov %c[cr2](%0), %%rax \n\t"
2982                 "mov %%rax, %%cr2 \n\t"
2983                 "mov %c[rax](%0), %%rax \n\t"
2984                 "mov %c[rbx](%0), %%rbx \n\t"
2985                 "mov %c[rdx](%0), %%rdx \n\t"
2986                 "mov %c[rsi](%0), %%rsi \n\t"
2987                 "mov %c[rdi](%0), %%rdi \n\t"
2988                 "mov %c[rbp](%0), %%rbp \n\t"
2989                 "mov %c[r8](%0),  %%r8  \n\t"
2990                 "mov %c[r9](%0),  %%r9  \n\t"
2991                 "mov %c[r10](%0), %%r10 \n\t"
2992                 "mov %c[r11](%0), %%r11 \n\t"
2993                 "mov %c[r12](%0), %%r12 \n\t"
2994                 "mov %c[r13](%0), %%r13 \n\t"
2995                 "mov %c[r14](%0), %%r14 \n\t"
2996                 "mov %c[r15](%0), %%r15 \n\t"
2997                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2998 #else
2999                 "mov %c[cr2](%0), %%eax \n\t"
3000                 "mov %%eax,   %%cr2 \n\t"
3001                 "mov %c[rax](%0), %%eax \n\t"
3002                 "mov %c[rbx](%0), %%ebx \n\t"
3003                 "mov %c[rdx](%0), %%edx \n\t"
3004                 "mov %c[rsi](%0), %%esi \n\t"
3005                 "mov %c[rdi](%0), %%edi \n\t"
3006                 "mov %c[rbp](%0), %%ebp \n\t"
3007                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
3008 #endif
3009                 /* Enter guest mode */
3010                 "jne .Llaunched \n\t"
3011                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3012                 "jmp .Lkvm_vmx_return \n\t"
3013                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3014                 ".Lkvm_vmx_return: "
3015                 /* Save guest registers, load host registers, keep flags */
3016 #ifdef CONFIG_X86_64
3017                 "xchg %0,     (%%rsp) \n\t"
3018                 "mov %%rax, %c[rax](%0) \n\t"
3019                 "mov %%rbx, %c[rbx](%0) \n\t"
3020                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
3021                 "mov %%rdx, %c[rdx](%0) \n\t"
3022                 "mov %%rsi, %c[rsi](%0) \n\t"
3023                 "mov %%rdi, %c[rdi](%0) \n\t"
3024                 "mov %%rbp, %c[rbp](%0) \n\t"
3025                 "mov %%r8,  %c[r8](%0) \n\t"
3026                 "mov %%r9,  %c[r9](%0) \n\t"
3027                 "mov %%r10, %c[r10](%0) \n\t"
3028                 "mov %%r11, %c[r11](%0) \n\t"
3029                 "mov %%r12, %c[r12](%0) \n\t"
3030                 "mov %%r13, %c[r13](%0) \n\t"
3031                 "mov %%r14, %c[r14](%0) \n\t"
3032                 "mov %%r15, %c[r15](%0) \n\t"
3033                 "mov %%cr2, %%rax   \n\t"
3034                 "mov %%rax, %c[cr2](%0) \n\t"
3035
3036                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
3037 #else
3038                 "xchg %0, (%%esp) \n\t"
3039                 "mov %%eax, %c[rax](%0) \n\t"
3040                 "mov %%ebx, %c[rbx](%0) \n\t"
3041                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
3042                 "mov %%edx, %c[rdx](%0) \n\t"
3043                 "mov %%esi, %c[rsi](%0) \n\t"
3044                 "mov %%edi, %c[rdi](%0) \n\t"
3045                 "mov %%ebp, %c[rbp](%0) \n\t"
3046                 "mov %%cr2, %%eax  \n\t"
3047                 "mov %%eax, %c[cr2](%0) \n\t"
3048
3049                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
3050 #endif
3051                 "setbe %c[fail](%0) \n\t"
3052               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3053                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3054                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3055                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3056                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3057                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3058                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3059                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3060                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3061                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3062 #ifdef CONFIG_X86_64
3063                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3064                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3065                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3066                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3067                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3068                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3069                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3070                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3071 #endif
3072                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3073               : "cc", "memory"
3074 #ifdef CONFIG_X86_64
3075                 , "rbx", "rdi", "rsi"
3076                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3077 #else
3078                 , "ebx", "edi", "rsi"
3079 #endif
3080               );
3081
3082         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3083         vcpu->arch.regs_dirty = 0;
3084
3085         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3086         if (vmx->rmode.irq.pending)
3087                 fixup_rmode_irq(vmx);
3088
3089         vcpu->arch.interrupt_window_open =
3090                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3091                  (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
3092
3093         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3094         vmx->launched = 1;
3095
3096         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3097
3098         /* We need to handle NMIs before interrupts are enabled */
3099         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3100             (intr_info & INTR_INFO_VALID_MASK)) {
3101                 KVMTRACE_0D(NMI, vcpu, handler);
3102                 asm("int $2");
3103         }
3104
3105         vmx_complete_interrupts(vmx);
3106 }
3107
3108 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3109 {
3110         struct vcpu_vmx *vmx = to_vmx(vcpu);
3111
3112         if (vmx->vmcs) {
3113                 vcpu_clear(vmx);
3114                 free_vmcs(vmx->vmcs);
3115                 vmx->vmcs = NULL;
3116         }
3117 }
3118
3119 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3120 {
3121         struct vcpu_vmx *vmx = to_vmx(vcpu);
3122
3123         spin_lock(&vmx_vpid_lock);
3124         if (vmx->vpid != 0)
3125                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3126         spin_unlock(&vmx_vpid_lock);
3127         vmx_free_vmcs(vcpu);
3128         kfree(vmx->host_msrs);
3129         kfree(vmx->guest_msrs);
3130         kvm_vcpu_uninit(vcpu);
3131         kmem_cache_free(kvm_vcpu_cache, vmx);
3132 }
3133
3134 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3135 {
3136         int err;
3137         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3138         int cpu;
3139
3140         if (!vmx)
3141                 return ERR_PTR(-ENOMEM);
3142
3143         allocate_vpid(vmx);
3144
3145         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3146         if (err)
3147                 goto free_vcpu;
3148
3149         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3150         if (!vmx->guest_msrs) {
3151                 err = -ENOMEM;
3152                 goto uninit_vcpu;
3153         }
3154
3155         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3156         if (!vmx->host_msrs)
3157                 goto free_guest_msrs;
3158
3159         vmx->vmcs = alloc_vmcs();
3160         if (!vmx->vmcs)
3161                 goto free_msrs;
3162
3163         vmcs_clear(vmx->vmcs);
3164
3165         cpu = get_cpu();
3166         vmx_vcpu_load(&vmx->vcpu, cpu);
3167         err = vmx_vcpu_setup(vmx);
3168         vmx_vcpu_put(&vmx->vcpu);
3169         put_cpu();
3170         if (err)
3171                 goto free_vmcs;
3172         if (vm_need_virtualize_apic_accesses(kvm))
3173                 if (alloc_apic_access_page(kvm) != 0)
3174                         goto free_vmcs;
3175
3176         if (vm_need_ept())
3177                 if (alloc_identity_pagetable(kvm) != 0)
3178                         goto free_vmcs;
3179
3180         return &vmx->vcpu;
3181
3182 free_vmcs:
3183         free_vmcs(vmx->vmcs);
3184 free_msrs:
3185         kfree(vmx->host_msrs);
3186 free_guest_msrs:
3187         kfree(vmx->guest_msrs);
3188 uninit_vcpu:
3189         kvm_vcpu_uninit(&vmx->vcpu);
3190 free_vcpu:
3191         kmem_cache_free(kvm_vcpu_cache, vmx);
3192         return ERR_PTR(err);
3193 }
3194
3195 static void __init vmx_check_processor_compat(void *rtn)
3196 {
3197         struct vmcs_config vmcs_conf;
3198
3199         *(int *)rtn = 0;
3200         if (setup_vmcs_config(&vmcs_conf) < 0)
3201                 *(int *)rtn = -EIO;
3202         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3203                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3204                                 smp_processor_id());
3205                 *(int *)rtn = -EIO;
3206         }
3207 }
3208
3209 static int get_ept_level(void)
3210 {
3211         return VMX_EPT_DEFAULT_GAW + 1;
3212 }
3213
3214 static struct kvm_x86_ops vmx_x86_ops = {
3215         .cpu_has_kvm_support = cpu_has_kvm_support,
3216         .disabled_by_bios = vmx_disabled_by_bios,
3217         .hardware_setup = hardware_setup,
3218         .hardware_unsetup = hardware_unsetup,
3219         .check_processor_compatibility = vmx_check_processor_compat,
3220         .hardware_enable = hardware_enable,
3221         .hardware_disable = hardware_disable,
3222         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3223
3224         .vcpu_create = vmx_create_vcpu,
3225         .vcpu_free = vmx_free_vcpu,
3226         .vcpu_reset = vmx_vcpu_reset,
3227
3228         .prepare_guest_switch = vmx_save_host_state,
3229         .vcpu_load = vmx_vcpu_load,
3230         .vcpu_put = vmx_vcpu_put,
3231
3232         .set_guest_debug = set_guest_debug,
3233         .guest_debug_pre = kvm_guest_debug_pre,
3234         .get_msr = vmx_get_msr,
3235         .set_msr = vmx_set_msr,
3236         .get_segment_base = vmx_get_segment_base,
3237         .get_segment = vmx_get_segment,
3238         .set_segment = vmx_set_segment,
3239         .get_cpl = vmx_get_cpl,
3240         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3241         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3242         .set_cr0 = vmx_set_cr0,
3243         .set_cr3 = vmx_set_cr3,
3244         .set_cr4 = vmx_set_cr4,
3245         .set_efer = vmx_set_efer,
3246         .get_idt = vmx_get_idt,
3247         .set_idt = vmx_set_idt,
3248         .get_gdt = vmx_get_gdt,
3249         .set_gdt = vmx_set_gdt,
3250         .cache_reg = vmx_cache_reg,
3251         .get_rflags = vmx_get_rflags,
3252         .set_rflags = vmx_set_rflags,
3253
3254         .tlb_flush = vmx_flush_tlb,
3255
3256         .run = vmx_vcpu_run,
3257         .handle_exit = kvm_handle_exit,
3258         .skip_emulated_instruction = skip_emulated_instruction,
3259         .patch_hypercall = vmx_patch_hypercall,
3260         .get_irq = vmx_get_irq,
3261         .set_irq = vmx_inject_irq,
3262         .queue_exception = vmx_queue_exception,
3263         .exception_injected = vmx_exception_injected,
3264         .inject_pending_irq = vmx_intr_assist,
3265         .inject_pending_vectors = do_interrupt_requests,
3266
3267         .set_tss_addr = vmx_set_tss_addr,
3268         .get_tdp_level = get_ept_level,
3269 };
3270
3271 static int __init vmx_init(void)
3272 {
3273         void *va;
3274         int r;
3275
3276         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3277         if (!vmx_io_bitmap_a)
3278                 return -ENOMEM;
3279
3280         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3281         if (!vmx_io_bitmap_b) {
3282                 r = -ENOMEM;
3283                 goto out;
3284         }
3285
3286         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3287         if (!vmx_msr_bitmap) {
3288                 r = -ENOMEM;
3289                 goto out1;
3290         }
3291
3292         /*
3293          * Allow direct access to the PC debug port (it is often used for I/O
3294          * delays, but the vmexits simply slow things down).
3295          */
3296         va = kmap(vmx_io_bitmap_a);
3297         memset(va, 0xff, PAGE_SIZE);
3298         clear_bit(0x80, va);
3299         kunmap(vmx_io_bitmap_a);
3300
3301         va = kmap(vmx_io_bitmap_b);
3302         memset(va, 0xff, PAGE_SIZE);
3303         kunmap(vmx_io_bitmap_b);
3304
3305         va = kmap(vmx_msr_bitmap);
3306         memset(va, 0xff, PAGE_SIZE);
3307         kunmap(vmx_msr_bitmap);
3308
3309         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3310
3311         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3312         if (r)
3313                 goto out2;
3314
3315         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3316         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3317         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3318         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3319         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3320
3321         if (vm_need_ept()) {
3322                 bypass_guest_pf = 0;
3323                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3324                         VMX_EPT_WRITABLE_MASK |
3325                         VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3326                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3327                                 VMX_EPT_EXECUTABLE_MASK);
3328                 kvm_enable_tdp();
3329         } else
3330                 kvm_disable_tdp();
3331
3332         if (bypass_guest_pf)
3333                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3334
3335         ept_sync_global();
3336
3337         return 0;
3338
3339 out2:
3340         __free_page(vmx_msr_bitmap);
3341 out1:
3342         __free_page(vmx_io_bitmap_b);
3343 out:
3344         __free_page(vmx_io_bitmap_a);
3345         return r;
3346 }
3347
3348 static void __exit vmx_exit(void)
3349 {
3350         __free_page(vmx_msr_bitmap);
3351         __free_page(vmx_io_bitmap_b);
3352         __free_page(vmx_io_bitmap_a);
3353
3354         kvm_exit();
3355 }
3356
3357 module_init(vmx_init)
3358 module_exit(vmx_exit)