SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 struct vmcs {
  65         u32 revision_id;
  66         u32 abort;
  67         char data[0];
  68 };
  69
  70 struct vcpu_vmx {
  71         struct kvm_vcpu       vcpu;
  72         struct list_head      local_vcpus_link;
  73         unsigned long         host_rsp;
  74         int                   launched;
  75         u8                    fail;
  76         u32                   idt_vectoring_info;
  77         struct kvm_msr_entry *guest_msrs;
  78         struct kvm_msr_entry *host_msrs;
  79         int                   nmsrs;
  80         int                   save_nmsrs;
  81         int                   msr_offset_efer;
  82 #ifdef CONFIG_X86_64
  83         int                   msr_offset_kernel_gs_base;
  84 #endif
  85         struct vmcs          *vmcs;
  86         struct {
  87                 int           loaded;
  88                 u16           fs_sel, gs_sel, ldt_sel;
  89                 int           gs_ldt_reload_needed;
  90                 int           fs_reload_needed;
  91                 int           guest_efer_loaded;
  92         } host_state;
  93         struct {
  94                 int vm86_active;
  95                 u8 save_iopl;
  96                 struct kvm_save_segment {
  97                         u16 selector;
  98                         unsigned long base;
  99                         u32 limit;
 100                         u32 ar;
 101                 } tr, es, ds, fs, gs;
 102                 struct {
 103                         bool pending;
 104                         u8 vector;
 105                         unsigned rip;
 106                 } irq;
 107         } rmode;
 108         int vpid;
 109         bool emulation_required;
 110
 111         /* Support for vnmi-less CPUs */
 112         int soft_vnmi_blocked;
 113         ktime_t entry_time;
 114         s64 vnmi_blocked_time;
 115         u32 exit_reason;
 116 };
 117
 118 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 119 {
 120         return container_of(vcpu, struct vcpu_vmx, vcpu);
 121 }
 122
 123 static int init_rmode(struct kvm *kvm);
 124 static u64 construct_eptp(unsigned long root_hpa);
 125
 126 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 127 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 128 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 129
 130 static unsigned long *vmx_io_bitmap_a;
 131 static unsigned long *vmx_io_bitmap_b;
 132 static unsigned long *vmx_msr_bitmap_legacy;
 133 static unsigned long *vmx_msr_bitmap_longmode;
 134
 135 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 136 static DEFINE_SPINLOCK(vmx_vpid_lock);
 137
 138 static struct vmcs_config {
 139         int size;
 140         int order;
 141         u32 revision_id;
 142         u32 pin_based_exec_ctrl;
 143         u32 cpu_based_exec_ctrl;
 144         u32 cpu_based_2nd_exec_ctrl;
 145         u32 vmexit_ctrl;
 146         u32 vmentry_ctrl;
 147 } vmcs_config;
 148
 149 static struct vmx_capability {
 150         u32 ept;
 151         u32 vpid;
 152 } vmx_capability;
 153
 154 #define VMX_SEGMENT_FIELD(seg)                                  \
 155         [VCPU_SREG_##seg] = {                                   \
 156                 .selector = GUEST_##seg##_SELECTOR,             \
 157                 .base = GUEST_##seg##_BASE,                     \
 158                 .limit = GUEST_##seg##_LIMIT,                   \
 159                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 160         }
 161
 162 static struct kvm_vmx_segment_field {
 163         unsigned selector;
 164         unsigned base;
 165         unsigned limit;
 166         unsigned ar_bytes;
 167 } kvm_vmx_segment_fields[] = {
 168         VMX_SEGMENT_FIELD(CS),
 169         VMX_SEGMENT_FIELD(DS),
 170         VMX_SEGMENT_FIELD(ES),
 171         VMX_SEGMENT_FIELD(FS),
 172         VMX_SEGMENT_FIELD(GS),
 173         VMX_SEGMENT_FIELD(SS),
 174         VMX_SEGMENT_FIELD(TR),
 175         VMX_SEGMENT_FIELD(LDTR),
 176 };
 177
 178 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 179
 180 /*
 181  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 182  * away by decrementing the array size.
 183  */
 184 static const u32 vmx_msr_index[] = {
 185 #ifdef CONFIG_X86_64
 186         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 187 #endif
 188         MSR_EFER, MSR_K6_STAR,
 189 };
 190 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 191
 192 static void load_msrs(struct kvm_msr_entry *e, int n)
 193 {
 194         int i;
 195
 196         for (i = 0; i < n; ++i)
 197                 wrmsrl(e[i].index, e[i].data);
 198 }
 199
 200 static void save_msrs(struct kvm_msr_entry *e, int n)
 201 {
 202         int i;
 203
 204         for (i = 0; i < n; ++i)
 205                 rdmsrl(e[i].index, e[i].data);
 206 }
 207
 208 static inline int is_page_fault(u32 intr_info)
 209 {
 210         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 211                              INTR_INFO_VALID_MASK)) ==
 212                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 213 }
 214
 215 static inline int is_no_device(u32 intr_info)
 216 {
 217         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 218                              INTR_INFO_VALID_MASK)) ==
 219                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 220 }
 221
 222 static inline int is_invalid_opcode(u32 intr_info)
 223 {
 224         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 225                              INTR_INFO_VALID_MASK)) ==
 226                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 227 }
 228
 229 static inline int is_external_interrupt(u32 intr_info)
 230 {
 231         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 232                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 233 }
 234
 235 static inline int is_machine_check(u32 intr_info)
 236 {
 237         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 238                              INTR_INFO_VALID_MASK)) ==
 239                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 240 }
 241
 242 static inline int cpu_has_vmx_msr_bitmap(void)
 243 {
 244         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 245 }
 246
 247 static inline int cpu_has_vmx_tpr_shadow(void)
 248 {
 249         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 250 }
 251
 252 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 253 {
 254         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 255 }
 256
 257 static inline int cpu_has_secondary_exec_ctrls(void)
 258 {
 259         return vmcs_config.cpu_based_exec_ctrl &
 260                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 261 }
 262
 263 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 264 {
 265         return vmcs_config.cpu_based_2nd_exec_ctrl &
 266                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 267 }
 268
 269 static inline bool cpu_has_vmx_flexpriority(void)
 270 {
 271         return cpu_has_vmx_tpr_shadow() &&
 272                 cpu_has_vmx_virtualize_apic_accesses();
 273 }
 274
 275 static inline bool cpu_has_vmx_ept_execute_only(void)
 276 {
 277         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 278 }
 279
 280 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 281 {
 282         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 283 }
 284
 285 static inline bool cpu_has_vmx_eptp_writeback(void)
 286 {
 287         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 288 }
 289
 290 static inline bool cpu_has_vmx_ept_2m_page(void)
 291 {
 292         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 293 }
 294
 295 static inline int cpu_has_vmx_invept_individual_addr(void)
 296 {
 297         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 298 }
 299
 300 static inline int cpu_has_vmx_invept_context(void)
 301 {
 302         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 303 }
 304
 305 static inline int cpu_has_vmx_invept_global(void)
 306 {
 307         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 308 }
 309
 310 static inline int cpu_has_vmx_ept(void)
 311 {
 312         return vmcs_config.cpu_based_2nd_exec_ctrl &
 313                 SECONDARY_EXEC_ENABLE_EPT;
 314 }
 315
 316 static inline int cpu_has_vmx_unrestricted_guest(void)
 317 {
 318         return vmcs_config.cpu_based_2nd_exec_ctrl &
 319                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 320 }
 321
 322 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 323 {
 324         return flexpriority_enabled &&
 325                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 326                 (irqchip_in_kernel(kvm));
 327 }
 328
 329 static inline int cpu_has_vmx_vpid(void)
 330 {
 331         return vmcs_config.cpu_based_2nd_exec_ctrl &
 332                 SECONDARY_EXEC_ENABLE_VPID;
 333 }
 334
 335 static inline int cpu_has_virtual_nmis(void)
 336 {
 337         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 338 }
 339
 340 static inline bool report_flexpriority(void)
 341 {
 342         return flexpriority_enabled;
 343 }
 344
 345 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 346 {
 347         int i;
 348
 349         for (i = 0; i < vmx->nmsrs; ++i)
 350                 if (vmx->guest_msrs[i].index == msr)
 351                         return i;
 352         return -1;
 353 }
 354
 355 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 356 {
 357     struct {
 358         u64 vpid : 16;
 359         u64 rsvd : 48;
 360         u64 gva;
 361     } operand = { vpid, 0, gva };
 362
 363     asm volatile (__ex(ASM_VMX_INVVPID)
 364                   /* CF==1 or ZF==1 --> rc = -1 */
 365                   "; ja 1f ; ud2 ; 1:"
 366                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 367 }
 368
 369 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 370 {
 371         struct {
 372                 u64 eptp, gpa;
 373         } operand = {eptp, gpa};
 374
 375         asm volatile (__ex(ASM_VMX_INVEPT)
 376                         /* CF==1 or ZF==1 --> rc = -1 */
 377                         "; ja 1f ; ud2 ; 1:\n"
 378                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 379 }
 380
 381 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 382 {
 383         int i;
 384
 385         i = __find_msr_index(vmx, msr);
 386         if (i >= 0)
 387                 return &vmx->guest_msrs[i];
 388         return NULL;
 389 }
 390
 391 static void vmcs_clear(struct vmcs *vmcs)
 392 {
 393         u64 phys_addr = __pa(vmcs);
 394         u8 error;
 395
 396         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 397                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 398                       : "cc", "memory");
 399         if (error)
 400                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 401                        vmcs, phys_addr);
 402 }
 403
 404 static void __vcpu_clear(void *arg)
 405 {
 406         struct vcpu_vmx *vmx = arg;
 407         int cpu = raw_smp_processor_id();
 408
 409         if (vmx->vcpu.cpu == cpu)
 410                 vmcs_clear(vmx->vmcs);
 411         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 412                 per_cpu(current_vmcs, cpu) = NULL;
 413         rdtscll(vmx->vcpu.arch.host_tsc);
 414         list_del(&vmx->local_vcpus_link);
 415         vmx->vcpu.cpu = -1;
 416         vmx->launched = 0;
 417 }
 418
 419 static void vcpu_clear(struct vcpu_vmx *vmx)
 420 {
 421         if (vmx->vcpu.cpu == -1)
 422                 return;
 423         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 424 }
 425
 426 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 427 {
 428         if (vmx->vpid == 0)
 429                 return;
 430
 431         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 432 }
 433
 434 static inline void ept_sync_global(void)
 435 {
 436         if (cpu_has_vmx_invept_global())
 437                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 438 }
 439
 440 static inline void ept_sync_context(u64 eptp)
 441 {
 442         if (enable_ept) {
 443                 if (cpu_has_vmx_invept_context())
 444                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 445                 else
 446                         ept_sync_global();
 447         }
 448 }
 449
 450 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 451 {
 452         if (enable_ept) {
 453                 if (cpu_has_vmx_invept_individual_addr())
 454                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 455                                         eptp, gpa);
 456                 else
 457                         ept_sync_context(eptp);
 458         }
 459 }
 460
 461 static unsigned long vmcs_readl(unsigned long field)
 462 {
 463         unsigned long value;
 464
 465         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 466                       : "=a"(value) : "d"(field) : "cc");
 467         return value;
 468 }
 469
 470 static u16 vmcs_read16(unsigned long field)
 471 {
 472         return vmcs_readl(field);
 473 }
 474
 475 static u32 vmcs_read32(unsigned long field)
 476 {
 477         return vmcs_readl(field);
 478 }
 479
 480 static u64 vmcs_read64(unsigned long field)
 481 {
 482 #ifdef CONFIG_X86_64
 483         return vmcs_readl(field);
 484 #else
 485         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 486 #endif
 487 }
 488
 489 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 490 {
 491         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 492                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 493         dump_stack();
 494 }
 495
 496 static void vmcs_writel(unsigned long field, unsigned long value)
 497 {
 498         u8 error;
 499
 500         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 501                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 502         if (unlikely(error))
 503                 vmwrite_error(field, value);
 504 }
 505
 506 static void vmcs_write16(unsigned long field, u16 value)
 507 {
 508         vmcs_writel(field, value);
 509 }
 510
 511 static void vmcs_write32(unsigned long field, u32 value)
 512 {
 513         vmcs_writel(field, value);
 514 }
 515
 516 static void vmcs_write64(unsigned long field, u64 value)
 517 {
 518         vmcs_writel(field, value);
 519 #ifndef CONFIG_X86_64
 520         asm volatile ("");
 521         vmcs_writel(field+1, value >> 32);
 522 #endif
 523 }
 524
 525 static void vmcs_clear_bits(unsigned long field, u32 mask)
 526 {
 527         vmcs_writel(field, vmcs_readl(field) & ~mask);
 528 }
 529
 530 static void vmcs_set_bits(unsigned long field, u32 mask)
 531 {
 532         vmcs_writel(field, vmcs_readl(field) | mask);
 533 }
 534
 535 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 536 {
 537         u32 eb;
 538
 539         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 540         if (!vcpu->fpu_active)
 541                 eb |= 1u << NM_VECTOR;
 542         /*
 543          * Unconditionally intercept #DB so we can maintain dr6 without
 544          * reading it every exit.
 545          */
 546         eb |= 1u << DB_VECTOR;
 547         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 548                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 549                         eb |= 1u << BP_VECTOR;
 550         }
 551         if (to_vmx(vcpu)->rmode.vm86_active)
 552                 eb = ~0;
 553         if (enable_ept)
 554                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 555         vmcs_write32(EXCEPTION_BITMAP, eb);
 556 }
 557
 558 static void reload_tss(void)
 559 {
 560         /*
 561          * VT restores TR but not its size.  Useless.
 562          */
 563         struct descriptor_table gdt;
 564         struct desc_struct *descs;
 565
 566         kvm_get_gdt(&gdt);
 567         descs = (void *)gdt.base;
 568         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 569         load_TR_desc();
 570 }
 571
 572 static void load_transition_efer(struct vcpu_vmx *vmx)
 573 {
 574         int efer_offset = vmx->msr_offset_efer;
 575         u64 host_efer;
 576         u64 guest_efer;
 577         u64 ignore_bits;
 578
 579         if (efer_offset < 0)
 580                 return;
 581         host_efer = vmx->host_msrs[efer_offset].data;
 582         guest_efer = vmx->guest_msrs[efer_offset].data;
 583
 584         /*
 585          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 586          * outside long mode
 587          */
 588         ignore_bits = EFER_NX | EFER_SCE;
 589 #ifdef CONFIG_X86_64
 590         ignore_bits |= EFER_LMA | EFER_LME;
 591         /* SCE is meaningful only in long mode on Intel */
 592         if (guest_efer & EFER_LMA)
 593                 ignore_bits &= ~(u64)EFER_SCE;
 594 #endif
 595         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 596                 return;
 597
 598         vmx->host_state.guest_efer_loaded = 1;
 599         guest_efer &= ~ignore_bits;
 600         guest_efer |= host_efer & ignore_bits;
 601         wrmsrl(MSR_EFER, guest_efer);
 602         vmx->vcpu.stat.efer_reload++;
 603 }
 604
 605 static void reload_host_efer(struct vcpu_vmx *vmx)
 606 {
 607         if (vmx->host_state.guest_efer_loaded) {
 608                 vmx->host_state.guest_efer_loaded = 0;
 609                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 610         }
 611 }
 612
 613 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 614 {
 615         struct vcpu_vmx *vmx = to_vmx(vcpu);
 616
 617         if (vmx->host_state.loaded)
 618                 return;
 619
 620         vmx->host_state.loaded = 1;
 621         /*
 622          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 623          * allow segment selectors with cpl > 0 or ti == 1.
 624          */
 625         vmx->host_state.ldt_sel = kvm_read_ldt();
 626         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 627         vmx->host_state.fs_sel = kvm_read_fs();
 628         if (!(vmx->host_state.fs_sel & 7)) {
 629                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 630                 vmx->host_state.fs_reload_needed = 0;
 631         } else {
 632                 vmcs_write16(HOST_FS_SELECTOR, 0);
 633                 vmx->host_state.fs_reload_needed = 1;
 634         }
 635         vmx->host_state.gs_sel = kvm_read_gs();
 636         if (!(vmx->host_state.gs_sel & 7))
 637                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 638         else {
 639                 vmcs_write16(HOST_GS_SELECTOR, 0);
 640                 vmx->host_state.gs_ldt_reload_needed = 1;
 641         }
 642
 643 #ifdef CONFIG_X86_64
 644         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 645         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 646 #else
 647         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 648         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 649 #endif
 650
 651 #ifdef CONFIG_X86_64
 652         if (is_long_mode(&vmx->vcpu))
 653                 save_msrs(vmx->host_msrs +
 654                           vmx->msr_offset_kernel_gs_base, 1);
 655
 656 #endif
 657         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 658         load_transition_efer(vmx);
 659 }
 660
 661 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 662 {
 663         unsigned long flags;
 664
 665         if (!vmx->host_state.loaded)
 666                 return;
 667
 668         ++vmx->vcpu.stat.host_state_reload;
 669         vmx->host_state.loaded = 0;
 670         if (vmx->host_state.fs_reload_needed)
 671                 kvm_load_fs(vmx->host_state.fs_sel);
 672         if (vmx->host_state.gs_ldt_reload_needed) {
 673                 kvm_load_ldt(vmx->host_state.ldt_sel);
 674                 /*
 675                  * If we have to reload gs, we must take care to
 676                  * preserve our gs base.
 677                  */
 678                 local_irq_save(flags);
 679                 kvm_load_gs(vmx->host_state.gs_sel);
 680 #ifdef CONFIG_X86_64
 681                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 682 #endif
 683                 local_irq_restore(flags);
 684         }
 685         reload_tss();
 686         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 687         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 688         reload_host_efer(vmx);
 689 }
 690
 691 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 692 {
 693         preempt_disable();
 694         __vmx_load_host_state(vmx);
 695         preempt_enable();
 696 }
 697
 698 /*
 699  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 700  * vcpu mutex is already taken.
 701  */
 702 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 703 {
 704         struct vcpu_vmx *vmx = to_vmx(vcpu);
 705         u64 phys_addr = __pa(vmx->vmcs);
 706         u64 tsc_this, delta, new_offset;
 707
 708         if (vcpu->cpu != cpu) {
 709                 vcpu_clear(vmx);
 710                 kvm_migrate_timers(vcpu);
 711                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 712                 local_irq_disable();
 713                 list_add(&vmx->local_vcpus_link,
 714                          &per_cpu(vcpus_on_cpu, cpu));
 715                 local_irq_enable();
 716         }
 717
 718         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 719                 u8 error;
 720
 721                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 722                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 723                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 724                               : "cc");
 725                 if (error)
 726                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 727                                vmx->vmcs, phys_addr);
 728         }
 729
 730         if (vcpu->cpu != cpu) {
 731                 struct descriptor_table dt;
 732                 unsigned long sysenter_esp;
 733
 734                 vcpu->cpu = cpu;
 735                 /*
 736                  * Linux uses per-cpu TSS and GDT, so set these when switching
 737                  * processors.
 738                  */
 739                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 740                 kvm_get_gdt(&dt);
 741                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 742
 743                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 744                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 745
 746                 /*
 747                  * Make sure the time stamp counter is monotonous.
 748                  */
 749                 rdtscll(tsc_this);
 750                 if (tsc_this < vcpu->arch.host_tsc) {
 751                         delta = vcpu->arch.host_tsc - tsc_this;
 752                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 753                         vmcs_write64(TSC_OFFSET, new_offset);
 754                 }
 755         }
 756 }
 757
 758 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 759 {
 760         __vmx_load_host_state(to_vmx(vcpu));
 761 }
 762
 763 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 764 {
 765         if (vcpu->fpu_active)
 766                 return;
 767         vcpu->fpu_active = 1;
 768         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 769         if (vcpu->arch.cr0 & X86_CR0_TS)
 770                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 771         update_exception_bitmap(vcpu);
 772 }
 773
 774 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 775 {
 776         if (!vcpu->fpu_active)
 777                 return;
 778         vcpu->fpu_active = 0;
 779         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 780         update_exception_bitmap(vcpu);
 781 }
 782
 783 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 784 {
 785         unsigned long rflags;
 786
 787         rflags = vmcs_readl(GUEST_RFLAGS);
 788         if (to_vmx(vcpu)->rmode.vm86_active)
 789                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 790         return rflags;
 791 }
 792
 793 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 794 {
 795         if (to_vmx(vcpu)->rmode.vm86_active)
 796                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 797         vmcs_writel(GUEST_RFLAGS, rflags);
 798 }
 799
 800 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 801 {
 802         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 803         int ret = 0;
 804
 805         if (interruptibility & GUEST_INTR_STATE_STI)
 806                 ret |= X86_SHADOW_INT_STI;
 807         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 808                 ret |= X86_SHADOW_INT_MOV_SS;
 809
 810         return ret & mask;
 811 }
 812
 813 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 814 {
 815         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 816         u32 interruptibility = interruptibility_old;
 817
 818         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 819
 820         if (mask & X86_SHADOW_INT_MOV_SS)
 821                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 822         if (mask & X86_SHADOW_INT_STI)
 823                 interruptibility |= GUEST_INTR_STATE_STI;
 824
 825         if ((interruptibility != interruptibility_old))
 826                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 827 }
 828
 829 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 830 {
 831         unsigned long rip;
 832
 833         rip = kvm_rip_read(vcpu);
 834         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 835         kvm_rip_write(vcpu, rip);
 836
 837         /* skipping an emulated instruction also counts */
 838         vmx_set_interrupt_shadow(vcpu, 0);
 839 }
 840
 841 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 842                                 bool has_error_code, u32 error_code)
 843 {
 844         struct vcpu_vmx *vmx = to_vmx(vcpu);
 845         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 846
 847         if (has_error_code) {
 848                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 849                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 850         }
 851
 852         if (vmx->rmode.vm86_active) {
 853                 vmx->rmode.irq.pending = true;
 854                 vmx->rmode.irq.vector = nr;
 855                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 856                 if (kvm_exception_is_soft(nr))
 857                         vmx->rmode.irq.rip +=
 858                                 vmx->vcpu.arch.event_exit_inst_len;
 859                 intr_info |= INTR_TYPE_SOFT_INTR;
 860                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 861                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 862                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 863                 return;
 864         }
 865
 866         if (kvm_exception_is_soft(nr)) {
 867                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 868                              vmx->vcpu.arch.event_exit_inst_len);
 869                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 870         } else
 871                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 872
 873         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 874 }
 875
 876 /*
 877  * Swap MSR entry in host/guest MSR entry array.
 878  */
 879 #ifdef CONFIG_X86_64
 880 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 881 {
 882         struct kvm_msr_entry tmp;
 883
 884         tmp = vmx->guest_msrs[to];
 885         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 886         vmx->guest_msrs[from] = tmp;
 887         tmp = vmx->host_msrs[to];
 888         vmx->host_msrs[to] = vmx->host_msrs[from];
 889         vmx->host_msrs[from] = tmp;
 890 }
 891 #endif
 892
 893 /*
 894  * Set up the vmcs to automatically save and restore system
 895  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 896  * mode, as fiddling with msrs is very expensive.
 897  */
 898 static void setup_msrs(struct vcpu_vmx *vmx)
 899 {
 900         int save_nmsrs;
 901         unsigned long *msr_bitmap;
 902
 903         vmx_load_host_state(vmx);
 904         save_nmsrs = 0;
 905 #ifdef CONFIG_X86_64
 906         if (is_long_mode(&vmx->vcpu)) {
 907                 int index;
 908
 909                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 910                 if (index >= 0)
 911                         move_msr_up(vmx, index, save_nmsrs++);
 912                 index = __find_msr_index(vmx, MSR_LSTAR);
 913                 if (index >= 0)
 914                         move_msr_up(vmx, index, save_nmsrs++);
 915                 index = __find_msr_index(vmx, MSR_CSTAR);
 916                 if (index >= 0)
 917                         move_msr_up(vmx, index, save_nmsrs++);
 918                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 919                 if (index >= 0)
 920                         move_msr_up(vmx, index, save_nmsrs++);
 921                 /*
 922                  * MSR_K6_STAR is only needed on long mode guests, and only
 923                  * if efer.sce is enabled.
 924                  */
 925                 index = __find_msr_index(vmx, MSR_K6_STAR);
 926                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 927                         move_msr_up(vmx, index, save_nmsrs++);
 928         }
 929 #endif
 930         vmx->save_nmsrs = save_nmsrs;
 931
 932 #ifdef CONFIG_X86_64
 933         vmx->msr_offset_kernel_gs_base =
 934                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 935 #endif
 936         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 937
 938         if (cpu_has_vmx_msr_bitmap()) {
 939                 if (is_long_mode(&vmx->vcpu))
 940                         msr_bitmap = vmx_msr_bitmap_longmode;
 941                 else
 942                         msr_bitmap = vmx_msr_bitmap_legacy;
 943
 944                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 945         }
 946 }
 947
 948 /*
 949  * reads and returns guest's timestamp counter "register"
 950  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 951  */
 952 static u64 guest_read_tsc(void)
 953 {
 954         u64 host_tsc, tsc_offset;
 955
 956         rdtscll(host_tsc);
 957         tsc_offset = vmcs_read64(TSC_OFFSET);
 958         return host_tsc + tsc_offset;
 959 }
 960
 961 /*
 962  * writes 'guest_tsc' into guest's timestamp counter "register"
 963  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 964  */
 965 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 966 {
 967         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 968 }
 969
 970 /*
 971  * Reads an msr value (of 'msr_index') into 'pdata'.
 972  * Returns 0 on success, non-0 otherwise.
 973  * Assumes vcpu_load() was already called.
 974  */
 975 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 976 {
 977         u64 data;
 978         struct kvm_msr_entry *msr;
 979
 980         if (!pdata) {
 981                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 982                 return -EINVAL;
 983         }
 984
 985         switch (msr_index) {
 986 #ifdef CONFIG_X86_64
 987         case MSR_FS_BASE:
 988                 data = vmcs_readl(GUEST_FS_BASE);
 989                 break;
 990         case MSR_GS_BASE:
 991                 data = vmcs_readl(GUEST_GS_BASE);
 992                 break;
 993         case MSR_EFER:
 994                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 995 #endif
 996         case MSR_IA32_TSC:
 997                 data = guest_read_tsc();
 998                 break;
 999         case MSR_IA32_SYSENTER_CS:
1000                 data = vmcs_read32(GUEST_SYSENTER_CS);
1001                 break;
1002         case MSR_IA32_SYSENTER_EIP:
1003                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1004                 break;
1005         case MSR_IA32_SYSENTER_ESP:
1006                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1007                 break;
1008         default:
1009                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1010                 if (msr) {
1011                         vmx_load_host_state(to_vmx(vcpu));
1012                         data = msr->data;
1013                         break;
1014                 }
1015                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1016         }
1017
1018         *pdata = data;
1019         return 0;
1020 }
1021
1022 /*
1023  * Writes msr value into into the appropriate "register".
1024  * Returns 0 on success, non-0 otherwise.
1025  * Assumes vcpu_load() was already called.
1026  */
1027 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1028 {
1029         struct vcpu_vmx *vmx = to_vmx(vcpu);
1030         struct kvm_msr_entry *msr;
1031         u64 host_tsc;
1032         int ret = 0;
1033
1034         switch (msr_index) {
1035         case MSR_EFER:
1036                 vmx_load_host_state(vmx);
1037                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1038                 break;
1039 #ifdef CONFIG_X86_64
1040         case MSR_FS_BASE:
1041                 vmcs_writel(GUEST_FS_BASE, data);
1042                 break;
1043         case MSR_GS_BASE:
1044                 vmcs_writel(GUEST_GS_BASE, data);
1045                 break;
1046 #endif
1047         case MSR_IA32_SYSENTER_CS:
1048                 vmcs_write32(GUEST_SYSENTER_CS, data);
1049                 break;
1050         case MSR_IA32_SYSENTER_EIP:
1051                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1052                 break;
1053         case MSR_IA32_SYSENTER_ESP:
1054                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1055                 break;
1056         case MSR_IA32_TSC:
1057                 rdtscll(host_tsc);
1058                 guest_write_tsc(data, host_tsc);
1059                 break;
1060         case MSR_IA32_CR_PAT:
1061                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1062                         vmcs_write64(GUEST_IA32_PAT, data);
1063                         vcpu->arch.pat = data;
1064                         break;
1065                 }
1066                 /* Otherwise falls through to kvm_set_msr_common */
1067         default:
1068                 msr = find_msr_entry(vmx, msr_index);
1069                 if (msr) {
1070                         vmx_load_host_state(vmx);
1071                         msr->data = data;
1072                         break;
1073                 }
1074                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1075         }
1076
1077         return ret;
1078 }
1079
1080 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1081 {
1082         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1083         switch (reg) {
1084         case VCPU_REGS_RSP:
1085                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1086                 break;
1087         case VCPU_REGS_RIP:
1088                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1089                 break;
1090         case VCPU_EXREG_PDPTR:
1091                 if (enable_ept)
1092                         ept_save_pdptrs(vcpu);
1093                 break;
1094         default:
1095                 break;
1096         }
1097 }
1098
1099 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1100 {
1101         int old_debug = vcpu->guest_debug;
1102         unsigned long flags;
1103
1104         vcpu->guest_debug = dbg->control;
1105         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1106                 vcpu->guest_debug = 0;
1107
1108         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1109                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1110         else
1111                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1112
1113         flags = vmcs_readl(GUEST_RFLAGS);
1114         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1115                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1116         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1117                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1118         vmcs_writel(GUEST_RFLAGS, flags);
1119
1120         update_exception_bitmap(vcpu);
1121
1122         return 0;
1123 }
1124
1125 static __init int cpu_has_kvm_support(void)
1126 {
1127         return cpu_has_vmx();
1128 }
1129
1130 static __init int vmx_disabled_by_bios(void)
1131 {
1132         u64 msr;
1133
1134         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1135         return (msr & (FEATURE_CONTROL_LOCKED |
1136                        FEATURE_CONTROL_VMXON_ENABLED))
1137             == FEATURE_CONTROL_LOCKED;
1138         /* locked but not enabled */
1139 }
1140
1141 static int hardware_enable(void *garbage)
1142 {
1143         int cpu = raw_smp_processor_id();
1144         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1145         u64 old;
1146
1147         if (read_cr4() & X86_CR4_VMXE)
1148                 return -EBUSY;
1149
1150         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1151         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1152         if ((old & (FEATURE_CONTROL_LOCKED |
1153                     FEATURE_CONTROL_VMXON_ENABLED))
1154             != (FEATURE_CONTROL_LOCKED |
1155                 FEATURE_CONTROL_VMXON_ENABLED))
1156                 /* enable and lock */
1157                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1158                        FEATURE_CONTROL_LOCKED |
1159                        FEATURE_CONTROL_VMXON_ENABLED);
1160         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1161         asm volatile (ASM_VMX_VMXON_RAX
1162                       : : "a"(&phys_addr), "m"(phys_addr)
1163                       : "memory", "cc");
1164
1165         ept_sync_global();
1166
1167         return 0;
1168 }
1169
1170 static void vmclear_local_vcpus(void)
1171 {
1172         int cpu = raw_smp_processor_id();
1173         struct vcpu_vmx *vmx, *n;
1174
1175         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1176                                  local_vcpus_link)
1177                 __vcpu_clear(vmx);
1178 }
1179
1180
1181 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1182  * tricks.
1183  */
1184 static void kvm_cpu_vmxoff(void)
1185 {
1186         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1187         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1188 }
1189
1190 static void hardware_disable(void *garbage)
1191 {
1192         vmclear_local_vcpus();
1193         kvm_cpu_vmxoff();
1194 }
1195
1196 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1197                                       u32 msr, u32 *result)
1198 {
1199         u32 vmx_msr_low, vmx_msr_high;
1200         u32 ctl = ctl_min | ctl_opt;
1201
1202         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1203
1204         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1205         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1206
1207         /* Ensure minimum (required) set of control bits are supported. */
1208         if (ctl_min & ~ctl)
1209                 return -EIO;
1210
1211         *result = ctl;
1212         return 0;
1213 }
1214
1215 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1216 {
1217         u32 vmx_msr_low, vmx_msr_high;
1218         u32 min, opt, min2, opt2;
1219         u32 _pin_based_exec_control = 0;
1220         u32 _cpu_based_exec_control = 0;
1221         u32 _cpu_based_2nd_exec_control = 0;
1222         u32 _vmexit_control = 0;
1223         u32 _vmentry_control = 0;
1224
1225         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1226         opt = PIN_BASED_VIRTUAL_NMIS;
1227         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1228                                 &_pin_based_exec_control) < 0)
1229                 return -EIO;
1230
1231         min = CPU_BASED_HLT_EXITING |
1232 #ifdef CONFIG_X86_64
1233               CPU_BASED_CR8_LOAD_EXITING |
1234               CPU_BASED_CR8_STORE_EXITING |
1235 #endif
1236               CPU_BASED_CR3_LOAD_EXITING |
1237               CPU_BASED_CR3_STORE_EXITING |
1238               CPU_BASED_USE_IO_BITMAPS |
1239               CPU_BASED_MOV_DR_EXITING |
1240               CPU_BASED_USE_TSC_OFFSETING |
1241               CPU_BASED_INVLPG_EXITING;
1242         opt = CPU_BASED_TPR_SHADOW |
1243               CPU_BASED_USE_MSR_BITMAPS |
1244               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1245         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1246                                 &_cpu_based_exec_control) < 0)
1247                 return -EIO;
1248 #ifdef CONFIG_X86_64
1249         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1250                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1251                                            ~CPU_BASED_CR8_STORE_EXITING;
1252 #endif
1253         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1254                 min2 = 0;
1255                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1256                         SECONDARY_EXEC_WBINVD_EXITING |
1257                         SECONDARY_EXEC_ENABLE_VPID |
1258                         SECONDARY_EXEC_ENABLE_EPT |
1259                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
1260                 if (adjust_vmx_controls(min2, opt2,
1261                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1262                                         &_cpu_based_2nd_exec_control) < 0)
1263                         return -EIO;
1264         }
1265 #ifndef CONFIG_X86_64
1266         if (!(_cpu_based_2nd_exec_control &
1267                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1268                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1269 #endif
1270         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1271                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1272                    enabled */
1273                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1274                                              CPU_BASED_CR3_STORE_EXITING |
1275                                              CPU_BASED_INVLPG_EXITING);
1276                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1277                       vmx_capability.ept, vmx_capability.vpid);
1278         }
1279
1280         min = 0;
1281 #ifdef CONFIG_X86_64
1282         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1283 #endif
1284         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1285         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1286                                 &_vmexit_control) < 0)
1287                 return -EIO;
1288
1289         min = 0;
1290         opt = VM_ENTRY_LOAD_IA32_PAT;
1291         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1292                                 &_vmentry_control) < 0)
1293                 return -EIO;
1294
1295         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1296
1297         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1298         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1299                 return -EIO;
1300
1301 #ifdef CONFIG_X86_64
1302         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1303         if (vmx_msr_high & (1u<<16))
1304                 return -EIO;
1305 #endif
1306
1307         /* Require Write-Back (WB) memory type for VMCS accesses. */
1308         if (((vmx_msr_high >> 18) & 15) != 6)
1309                 return -EIO;
1310
1311         vmcs_conf->size = vmx_msr_high & 0x1fff;
1312         vmcs_conf->order = get_order(vmcs_config.size);
1313         vmcs_conf->revision_id = vmx_msr_low;
1314
1315         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1316         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1317         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1318         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1319         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1320
1321         return 0;
1322 }
1323
1324 static struct vmcs *alloc_vmcs_cpu(int cpu)
1325 {
1326         int node = cpu_to_node(cpu);
1327         struct page *pages;
1328         struct vmcs *vmcs;
1329
1330         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1331         if (!pages)
1332                 return NULL;
1333         vmcs = page_address(pages);
1334         memset(vmcs, 0, vmcs_config.size);
1335         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1336         return vmcs;
1337 }
1338
1339 static struct vmcs *alloc_vmcs(void)
1340 {
1341         return alloc_vmcs_cpu(raw_smp_processor_id());
1342 }
1343
1344 static void free_vmcs(struct vmcs *vmcs)
1345 {
1346         free_pages((unsigned long)vmcs, vmcs_config.order);
1347 }
1348
1349 static void free_kvm_area(void)
1350 {
1351         int cpu;
1352
1353         for_each_online_cpu(cpu)
1354                 free_vmcs(per_cpu(vmxarea, cpu));
1355 }
1356
1357 static __init int alloc_kvm_area(void)
1358 {
1359         int cpu;
1360
1361         for_each_online_cpu(cpu) {
1362                 struct vmcs *vmcs;
1363
1364                 vmcs = alloc_vmcs_cpu(cpu);
1365                 if (!vmcs) {
1366                         free_kvm_area();
1367                         return -ENOMEM;
1368                 }
1369
1370                 per_cpu(vmxarea, cpu) = vmcs;
1371         }
1372         return 0;
1373 }
1374
1375 static __init int hardware_setup(void)
1376 {
1377         if (setup_vmcs_config(&vmcs_config) < 0)
1378                 return -EIO;
1379
1380         if (boot_cpu_has(X86_FEATURE_NX))
1381                 kvm_enable_efer_bits(EFER_NX);
1382
1383         if (!cpu_has_vmx_vpid())
1384                 enable_vpid = 0;
1385
1386         if (!cpu_has_vmx_ept()) {
1387                 enable_ept = 0;
1388                 enable_unrestricted_guest = 0;
1389         }
1390
1391         if (!cpu_has_vmx_unrestricted_guest())
1392                 enable_unrestricted_guest = 0;
1393
1394         if (!cpu_has_vmx_flexpriority())
1395                 flexpriority_enabled = 0;
1396
1397         if (!cpu_has_vmx_tpr_shadow())
1398                 kvm_x86_ops->update_cr8_intercept = NULL;
1399
1400         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1401                 kvm_disable_largepages();
1402
1403         return alloc_kvm_area();
1404 }
1405
1406 static __exit void hardware_unsetup(void)
1407 {
1408         free_kvm_area();
1409 }
1410
1411 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1412 {
1413         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1414
1415         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1416                 vmcs_write16(sf->selector, save->selector);
1417                 vmcs_writel(sf->base, save->base);
1418                 vmcs_write32(sf->limit, save->limit);
1419                 vmcs_write32(sf->ar_bytes, save->ar);
1420         } else {
1421                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1422                         << AR_DPL_SHIFT;
1423                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1424         }
1425 }
1426
1427 static void enter_pmode(struct kvm_vcpu *vcpu)
1428 {
1429         unsigned long flags;
1430         struct vcpu_vmx *vmx = to_vmx(vcpu);
1431
1432         vmx->emulation_required = 1;
1433         vmx->rmode.vm86_active = 0;
1434
1435         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1436         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1437         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1438
1439         flags = vmcs_readl(GUEST_RFLAGS);
1440         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1441         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1442         vmcs_writel(GUEST_RFLAGS, flags);
1443
1444         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1445                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1446
1447         update_exception_bitmap(vcpu);
1448
1449         if (emulate_invalid_guest_state)
1450                 return;
1451
1452         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1453         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1454         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1455         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1456
1457         vmcs_write16(GUEST_SS_SELECTOR, 0);
1458         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1459
1460         vmcs_write16(GUEST_CS_SELECTOR,
1461                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1462         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1463 }
1464
1465 static gva_t rmode_tss_base(struct kvm *kvm)
1466 {
1467         if (!kvm->arch.tss_addr) {
1468                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1469                                  kvm->memslots[0].npages - 3;
1470                 return base_gfn << PAGE_SHIFT;
1471         }
1472         return kvm->arch.tss_addr;
1473 }
1474
1475 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1476 {
1477         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1478
1479         save->selector = vmcs_read16(sf->selector);
1480         save->base = vmcs_readl(sf->base);
1481         save->limit = vmcs_read32(sf->limit);
1482         save->ar = vmcs_read32(sf->ar_bytes);
1483         vmcs_write16(sf->selector, save->base >> 4);
1484         vmcs_write32(sf->base, save->base & 0xfffff);
1485         vmcs_write32(sf->limit, 0xffff);
1486         vmcs_write32(sf->ar_bytes, 0xf3);
1487 }
1488
1489 static void enter_rmode(struct kvm_vcpu *vcpu)
1490 {
1491         unsigned long flags;
1492         struct vcpu_vmx *vmx = to_vmx(vcpu);
1493
1494         if (enable_unrestricted_guest)
1495                 return;
1496
1497         vmx->emulation_required = 1;
1498         vmx->rmode.vm86_active = 1;
1499
1500         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1501         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1502
1503         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1504         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1505
1506         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1507         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1508
1509         flags = vmcs_readl(GUEST_RFLAGS);
1510         vmx->rmode.save_iopl
1511                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1512
1513         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1514
1515         vmcs_writel(GUEST_RFLAGS, flags);
1516         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1517         update_exception_bitmap(vcpu);
1518
1519         if (emulate_invalid_guest_state)
1520                 goto continue_rmode;
1521
1522         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1523         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1524         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1525
1526         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1527         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1528         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1529                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1530         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1531
1532         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1533         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1534         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1535         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1536
1537 continue_rmode:
1538         kvm_mmu_reset_context(vcpu);
1539         init_rmode(vcpu->kvm);
1540 }
1541
1542 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1543 {
1544         struct vcpu_vmx *vmx = to_vmx(vcpu);
1545         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1546
1547         vcpu->arch.shadow_efer = efer;
1548         if (!msr)
1549                 return;
1550         if (efer & EFER_LMA) {
1551                 vmcs_write32(VM_ENTRY_CONTROLS,
1552                              vmcs_read32(VM_ENTRY_CONTROLS) |
1553                              VM_ENTRY_IA32E_MODE);
1554                 msr->data = efer;
1555         } else {
1556                 vmcs_write32(VM_ENTRY_CONTROLS,
1557                              vmcs_read32(VM_ENTRY_CONTROLS) &
1558                              ~VM_ENTRY_IA32E_MODE);
1559
1560                 msr->data = efer & ~EFER_LME;
1561         }
1562         setup_msrs(vmx);
1563 }
1564
1565 #ifdef CONFIG_X86_64
1566
1567 static void enter_lmode(struct kvm_vcpu *vcpu)
1568 {
1569         u32 guest_tr_ar;
1570
1571         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1572         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1573                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1574                        __func__);
1575                 vmcs_write32(GUEST_TR_AR_BYTES,
1576                              (guest_tr_ar & ~AR_TYPE_MASK)
1577                              | AR_TYPE_BUSY_64_TSS);
1578         }
1579         vcpu->arch.shadow_efer |= EFER_LMA;
1580         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1581 }
1582
1583 static void exit_lmode(struct kvm_vcpu *vcpu)
1584 {
1585         vcpu->arch.shadow_efer &= ~EFER_LMA;
1586
1587         vmcs_write32(VM_ENTRY_CONTROLS,
1588                      vmcs_read32(VM_ENTRY_CONTROLS)
1589                      & ~VM_ENTRY_IA32E_MODE);
1590 }
1591
1592 #endif
1593
1594 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1595 {
1596         vpid_sync_vcpu_all(to_vmx(vcpu));
1597         if (enable_ept)
1598                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1599 }
1600
1601 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1602 {
1603         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1604         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1605 }
1606
1607 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1608 {
1609         if (!test_bit(VCPU_EXREG_PDPTR,
1610                       (unsigned long *)&vcpu->arch.regs_dirty))
1611                 return;
1612
1613         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1614                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1615                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1616                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1617                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1618         }
1619 }
1620
1621 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1622 {
1623         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1624                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1625                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1626                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1627                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1628         }
1629
1630         __set_bit(VCPU_EXREG_PDPTR,
1631                   (unsigned long *)&vcpu->arch.regs_avail);
1632         __set_bit(VCPU_EXREG_PDPTR,
1633                   (unsigned long *)&vcpu->arch.regs_dirty);
1634 }
1635
1636 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1637
1638 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1639                                         unsigned long cr0,
1640                                         struct kvm_vcpu *vcpu)
1641 {
1642         if (!(cr0 & X86_CR0_PG)) {
1643                 /* From paging/starting to nonpaging */
1644                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1645                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1646                              (CPU_BASED_CR3_LOAD_EXITING |
1647                               CPU_BASED_CR3_STORE_EXITING));
1648                 vcpu->arch.cr0 = cr0;
1649                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1650         } else if (!is_paging(vcpu)) {
1651                 /* From nonpaging to paging */
1652                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1653                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1654                              ~(CPU_BASED_CR3_LOAD_EXITING |
1655                                CPU_BASED_CR3_STORE_EXITING));
1656                 vcpu->arch.cr0 = cr0;
1657                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1658         }
1659
1660         if (!(cr0 & X86_CR0_WP))
1661                 *hw_cr0 &= ~X86_CR0_WP;
1662 }
1663
1664 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1665                                         struct kvm_vcpu *vcpu)
1666 {
1667         if (!is_paging(vcpu)) {
1668                 *hw_cr4 &= ~X86_CR4_PAE;
1669                 *hw_cr4 |= X86_CR4_PSE;
1670         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1671                 *hw_cr4 &= ~X86_CR4_PAE;
1672 }
1673
1674 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1675 {
1676         struct vcpu_vmx *vmx = to_vmx(vcpu);
1677         unsigned long hw_cr0;
1678
1679         if (enable_unrestricted_guest)
1680                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1681                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1682         else
1683                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1684
1685         vmx_fpu_deactivate(vcpu);
1686
1687         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1688                 enter_pmode(vcpu);
1689
1690         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1691                 enter_rmode(vcpu);
1692
1693 #ifdef CONFIG_X86_64
1694         if (vcpu->arch.shadow_efer & EFER_LME) {
1695                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1696                         enter_lmode(vcpu);
1697                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1698                         exit_lmode(vcpu);
1699         }
1700 #endif
1701
1702         if (enable_ept)
1703                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1704
1705         vmcs_writel(CR0_READ_SHADOW, cr0);
1706         vmcs_writel(GUEST_CR0, hw_cr0);
1707         vcpu->arch.cr0 = cr0;
1708
1709         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1710                 vmx_fpu_activate(vcpu);
1711 }
1712
1713 static u64 construct_eptp(unsigned long root_hpa)
1714 {
1715         u64 eptp;
1716
1717         /* TODO write the value reading from MSR */
1718         eptp = VMX_EPT_DEFAULT_MT |
1719                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1720         eptp |= (root_hpa & PAGE_MASK);
1721
1722         return eptp;
1723 }
1724
1725 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1726 {
1727         unsigned long guest_cr3;
1728         u64 eptp;
1729
1730         guest_cr3 = cr3;
1731         if (enable_ept) {
1732                 eptp = construct_eptp(cr3);
1733                 vmcs_write64(EPT_POINTER, eptp);
1734                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1735                         vcpu->kvm->arch.ept_identity_map_addr;
1736         }
1737
1738         vmx_flush_tlb(vcpu);
1739         vmcs_writel(GUEST_CR3, guest_cr3);
1740         if (vcpu->arch.cr0 & X86_CR0_PE)
1741                 vmx_fpu_deactivate(vcpu);
1742 }
1743
1744 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1745 {
1746         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1747                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1748
1749         vcpu->arch.cr4 = cr4;
1750         if (enable_ept)
1751                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1752
1753         vmcs_writel(CR4_READ_SHADOW, cr4);
1754         vmcs_writel(GUEST_CR4, hw_cr4);
1755 }
1756
1757 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1758 {
1759         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1760
1761         return vmcs_readl(sf->base);
1762 }
1763
1764 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1765                             struct kvm_segment *var, int seg)
1766 {
1767         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1768         u32 ar;
1769
1770         var->base = vmcs_readl(sf->base);
1771         var->limit = vmcs_read32(sf->limit);
1772         var->selector = vmcs_read16(sf->selector);
1773         ar = vmcs_read32(sf->ar_bytes);
1774         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1775                 ar = 0;
1776         var->type = ar & 15;
1777         var->s = (ar >> 4) & 1;
1778         var->dpl = (ar >> 5) & 3;
1779         var->present = (ar >> 7) & 1;
1780         var->avl = (ar >> 12) & 1;
1781         var->l = (ar >> 13) & 1;
1782         var->db = (ar >> 14) & 1;
1783         var->g = (ar >> 15) & 1;
1784         var->unusable = (ar >> 16) & 1;
1785 }
1786
1787 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1788 {
1789         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1790                 return 0;
1791
1792         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1793                 return 3;
1794
1795         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1796 }
1797
1798 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1799 {
1800         u32 ar;
1801
1802         if (var->unusable)
1803                 ar = 1 << 16;
1804         else {
1805                 ar = var->type & 15;
1806                 ar |= (var->s & 1) << 4;
1807                 ar |= (var->dpl & 3) << 5;
1808                 ar |= (var->present & 1) << 7;
1809                 ar |= (var->avl & 1) << 12;
1810                 ar |= (var->l & 1) << 13;
1811                 ar |= (var->db & 1) << 14;
1812                 ar |= (var->g & 1) << 15;
1813         }
1814         if (ar == 0) /* a 0 value means unusable */
1815                 ar = AR_UNUSABLE_MASK;
1816
1817         return ar;
1818 }
1819
1820 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1821                             struct kvm_segment *var, int seg)
1822 {
1823         struct vcpu_vmx *vmx = to_vmx(vcpu);
1824         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1825         u32 ar;
1826
1827         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1828                 vmx->rmode.tr.selector = var->selector;
1829                 vmx->rmode.tr.base = var->base;
1830                 vmx->rmode.tr.limit = var->limit;
1831                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1832                 return;
1833         }
1834         vmcs_writel(sf->base, var->base);
1835         vmcs_write32(sf->limit, var->limit);
1836         vmcs_write16(sf->selector, var->selector);
1837         if (vmx->rmode.vm86_active && var->s) {
1838                 /*
1839                  * Hack real-mode segments into vm86 compatibility.
1840                  */
1841                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1842                         vmcs_writel(sf->base, 0xf0000);
1843                 ar = 0xf3;
1844         } else
1845                 ar = vmx_segment_access_rights(var);
1846
1847         /*
1848          *   Fix the "Accessed" bit in AR field of segment registers for older
1849          * qemu binaries.
1850          *   IA32 arch specifies that at the time of processor reset the
1851          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1852          * is setting it to 0 in the usedland code. This causes invalid guest
1853          * state vmexit when "unrestricted guest" mode is turned on.
1854          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1855          * tree. Newer qemu binaries with that qemu fix would not need this
1856          * kvm hack.
1857          */
1858         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1859                 ar |= 0x1; /* Accessed */
1860
1861         vmcs_write32(sf->ar_bytes, ar);
1862 }
1863
1864 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1865 {
1866         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1867
1868         *db = (ar >> 14) & 1;
1869         *l = (ar >> 13) & 1;
1870 }
1871
1872 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1873 {
1874         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1875         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1876 }
1877
1878 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1879 {
1880         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1881         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1882 }
1883
1884 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1885 {
1886         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1887         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1888 }
1889
1890 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1891 {
1892         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1893         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1894 }
1895
1896 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1897 {
1898         struct kvm_segment var;
1899         u32 ar;
1900
1901         vmx_get_segment(vcpu, &var, seg);
1902         ar = vmx_segment_access_rights(&var);
1903
1904         if (var.base != (var.selector << 4))
1905                 return false;
1906         if (var.limit != 0xffff)
1907                 return false;
1908         if (ar != 0xf3)
1909                 return false;
1910
1911         return true;
1912 }
1913
1914 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1915 {
1916         struct kvm_segment cs;
1917         unsigned int cs_rpl;
1918
1919         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1920         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1921
1922         if (cs.unusable)
1923                 return false;
1924         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1925                 return false;
1926         if (!cs.s)
1927                 return false;
1928         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1929                 if (cs.dpl > cs_rpl)
1930                         return false;
1931         } else {
1932                 if (cs.dpl != cs_rpl)
1933                         return false;
1934         }
1935         if (!cs.present)
1936                 return false;
1937
1938         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1939         return true;
1940 }
1941
1942 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1943 {
1944         struct kvm_segment ss;
1945         unsigned int ss_rpl;
1946
1947         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1948         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1949
1950         if (ss.unusable)
1951                 return true;
1952         if (ss.type != 3 && ss.type != 7)
1953                 return false;
1954         if (!ss.s)
1955                 return false;
1956         if (ss.dpl != ss_rpl) /* DPL != RPL */
1957                 return false;
1958         if (!ss.present)
1959                 return false;
1960
1961         return true;
1962 }
1963
1964 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1965 {
1966         struct kvm_segment var;
1967         unsigned int rpl;
1968
1969         vmx_get_segment(vcpu, &var, seg);
1970         rpl = var.selector & SELECTOR_RPL_MASK;
1971
1972         if (var.unusable)
1973                 return true;
1974         if (!var.s)
1975                 return false;
1976         if (!var.present)
1977                 return false;
1978         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1979                 if (var.dpl < rpl) /* DPL < RPL */
1980                         return false;
1981         }
1982
1983         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1984          * rights flags
1985          */
1986         return true;
1987 }
1988
1989 static bool tr_valid(struct kvm_vcpu *vcpu)
1990 {
1991         struct kvm_segment tr;
1992
1993         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1994
1995         if (tr.unusable)
1996                 return false;
1997         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1998                 return false;
1999         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2000                 return false;
2001         if (!tr.present)
2002                 return false;
2003
2004         return true;
2005 }
2006
2007 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2008 {
2009         struct kvm_segment ldtr;
2010
2011         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2012
2013         if (ldtr.unusable)
2014                 return true;
2015         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2016                 return false;
2017         if (ldtr.type != 2)
2018                 return false;
2019         if (!ldtr.present)
2020                 return false;
2021
2022         return true;
2023 }
2024
2025 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2026 {
2027         struct kvm_segment cs, ss;
2028
2029         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2030         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2031
2032         return ((cs.selector & SELECTOR_RPL_MASK) ==
2033                  (ss.selector & SELECTOR_RPL_MASK));
2034 }
2035
2036 /*
2037  * Check if guest state is valid. Returns true if valid, false if
2038  * not.
2039  * We assume that registers are always usable
2040  */
2041 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2042 {
2043         /* real mode guest state checks */
2044         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2045                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2046                         return false;
2047                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2048                         return false;
2049                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2050                         return false;
2051                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2052                         return false;
2053                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2054                         return false;
2055                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2056                         return false;
2057         } else {
2058         /* protected mode guest state checks */
2059                 if (!cs_ss_rpl_check(vcpu))
2060                         return false;
2061                 if (!code_segment_valid(vcpu))
2062                         return false;
2063                 if (!stack_segment_valid(vcpu))
2064                         return false;
2065                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2066                         return false;
2067                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2068                         return false;
2069                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2070                         return false;
2071                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2072                         return false;
2073                 if (!tr_valid(vcpu))
2074                         return false;
2075                 if (!ldtr_valid(vcpu))
2076                         return false;
2077         }
2078         /* TODO:
2079          * - Add checks on RIP
2080          * - Add checks on RFLAGS
2081          */
2082
2083         return true;
2084 }
2085
2086 static int init_rmode_tss(struct kvm *kvm)
2087 {
2088         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2089         u16 data = 0;
2090         int ret = 0;
2091         int r;
2092
2093         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2094         if (r < 0)
2095                 goto out;
2096         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2097         r = kvm_write_guest_page(kvm, fn++, &data,
2098                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2099         if (r < 0)
2100                 goto out;
2101         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2102         if (r < 0)
2103                 goto out;
2104         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2105         if (r < 0)
2106                 goto out;
2107         data = ~0;
2108         r = kvm_write_guest_page(kvm, fn, &data,
2109                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2110                                  sizeof(u8));
2111         if (r < 0)
2112                 goto out;
2113
2114         ret = 1;
2115 out:
2116         return ret;
2117 }
2118
2119 static int init_rmode_identity_map(struct kvm *kvm)
2120 {
2121         int i, r, ret;
2122         pfn_t identity_map_pfn;
2123         u32 tmp;
2124
2125         if (!enable_ept)
2126                 return 1;
2127         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2128                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2129                         "haven't been allocated!\n");
2130                 return 0;
2131         }
2132         if (likely(kvm->arch.ept_identity_pagetable_done))
2133                 return 1;
2134         ret = 0;
2135         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2136         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2137         if (r < 0)
2138                 goto out;
2139         /* Set up identity-mapping pagetable for EPT in real mode */
2140         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2141                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2142                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2143                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2144                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2145                 if (r < 0)
2146                         goto out;
2147         }
2148         kvm->arch.ept_identity_pagetable_done = true;
2149         ret = 1;
2150 out:
2151         return ret;
2152 }
2153
2154 static void seg_setup(int seg)
2155 {
2156         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2157         unsigned int ar;
2158
2159         vmcs_write16(sf->selector, 0);
2160         vmcs_writel(sf->base, 0);
2161         vmcs_write32(sf->limit, 0xffff);
2162         if (enable_unrestricted_guest) {
2163                 ar = 0x93;
2164                 if (seg == VCPU_SREG_CS)
2165                         ar |= 0x08; /* code segment */
2166         } else
2167                 ar = 0xf3;
2168
2169         vmcs_write32(sf->ar_bytes, ar);
2170 }
2171
2172 static int alloc_apic_access_page(struct kvm *kvm)
2173 {
2174         struct kvm_userspace_memory_region kvm_userspace_mem;
2175         int r = 0;
2176
2177         down_write(&kvm->slots_lock);
2178         if (kvm->arch.apic_access_page)
2179                 goto out;
2180         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2181         kvm_userspace_mem.flags = 0;
2182         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2183         kvm_userspace_mem.memory_size = PAGE_SIZE;
2184         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2185         if (r)
2186                 goto out;
2187
2188         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2189 out:
2190         up_write(&kvm->slots_lock);
2191         return r;
2192 }
2193
2194 static int alloc_identity_pagetable(struct kvm *kvm)
2195 {
2196         struct kvm_userspace_memory_region kvm_userspace_mem;
2197         int r = 0;
2198
2199         down_write(&kvm->slots_lock);
2200         if (kvm->arch.ept_identity_pagetable)
2201                 goto out;
2202         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2203         kvm_userspace_mem.flags = 0;
2204         kvm_userspace_mem.guest_phys_addr =
2205                 kvm->arch.ept_identity_map_addr;
2206         kvm_userspace_mem.memory_size = PAGE_SIZE;
2207         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2208         if (r)
2209                 goto out;
2210
2211         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2212                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2213 out:
2214         up_write(&kvm->slots_lock);
2215         return r;
2216 }
2217
2218 static void allocate_vpid(struct vcpu_vmx *vmx)
2219 {
2220         int vpid;
2221
2222         vmx->vpid = 0;
2223         if (!enable_vpid)
2224                 return;
2225         spin_lock(&vmx_vpid_lock);
2226         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2227         if (vpid < VMX_NR_VPIDS) {
2228                 vmx->vpid = vpid;
2229                 __set_bit(vpid, vmx_vpid_bitmap);
2230         }
2231         spin_unlock(&vmx_vpid_lock);
2232 }
2233
2234 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2235 {
2236         int f = sizeof(unsigned long);
2237
2238         if (!cpu_has_vmx_msr_bitmap())
2239                 return;
2240
2241         /*
2242          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2243          * have the write-low and read-high bitmap offsets the wrong way round.
2244          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2245          */
2246         if (msr <= 0x1fff) {
2247                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2248                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2249         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2250                 msr &= 0x1fff;
2251                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2252                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2253         }
2254 }
2255
2256 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2257 {
2258         if (!longmode_only)
2259                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2260         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2261 }
2262
2263 /*
2264  * Sets up the vmcs for emulated real mode.
2265  */
2266 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2267 {
2268         u32 host_sysenter_cs, msr_low, msr_high;
2269         u32 junk;
2270         u64 host_pat, tsc_this, tsc_base;
2271         unsigned long a;
2272         struct descriptor_table dt;
2273         int i;
2274         unsigned long kvm_vmx_return;
2275         u32 exec_control;
2276
2277         /* I/O */
2278         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2279         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2280
2281         if (cpu_has_vmx_msr_bitmap())
2282                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2283
2284         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2285
2286         /* Control */
2287         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2288                 vmcs_config.pin_based_exec_ctrl);
2289
2290         exec_control = vmcs_config.cpu_based_exec_ctrl;
2291         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2292                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2293 #ifdef CONFIG_X86_64
2294                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2295                                 CPU_BASED_CR8_LOAD_EXITING;
2296 #endif
2297         }
2298         if (!enable_ept)
2299                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2300                                 CPU_BASED_CR3_LOAD_EXITING  |
2301                                 CPU_BASED_INVLPG_EXITING;
2302         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2303
2304         if (cpu_has_secondary_exec_ctrls()) {
2305                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2306                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2307                         exec_control &=
2308                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2309                 if (vmx->vpid == 0)
2310                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2311                 if (!enable_ept)
2312                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2313                 if (!enable_unrestricted_guest)
2314                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2315                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2316         }
2317
2318         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2319         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2320         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2321
2322         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2323         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2324         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2325
2326         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2327         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2328         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2329         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2330         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2331         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2332 #ifdef CONFIG_X86_64
2333         rdmsrl(MSR_FS_BASE, a);
2334         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2335         rdmsrl(MSR_GS_BASE, a);
2336         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2337 #else
2338         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2339         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2340 #endif
2341
2342         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2343
2344         kvm_get_idt(&dt);
2345         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2346
2347         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2348         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2349         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2350         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2351         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2352
2353         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2354         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2355         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2356         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2357         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2358         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2359
2360         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2361                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2362                 host_pat = msr_low | ((u64) msr_high << 32);
2363                 vmcs_write64(HOST_IA32_PAT, host_pat);
2364         }
2365         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2366                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2367                 host_pat = msr_low | ((u64) msr_high << 32);
2368                 /* Write the default value follow host pat */
2369                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2370                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2371                 vmx->vcpu.arch.pat = host_pat;
2372         }
2373
2374         for (i = 0; i < NR_VMX_MSR; ++i) {
2375                 u32 index = vmx_msr_index[i];
2376                 u32 data_low, data_high;
2377                 u64 data;
2378                 int j = vmx->nmsrs;
2379
2380                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2381                         continue;
2382                 if (wrmsr_safe(index, data_low, data_high) < 0)
2383                         continue;
2384                 data = data_low | ((u64)data_high << 32);
2385                 vmx->host_msrs[j].index = index;
2386                 vmx->host_msrs[j].reserved = 0;
2387                 vmx->host_msrs[j].data = data;
2388                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2389                 ++vmx->nmsrs;
2390         }
2391
2392         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2393
2394         /* 22.2.1, 20.8.1 */
2395         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2396
2397         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2398         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2399
2400         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2401         rdtscll(tsc_this);
2402         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2403                 tsc_base = tsc_this;
2404
2405         guest_write_tsc(0, tsc_base);
2406
2407         return 0;
2408 }
2409
2410 static int init_rmode(struct kvm *kvm)
2411 {
2412         if (!init_rmode_tss(kvm))
2413                 return 0;
2414         if (!init_rmode_identity_map(kvm))
2415                 return 0;
2416         return 1;
2417 }
2418
2419 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2420 {
2421         struct vcpu_vmx *vmx = to_vmx(vcpu);
2422         u64 msr;
2423         int ret;
2424
2425         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2426         down_read(&vcpu->kvm->slots_lock);
2427         if (!init_rmode(vmx->vcpu.kvm)) {
2428                 ret = -ENOMEM;
2429                 goto out;
2430         }
2431
2432         vmx->rmode.vm86_active = 0;
2433
2434         vmx->soft_vnmi_blocked = 0;
2435
2436         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2437         kvm_set_cr8(&vmx->vcpu, 0);
2438         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2439         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2440                 msr |= MSR_IA32_APICBASE_BSP;
2441         kvm_set_apic_base(&vmx->vcpu, msr);
2442
2443         fx_init(&vmx->vcpu);
2444
2445         seg_setup(VCPU_SREG_CS);
2446         /*
2447          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2448          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2449          */
2450         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2451                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2452                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2453         } else {
2454                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2455                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2456         }
2457
2458         seg_setup(VCPU_SREG_DS);
2459         seg_setup(VCPU_SREG_ES);
2460         seg_setup(VCPU_SREG_FS);
2461         seg_setup(VCPU_SREG_GS);
2462         seg_setup(VCPU_SREG_SS);
2463
2464         vmcs_write16(GUEST_TR_SELECTOR, 0);
2465         vmcs_writel(GUEST_TR_BASE, 0);
2466         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2467         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2468
2469         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2470         vmcs_writel(GUEST_LDTR_BASE, 0);
2471         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2472         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2473
2474         vmcs_write32(GUEST_SYSENTER_CS, 0);
2475         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2476         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2477
2478         vmcs_writel(GUEST_RFLAGS, 0x02);
2479         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2480                 kvm_rip_write(vcpu, 0xfff0);
2481         else
2482                 kvm_rip_write(vcpu, 0);
2483         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2484
2485         vmcs_writel(GUEST_DR7, 0x400);
2486
2487         vmcs_writel(GUEST_GDTR_BASE, 0);
2488         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2489
2490         vmcs_writel(GUEST_IDTR_BASE, 0);
2491         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2492
2493         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2494         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2495         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2496
2497         /* Special registers */
2498         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2499
2500         setup_msrs(vmx);
2501
2502         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2503
2504         if (cpu_has_vmx_tpr_shadow()) {
2505                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2506                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2507                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2508                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2509                 vmcs_write32(TPR_THRESHOLD, 0);
2510         }
2511
2512         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2513                 vmcs_write64(APIC_ACCESS_ADDR,
2514                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2515
2516         if (vmx->vpid != 0)
2517                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2518
2519         vmx->vcpu.arch.cr0 = 0x60000010;
2520         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2521         vmx_set_cr4(&vmx->vcpu, 0);
2522         vmx_set_efer(&vmx->vcpu, 0);
2523         vmx_fpu_activate(&vmx->vcpu);
2524         update_exception_bitmap(&vmx->vcpu);
2525
2526         vpid_sync_vcpu_all(vmx);
2527
2528         ret = 0;
2529
2530         /* HACK: Don't enable emulation on guest boot/reset */
2531         vmx->emulation_required = 0;
2532
2533 out:
2534         up_read(&vcpu->kvm->slots_lock);
2535         return ret;
2536 }
2537
2538 static void enable_irq_window(struct kvm_vcpu *vcpu)
2539 {
2540         u32 cpu_based_vm_exec_control;
2541
2542         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2543         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2544         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2545 }
2546
2547 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2548 {
2549         u32 cpu_based_vm_exec_control;
2550
2551         if (!cpu_has_virtual_nmis()) {
2552                 enable_irq_window(vcpu);
2553                 return;
2554         }
2555
2556         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2557         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2558         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2559 }
2560
2561 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2562 {
2563         struct vcpu_vmx *vmx = to_vmx(vcpu);
2564         uint32_t intr;
2565         int irq = vcpu->arch.interrupt.nr;
2566
2567         trace_kvm_inj_virq(irq);
2568
2569         ++vcpu->stat.irq_injections;
2570         if (vmx->rmode.vm86_active) {
2571                 vmx->rmode.irq.pending = true;
2572                 vmx->rmode.irq.vector = irq;
2573                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2574                 if (vcpu->arch.interrupt.soft)
2575                         vmx->rmode.irq.rip +=
2576                                 vmx->vcpu.arch.event_exit_inst_len;
2577                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2578                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2579                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2580                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2581                 return;
2582         }
2583         intr = irq | INTR_INFO_VALID_MASK;
2584         if (vcpu->arch.interrupt.soft) {
2585                 intr |= INTR_TYPE_SOFT_INTR;
2586                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2587                              vmx->vcpu.arch.event_exit_inst_len);
2588         } else
2589                 intr |= INTR_TYPE_EXT_INTR;
2590         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2591 }
2592
2593 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2594 {
2595         struct vcpu_vmx *vmx = to_vmx(vcpu);
2596
2597         if (!cpu_has_virtual_nmis()) {
2598                 /*
2599                  * Tracking the NMI-blocked state in software is built upon
2600                  * finding the next open IRQ window. This, in turn, depends on
2601                  * well-behaving guests: They have to keep IRQs disabled at
2602                  * least as long as the NMI handler runs. Otherwise we may
2603                  * cause NMI nesting, maybe breaking the guest. But as this is
2604                  * highly unlikely, we can live with the residual risk.
2605                  */
2606                 vmx->soft_vnmi_blocked = 1;
2607                 vmx->vnmi_blocked_time = 0;
2608         }
2609
2610         ++vcpu->stat.nmi_injections;
2611         if (vmx->rmode.vm86_active) {
2612                 vmx->rmode.irq.pending = true;
2613                 vmx->rmode.irq.vector = NMI_VECTOR;
2614                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2615                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2616                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2617                              INTR_INFO_VALID_MASK);
2618                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2619                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2620                 return;
2621         }
2622         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2623                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2624 }
2625
2626 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2627 {
2628         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2629                 return 0;
2630
2631         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2632                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2633                                 GUEST_INTR_STATE_NMI));
2634 }
2635
2636 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2637 {
2638         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2639                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2640                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2641 }
2642
2643 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2644 {
2645         int ret;
2646         struct kvm_userspace_memory_region tss_mem = {
2647                 .slot = TSS_PRIVATE_MEMSLOT,
2648                 .guest_phys_addr = addr,
2649                 .memory_size = PAGE_SIZE * 3,
2650                 .flags = 0,
2651         };
2652
2653         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2654         if (ret)
2655                 return ret;
2656         kvm->arch.tss_addr = addr;
2657         return 0;
2658 }
2659
2660 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2661                                   int vec, u32 err_code)
2662 {
2663         /*
2664          * Instruction with address size override prefix opcode 0x67
2665          * Cause the #SS fault with 0 error code in VM86 mode.
2666          */
2667         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2668                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2669                         return 1;
2670         /*
2671          * Forward all other exceptions that are valid in real mode.
2672          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2673          *        the required debugging infrastructure rework.
2674          */
2675         switch (vec) {
2676         case DB_VECTOR:
2677                 if (vcpu->guest_debug &
2678                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2679                         return 0;
2680                 kvm_queue_exception(vcpu, vec);
2681                 return 1;
2682         case BP_VECTOR:
2683                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2684                         return 0;
2685                 /* fall through */
2686         case DE_VECTOR:
2687         case OF_VECTOR:
2688         case BR_VECTOR:
2689         case UD_VECTOR:
2690         case DF_VECTOR:
2691         case SS_VECTOR:
2692         case GP_VECTOR:
2693         case MF_VECTOR:
2694                 kvm_queue_exception(vcpu, vec);
2695                 return 1;
2696         }
2697         return 0;
2698 }
2699
2700 /*
2701  * Trigger machine check on the host. We assume all the MSRs are already set up
2702  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2703  * We pass a fake environment to the machine check handler because we want
2704  * the guest to be always treated like user space, no matter what context
2705  * it used internally.
2706  */
2707 static void kvm_machine_check(void)
2708 {
2709 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2710         struct pt_regs regs = {
2711                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2712                 .flags = X86_EFLAGS_IF,
2713         };
2714
2715         do_machine_check(&regs, 0);
2716 #endif
2717 }
2718
2719 static int handle_machine_check(struct kvm_vcpu *vcpu)
2720 {
2721         /* already handled by vcpu_run */
2722         return 1;
2723 }
2724
2725 static int handle_exception(struct kvm_vcpu *vcpu)
2726 {
2727         struct vcpu_vmx *vmx = to_vmx(vcpu);
2728         struct kvm_run *kvm_run = vcpu->run;
2729         u32 intr_info, ex_no, error_code;
2730         unsigned long cr2, rip, dr6;
2731         u32 vect_info;
2732         enum emulation_result er;
2733
2734         vect_info = vmx->idt_vectoring_info;
2735         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2736
2737         if (is_machine_check(intr_info))
2738                 return handle_machine_check(vcpu);
2739
2740         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2741                                                 !is_page_fault(intr_info))
2742                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2743                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2744
2745         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2746                 return 1;  /* already handled by vmx_vcpu_run() */
2747
2748         if (is_no_device(intr_info)) {
2749                 vmx_fpu_activate(vcpu);
2750                 return 1;
2751         }
2752
2753         if (is_invalid_opcode(intr_info)) {
2754                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2755                 if (er != EMULATE_DONE)
2756                         kvm_queue_exception(vcpu, UD_VECTOR);
2757                 return 1;
2758         }
2759
2760         error_code = 0;
2761         rip = kvm_rip_read(vcpu);
2762         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2763                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2764         if (is_page_fault(intr_info)) {
2765                 /* EPT won't cause page fault directly */
2766                 if (enable_ept)
2767                         BUG();
2768                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2769                 trace_kvm_page_fault(cr2, error_code);
2770
2771                 if (kvm_event_needs_reinjection(vcpu))
2772                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2773                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2774         }
2775
2776         if (vmx->rmode.vm86_active &&
2777             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2778                                                                 error_code)) {
2779                 if (vcpu->arch.halt_request) {
2780                         vcpu->arch.halt_request = 0;
2781                         return kvm_emulate_halt(vcpu);
2782                 }
2783                 return 1;
2784         }
2785
2786         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2787         switch (ex_no) {
2788         case DB_VECTOR:
2789                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2790                 if (!(vcpu->guest_debug &
2791                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2792                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2793                         kvm_queue_exception(vcpu, DB_VECTOR);
2794                         return 1;
2795                 }
2796                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2797                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2798                 /* fall through */
2799         case BP_VECTOR:
2800                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2801                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2802                 kvm_run->debug.arch.exception = ex_no;
2803                 break;
2804         default:
2805                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2806                 kvm_run->ex.exception = ex_no;
2807                 kvm_run->ex.error_code = error_code;
2808                 break;
2809         }
2810         return 0;
2811 }
2812
2813 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2814 {
2815         ++vcpu->stat.irq_exits;
2816         return 1;
2817 }
2818
2819 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2820 {
2821         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2822         return 0;
2823 }
2824
2825 static int handle_io(struct kvm_vcpu *vcpu)
2826 {
2827         unsigned long exit_qualification;
2828         int size, in, string;
2829         unsigned port;
2830
2831         ++vcpu->stat.io_exits;
2832         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2833         string = (exit_qualification & 16) != 0;
2834
2835         if (string) {
2836                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2837                         return 0;
2838                 return 1;
2839         }
2840
2841         size = (exit_qualification & 7) + 1;
2842         in = (exit_qualification & 8) != 0;
2843         port = exit_qualification >> 16;
2844
2845         skip_emulated_instruction(vcpu);
2846         return kvm_emulate_pio(vcpu, in, size, port);
2847 }
2848
2849 static void
2850 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2851 {
2852         /*
2853          * Patch in the VMCALL instruction:
2854          */
2855         hypercall[0] = 0x0f;
2856         hypercall[1] = 0x01;
2857         hypercall[2] = 0xc1;
2858 }
2859
2860 static int handle_cr(struct kvm_vcpu *vcpu)
2861 {
2862         unsigned long exit_qualification, val;
2863         int cr;
2864         int reg;
2865
2866         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2867         cr = exit_qualification & 15;
2868         reg = (exit_qualification >> 8) & 15;
2869         switch ((exit_qualification >> 4) & 3) {
2870         case 0: /* mov to cr */
2871                 val = kvm_register_read(vcpu, reg);
2872                 trace_kvm_cr_write(cr, val);
2873                 switch (cr) {
2874                 case 0:
2875                         kvm_set_cr0(vcpu, val);
2876                         skip_emulated_instruction(vcpu);
2877                         return 1;
2878                 case 3:
2879                         kvm_set_cr3(vcpu, val);
2880                         skip_emulated_instruction(vcpu);
2881                         return 1;
2882                 case 4:
2883                         kvm_set_cr4(vcpu, val);
2884                         skip_emulated_instruction(vcpu);
2885                         return 1;
2886                 case 8: {
2887                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2888                                 u8 cr8 = kvm_register_read(vcpu, reg);
2889                                 kvm_set_cr8(vcpu, cr8);
2890                                 skip_emulated_instruction(vcpu);
2891                                 if (irqchip_in_kernel(vcpu->kvm))
2892                                         return 1;
2893                                 if (cr8_prev <= cr8)
2894                                         return 1;
2895                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2896                                 return 0;
2897                         }
2898                 };
2899                 break;
2900         case 2: /* clts */
2901                 vmx_fpu_deactivate(vcpu);
2902                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2903                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2904                 vmx_fpu_activate(vcpu);
2905                 skip_emulated_instruction(vcpu);
2906                 return 1;
2907         case 1: /*mov from cr*/
2908                 switch (cr) {
2909                 case 3:
2910                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2911                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2912                         skip_emulated_instruction(vcpu);
2913                         return 1;
2914                 case 8:
2915                         val = kvm_get_cr8(vcpu);
2916                         kvm_register_write(vcpu, reg, val);
2917                         trace_kvm_cr_read(cr, val);
2918                         skip_emulated_instruction(vcpu);
2919                         return 1;
2920                 }
2921                 break;
2922         case 3: /* lmsw */
2923                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2924
2925                 skip_emulated_instruction(vcpu);
2926                 return 1;
2927         default:
2928                 break;
2929         }
2930         vcpu->run->exit_reason = 0;
2931         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2932                (int)(exit_qualification >> 4) & 3, cr);
2933         return 0;
2934 }
2935
2936 static int handle_dr(struct kvm_vcpu *vcpu)
2937 {
2938         unsigned long exit_qualification;
2939         unsigned long val;
2940         int dr, reg;
2941
2942         if (!kvm_require_cpl(vcpu, 0))
2943                 return 1;
2944         dr = vmcs_readl(GUEST_DR7);
2945         if (dr & DR7_GD) {
2946                 /*
2947                  * As the vm-exit takes precedence over the debug trap, we
2948                  * need to emulate the latter, either for the host or the
2949                  * guest debugging itself.
2950                  */
2951                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2952                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2953                         vcpu->run->debug.arch.dr7 = dr;
2954                         vcpu->run->debug.arch.pc =
2955                                 vmcs_readl(GUEST_CS_BASE) +
2956                                 vmcs_readl(GUEST_RIP);
2957                         vcpu->run->debug.arch.exception = DB_VECTOR;
2958                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
2959                         return 0;
2960                 } else {
2961                         vcpu->arch.dr7 &= ~DR7_GD;
2962                         vcpu->arch.dr6 |= DR6_BD;
2963                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2964                         kvm_queue_exception(vcpu, DB_VECTOR);
2965                         return 1;
2966                 }
2967         }
2968
2969         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2970         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2971         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2972         if (exit_qualification & TYPE_MOV_FROM_DR) {
2973                 switch (dr) {
2974                 case 0 ... 3:
2975                         val = vcpu->arch.db[dr];
2976                         break;
2977                 case 6:
2978                         val = vcpu->arch.dr6;
2979                         break;
2980                 case 7:
2981                         val = vcpu->arch.dr7;
2982                         break;
2983                 default:
2984                         val = 0;
2985                 }
2986                 kvm_register_write(vcpu, reg, val);
2987         } else {
2988                 val = vcpu->arch.regs[reg];
2989                 switch (dr) {
2990                 case 0 ... 3:
2991                         vcpu->arch.db[dr] = val;
2992                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2993                                 vcpu->arch.eff_db[dr] = val;
2994                         break;
2995                 case 4 ... 5:
2996                         if (vcpu->arch.cr4 & X86_CR4_DE)
2997                                 kvm_queue_exception(vcpu, UD_VECTOR);
2998                         break;
2999                 case 6:
3000                         if (val & 0xffffffff00000000ULL) {
3001                                 kvm_queue_exception(vcpu, GP_VECTOR);
3002                                 break;
3003                         }
3004                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3005                         break;
3006                 case 7:
3007                         if (val & 0xffffffff00000000ULL) {
3008                                 kvm_queue_exception(vcpu, GP_VECTOR);
3009                                 break;
3010                         }
3011                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3012                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3013                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3014                                 vcpu->arch.switch_db_regs =
3015                                         (val & DR7_BP_EN_MASK);
3016                         }
3017                         break;
3018                 }
3019         }
3020         skip_emulated_instruction(vcpu);
3021         return 1;
3022 }
3023
3024 static int handle_cpuid(struct kvm_vcpu *vcpu)
3025 {
3026         kvm_emulate_cpuid(vcpu);
3027         return 1;
3028 }
3029
3030 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3031 {
3032         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3033         u64 data;
3034
3035         if (vmx_get_msr(vcpu, ecx, &data)) {
3036                 kvm_inject_gp(vcpu, 0);
3037                 return 1;
3038         }
3039
3040         trace_kvm_msr_read(ecx, data);
3041
3042         /* FIXME: handling of bits 32:63 of rax, rdx */
3043         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3044         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3045         skip_emulated_instruction(vcpu);
3046         return 1;
3047 }
3048
3049 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3050 {
3051         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3052         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3053                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3054
3055         trace_kvm_msr_write(ecx, data);
3056
3057         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3058                 kvm_inject_gp(vcpu, 0);
3059                 return 1;
3060         }
3061
3062         skip_emulated_instruction(vcpu);
3063         return 1;
3064 }
3065
3066 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3067 {
3068         return 1;
3069 }
3070
3071 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3072 {
3073         u32 cpu_based_vm_exec_control;
3074
3075         /* clear pending irq */
3076         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3077         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3078         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3079
3080         ++vcpu->stat.irq_window_exits;
3081
3082         /*
3083          * If the user space waits to inject interrupts, exit as soon as
3084          * possible
3085          */
3086         if (!irqchip_in_kernel(vcpu->kvm) &&
3087             vcpu->run->request_interrupt_window &&
3088             !kvm_cpu_has_interrupt(vcpu)) {
3089                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3090                 return 0;
3091         }
3092         return 1;
3093 }
3094
3095 static int handle_halt(struct kvm_vcpu *vcpu)
3096 {
3097         skip_emulated_instruction(vcpu);
3098         return kvm_emulate_halt(vcpu);
3099 }
3100
3101 static int handle_vmcall(struct kvm_vcpu *vcpu)
3102 {
3103         skip_emulated_instruction(vcpu);
3104         kvm_emulate_hypercall(vcpu);
3105         return 1;
3106 }
3107
3108 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3109 {
3110         kvm_queue_exception(vcpu, UD_VECTOR);
3111         return 1;
3112 }
3113
3114 static int handle_invlpg(struct kvm_vcpu *vcpu)
3115 {
3116         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3117
3118         kvm_mmu_invlpg(vcpu, exit_qualification);
3119         skip_emulated_instruction(vcpu);
3120         return 1;
3121 }
3122
3123 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3124 {
3125         skip_emulated_instruction(vcpu);
3126         /* TODO: Add support for VT-d/pass-through device */
3127         return 1;
3128 }
3129
3130 static int handle_apic_access(struct kvm_vcpu *vcpu)
3131 {
3132         unsigned long exit_qualification;
3133         enum emulation_result er;
3134         unsigned long offset;
3135
3136         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3137         offset = exit_qualification & 0xffful;
3138
3139         er = emulate_instruction(vcpu, 0, 0, 0);
3140
3141         if (er !=  EMULATE_DONE) {
3142                 printk(KERN_ERR
3143                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3144                        offset);
3145                 return -ENOEXEC;
3146         }
3147         return 1;
3148 }
3149
3150 static int handle_task_switch(struct kvm_vcpu *vcpu)
3151 {
3152         struct vcpu_vmx *vmx = to_vmx(vcpu);
3153         unsigned long exit_qualification;
3154         u16 tss_selector;
3155         int reason, type, idt_v;
3156
3157         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3158         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3159
3160         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3161
3162         reason = (u32)exit_qualification >> 30;
3163         if (reason == TASK_SWITCH_GATE && idt_v) {
3164                 switch (type) {
3165                 case INTR_TYPE_NMI_INTR:
3166                         vcpu->arch.nmi_injected = false;
3167                         if (cpu_has_virtual_nmis())
3168                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3169                                               GUEST_INTR_STATE_NMI);
3170                         break;
3171                 case INTR_TYPE_EXT_INTR:
3172                 case INTR_TYPE_SOFT_INTR:
3173                         kvm_clear_interrupt_queue(vcpu);
3174                         break;
3175                 case INTR_TYPE_HARD_EXCEPTION:
3176                 case INTR_TYPE_SOFT_EXCEPTION:
3177                         kvm_clear_exception_queue(vcpu);
3178                         break;
3179                 default:
3180                         break;
3181                 }
3182         }
3183         tss_selector = exit_qualification;
3184
3185         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3186                        type != INTR_TYPE_EXT_INTR &&
3187                        type != INTR_TYPE_NMI_INTR))
3188                 skip_emulated_instruction(vcpu);
3189
3190         if (!kvm_task_switch(vcpu, tss_selector, reason))
3191                 return 0;
3192
3193         /* clear all local breakpoint enable flags */
3194         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3195
3196         /*
3197          * TODO: What about debug traps on tss switch?
3198          *       Are we supposed to inject them and update dr6?
3199          */
3200
3201         return 1;
3202 }
3203
3204 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3205 {
3206         unsigned long exit_qualification;
3207         gpa_t gpa;
3208         int gla_validity;
3209
3210         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3211
3212         if (exit_qualification & (1 << 6)) {
3213                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3214                 return -EINVAL;
3215         }
3216
3217         gla_validity = (exit_qualification >> 7) & 0x3;
3218         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3219                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3220                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3221                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3222                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3223                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3224                         (long unsigned int)exit_qualification);
3225                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3226                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3227                 return 0;
3228         }
3229
3230         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3231         trace_kvm_page_fault(gpa, exit_qualification);
3232         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3233 }
3234
3235 static u64 ept_rsvd_mask(u64 spte, int level)
3236 {
3237         int i;
3238         u64 mask = 0;
3239
3240         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3241                 mask |= (1ULL << i);
3242
3243         if (level > 2)
3244                 /* bits 7:3 reserved */
3245                 mask |= 0xf8;
3246         else if (level == 2) {
3247                 if (spte & (1ULL << 7))
3248                         /* 2MB ref, bits 20:12 reserved */
3249                         mask |= 0x1ff000;
3250                 else
3251                         /* bits 6:3 reserved */
3252                         mask |= 0x78;
3253         }
3254
3255         return mask;
3256 }
3257
3258 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3259                                        int level)
3260 {
3261         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3262
3263         /* 010b (write-only) */
3264         WARN_ON((spte & 0x7) == 0x2);
3265
3266         /* 110b (write/execute) */
3267         WARN_ON((spte & 0x7) == 0x6);
3268
3269         /* 100b (execute-only) and value not supported by logical processor */
3270         if (!cpu_has_vmx_ept_execute_only())
3271                 WARN_ON((spte & 0x7) == 0x4);
3272
3273         /* not 000b */
3274         if ((spte & 0x7)) {
3275                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3276
3277                 if (rsvd_bits != 0) {
3278                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3279                                          __func__, rsvd_bits);
3280                         WARN_ON(1);
3281                 }
3282
3283                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3284                         u64 ept_mem_type = (spte & 0x38) >> 3;
3285
3286                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3287                             ept_mem_type == 7) {
3288                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3289                                                 __func__, ept_mem_type);
3290                                 WARN_ON(1);
3291                         }
3292                 }
3293         }
3294 }
3295
3296 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3297 {
3298         u64 sptes[4];
3299         int nr_sptes, i;
3300         gpa_t gpa;
3301
3302         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3303
3304         printk(KERN_ERR "EPT: Misconfiguration.\n");
3305         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3306
3307         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3308
3309         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3310                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3311
3312         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3313         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3314
3315         return 0;
3316 }
3317
3318 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3319 {
3320         u32 cpu_based_vm_exec_control;
3321
3322         /* clear pending NMI */
3323         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3324         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3325         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3326         ++vcpu->stat.nmi_window_exits;
3327
3328         return 1;
3329 }
3330
3331 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3332 {
3333         struct vcpu_vmx *vmx = to_vmx(vcpu);
3334         enum emulation_result err = EMULATE_DONE;
3335         int ret = 1;
3336
3337         while (!guest_state_valid(vcpu)) {
3338                 err = emulate_instruction(vcpu, 0, 0, 0);
3339
3340                 if (err == EMULATE_DO_MMIO) {
3341                         ret = 0;
3342                         goto out;
3343                 }
3344
3345                 if (err != EMULATE_DONE) {
3346                         kvm_report_emulation_failure(vcpu, "emulation failure");
3347                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3348                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3349                         ret = 0;
3350                         goto out;
3351                 }
3352
3353                 if (signal_pending(current))
3354                         goto out;
3355                 if (need_resched())
3356                         schedule();
3357         }
3358
3359         vmx->emulation_required = 0;
3360 out:
3361         return ret;
3362 }
3363
3364 /*
3365  * The exit handlers return 1 if the exit was handled fully and guest execution
3366  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3367  * to be done to userspace and return 0.
3368  */
3369 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3370         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3371         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3372         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3373         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3374         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3375         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3376         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3377         [EXIT_REASON_CPUID]                   = handle_cpuid,
3378         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3379         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3380         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3381         [EXIT_REASON_HLT]                     = handle_halt,
3382         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3383         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3384         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3385         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3386         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3387         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3388         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3389         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3390         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3391         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3392         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3393         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3394         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3395         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3396         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3397         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3398         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3399         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3400 };
3401
3402 static const int kvm_vmx_max_exit_handlers =
3403         ARRAY_SIZE(kvm_vmx_exit_handlers);
3404
3405 /*
3406  * The guest has exited.  See if we can fix it or if we need userspace
3407  * assistance.
3408  */
3409 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3410 {
3411         struct vcpu_vmx *vmx = to_vmx(vcpu);
3412         u32 exit_reason = vmx->exit_reason;
3413         u32 vectoring_info = vmx->idt_vectoring_info;
3414
3415         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3416
3417         /* If guest state is invalid, start emulating */
3418         if (vmx->emulation_required && emulate_invalid_guest_state)
3419                 return handle_invalid_guest_state(vcpu);
3420
3421         /* Access CR3 don't cause VMExit in paging mode, so we need
3422          * to sync with guest real CR3. */
3423         if (enable_ept && is_paging(vcpu))
3424                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3425
3426         if (unlikely(vmx->fail)) {
3427                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3428                 vcpu->run->fail_entry.hardware_entry_failure_reason
3429                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3430                 return 0;
3431         }
3432
3433         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3434                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3435                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3436                         exit_reason != EXIT_REASON_TASK_SWITCH))
3437                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3438                        "(0x%x) and exit reason is 0x%x\n",
3439                        __func__, vectoring_info, exit_reason);
3440
3441         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3442                 if (vmx_interrupt_allowed(vcpu)) {
3443                         vmx->soft_vnmi_blocked = 0;
3444                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3445                            vcpu->arch.nmi_pending) {
3446                         /*
3447                          * This CPU don't support us in finding the end of an
3448                          * NMI-blocked window if the guest runs with IRQs
3449                          * disabled. So we pull the trigger after 1 s of
3450                          * futile waiting, but inform the user about this.
3451                          */
3452                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3453                                "state on VCPU %d after 1 s timeout\n",
3454                                __func__, vcpu->vcpu_id);
3455                         vmx->soft_vnmi_blocked = 0;
3456                 }
3457         }
3458
3459         if (exit_reason < kvm_vmx_max_exit_handlers
3460             && kvm_vmx_exit_handlers[exit_reason])
3461                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3462         else {
3463                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3464                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3465         }
3466         return 0;
3467 }
3468
3469 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3470 {
3471         if (irr == -1 || tpr < irr) {
3472                 vmcs_write32(TPR_THRESHOLD, 0);
3473                 return;
3474         }
3475
3476         vmcs_write32(TPR_THRESHOLD, irr);
3477 }
3478
3479 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3480 {
3481         u32 exit_intr_info;
3482         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3483         bool unblock_nmi;
3484         u8 vector;
3485         int type;
3486         bool idtv_info_valid;
3487
3488         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3489
3490         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3491
3492         /* Handle machine checks before interrupts are enabled */
3493         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3494             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3495                 && is_machine_check(exit_intr_info)))
3496                 kvm_machine_check();
3497
3498         /* We need to handle NMIs before interrupts are enabled */
3499         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3500             (exit_intr_info & INTR_INFO_VALID_MASK))
3501                 asm("int $2");
3502
3503         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3504
3505         if (cpu_has_virtual_nmis()) {
3506                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3507                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3508                 /*
3509                  * SDM 3: 27.7.1.2 (September 2008)
3510                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3511                  * a guest IRET fault.
3512                  * SDM 3: 23.2.2 (September 2008)
3513                  * Bit 12 is undefined in any of the following cases:
3514                  *  If the VM exit sets the valid bit in the IDT-vectoring
3515                  *   information field.
3516                  *  If the VM exit is due to a double fault.
3517                  */
3518                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3519                     vector != DF_VECTOR && !idtv_info_valid)
3520                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3521                                       GUEST_INTR_STATE_NMI);
3522         } else if (unlikely(vmx->soft_vnmi_blocked))
3523                 vmx->vnmi_blocked_time +=
3524                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3525
3526         vmx->vcpu.arch.nmi_injected = false;
3527         kvm_clear_exception_queue(&vmx->vcpu);
3528         kvm_clear_interrupt_queue(&vmx->vcpu);
3529
3530         if (!idtv_info_valid)
3531                 return;
3532
3533         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3534         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3535
3536         switch (type) {
3537         case INTR_TYPE_NMI_INTR:
3538                 vmx->vcpu.arch.nmi_injected = true;
3539                 /*
3540                  * SDM 3: 27.7.1.2 (September 2008)
3541                  * Clear bit "block by NMI" before VM entry if a NMI
3542                  * delivery faulted.
3543                  */
3544                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3545                                 GUEST_INTR_STATE_NMI);
3546                 break;
3547         case INTR_TYPE_SOFT_EXCEPTION:
3548                 vmx->vcpu.arch.event_exit_inst_len =
3549                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3550                 /* fall through */
3551         case INTR_TYPE_HARD_EXCEPTION:
3552                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3553                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3554                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3555                 } else
3556                         kvm_queue_exception(&vmx->vcpu, vector);
3557                 break;
3558         case INTR_TYPE_SOFT_INTR:
3559                 vmx->vcpu.arch.event_exit_inst_len =
3560                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3561                 /* fall through */
3562         case INTR_TYPE_EXT_INTR:
3563                 kvm_queue_interrupt(&vmx->vcpu, vector,
3564                         type == INTR_TYPE_SOFT_INTR);
3565                 break;
3566         default:
3567                 break;
3568         }
3569 }
3570
3571 /*
3572  * Failure to inject an interrupt should give us the information
3573  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3574  * when fetching the interrupt redirection bitmap in the real-mode
3575  * tss, this doesn't happen.  So we do it ourselves.
3576  */
3577 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3578 {
3579         vmx->rmode.irq.pending = 0;
3580         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3581                 return;
3582         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3583         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3584                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3585                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3586                 return;
3587         }
3588         vmx->idt_vectoring_info =
3589                 VECTORING_INFO_VALID_MASK
3590                 | INTR_TYPE_EXT_INTR
3591                 | vmx->rmode.irq.vector;
3592 }
3593
3594 #ifdef CONFIG_X86_64
3595 #define R "r"
3596 #define Q "q"
3597 #else
3598 #define R "e"
3599 #define Q "l"
3600 #endif
3601
3602 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3603 {
3604         struct vcpu_vmx *vmx = to_vmx(vcpu);
3605
3606         if (enable_ept && is_paging(vcpu)) {
3607                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3608                 ept_load_pdptrs(vcpu);
3609         }
3610         /* Record the guest's net vcpu time for enforced NMI injections. */
3611         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3612                 vmx->entry_time = ktime_get();
3613
3614         /* Don't enter VMX if guest state is invalid, let the exit handler
3615            start emulation until we arrive back to a valid state */
3616         if (vmx->emulation_required && emulate_invalid_guest_state)
3617                 return;
3618
3619         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3620                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3621         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3622                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3623
3624         /* When single-stepping over STI and MOV SS, we must clear the
3625          * corresponding interruptibility bits in the guest state. Otherwise
3626          * vmentry fails as it then expects bit 14 (BS) in pending debug
3627          * exceptions being set, but that's not correct for the guest debugging
3628          * case. */
3629         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3630                 vmx_set_interrupt_shadow(vcpu, 0);
3631
3632         /*
3633          * Loading guest fpu may have cleared host cr0.ts
3634          */
3635         vmcs_writel(HOST_CR0, read_cr0());
3636
3637         if (vcpu->arch.switch_db_regs)
3638                 set_debugreg(vcpu->arch.dr6, 6);
3639
3640         asm(
3641                 /* Store host registers */
3642                 "push %%"R"dx; push %%"R"bp;"
3643                 "push %%"R"cx \n\t"
3644                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3645                 "je 1f \n\t"
3646                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3647                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3648                 "1: \n\t"
3649                 /* Reload cr2 if changed */
3650                 "mov %c[cr2](%0), %%"R"ax \n\t"
3651                 "mov %%cr2, %%"R"dx \n\t"
3652                 "cmp %%"R"ax, %%"R"dx \n\t"
3653                 "je 2f \n\t"
3654                 "mov %%"R"ax, %%cr2 \n\t"
3655                 "2: \n\t"
3656                 /* Check if vmlaunch of vmresume is needed */
3657                 "cmpl $0, %c[launched](%0) \n\t"
3658                 /* Load guest registers.  Don't clobber flags. */
3659                 "mov %c[rax](%0), %%"R"ax \n\t"
3660                 "mov %c[rbx](%0), %%"R"bx \n\t"
3661                 "mov %c[rdx](%0), %%"R"dx \n\t"
3662                 "mov %c[rsi](%0), %%"R"si \n\t"
3663                 "mov %c[rdi](%0), %%"R"di \n\t"
3664                 "mov %c[rbp](%0), %%"R"bp \n\t"
3665 #ifdef CONFIG_X86_64
3666                 "mov %c[r8](%0),  %%r8  \n\t"
3667                 "mov %c[r9](%0),  %%r9  \n\t"
3668                 "mov %c[r10](%0), %%r10 \n\t"
3669                 "mov %c[r11](%0), %%r11 \n\t"
3670                 "mov %c[r12](%0), %%r12 \n\t"
3671                 "mov %c[r13](%0), %%r13 \n\t"
3672                 "mov %c[r14](%0), %%r14 \n\t"
3673                 "mov %c[r15](%0), %%r15 \n\t"
3674 #endif
3675                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3676
3677                 /* Enter guest mode */
3678                 "jne .Llaunched \n\t"
3679                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3680                 "jmp .Lkvm_vmx_return \n\t"
3681                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3682                 ".Lkvm_vmx_return: "
3683                 /* Save guest registers, load host registers, keep flags */
3684                 "xchg %0,     (%%"R"sp) \n\t"
3685                 "mov %%"R"ax, %c[rax](%0) \n\t"
3686                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3687                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3688                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3689                 "mov %%"R"si, %c[rsi](%0) \n\t"
3690                 "mov %%"R"di, %c[rdi](%0) \n\t"
3691                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3692 #ifdef CONFIG_X86_64
3693                 "mov %%r8,  %c[r8](%0) \n\t"
3694                 "mov %%r9,  %c[r9](%0) \n\t"
3695                 "mov %%r10, %c[r10](%0) \n\t"
3696                 "mov %%r11, %c[r11](%0) \n\t"
3697                 "mov %%r12, %c[r12](%0) \n\t"
3698                 "mov %%r13, %c[r13](%0) \n\t"
3699                 "mov %%r14, %c[r14](%0) \n\t"
3700                 "mov %%r15, %c[r15](%0) \n\t"
3701 #endif
3702                 "mov %%cr2, %%"R"ax   \n\t"
3703                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3704
3705                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3706                 "setbe %c[fail](%0) \n\t"
3707               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3708                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3709                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3710                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3711                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3712                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3713                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3714                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3715                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3716                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3717                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3718 #ifdef CONFIG_X86_64
3719                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3720                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3721                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3722                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3723                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3724                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3725                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3726                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3727 #endif
3728                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3729               : "cc", "memory"
3730                 , R"bx", R"di", R"si"
3731 #ifdef CONFIG_X86_64
3732                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3733 #endif
3734               );
3735
3736         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3737                                   | (1 << VCPU_EXREG_PDPTR));
3738         vcpu->arch.regs_dirty = 0;
3739
3740         if (vcpu->arch.switch_db_regs)
3741                 get_debugreg(vcpu->arch.dr6, 6);
3742
3743         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3744         if (vmx->rmode.irq.pending)
3745                 fixup_rmode_irq(vmx);
3746
3747         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3748         vmx->launched = 1;
3749
3750         vmx_complete_interrupts(vmx);
3751 }
3752
3753 #undef R
3754 #undef Q
3755
3756 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3757 {
3758         struct vcpu_vmx *vmx = to_vmx(vcpu);
3759
3760         if (vmx->vmcs) {
3761                 vcpu_clear(vmx);
3762                 free_vmcs(vmx->vmcs);
3763                 vmx->vmcs = NULL;
3764         }
3765 }
3766
3767 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3768 {
3769         struct vcpu_vmx *vmx = to_vmx(vcpu);
3770
3771         spin_lock(&vmx_vpid_lock);
3772         if (vmx->vpid != 0)
3773                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3774         spin_unlock(&vmx_vpid_lock);
3775         vmx_free_vmcs(vcpu);
3776         kfree(vmx->host_msrs);
3777         kfree(vmx->guest_msrs);
3778         kvm_vcpu_uninit(vcpu);
3779         kmem_cache_free(kvm_vcpu_cache, vmx);
3780 }
3781
3782 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3783 {
3784         int err;
3785         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3786         int cpu;
3787
3788         if (!vmx)
3789                 return ERR_PTR(-ENOMEM);
3790
3791         allocate_vpid(vmx);
3792
3793         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3794         if (err)
3795                 goto free_vcpu;
3796
3797         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3798         if (!vmx->guest_msrs) {
3799                 err = -ENOMEM;
3800                 goto uninit_vcpu;
3801         }
3802
3803         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3804         if (!vmx->host_msrs)
3805                 goto free_guest_msrs;
3806
3807         vmx->vmcs = alloc_vmcs();
3808         if (!vmx->vmcs)
3809                 goto free_msrs;
3810
3811         vmcs_clear(vmx->vmcs);
3812
3813         cpu = get_cpu();
3814         vmx_vcpu_load(&vmx->vcpu, cpu);
3815         err = vmx_vcpu_setup(vmx);
3816         vmx_vcpu_put(&vmx->vcpu);
3817         put_cpu();
3818         if (err)
3819                 goto free_vmcs;
3820         if (vm_need_virtualize_apic_accesses(kvm))
3821                 if (alloc_apic_access_page(kvm) != 0)
3822                         goto free_vmcs;
3823
3824         if (enable_ept) {
3825                 if (!kvm->arch.ept_identity_map_addr)
3826                         kvm->arch.ept_identity_map_addr =
3827                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3828                 if (alloc_identity_pagetable(kvm) != 0)
3829                         goto free_vmcs;
3830         }
3831
3832         return &vmx->vcpu;
3833
3834 free_vmcs:
3835         free_vmcs(vmx->vmcs);
3836 free_msrs:
3837         kfree(vmx->host_msrs);
3838 free_guest_msrs:
3839         kfree(vmx->guest_msrs);
3840 uninit_vcpu:
3841         kvm_vcpu_uninit(&vmx->vcpu);
3842 free_vcpu:
3843         kmem_cache_free(kvm_vcpu_cache, vmx);
3844         return ERR_PTR(err);
3845 }
3846
3847 static void __init vmx_check_processor_compat(void *rtn)
3848 {
3849         struct vmcs_config vmcs_conf;
3850
3851         *(int *)rtn = 0;
3852         if (setup_vmcs_config(&vmcs_conf) < 0)
3853                 *(int *)rtn = -EIO;
3854         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3855                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3856                                 smp_processor_id());
3857                 *(int *)rtn = -EIO;
3858         }
3859 }
3860
3861 static int get_ept_level(void)
3862 {
3863         return VMX_EPT_DEFAULT_GAW + 1;
3864 }
3865
3866 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3867 {
3868         u64 ret;
3869
3870         /* For VT-d and EPT combination
3871          * 1. MMIO: always map as UC
3872          * 2. EPT with VT-d:
3873          *   a. VT-d without snooping control feature: can't guarantee the
3874          *      result, try to trust guest.
3875          *   b. VT-d with snooping control feature: snooping control feature of
3876          *      VT-d engine can guarantee the cache correctness. Just set it
3877          *      to WB to keep consistent with host. So the same as item 3.
3878          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3879          *    consistent with host MTRR
3880          */
3881         if (is_mmio)
3882                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3883         else if (vcpu->kvm->arch.iommu_domain &&
3884                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3885                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3886                       VMX_EPT_MT_EPTE_SHIFT;
3887         else
3888                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3889                         | VMX_EPT_IGMT_BIT;
3890
3891         return ret;
3892 }
3893
3894 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3895         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3896         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3897         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3898         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3899         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3900         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3901         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3902         { EXIT_REASON_CPUID,                   "cpuid" },
3903         { EXIT_REASON_MSR_READ,                "rdmsr" },
3904         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3905         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3906         { EXIT_REASON_HLT,                     "halt" },
3907         { EXIT_REASON_INVLPG,                  "invlpg" },
3908         { EXIT_REASON_VMCALL,                  "hypercall" },
3909         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3910         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3911         { EXIT_REASON_WBINVD,                  "wbinvd" },
3912         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3913         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3914         { -1, NULL }
3915 };
3916
3917 static bool vmx_gb_page_enable(void)
3918 {
3919         return false;
3920 }
3921
3922 static struct kvm_x86_ops vmx_x86_ops = {
3923         .cpu_has_kvm_support = cpu_has_kvm_support,
3924         .disabled_by_bios = vmx_disabled_by_bios,
3925         .hardware_setup = hardware_setup,
3926         .hardware_unsetup = hardware_unsetup,
3927         .check_processor_compatibility = vmx_check_processor_compat,
3928         .hardware_enable = hardware_enable,
3929         .hardware_disable = hardware_disable,
3930         .cpu_has_accelerated_tpr = report_flexpriority,
3931
3932         .vcpu_create = vmx_create_vcpu,
3933         .vcpu_free = vmx_free_vcpu,
3934         .vcpu_reset = vmx_vcpu_reset,
3935
3936         .prepare_guest_switch = vmx_save_host_state,
3937         .vcpu_load = vmx_vcpu_load,
3938         .vcpu_put = vmx_vcpu_put,
3939
3940         .set_guest_debug = set_guest_debug,
3941         .get_msr = vmx_get_msr,
3942         .set_msr = vmx_set_msr,
3943         .get_segment_base = vmx_get_segment_base,
3944         .get_segment = vmx_get_segment,
3945         .set_segment = vmx_set_segment,
3946         .get_cpl = vmx_get_cpl,
3947         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3948         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3949         .set_cr0 = vmx_set_cr0,
3950         .set_cr3 = vmx_set_cr3,
3951         .set_cr4 = vmx_set_cr4,
3952         .set_efer = vmx_set_efer,
3953         .get_idt = vmx_get_idt,
3954         .set_idt = vmx_set_idt,
3955         .get_gdt = vmx_get_gdt,
3956         .set_gdt = vmx_set_gdt,
3957         .cache_reg = vmx_cache_reg,
3958         .get_rflags = vmx_get_rflags,
3959         .set_rflags = vmx_set_rflags,
3960
3961         .tlb_flush = vmx_flush_tlb,
3962
3963         .run = vmx_vcpu_run,
3964         .handle_exit = vmx_handle_exit,
3965         .skip_emulated_instruction = skip_emulated_instruction,
3966         .set_interrupt_shadow = vmx_set_interrupt_shadow,
3967         .get_interrupt_shadow = vmx_get_interrupt_shadow,
3968         .patch_hypercall = vmx_patch_hypercall,
3969         .set_irq = vmx_inject_irq,
3970         .set_nmi = vmx_inject_nmi,
3971         .queue_exception = vmx_queue_exception,
3972         .interrupt_allowed = vmx_interrupt_allowed,
3973         .nmi_allowed = vmx_nmi_allowed,
3974         .enable_nmi_window = enable_nmi_window,
3975         .enable_irq_window = enable_irq_window,
3976         .update_cr8_intercept = update_cr8_intercept,
3977
3978         .set_tss_addr = vmx_set_tss_addr,
3979         .get_tdp_level = get_ept_level,
3980         .get_mt_mask = vmx_get_mt_mask,
3981
3982         .exit_reasons_str = vmx_exit_reasons_str,
3983         .gb_page_enable = vmx_gb_page_enable,
3984 };
3985
3986 static int __init vmx_init(void)
3987 {
3988         int r;
3989
3990         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3991         if (!vmx_io_bitmap_a)
3992                 return -ENOMEM;
3993
3994         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3995         if (!vmx_io_bitmap_b) {
3996                 r = -ENOMEM;
3997                 goto out;
3998         }
3999
4000         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4001         if (!vmx_msr_bitmap_legacy) {
4002                 r = -ENOMEM;
4003                 goto out1;
4004         }
4005
4006         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4007         if (!vmx_msr_bitmap_longmode) {
4008                 r = -ENOMEM;
4009                 goto out2;
4010         }
4011
4012         /*
4013          * Allow direct access to the PC debug port (it is often used for I/O
4014          * delays, but the vmexits simply slow things down).
4015          */
4016         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4017         clear_bit(0x80, vmx_io_bitmap_a);
4018
4019         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4020
4021         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4022         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4023
4024         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4025
4026         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4027         if (r)
4028                 goto out3;
4029
4030         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4031         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4032         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4033         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4034         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4035         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4036
4037         if (enable_ept) {
4038                 bypass_guest_pf = 0;
4039                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4040                         VMX_EPT_WRITABLE_MASK);
4041                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4042                                 VMX_EPT_EXECUTABLE_MASK);
4043                 kvm_enable_tdp();
4044         } else
4045                 kvm_disable_tdp();
4046
4047         if (bypass_guest_pf)
4048                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4049
4050         return 0;
4051
4052 out3:
4053         free_page((unsigned long)vmx_msr_bitmap_longmode);
4054 out2:
4055         free_page((unsigned long)vmx_msr_bitmap_legacy);
4056 out1:
4057         free_page((unsigned long)vmx_io_bitmap_b);
4058 out:
4059         free_page((unsigned long)vmx_io_bitmap_a);
4060         return r;
4061 }
4062
4063 static void __exit vmx_exit(void)
4064 {
4065         free_page((unsigned long)vmx_msr_bitmap_legacy);
4066         free_page((unsigned long)vmx_msr_bitmap_longmode);
4067         free_page((unsigned long)vmx_io_bitmap_b);
4068         free_page((unsigned long)vmx_io_bitmap_a);
4069
4070         kvm_exit();
4071 }
4072
4073 module_init(vmx_init)
4074 module_exit(vmx_exit)