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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "vmx.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 static int bypass_guest_pf = 1;
  41 module_param(bypass_guest_pf, bool, 0);
  42
  43 static int enable_vpid = 1;
  44 module_param(enable_vpid, bool, 0);
  45
  46 static int flexpriority_enabled = 1;
  47 module_param(flexpriority_enabled, bool, 0);
  48
  49 static int enable_ept = 1;
  50 module_param(enable_ept, bool, 0);
  51
  52 struct vmcs {
  53         u32 revision_id;
  54         u32 abort;
  55         char data[0];
  56 };
  57
  58 struct vcpu_vmx {
  59         struct kvm_vcpu       vcpu;
  60         struct list_head      local_vcpus_link;
  61         int                   launched;
  62         u8                    fail;
  63         u32                   idt_vectoring_info;
  64         struct kvm_msr_entry *guest_msrs;
  65         struct kvm_msr_entry *host_msrs;
  66         int                   nmsrs;
  67         int                   save_nmsrs;
  68         int                   msr_offset_efer;
  69 #ifdef CONFIG_X86_64
  70         int                   msr_offset_kernel_gs_base;
  71 #endif
  72         struct vmcs          *vmcs;
  73         struct {
  74                 int           loaded;
  75                 u16           fs_sel, gs_sel, ldt_sel;
  76                 int           gs_ldt_reload_needed;
  77                 int           fs_reload_needed;
  78                 int           guest_efer_loaded;
  79         } host_state;
  80         struct {
  81                 struct {
  82                         bool pending;
  83                         u8 vector;
  84                         unsigned rip;
  85                 } irq;
  86         } rmode;
  87         int vpid;
  88 };
  89
  90 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  91 {
  92         return container_of(vcpu, struct vcpu_vmx, vcpu);
  93 }
  94
  95 static int init_rmode(struct kvm *kvm);
  96 static u64 construct_eptp(unsigned long root_hpa);
  97
  98 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  99 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 100 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 101
 102 static struct page *vmx_io_bitmap_a;
 103 static struct page *vmx_io_bitmap_b;
 104 static struct page *vmx_msr_bitmap;
 105
 106 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 107 static DEFINE_SPINLOCK(vmx_vpid_lock);
 108
 109 static struct vmcs_config {
 110         int size;
 111         int order;
 112         u32 revision_id;
 113         u32 pin_based_exec_ctrl;
 114         u32 cpu_based_exec_ctrl;
 115         u32 cpu_based_2nd_exec_ctrl;
 116         u32 vmexit_ctrl;
 117         u32 vmentry_ctrl;
 118 } vmcs_config;
 119
 120 struct vmx_capability {
 121         u32 ept;
 122         u32 vpid;
 123 } vmx_capability;
 124
 125 #define VMX_SEGMENT_FIELD(seg)                                  \
 126         [VCPU_SREG_##seg] = {                                   \
 127                 .selector = GUEST_##seg##_SELECTOR,             \
 128                 .base = GUEST_##seg##_BASE,                     \
 129                 .limit = GUEST_##seg##_LIMIT,                   \
 130                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 131         }
 132
 133 static struct kvm_vmx_segment_field {
 134         unsigned selector;
 135         unsigned base;
 136         unsigned limit;
 137         unsigned ar_bytes;
 138 } kvm_vmx_segment_fields[] = {
 139         VMX_SEGMENT_FIELD(CS),
 140         VMX_SEGMENT_FIELD(DS),
 141         VMX_SEGMENT_FIELD(ES),
 142         VMX_SEGMENT_FIELD(FS),
 143         VMX_SEGMENT_FIELD(GS),
 144         VMX_SEGMENT_FIELD(SS),
 145         VMX_SEGMENT_FIELD(TR),
 146         VMX_SEGMENT_FIELD(LDTR),
 147 };
 148
 149 /*
 150  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 151  * away by decrementing the array size.
 152  */
 153 static const u32 vmx_msr_index[] = {
 154 #ifdef CONFIG_X86_64
 155         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 156 #endif
 157         MSR_EFER, MSR_K6_STAR,
 158 };
 159 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 160
 161 static void load_msrs(struct kvm_msr_entry *e, int n)
 162 {
 163         int i;
 164
 165         for (i = 0; i < n; ++i)
 166                 wrmsrl(e[i].index, e[i].data);
 167 }
 168
 169 static void save_msrs(struct kvm_msr_entry *e, int n)
 170 {
 171         int i;
 172
 173         for (i = 0; i < n; ++i)
 174                 rdmsrl(e[i].index, e[i].data);
 175 }
 176
 177 static inline int is_page_fault(u32 intr_info)
 178 {
 179         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 180                              INTR_INFO_VALID_MASK)) ==
 181                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 182 }
 183
 184 static inline int is_no_device(u32 intr_info)
 185 {
 186         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 187                              INTR_INFO_VALID_MASK)) ==
 188                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 189 }
 190
 191 static inline int is_invalid_opcode(u32 intr_info)
 192 {
 193         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 194                              INTR_INFO_VALID_MASK)) ==
 195                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 196 }
 197
 198 static inline int is_external_interrupt(u32 intr_info)
 199 {
 200         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 201                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 202 }
 203
 204 static inline int cpu_has_vmx_msr_bitmap(void)
 205 {
 206         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 207 }
 208
 209 static inline int cpu_has_vmx_tpr_shadow(void)
 210 {
 211         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 212 }
 213
 214 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 215 {
 216         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 217 }
 218
 219 static inline int cpu_has_secondary_exec_ctrls(void)
 220 {
 221         return (vmcs_config.cpu_based_exec_ctrl &
 222                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 223 }
 224
 225 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 226 {
 227         return flexpriority_enabled
 228                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 229                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 230 }
 231
 232 static inline int cpu_has_vmx_invept_individual_addr(void)
 233 {
 234         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 235 }
 236
 237 static inline int cpu_has_vmx_invept_context(void)
 238 {
 239         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 240 }
 241
 242 static inline int cpu_has_vmx_invept_global(void)
 243 {
 244         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 245 }
 246
 247 static inline int cpu_has_vmx_ept(void)
 248 {
 249         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 250                 SECONDARY_EXEC_ENABLE_EPT);
 251 }
 252
 253 static inline int vm_need_ept(void)
 254 {
 255         return (cpu_has_vmx_ept() && enable_ept);
 256 }
 257
 258 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 259 {
 260         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 261                 (irqchip_in_kernel(kvm)));
 262 }
 263
 264 static inline int cpu_has_vmx_vpid(void)
 265 {
 266         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 267                 SECONDARY_EXEC_ENABLE_VPID);
 268 }
 269
 270 static inline int cpu_has_virtual_nmis(void)
 271 {
 272         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 273 }
 274
 275 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 276 {
 277         int i;
 278
 279         for (i = 0; i < vmx->nmsrs; ++i)
 280                 if (vmx->guest_msrs[i].index == msr)
 281                         return i;
 282         return -1;
 283 }
 284
 285 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 286 {
 287     struct {
 288         u64 vpid : 16;
 289         u64 rsvd : 48;
 290         u64 gva;
 291     } operand = { vpid, 0, gva };
 292
 293     asm volatile (__ex(ASM_VMX_INVVPID)
 294                   /* CF==1 or ZF==1 --> rc = -1 */
 295                   "; ja 1f ; ud2 ; 1:"
 296                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 297 }
 298
 299 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 300 {
 301         struct {
 302                 u64 eptp, gpa;
 303         } operand = {eptp, gpa};
 304
 305         asm volatile (__ex(ASM_VMX_INVEPT)
 306                         /* CF==1 or ZF==1 --> rc = -1 */
 307                         "; ja 1f ; ud2 ; 1:\n"
 308                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 309 }
 310
 311 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 312 {
 313         int i;
 314
 315         i = __find_msr_index(vmx, msr);
 316         if (i >= 0)
 317                 return &vmx->guest_msrs[i];
 318         return NULL;
 319 }
 320
 321 static void vmcs_clear(struct vmcs *vmcs)
 322 {
 323         u64 phys_addr = __pa(vmcs);
 324         u8 error;
 325
 326         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 327                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 328                       : "cc", "memory");
 329         if (error)
 330                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 331                        vmcs, phys_addr);
 332 }
 333
 334 static void __vcpu_clear(void *arg)
 335 {
 336         struct vcpu_vmx *vmx = arg;
 337         int cpu = raw_smp_processor_id();
 338
 339         if (vmx->vcpu.cpu == cpu)
 340                 vmcs_clear(vmx->vmcs);
 341         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 342                 per_cpu(current_vmcs, cpu) = NULL;
 343         rdtscll(vmx->vcpu.arch.host_tsc);
 344         list_del(&vmx->local_vcpus_link);
 345         vmx->vcpu.cpu = -1;
 346         vmx->launched = 0;
 347 }
 348
 349 static void vcpu_clear(struct vcpu_vmx *vmx)
 350 {
 351         if (vmx->vcpu.cpu == -1)
 352                 return;
 353         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 354 }
 355
 356 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 357 {
 358         if (vmx->vpid == 0)
 359                 return;
 360
 361         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 362 }
 363
 364 static inline void ept_sync_global(void)
 365 {
 366         if (cpu_has_vmx_invept_global())
 367                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 368 }
 369
 370 static inline void ept_sync_context(u64 eptp)
 371 {
 372         if (vm_need_ept()) {
 373                 if (cpu_has_vmx_invept_context())
 374                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 375                 else
 376                         ept_sync_global();
 377         }
 378 }
 379
 380 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 381 {
 382         if (vm_need_ept()) {
 383                 if (cpu_has_vmx_invept_individual_addr())
 384                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 385                                         eptp, gpa);
 386                 else
 387                         ept_sync_context(eptp);
 388         }
 389 }
 390
 391 static unsigned long vmcs_readl(unsigned long field)
 392 {
 393         unsigned long value;
 394
 395         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 396                       : "=a"(value) : "d"(field) : "cc");
 397         return value;
 398 }
 399
 400 static u16 vmcs_read16(unsigned long field)
 401 {
 402         return vmcs_readl(field);
 403 }
 404
 405 static u32 vmcs_read32(unsigned long field)
 406 {
 407         return vmcs_readl(field);
 408 }
 409
 410 static u64 vmcs_read64(unsigned long field)
 411 {
 412 #ifdef CONFIG_X86_64
 413         return vmcs_readl(field);
 414 #else
 415         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 416 #endif
 417 }
 418
 419 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 420 {
 421         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 422                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 423         dump_stack();
 424 }
 425
 426 static void vmcs_writel(unsigned long field, unsigned long value)
 427 {
 428         u8 error;
 429
 430         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 431                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 432         if (unlikely(error))
 433                 vmwrite_error(field, value);
 434 }
 435
 436 static void vmcs_write16(unsigned long field, u16 value)
 437 {
 438         vmcs_writel(field, value);
 439 }
 440
 441 static void vmcs_write32(unsigned long field, u32 value)
 442 {
 443         vmcs_writel(field, value);
 444 }
 445
 446 static void vmcs_write64(unsigned long field, u64 value)
 447 {
 448         vmcs_writel(field, value);
 449 #ifndef CONFIG_X86_64
 450         asm volatile ("");
 451         vmcs_writel(field+1, value >> 32);
 452 #endif
 453 }
 454
 455 static void vmcs_clear_bits(unsigned long field, u32 mask)
 456 {
 457         vmcs_writel(field, vmcs_readl(field) & ~mask);
 458 }
 459
 460 static void vmcs_set_bits(unsigned long field, u32 mask)
 461 {
 462         vmcs_writel(field, vmcs_readl(field) | mask);
 463 }
 464
 465 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 466 {
 467         u32 eb;
 468
 469         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 470         if (!vcpu->fpu_active)
 471                 eb |= 1u << NM_VECTOR;
 472         if (vcpu->guest_debug.enabled)
 473                 eb |= 1u << DB_VECTOR;
 474         if (vcpu->arch.rmode.active)
 475                 eb = ~0;
 476         if (vm_need_ept())
 477                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 478         vmcs_write32(EXCEPTION_BITMAP, eb);
 479 }
 480
 481 static void reload_tss(void)
 482 {
 483         /*
 484          * VT restores TR but not its size.  Useless.
 485          */
 486         struct descriptor_table gdt;
 487         struct desc_struct *descs;
 488
 489         kvm_get_gdt(&gdt);
 490         descs = (void *)gdt.base;
 491         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 492         load_TR_desc();
 493 }
 494
 495 static void load_transition_efer(struct vcpu_vmx *vmx)
 496 {
 497         int efer_offset = vmx->msr_offset_efer;
 498         u64 host_efer = vmx->host_msrs[efer_offset].data;
 499         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 500         u64 ignore_bits;
 501
 502         if (efer_offset < 0)
 503                 return;
 504         /*
 505          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 506          * outside long mode
 507          */
 508         ignore_bits = EFER_NX | EFER_SCE;
 509 #ifdef CONFIG_X86_64
 510         ignore_bits |= EFER_LMA | EFER_LME;
 511         /* SCE is meaningful only in long mode on Intel */
 512         if (guest_efer & EFER_LMA)
 513                 ignore_bits &= ~(u64)EFER_SCE;
 514 #endif
 515         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 516                 return;
 517
 518         vmx->host_state.guest_efer_loaded = 1;
 519         guest_efer &= ~ignore_bits;
 520         guest_efer |= host_efer & ignore_bits;
 521         wrmsrl(MSR_EFER, guest_efer);
 522         vmx->vcpu.stat.efer_reload++;
 523 }
 524
 525 static void reload_host_efer(struct vcpu_vmx *vmx)
 526 {
 527         if (vmx->host_state.guest_efer_loaded) {
 528                 vmx->host_state.guest_efer_loaded = 0;
 529                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 530         }
 531 }
 532
 533 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 534 {
 535         struct vcpu_vmx *vmx = to_vmx(vcpu);
 536
 537         if (vmx->host_state.loaded)
 538                 return;
 539
 540         vmx->host_state.loaded = 1;
 541         /*
 542          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 543          * allow segment selectors with cpl > 0 or ti == 1.
 544          */
 545         vmx->host_state.ldt_sel = kvm_read_ldt();
 546         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 547         vmx->host_state.fs_sel = kvm_read_fs();
 548         if (!(vmx->host_state.fs_sel & 7)) {
 549                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 550                 vmx->host_state.fs_reload_needed = 0;
 551         } else {
 552                 vmcs_write16(HOST_FS_SELECTOR, 0);
 553                 vmx->host_state.fs_reload_needed = 1;
 554         }
 555         vmx->host_state.gs_sel = kvm_read_gs();
 556         if (!(vmx->host_state.gs_sel & 7))
 557                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 558         else {
 559                 vmcs_write16(HOST_GS_SELECTOR, 0);
 560                 vmx->host_state.gs_ldt_reload_needed = 1;
 561         }
 562
 563 #ifdef CONFIG_X86_64
 564         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 565         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 566 #else
 567         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 568         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 569 #endif
 570
 571 #ifdef CONFIG_X86_64
 572         if (is_long_mode(&vmx->vcpu))
 573                 save_msrs(vmx->host_msrs +
 574                           vmx->msr_offset_kernel_gs_base, 1);
 575
 576 #endif
 577         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 578         load_transition_efer(vmx);
 579 }
 580
 581 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 582 {
 583         unsigned long flags;
 584
 585         if (!vmx->host_state.loaded)
 586                 return;
 587
 588         ++vmx->vcpu.stat.host_state_reload;
 589         vmx->host_state.loaded = 0;
 590         if (vmx->host_state.fs_reload_needed)
 591                 kvm_load_fs(vmx->host_state.fs_sel);
 592         if (vmx->host_state.gs_ldt_reload_needed) {
 593                 kvm_load_ldt(vmx->host_state.ldt_sel);
 594                 /*
 595                  * If we have to reload gs, we must take care to
 596                  * preserve our gs base.
 597                  */
 598                 local_irq_save(flags);
 599                 kvm_load_gs(vmx->host_state.gs_sel);
 600 #ifdef CONFIG_X86_64
 601                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 602 #endif
 603                 local_irq_restore(flags);
 604         }
 605         reload_tss();
 606         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 607         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 608         reload_host_efer(vmx);
 609 }
 610
 611 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 612 {
 613         preempt_disable();
 614         __vmx_load_host_state(vmx);
 615         preempt_enable();
 616 }
 617
 618 /*
 619  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 620  * vcpu mutex is already taken.
 621  */
 622 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 623 {
 624         struct vcpu_vmx *vmx = to_vmx(vcpu);
 625         u64 phys_addr = __pa(vmx->vmcs);
 626         u64 tsc_this, delta, new_offset;
 627
 628         if (vcpu->cpu != cpu) {
 629                 vcpu_clear(vmx);
 630                 kvm_migrate_timers(vcpu);
 631                 vpid_sync_vcpu_all(vmx);
 632                 local_irq_disable();
 633                 list_add(&vmx->local_vcpus_link,
 634                          &per_cpu(vcpus_on_cpu, cpu));
 635                 local_irq_enable();
 636         }
 637
 638         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 639                 u8 error;
 640
 641                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 642                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 643                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 644                               : "cc");
 645                 if (error)
 646                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 647                                vmx->vmcs, phys_addr);
 648         }
 649
 650         if (vcpu->cpu != cpu) {
 651                 struct descriptor_table dt;
 652                 unsigned long sysenter_esp;
 653
 654                 vcpu->cpu = cpu;
 655                 /*
 656                  * Linux uses per-cpu TSS and GDT, so set these when switching
 657                  * processors.
 658                  */
 659                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 660                 kvm_get_gdt(&dt);
 661                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 662
 663                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 664                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 665
 666                 /*
 667                  * Make sure the time stamp counter is monotonous.
 668                  */
 669                 rdtscll(tsc_this);
 670                 if (tsc_this < vcpu->arch.host_tsc) {
 671                         delta = vcpu->arch.host_tsc - tsc_this;
 672                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 673                         vmcs_write64(TSC_OFFSET, new_offset);
 674                 }
 675         }
 676 }
 677
 678 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 679 {
 680         __vmx_load_host_state(to_vmx(vcpu));
 681 }
 682
 683 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 684 {
 685         if (vcpu->fpu_active)
 686                 return;
 687         vcpu->fpu_active = 1;
 688         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 689         if (vcpu->arch.cr0 & X86_CR0_TS)
 690                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 691         update_exception_bitmap(vcpu);
 692 }
 693
 694 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 695 {
 696         if (!vcpu->fpu_active)
 697                 return;
 698         vcpu->fpu_active = 0;
 699         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 700         update_exception_bitmap(vcpu);
 701 }
 702
 703 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 704 {
 705         return vmcs_readl(GUEST_RFLAGS);
 706 }
 707
 708 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 709 {
 710         if (vcpu->arch.rmode.active)
 711                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 712         vmcs_writel(GUEST_RFLAGS, rflags);
 713 }
 714
 715 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 716 {
 717         unsigned long rip;
 718         u32 interruptibility;
 719
 720         rip = kvm_rip_read(vcpu);
 721         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 722         kvm_rip_write(vcpu, rip);
 723
 724         /*
 725          * We emulated an instruction, so temporary interrupt blocking
 726          * should be removed, if set.
 727          */
 728         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 729         if (interruptibility & 3)
 730                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 731                              interruptibility & ~3);
 732         vcpu->arch.interrupt_window_open = 1;
 733 }
 734
 735 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 736                                 bool has_error_code, u32 error_code)
 737 {
 738         struct vcpu_vmx *vmx = to_vmx(vcpu);
 739
 740         if (has_error_code)
 741                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 742
 743         if (vcpu->arch.rmode.active) {
 744                 vmx->rmode.irq.pending = true;
 745                 vmx->rmode.irq.vector = nr;
 746                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 747                 if (nr == BP_VECTOR)
 748                         vmx->rmode.irq.rip++;
 749                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 750                              nr | INTR_TYPE_SOFT_INTR
 751                              | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 752                              | INTR_INFO_VALID_MASK);
 753                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 754                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 755                 return;
 756         }
 757
 758         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 759                      nr | INTR_TYPE_EXCEPTION
 760                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 761                      | INTR_INFO_VALID_MASK);
 762 }
 763
 764 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 765 {
 766         return false;
 767 }
 768
 769 /*
 770  * Swap MSR entry in host/guest MSR entry array.
 771  */
 772 #ifdef CONFIG_X86_64
 773 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 774 {
 775         struct kvm_msr_entry tmp;
 776
 777         tmp = vmx->guest_msrs[to];
 778         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 779         vmx->guest_msrs[from] = tmp;
 780         tmp = vmx->host_msrs[to];
 781         vmx->host_msrs[to] = vmx->host_msrs[from];
 782         vmx->host_msrs[from] = tmp;
 783 }
 784 #endif
 785
 786 /*
 787  * Set up the vmcs to automatically save and restore system
 788  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 789  * mode, as fiddling with msrs is very expensive.
 790  */
 791 static void setup_msrs(struct vcpu_vmx *vmx)
 792 {
 793         int save_nmsrs;
 794
 795         vmx_load_host_state(vmx);
 796         save_nmsrs = 0;
 797 #ifdef CONFIG_X86_64
 798         if (is_long_mode(&vmx->vcpu)) {
 799                 int index;
 800
 801                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 802                 if (index >= 0)
 803                         move_msr_up(vmx, index, save_nmsrs++);
 804                 index = __find_msr_index(vmx, MSR_LSTAR);
 805                 if (index >= 0)
 806                         move_msr_up(vmx, index, save_nmsrs++);
 807                 index = __find_msr_index(vmx, MSR_CSTAR);
 808                 if (index >= 0)
 809                         move_msr_up(vmx, index, save_nmsrs++);
 810                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 811                 if (index >= 0)
 812                         move_msr_up(vmx, index, save_nmsrs++);
 813                 /*
 814                  * MSR_K6_STAR is only needed on long mode guests, and only
 815                  * if efer.sce is enabled.
 816                  */
 817                 index = __find_msr_index(vmx, MSR_K6_STAR);
 818                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 819                         move_msr_up(vmx, index, save_nmsrs++);
 820         }
 821 #endif
 822         vmx->save_nmsrs = save_nmsrs;
 823
 824 #ifdef CONFIG_X86_64
 825         vmx->msr_offset_kernel_gs_base =
 826                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 827 #endif
 828         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 829 }
 830
 831 /*
 832  * reads and returns guest's timestamp counter "register"
 833  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 834  */
 835 static u64 guest_read_tsc(void)
 836 {
 837         u64 host_tsc, tsc_offset;
 838
 839         rdtscll(host_tsc);
 840         tsc_offset = vmcs_read64(TSC_OFFSET);
 841         return host_tsc + tsc_offset;
 842 }
 843
 844 /*
 845  * writes 'guest_tsc' into guest's timestamp counter "register"
 846  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 847  */
 848 static void guest_write_tsc(u64 guest_tsc)
 849 {
 850         u64 host_tsc;
 851
 852         rdtscll(host_tsc);
 853         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 854 }
 855
 856 /*
 857  * Reads an msr value (of 'msr_index') into 'pdata'.
 858  * Returns 0 on success, non-0 otherwise.
 859  * Assumes vcpu_load() was already called.
 860  */
 861 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 862 {
 863         u64 data;
 864         struct kvm_msr_entry *msr;
 865
 866         if (!pdata) {
 867                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 868                 return -EINVAL;
 869         }
 870
 871         switch (msr_index) {
 872 #ifdef CONFIG_X86_64
 873         case MSR_FS_BASE:
 874                 data = vmcs_readl(GUEST_FS_BASE);
 875                 break;
 876         case MSR_GS_BASE:
 877                 data = vmcs_readl(GUEST_GS_BASE);
 878                 break;
 879         case MSR_EFER:
 880                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 881 #endif
 882         case MSR_IA32_TIME_STAMP_COUNTER:
 883                 data = guest_read_tsc();
 884                 break;
 885         case MSR_IA32_SYSENTER_CS:
 886                 data = vmcs_read32(GUEST_SYSENTER_CS);
 887                 break;
 888         case MSR_IA32_SYSENTER_EIP:
 889                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 890                 break;
 891         case MSR_IA32_SYSENTER_ESP:
 892                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 893                 break;
 894         default:
 895                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 896                 if (msr) {
 897                         data = msr->data;
 898                         break;
 899                 }
 900                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 901         }
 902
 903         *pdata = data;
 904         return 0;
 905 }
 906
 907 /*
 908  * Writes msr value into into the appropriate "register".
 909  * Returns 0 on success, non-0 otherwise.
 910  * Assumes vcpu_load() was already called.
 911  */
 912 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 913 {
 914         struct vcpu_vmx *vmx = to_vmx(vcpu);
 915         struct kvm_msr_entry *msr;
 916         int ret = 0;
 917
 918         switch (msr_index) {
 919 #ifdef CONFIG_X86_64
 920         case MSR_EFER:
 921                 vmx_load_host_state(vmx);
 922                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 923                 break;
 924         case MSR_FS_BASE:
 925                 vmcs_writel(GUEST_FS_BASE, data);
 926                 break;
 927         case MSR_GS_BASE:
 928                 vmcs_writel(GUEST_GS_BASE, data);
 929                 break;
 930 #endif
 931         case MSR_IA32_SYSENTER_CS:
 932                 vmcs_write32(GUEST_SYSENTER_CS, data);
 933                 break;
 934         case MSR_IA32_SYSENTER_EIP:
 935                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 936                 break;
 937         case MSR_IA32_SYSENTER_ESP:
 938                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 939                 break;
 940         case MSR_IA32_TIME_STAMP_COUNTER:
 941                 guest_write_tsc(data);
 942                 break;
 943         case MSR_P6_PERFCTR0:
 944         case MSR_P6_PERFCTR1:
 945         case MSR_P6_EVNTSEL0:
 946         case MSR_P6_EVNTSEL1:
 947                 /*
 948                  * Just discard all writes to the performance counters; this
 949                  * should keep both older linux and windows 64-bit guests
 950                  * happy
 951                  */
 952                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 953
 954                 break;
 955         default:
 956                 vmx_load_host_state(vmx);
 957                 msr = find_msr_entry(vmx, msr_index);
 958                 if (msr) {
 959                         msr->data = data;
 960                         break;
 961                 }
 962                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 963         }
 964
 965         return ret;
 966 }
 967
 968 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 969 {
 970         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
 971         switch (reg) {
 972         case VCPU_REGS_RSP:
 973                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 974                 break;
 975         case VCPU_REGS_RIP:
 976                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
 977                 break;
 978         default:
 979                 break;
 980         }
 981 }
 982
 983 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 984 {
 985         unsigned long dr7 = 0x400;
 986         int old_singlestep;
 987
 988         old_singlestep = vcpu->guest_debug.singlestep;
 989
 990         vcpu->guest_debug.enabled = dbg->enabled;
 991         if (vcpu->guest_debug.enabled) {
 992                 int i;
 993
 994                 dr7 |= 0x200;  /* exact */
 995                 for (i = 0; i < 4; ++i) {
 996                         if (!dbg->breakpoints[i].enabled)
 997                                 continue;
 998                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 999                         dr7 |= 2 << (i*2);    /* global enable */
1000                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
1001                 }
1002
1003                 vcpu->guest_debug.singlestep = dbg->singlestep;
1004         } else
1005                 vcpu->guest_debug.singlestep = 0;
1006
1007         if (old_singlestep && !vcpu->guest_debug.singlestep) {
1008                 unsigned long flags;
1009
1010                 flags = vmcs_readl(GUEST_RFLAGS);
1011                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1012                 vmcs_writel(GUEST_RFLAGS, flags);
1013         }
1014
1015         update_exception_bitmap(vcpu);
1016         vmcs_writel(GUEST_DR7, dr7);
1017
1018         return 0;
1019 }
1020
1021 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1022 {
1023         if (!vcpu->arch.interrupt.pending)
1024                 return -1;
1025         return vcpu->arch.interrupt.nr;
1026 }
1027
1028 static __init int cpu_has_kvm_support(void)
1029 {
1030         unsigned long ecx = cpuid_ecx(1);
1031         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1032 }
1033
1034 static __init int vmx_disabled_by_bios(void)
1035 {
1036         u64 msr;
1037
1038         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1039         return (msr & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1040                        IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1041             == IA32_FEATURE_CONTROL_LOCKED_BIT;
1042         /* locked but not enabled */
1043 }
1044
1045 static void hardware_enable(void *garbage)
1046 {
1047         int cpu = raw_smp_processor_id();
1048         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1049         u64 old;
1050
1051         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1052         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1053         if ((old & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1054                     IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1055             != (IA32_FEATURE_CONTROL_LOCKED_BIT |
1056                 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1057                 /* enable and lock */
1058                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1059                        IA32_FEATURE_CONTROL_LOCKED_BIT |
1060                        IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT);
1061         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1062         asm volatile (ASM_VMX_VMXON_RAX
1063                       : : "a"(&phys_addr), "m"(phys_addr)
1064                       : "memory", "cc");
1065 }
1066
1067 static void vmclear_local_vcpus(void)
1068 {
1069         int cpu = raw_smp_processor_id();
1070         struct vcpu_vmx *vmx, *n;
1071
1072         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1073                                  local_vcpus_link)
1074                 __vcpu_clear(vmx);
1075 }
1076
1077 static void hardware_disable(void *garbage)
1078 {
1079         vmclear_local_vcpus();
1080         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1081         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1082 }
1083
1084 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1085                                       u32 msr, u32 *result)
1086 {
1087         u32 vmx_msr_low, vmx_msr_high;
1088         u32 ctl = ctl_min | ctl_opt;
1089
1090         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1091
1092         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1093         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1094
1095         /* Ensure minimum (required) set of control bits are supported. */
1096         if (ctl_min & ~ctl)
1097                 return -EIO;
1098
1099         *result = ctl;
1100         return 0;
1101 }
1102
1103 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1104 {
1105         u32 vmx_msr_low, vmx_msr_high;
1106         u32 min, opt, min2, opt2;
1107         u32 _pin_based_exec_control = 0;
1108         u32 _cpu_based_exec_control = 0;
1109         u32 _cpu_based_2nd_exec_control = 0;
1110         u32 _vmexit_control = 0;
1111         u32 _vmentry_control = 0;
1112
1113         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1114         opt = PIN_BASED_VIRTUAL_NMIS;
1115         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1116                                 &_pin_based_exec_control) < 0)
1117                 return -EIO;
1118
1119         min = CPU_BASED_HLT_EXITING |
1120 #ifdef CONFIG_X86_64
1121               CPU_BASED_CR8_LOAD_EXITING |
1122               CPU_BASED_CR8_STORE_EXITING |
1123 #endif
1124               CPU_BASED_CR3_LOAD_EXITING |
1125               CPU_BASED_CR3_STORE_EXITING |
1126               CPU_BASED_USE_IO_BITMAPS |
1127               CPU_BASED_MOV_DR_EXITING |
1128               CPU_BASED_USE_TSC_OFFSETING;
1129         opt = CPU_BASED_TPR_SHADOW |
1130               CPU_BASED_USE_MSR_BITMAPS |
1131               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1132         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1133                                 &_cpu_based_exec_control) < 0)
1134                 return -EIO;
1135 #ifdef CONFIG_X86_64
1136         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1137                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1138                                            ~CPU_BASED_CR8_STORE_EXITING;
1139 #endif
1140         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1141                 min2 = 0;
1142                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1143                         SECONDARY_EXEC_WBINVD_EXITING |
1144                         SECONDARY_EXEC_ENABLE_VPID |
1145                         SECONDARY_EXEC_ENABLE_EPT;
1146                 if (adjust_vmx_controls(min2, opt2,
1147                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1148                                         &_cpu_based_2nd_exec_control) < 0)
1149                         return -EIO;
1150         }
1151 #ifndef CONFIG_X86_64
1152         if (!(_cpu_based_2nd_exec_control &
1153                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1154                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1155 #endif
1156         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1157                 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1158                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1159                          CPU_BASED_CR3_STORE_EXITING);
1160                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1161                                         &_cpu_based_exec_control) < 0)
1162                         return -EIO;
1163                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1164                       vmx_capability.ept, vmx_capability.vpid);
1165         }
1166
1167         min = 0;
1168 #ifdef CONFIG_X86_64
1169         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1170 #endif
1171         opt = 0;
1172         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1173                                 &_vmexit_control) < 0)
1174                 return -EIO;
1175
1176         min = opt = 0;
1177         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1178                                 &_vmentry_control) < 0)
1179                 return -EIO;
1180
1181         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1182
1183         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1184         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1185                 return -EIO;
1186
1187 #ifdef CONFIG_X86_64
1188         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1189         if (vmx_msr_high & (1u<<16))
1190                 return -EIO;
1191 #endif
1192
1193         /* Require Write-Back (WB) memory type for VMCS accesses. */
1194         if (((vmx_msr_high >> 18) & 15) != 6)
1195                 return -EIO;
1196
1197         vmcs_conf->size = vmx_msr_high & 0x1fff;
1198         vmcs_conf->order = get_order(vmcs_config.size);
1199         vmcs_conf->revision_id = vmx_msr_low;
1200
1201         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1202         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1203         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1204         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1205         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1206
1207         return 0;
1208 }
1209
1210 static struct vmcs *alloc_vmcs_cpu(int cpu)
1211 {
1212         int node = cpu_to_node(cpu);
1213         struct page *pages;
1214         struct vmcs *vmcs;
1215
1216         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1217         if (!pages)
1218                 return NULL;
1219         vmcs = page_address(pages);
1220         memset(vmcs, 0, vmcs_config.size);
1221         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1222         return vmcs;
1223 }
1224
1225 static struct vmcs *alloc_vmcs(void)
1226 {
1227         return alloc_vmcs_cpu(raw_smp_processor_id());
1228 }
1229
1230 static void free_vmcs(struct vmcs *vmcs)
1231 {
1232         free_pages((unsigned long)vmcs, vmcs_config.order);
1233 }
1234
1235 static void free_kvm_area(void)
1236 {
1237         int cpu;
1238
1239         for_each_online_cpu(cpu)
1240                 free_vmcs(per_cpu(vmxarea, cpu));
1241 }
1242
1243 static __init int alloc_kvm_area(void)
1244 {
1245         int cpu;
1246
1247         for_each_online_cpu(cpu) {
1248                 struct vmcs *vmcs;
1249
1250                 vmcs = alloc_vmcs_cpu(cpu);
1251                 if (!vmcs) {
1252                         free_kvm_area();
1253                         return -ENOMEM;
1254                 }
1255
1256                 per_cpu(vmxarea, cpu) = vmcs;
1257         }
1258         return 0;
1259 }
1260
1261 static __init int hardware_setup(void)
1262 {
1263         if (setup_vmcs_config(&vmcs_config) < 0)
1264                 return -EIO;
1265
1266         if (boot_cpu_has(X86_FEATURE_NX))
1267                 kvm_enable_efer_bits(EFER_NX);
1268
1269         return alloc_kvm_area();
1270 }
1271
1272 static __exit void hardware_unsetup(void)
1273 {
1274         free_kvm_area();
1275 }
1276
1277 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1278 {
1279         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1280
1281         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1282                 vmcs_write16(sf->selector, save->selector);
1283                 vmcs_writel(sf->base, save->base);
1284                 vmcs_write32(sf->limit, save->limit);
1285                 vmcs_write32(sf->ar_bytes, save->ar);
1286         } else {
1287                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1288                         << AR_DPL_SHIFT;
1289                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1290         }
1291 }
1292
1293 static void enter_pmode(struct kvm_vcpu *vcpu)
1294 {
1295         unsigned long flags;
1296
1297         vcpu->arch.rmode.active = 0;
1298
1299         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1300         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1301         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1302
1303         flags = vmcs_readl(GUEST_RFLAGS);
1304         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1305         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1306         vmcs_writel(GUEST_RFLAGS, flags);
1307
1308         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1309                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1310
1311         update_exception_bitmap(vcpu);
1312
1313         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1314         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1315         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1316         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1317
1318         vmcs_write16(GUEST_SS_SELECTOR, 0);
1319         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1320
1321         vmcs_write16(GUEST_CS_SELECTOR,
1322                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1323         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1324 }
1325
1326 static gva_t rmode_tss_base(struct kvm *kvm)
1327 {
1328         if (!kvm->arch.tss_addr) {
1329                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1330                                  kvm->memslots[0].npages - 3;
1331                 return base_gfn << PAGE_SHIFT;
1332         }
1333         return kvm->arch.tss_addr;
1334 }
1335
1336 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1337 {
1338         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1339
1340         save->selector = vmcs_read16(sf->selector);
1341         save->base = vmcs_readl(sf->base);
1342         save->limit = vmcs_read32(sf->limit);
1343         save->ar = vmcs_read32(sf->ar_bytes);
1344         vmcs_write16(sf->selector, save->base >> 4);
1345         vmcs_write32(sf->base, save->base & 0xfffff);
1346         vmcs_write32(sf->limit, 0xffff);
1347         vmcs_write32(sf->ar_bytes, 0xf3);
1348 }
1349
1350 static void enter_rmode(struct kvm_vcpu *vcpu)
1351 {
1352         unsigned long flags;
1353
1354         vcpu->arch.rmode.active = 1;
1355
1356         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1357         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1358
1359         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1360         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1361
1362         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1363         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1364
1365         flags = vmcs_readl(GUEST_RFLAGS);
1366         vcpu->arch.rmode.save_iopl
1367                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1368
1369         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1370
1371         vmcs_writel(GUEST_RFLAGS, flags);
1372         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1373         update_exception_bitmap(vcpu);
1374
1375         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1376         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1377         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1378
1379         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1380         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1381         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1382                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1383         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1384
1385         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1386         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1387         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1388         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1389
1390         kvm_mmu_reset_context(vcpu);
1391         init_rmode(vcpu->kvm);
1392 }
1393
1394 #ifdef CONFIG_X86_64
1395
1396 static void enter_lmode(struct kvm_vcpu *vcpu)
1397 {
1398         u32 guest_tr_ar;
1399
1400         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1401         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1402                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1403                        __func__);
1404                 vmcs_write32(GUEST_TR_AR_BYTES,
1405                              (guest_tr_ar & ~AR_TYPE_MASK)
1406                              | AR_TYPE_BUSY_64_TSS);
1407         }
1408
1409         vcpu->arch.shadow_efer |= EFER_LMA;
1410
1411         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1412         vmcs_write32(VM_ENTRY_CONTROLS,
1413                      vmcs_read32(VM_ENTRY_CONTROLS)
1414                      | VM_ENTRY_IA32E_MODE);
1415 }
1416
1417 static void exit_lmode(struct kvm_vcpu *vcpu)
1418 {
1419         vcpu->arch.shadow_efer &= ~EFER_LMA;
1420
1421         vmcs_write32(VM_ENTRY_CONTROLS,
1422                      vmcs_read32(VM_ENTRY_CONTROLS)
1423                      & ~VM_ENTRY_IA32E_MODE);
1424 }
1425
1426 #endif
1427
1428 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1429 {
1430         vpid_sync_vcpu_all(to_vmx(vcpu));
1431         if (vm_need_ept())
1432                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1433 }
1434
1435 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1436 {
1437         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1438         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1439 }
1440
1441 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1442 {
1443         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1444                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1445                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1446                         return;
1447                 }
1448                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1449                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1450                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1451                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1452         }
1453 }
1454
1455 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1456
1457 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1458                                         unsigned long cr0,
1459                                         struct kvm_vcpu *vcpu)
1460 {
1461         if (!(cr0 & X86_CR0_PG)) {
1462                 /* From paging/starting to nonpaging */
1463                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1464                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1465                              (CPU_BASED_CR3_LOAD_EXITING |
1466                               CPU_BASED_CR3_STORE_EXITING));
1467                 vcpu->arch.cr0 = cr0;
1468                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1469                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1470                 *hw_cr0 &= ~X86_CR0_WP;
1471         } else if (!is_paging(vcpu)) {
1472                 /* From nonpaging to paging */
1473                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1474                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1475                              ~(CPU_BASED_CR3_LOAD_EXITING |
1476                                CPU_BASED_CR3_STORE_EXITING));
1477                 vcpu->arch.cr0 = cr0;
1478                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1479                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1480                         *hw_cr0 &= ~X86_CR0_WP;
1481         }
1482 }
1483
1484 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1485                                         struct kvm_vcpu *vcpu)
1486 {
1487         if (!is_paging(vcpu)) {
1488                 *hw_cr4 &= ~X86_CR4_PAE;
1489                 *hw_cr4 |= X86_CR4_PSE;
1490         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1491                 *hw_cr4 &= ~X86_CR4_PAE;
1492 }
1493
1494 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1495 {
1496         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1497                                 KVM_VM_CR0_ALWAYS_ON;
1498
1499         vmx_fpu_deactivate(vcpu);
1500
1501         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1502                 enter_pmode(vcpu);
1503
1504         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1505                 enter_rmode(vcpu);
1506
1507 #ifdef CONFIG_X86_64
1508         if (vcpu->arch.shadow_efer & EFER_LME) {
1509                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1510                         enter_lmode(vcpu);
1511                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1512                         exit_lmode(vcpu);
1513         }
1514 #endif
1515
1516         if (vm_need_ept())
1517                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1518
1519         vmcs_writel(CR0_READ_SHADOW, cr0);
1520         vmcs_writel(GUEST_CR0, hw_cr0);
1521         vcpu->arch.cr0 = cr0;
1522
1523         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1524                 vmx_fpu_activate(vcpu);
1525 }
1526
1527 static u64 construct_eptp(unsigned long root_hpa)
1528 {
1529         u64 eptp;
1530
1531         /* TODO write the value reading from MSR */
1532         eptp = VMX_EPT_DEFAULT_MT |
1533                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1534         eptp |= (root_hpa & PAGE_MASK);
1535
1536         return eptp;
1537 }
1538
1539 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1540 {
1541         unsigned long guest_cr3;
1542         u64 eptp;
1543
1544         guest_cr3 = cr3;
1545         if (vm_need_ept()) {
1546                 eptp = construct_eptp(cr3);
1547                 vmcs_write64(EPT_POINTER, eptp);
1548                 ept_sync_context(eptp);
1549                 ept_load_pdptrs(vcpu);
1550                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1551                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1552         }
1553
1554         vmx_flush_tlb(vcpu);
1555         vmcs_writel(GUEST_CR3, guest_cr3);
1556         if (vcpu->arch.cr0 & X86_CR0_PE)
1557                 vmx_fpu_deactivate(vcpu);
1558 }
1559
1560 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1561 {
1562         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1563                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1564
1565         vcpu->arch.cr4 = cr4;
1566         if (vm_need_ept())
1567                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1568
1569         vmcs_writel(CR4_READ_SHADOW, cr4);
1570         vmcs_writel(GUEST_CR4, hw_cr4);
1571 }
1572
1573 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1574 {
1575         struct vcpu_vmx *vmx = to_vmx(vcpu);
1576         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1577
1578         vcpu->arch.shadow_efer = efer;
1579         if (!msr)
1580                 return;
1581         if (efer & EFER_LMA) {
1582                 vmcs_write32(VM_ENTRY_CONTROLS,
1583                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1584                                      VM_ENTRY_IA32E_MODE);
1585                 msr->data = efer;
1586
1587         } else {
1588                 vmcs_write32(VM_ENTRY_CONTROLS,
1589                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1590                                      ~VM_ENTRY_IA32E_MODE);
1591
1592                 msr->data = efer & ~EFER_LME;
1593         }
1594         setup_msrs(vmx);
1595 }
1596
1597 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1598 {
1599         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1600
1601         return vmcs_readl(sf->base);
1602 }
1603
1604 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1605                             struct kvm_segment *var, int seg)
1606 {
1607         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1608         u32 ar;
1609
1610         var->base = vmcs_readl(sf->base);
1611         var->limit = vmcs_read32(sf->limit);
1612         var->selector = vmcs_read16(sf->selector);
1613         ar = vmcs_read32(sf->ar_bytes);
1614         if (ar & AR_UNUSABLE_MASK)
1615                 ar = 0;
1616         var->type = ar & 15;
1617         var->s = (ar >> 4) & 1;
1618         var->dpl = (ar >> 5) & 3;
1619         var->present = (ar >> 7) & 1;
1620         var->avl = (ar >> 12) & 1;
1621         var->l = (ar >> 13) & 1;
1622         var->db = (ar >> 14) & 1;
1623         var->g = (ar >> 15) & 1;
1624         var->unusable = (ar >> 16) & 1;
1625 }
1626
1627 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1628 {
1629         struct kvm_segment kvm_seg;
1630
1631         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1632                 return 0;
1633
1634         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1635                 return 3;
1636
1637         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1638         return kvm_seg.selector & 3;
1639 }
1640
1641 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1642 {
1643         u32 ar;
1644
1645         if (var->unusable)
1646                 ar = 1 << 16;
1647         else {
1648                 ar = var->type & 15;
1649                 ar |= (var->s & 1) << 4;
1650                 ar |= (var->dpl & 3) << 5;
1651                 ar |= (var->present & 1) << 7;
1652                 ar |= (var->avl & 1) << 12;
1653                 ar |= (var->l & 1) << 13;
1654                 ar |= (var->db & 1) << 14;
1655                 ar |= (var->g & 1) << 15;
1656         }
1657         if (ar == 0) /* a 0 value means unusable */
1658                 ar = AR_UNUSABLE_MASK;
1659
1660         return ar;
1661 }
1662
1663 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1664                             struct kvm_segment *var, int seg)
1665 {
1666         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1667         u32 ar;
1668
1669         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1670                 vcpu->arch.rmode.tr.selector = var->selector;
1671                 vcpu->arch.rmode.tr.base = var->base;
1672                 vcpu->arch.rmode.tr.limit = var->limit;
1673                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1674                 return;
1675         }
1676         vmcs_writel(sf->base, var->base);
1677         vmcs_write32(sf->limit, var->limit);
1678         vmcs_write16(sf->selector, var->selector);
1679         if (vcpu->arch.rmode.active && var->s) {
1680                 /*
1681                  * Hack real-mode segments into vm86 compatibility.
1682                  */
1683                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1684                         vmcs_writel(sf->base, 0xf0000);
1685                 ar = 0xf3;
1686         } else
1687                 ar = vmx_segment_access_rights(var);
1688         vmcs_write32(sf->ar_bytes, ar);
1689 }
1690
1691 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1692 {
1693         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1694
1695         *db = (ar >> 14) & 1;
1696         *l = (ar >> 13) & 1;
1697 }
1698
1699 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1700 {
1701         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1702         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1703 }
1704
1705 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1706 {
1707         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1708         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1709 }
1710
1711 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1712 {
1713         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1714         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1715 }
1716
1717 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1718 {
1719         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1720         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1721 }
1722
1723 static int init_rmode_tss(struct kvm *kvm)
1724 {
1725         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1726         u16 data = 0;
1727         int ret = 0;
1728         int r;
1729
1730         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1731         if (r < 0)
1732                 goto out;
1733         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1734         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1735         if (r < 0)
1736                 goto out;
1737         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1738         if (r < 0)
1739                 goto out;
1740         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1741         if (r < 0)
1742                 goto out;
1743         data = ~0;
1744         r = kvm_write_guest_page(kvm, fn, &data,
1745                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1746                                  sizeof(u8));
1747         if (r < 0)
1748                 goto out;
1749
1750         ret = 1;
1751 out:
1752         return ret;
1753 }
1754
1755 static int init_rmode_identity_map(struct kvm *kvm)
1756 {
1757         int i, r, ret;
1758         pfn_t identity_map_pfn;
1759         u32 tmp;
1760
1761         if (!vm_need_ept())
1762                 return 1;
1763         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1764                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1765                         "haven't been allocated!\n");
1766                 return 0;
1767         }
1768         if (likely(kvm->arch.ept_identity_pagetable_done))
1769                 return 1;
1770         ret = 0;
1771         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1772         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1773         if (r < 0)
1774                 goto out;
1775         /* Set up identity-mapping pagetable for EPT in real mode */
1776         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1777                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1778                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1779                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1780                                 &tmp, i * sizeof(tmp), sizeof(tmp));
1781                 if (r < 0)
1782                         goto out;
1783         }
1784         kvm->arch.ept_identity_pagetable_done = true;
1785         ret = 1;
1786 out:
1787         return ret;
1788 }
1789
1790 static void seg_setup(int seg)
1791 {
1792         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1793
1794         vmcs_write16(sf->selector, 0);
1795         vmcs_writel(sf->base, 0);
1796         vmcs_write32(sf->limit, 0xffff);
1797         vmcs_write32(sf->ar_bytes, 0x93);
1798 }
1799
1800 static int alloc_apic_access_page(struct kvm *kvm)
1801 {
1802         struct kvm_userspace_memory_region kvm_userspace_mem;
1803         int r = 0;
1804
1805         down_write(&kvm->slots_lock);
1806         if (kvm->arch.apic_access_page)
1807                 goto out;
1808         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1809         kvm_userspace_mem.flags = 0;
1810         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1811         kvm_userspace_mem.memory_size = PAGE_SIZE;
1812         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1813         if (r)
1814                 goto out;
1815
1816         down_read(&current->mm->mmap_sem);
1817         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1818         up_read(&current->mm->mmap_sem);
1819 out:
1820         up_write(&kvm->slots_lock);
1821         return r;
1822 }
1823
1824 static int alloc_identity_pagetable(struct kvm *kvm)
1825 {
1826         struct kvm_userspace_memory_region kvm_userspace_mem;
1827         int r = 0;
1828
1829         down_write(&kvm->slots_lock);
1830         if (kvm->arch.ept_identity_pagetable)
1831                 goto out;
1832         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1833         kvm_userspace_mem.flags = 0;
1834         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1835         kvm_userspace_mem.memory_size = PAGE_SIZE;
1836         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1837         if (r)
1838                 goto out;
1839
1840         down_read(&current->mm->mmap_sem);
1841         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1842                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1843         up_read(&current->mm->mmap_sem);
1844 out:
1845         up_write(&kvm->slots_lock);
1846         return r;
1847 }
1848
1849 static void allocate_vpid(struct vcpu_vmx *vmx)
1850 {
1851         int vpid;
1852
1853         vmx->vpid = 0;
1854         if (!enable_vpid || !cpu_has_vmx_vpid())
1855                 return;
1856         spin_lock(&vmx_vpid_lock);
1857         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1858         if (vpid < VMX_NR_VPIDS) {
1859                 vmx->vpid = vpid;
1860                 __set_bit(vpid, vmx_vpid_bitmap);
1861         }
1862         spin_unlock(&vmx_vpid_lock);
1863 }
1864
1865 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1866 {
1867         void *va;
1868
1869         if (!cpu_has_vmx_msr_bitmap())
1870                 return;
1871
1872         /*
1873          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1874          * have the write-low and read-high bitmap offsets the wrong way round.
1875          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1876          */
1877         va = kmap(msr_bitmap);
1878         if (msr <= 0x1fff) {
1879                 __clear_bit(msr, va + 0x000); /* read-low */
1880                 __clear_bit(msr, va + 0x800); /* write-low */
1881         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1882                 msr &= 0x1fff;
1883                 __clear_bit(msr, va + 0x400); /* read-high */
1884                 __clear_bit(msr, va + 0xc00); /* write-high */
1885         }
1886         kunmap(msr_bitmap);
1887 }
1888
1889 /*
1890  * Sets up the vmcs for emulated real mode.
1891  */
1892 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1893 {
1894         u32 host_sysenter_cs;
1895         u32 junk;
1896         unsigned long a;
1897         struct descriptor_table dt;
1898         int i;
1899         unsigned long kvm_vmx_return;
1900         u32 exec_control;
1901
1902         /* I/O */
1903         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1904         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1905
1906         if (cpu_has_vmx_msr_bitmap())
1907                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1908
1909         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1910
1911         /* Control */
1912         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1913                 vmcs_config.pin_based_exec_ctrl);
1914
1915         exec_control = vmcs_config.cpu_based_exec_ctrl;
1916         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1917                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1918 #ifdef CONFIG_X86_64
1919                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1920                                 CPU_BASED_CR8_LOAD_EXITING;
1921 #endif
1922         }
1923         if (!vm_need_ept())
1924                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1925                                 CPU_BASED_CR3_LOAD_EXITING;
1926         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1927
1928         if (cpu_has_secondary_exec_ctrls()) {
1929                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1930                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1931                         exec_control &=
1932                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1933                 if (vmx->vpid == 0)
1934                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1935                 if (!vm_need_ept())
1936                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
1937                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1938         }
1939
1940         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1941         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1942         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1943
1944         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1945         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1946         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1947
1948         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1949         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1950         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1951         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
1952         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
1953         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1954 #ifdef CONFIG_X86_64
1955         rdmsrl(MSR_FS_BASE, a);
1956         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1957         rdmsrl(MSR_GS_BASE, a);
1958         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1959 #else
1960         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1961         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1962 #endif
1963
1964         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1965
1966         kvm_get_idt(&dt);
1967         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1968
1969         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1970         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1971         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1972         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1973         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1974
1975         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1976         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1977         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1978         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1979         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1980         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1981
1982         for (i = 0; i < NR_VMX_MSR; ++i) {
1983                 u32 index = vmx_msr_index[i];
1984                 u32 data_low, data_high;
1985                 u64 data;
1986                 int j = vmx->nmsrs;
1987
1988                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1989                         continue;
1990                 if (wrmsr_safe(index, data_low, data_high) < 0)
1991                         continue;
1992                 data = data_low | ((u64)data_high << 32);
1993                 vmx->host_msrs[j].index = index;
1994                 vmx->host_msrs[j].reserved = 0;
1995                 vmx->host_msrs[j].data = data;
1996                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1997                 ++vmx->nmsrs;
1998         }
1999
2000         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2001
2002         /* 22.2.1, 20.8.1 */
2003         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2004
2005         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2006         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2007
2008
2009         return 0;
2010 }
2011
2012 static int init_rmode(struct kvm *kvm)
2013 {
2014         if (!init_rmode_tss(kvm))
2015                 return 0;
2016         if (!init_rmode_identity_map(kvm))
2017                 return 0;
2018         return 1;
2019 }
2020
2021 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2022 {
2023         struct vcpu_vmx *vmx = to_vmx(vcpu);
2024         u64 msr;
2025         int ret;
2026
2027         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2028         down_read(&vcpu->kvm->slots_lock);
2029         if (!init_rmode(vmx->vcpu.kvm)) {
2030                 ret = -ENOMEM;
2031                 goto out;
2032         }
2033
2034         vmx->vcpu.arch.rmode.active = 0;
2035
2036         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2037         kvm_set_cr8(&vmx->vcpu, 0);
2038         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2039         if (vmx->vcpu.vcpu_id == 0)
2040                 msr |= MSR_IA32_APICBASE_BSP;
2041         kvm_set_apic_base(&vmx->vcpu, msr);
2042
2043         fx_init(&vmx->vcpu);
2044
2045         /*
2046          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2047          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2048          */
2049         if (vmx->vcpu.vcpu_id == 0) {
2050                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2051                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2052         } else {
2053                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2054                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2055         }
2056         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2057         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2058
2059         seg_setup(VCPU_SREG_DS);
2060         seg_setup(VCPU_SREG_ES);
2061         seg_setup(VCPU_SREG_FS);
2062         seg_setup(VCPU_SREG_GS);
2063         seg_setup(VCPU_SREG_SS);
2064
2065         vmcs_write16(GUEST_TR_SELECTOR, 0);
2066         vmcs_writel(GUEST_TR_BASE, 0);
2067         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2068         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2069
2070         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2071         vmcs_writel(GUEST_LDTR_BASE, 0);
2072         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2073         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2074
2075         vmcs_write32(GUEST_SYSENTER_CS, 0);
2076         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2077         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2078
2079         vmcs_writel(GUEST_RFLAGS, 0x02);
2080         if (vmx->vcpu.vcpu_id == 0)
2081                 kvm_rip_write(vcpu, 0xfff0);
2082         else
2083                 kvm_rip_write(vcpu, 0);
2084         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2085
2086         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2087         vmcs_writel(GUEST_DR7, 0x400);
2088
2089         vmcs_writel(GUEST_GDTR_BASE, 0);
2090         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2091
2092         vmcs_writel(GUEST_IDTR_BASE, 0);
2093         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2094
2095         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2096         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2097         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2098
2099         guest_write_tsc(0);
2100
2101         /* Special registers */
2102         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2103
2104         setup_msrs(vmx);
2105
2106         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2107
2108         if (cpu_has_vmx_tpr_shadow()) {
2109                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2110                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2111                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2112                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2113                 vmcs_write32(TPR_THRESHOLD, 0);
2114         }
2115
2116         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2117                 vmcs_write64(APIC_ACCESS_ADDR,
2118                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2119
2120         if (vmx->vpid != 0)
2121                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2122
2123         vmx->vcpu.arch.cr0 = 0x60000010;
2124         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2125         vmx_set_cr4(&vmx->vcpu, 0);
2126         vmx_set_efer(&vmx->vcpu, 0);
2127         vmx_fpu_activate(&vmx->vcpu);
2128         update_exception_bitmap(&vmx->vcpu);
2129
2130         vpid_sync_vcpu_all(vmx);
2131
2132         ret = 0;
2133
2134 out:
2135         up_read(&vcpu->kvm->slots_lock);
2136         return ret;
2137 }
2138
2139 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2140 {
2141         struct vcpu_vmx *vmx = to_vmx(vcpu);
2142
2143         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2144
2145         if (vcpu->arch.rmode.active) {
2146                 vmx->rmode.irq.pending = true;
2147                 vmx->rmode.irq.vector = irq;
2148                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2149                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2150                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2151                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2152                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2153                 return;
2154         }
2155         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2156                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2157 }
2158
2159 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2160 {
2161         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2162                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2163 }
2164
2165 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2166 {
2167         int word_index = __ffs(vcpu->arch.irq_summary);
2168         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2169         int irq = word_index * BITS_PER_LONG + bit_index;
2170
2171         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2172         if (!vcpu->arch.irq_pending[word_index])
2173                 clear_bit(word_index, &vcpu->arch.irq_summary);
2174         vmx_inject_irq(vcpu, irq);
2175 }
2176
2177
2178 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2179                                        struct kvm_run *kvm_run)
2180 {
2181         u32 cpu_based_vm_exec_control;
2182
2183         vcpu->arch.interrupt_window_open =
2184                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2185                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2186
2187         if (vcpu->arch.interrupt_window_open &&
2188             vcpu->arch.irq_summary &&
2189             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
2190                 /*
2191                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2192                  */
2193                 kvm_do_inject_irq(vcpu);
2194
2195         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2196         if (!vcpu->arch.interrupt_window_open &&
2197             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2198                 /*
2199                  * Interrupts blocked.  Wait for unblock.
2200                  */
2201                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2202         else
2203                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2204         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2205 }
2206
2207 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2208 {
2209         int ret;
2210         struct kvm_userspace_memory_region tss_mem = {
2211                 .slot = 8,
2212                 .guest_phys_addr = addr,
2213                 .memory_size = PAGE_SIZE * 3,
2214                 .flags = 0,
2215         };
2216
2217         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2218         if (ret)
2219                 return ret;
2220         kvm->arch.tss_addr = addr;
2221         return 0;
2222 }
2223
2224 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2225 {
2226         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2227
2228         set_debugreg(dbg->bp[0], 0);
2229         set_debugreg(dbg->bp[1], 1);
2230         set_debugreg(dbg->bp[2], 2);
2231         set_debugreg(dbg->bp[3], 3);
2232
2233         if (dbg->singlestep) {
2234                 unsigned long flags;
2235
2236                 flags = vmcs_readl(GUEST_RFLAGS);
2237                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2238                 vmcs_writel(GUEST_RFLAGS, flags);
2239         }
2240 }
2241
2242 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2243                                   int vec, u32 err_code)
2244 {
2245         /*
2246          * Instruction with address size override prefix opcode 0x67
2247          * Cause the #SS fault with 0 error code in VM86 mode.
2248          */
2249         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2250                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2251                         return 1;
2252         /*
2253          * Forward all other exceptions that are valid in real mode.
2254          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2255          *        the required debugging infrastructure rework.
2256          */
2257         switch (vec) {
2258         case DE_VECTOR:
2259         case DB_VECTOR:
2260         case BP_VECTOR:
2261         case OF_VECTOR:
2262         case BR_VECTOR:
2263         case UD_VECTOR:
2264         case DF_VECTOR:
2265         case SS_VECTOR:
2266         case GP_VECTOR:
2267         case MF_VECTOR:
2268                 kvm_queue_exception(vcpu, vec);
2269                 return 1;
2270         }
2271         return 0;
2272 }
2273
2274 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2275 {
2276         struct vcpu_vmx *vmx = to_vmx(vcpu);
2277         u32 intr_info, error_code;
2278         unsigned long cr2, rip;
2279         u32 vect_info;
2280         enum emulation_result er;
2281
2282         vect_info = vmx->idt_vectoring_info;
2283         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2284
2285         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2286                                                 !is_page_fault(intr_info))
2287                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2288                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2289
2290         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2291                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2292                 set_bit(irq, vcpu->arch.irq_pending);
2293                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2294         }
2295
2296         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2297                 return 1;  /* already handled by vmx_vcpu_run() */
2298
2299         if (is_no_device(intr_info)) {
2300                 vmx_fpu_activate(vcpu);
2301                 return 1;
2302         }
2303
2304         if (is_invalid_opcode(intr_info)) {
2305                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2306                 if (er != EMULATE_DONE)
2307                         kvm_queue_exception(vcpu, UD_VECTOR);
2308                 return 1;
2309         }
2310
2311         error_code = 0;
2312         rip = kvm_rip_read(vcpu);
2313         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2314                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2315         if (is_page_fault(intr_info)) {
2316                 /* EPT won't cause page fault directly */
2317                 if (vm_need_ept())
2318                         BUG();
2319                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2320                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2321                             (u32)((u64)cr2 >> 32), handler);
2322                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2323                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2324                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2325         }
2326
2327         if (vcpu->arch.rmode.active &&
2328             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2329                                                                 error_code)) {
2330                 if (vcpu->arch.halt_request) {
2331                         vcpu->arch.halt_request = 0;
2332                         return kvm_emulate_halt(vcpu);
2333                 }
2334                 return 1;
2335         }
2336
2337         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2338             (INTR_TYPE_EXCEPTION | 1)) {
2339                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2340                 return 0;
2341         }
2342         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2343         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2344         kvm_run->ex.error_code = error_code;
2345         return 0;
2346 }
2347
2348 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2349                                      struct kvm_run *kvm_run)
2350 {
2351         ++vcpu->stat.irq_exits;
2352         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2353         return 1;
2354 }
2355
2356 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2357 {
2358         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2359         return 0;
2360 }
2361
2362 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2363 {
2364         unsigned long exit_qualification;
2365         int size, down, in, string, rep;
2366         unsigned port;
2367
2368         ++vcpu->stat.io_exits;
2369         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2370         string = (exit_qualification & 16) != 0;
2371
2372         if (string) {
2373                 if (emulate_instruction(vcpu,
2374                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2375                         return 0;
2376                 return 1;
2377         }
2378
2379         size = (exit_qualification & 7) + 1;
2380         in = (exit_qualification & 8) != 0;
2381         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2382         rep = (exit_qualification & 32) != 0;
2383         port = exit_qualification >> 16;
2384
2385         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2386 }
2387
2388 static void
2389 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2390 {
2391         /*
2392          * Patch in the VMCALL instruction:
2393          */
2394         hypercall[0] = 0x0f;
2395         hypercall[1] = 0x01;
2396         hypercall[2] = 0xc1;
2397 }
2398
2399 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2400 {
2401         unsigned long exit_qualification;
2402         int cr;
2403         int reg;
2404
2405         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2406         cr = exit_qualification & 15;
2407         reg = (exit_qualification >> 8) & 15;
2408         switch ((exit_qualification >> 4) & 3) {
2409         case 0: /* mov to cr */
2410                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2411                             (u32)kvm_register_read(vcpu, reg),
2412                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2413                             handler);
2414                 switch (cr) {
2415                 case 0:
2416                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2417                         skip_emulated_instruction(vcpu);
2418                         return 1;
2419                 case 3:
2420                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2421                         skip_emulated_instruction(vcpu);
2422                         return 1;
2423                 case 4:
2424                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2425                         skip_emulated_instruction(vcpu);
2426                         return 1;
2427                 case 8:
2428                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2429                         skip_emulated_instruction(vcpu);
2430                         if (irqchip_in_kernel(vcpu->kvm))
2431                                 return 1;
2432                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2433                         return 0;
2434                 };
2435                 break;
2436         case 2: /* clts */
2437                 vmx_fpu_deactivate(vcpu);
2438                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2439                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2440                 vmx_fpu_activate(vcpu);
2441                 KVMTRACE_0D(CLTS, vcpu, handler);
2442                 skip_emulated_instruction(vcpu);
2443                 return 1;
2444         case 1: /*mov from cr*/
2445                 switch (cr) {
2446                 case 3:
2447                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2448                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2449                                     (u32)kvm_register_read(vcpu, reg),
2450                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2451                                     handler);
2452                         skip_emulated_instruction(vcpu);
2453                         return 1;
2454                 case 8:
2455                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2456                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2457                                     (u32)kvm_register_read(vcpu, reg), handler);
2458                         skip_emulated_instruction(vcpu);
2459                         return 1;
2460                 }
2461                 break;
2462         case 3: /* lmsw */
2463                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2464
2465                 skip_emulated_instruction(vcpu);
2466                 return 1;
2467         default:
2468                 break;
2469         }
2470         kvm_run->exit_reason = 0;
2471         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2472                (int)(exit_qualification >> 4) & 3, cr);
2473         return 0;
2474 }
2475
2476 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2477 {
2478         unsigned long exit_qualification;
2479         unsigned long val;
2480         int dr, reg;
2481
2482         /*
2483          * FIXME: this code assumes the host is debugging the guest.
2484          *        need to deal with guest debugging itself too.
2485          */
2486         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2487         dr = exit_qualification & 7;
2488         reg = (exit_qualification >> 8) & 15;
2489         if (exit_qualification & 16) {
2490                 /* mov from dr */
2491                 switch (dr) {
2492                 case 6:
2493                         val = 0xffff0ff0;
2494                         break;
2495                 case 7:
2496                         val = 0x400;
2497                         break;
2498                 default:
2499                         val = 0;
2500                 }
2501                 kvm_register_write(vcpu, reg, val);
2502                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2503         } else {
2504                 /* mov to dr */
2505         }
2506         skip_emulated_instruction(vcpu);
2507         return 1;
2508 }
2509
2510 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2511 {
2512         kvm_emulate_cpuid(vcpu);
2513         return 1;
2514 }
2515
2516 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2517 {
2518         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2519         u64 data;
2520
2521         if (vmx_get_msr(vcpu, ecx, &data)) {
2522                 kvm_inject_gp(vcpu, 0);
2523                 return 1;
2524         }
2525
2526         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2527                     handler);
2528
2529         /* FIXME: handling of bits 32:63 of rax, rdx */
2530         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2531         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2532         skip_emulated_instruction(vcpu);
2533         return 1;
2534 }
2535
2536 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2537 {
2538         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2539         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2540                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2541
2542         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2543                     handler);
2544
2545         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2546                 kvm_inject_gp(vcpu, 0);
2547                 return 1;
2548         }
2549
2550         skip_emulated_instruction(vcpu);
2551         return 1;
2552 }
2553
2554 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2555                                       struct kvm_run *kvm_run)
2556 {
2557         return 1;
2558 }
2559
2560 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2561                                    struct kvm_run *kvm_run)
2562 {
2563         u32 cpu_based_vm_exec_control;
2564
2565         /* clear pending irq */
2566         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2567         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2568         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2569
2570         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2571
2572         /*
2573          * If the user space waits to inject interrupts, exit as soon as
2574          * possible
2575          */
2576         if (kvm_run->request_interrupt_window &&
2577             !vcpu->arch.irq_summary) {
2578                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2579                 ++vcpu->stat.irq_window_exits;
2580                 return 0;
2581         }
2582         return 1;
2583 }
2584
2585 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2586 {
2587         skip_emulated_instruction(vcpu);
2588         return kvm_emulate_halt(vcpu);
2589 }
2590
2591 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2592 {
2593         skip_emulated_instruction(vcpu);
2594         kvm_emulate_hypercall(vcpu);
2595         return 1;
2596 }
2597
2598 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2599 {
2600         skip_emulated_instruction(vcpu);
2601         /* TODO: Add support for VT-d/pass-through device */
2602         return 1;
2603 }
2604
2605 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2606 {
2607         u64 exit_qualification;
2608         enum emulation_result er;
2609         unsigned long offset;
2610
2611         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2612         offset = exit_qualification & 0xffful;
2613
2614         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2615
2616         if (er !=  EMULATE_DONE) {
2617                 printk(KERN_ERR
2618                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2619                        offset);
2620                 return -ENOTSUPP;
2621         }
2622         return 1;
2623 }
2624
2625 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2626 {
2627         unsigned long exit_qualification;
2628         u16 tss_selector;
2629         int reason;
2630
2631         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2632
2633         reason = (u32)exit_qualification >> 30;
2634         tss_selector = exit_qualification;
2635
2636         return kvm_task_switch(vcpu, tss_selector, reason);
2637 }
2638
2639 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2640 {
2641         u64 exit_qualification;
2642         enum emulation_result er;
2643         gpa_t gpa;
2644         unsigned long hva;
2645         int gla_validity;
2646         int r;
2647
2648         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2649
2650         if (exit_qualification & (1 << 6)) {
2651                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2652                 return -ENOTSUPP;
2653         }
2654
2655         gla_validity = (exit_qualification >> 7) & 0x3;
2656         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2657                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2658                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2659                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2660                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2661                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2662                         (long unsigned int)exit_qualification);
2663                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2664                 kvm_run->hw.hardware_exit_reason = 0;
2665                 return -ENOTSUPP;
2666         }
2667
2668         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2669         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2670         if (!kvm_is_error_hva(hva)) {
2671                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2672                 if (r < 0) {
2673                         printk(KERN_ERR "EPT: Not enough memory!\n");
2674                         return -ENOMEM;
2675                 }
2676                 return 1;
2677         } else {
2678                 /* must be MMIO */
2679                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2680
2681                 if (er == EMULATE_FAIL) {
2682                         printk(KERN_ERR
2683                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2684                          er);
2685                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2686                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2687                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2688                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2689                                 (long unsigned int)exit_qualification);
2690                         return -ENOTSUPP;
2691                 } else if (er == EMULATE_DO_MMIO)
2692                         return 0;
2693         }
2694         return 1;
2695 }
2696
2697 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2698 {
2699         u32 cpu_based_vm_exec_control;
2700
2701         /* clear pending NMI */
2702         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2703         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2704         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2705         ++vcpu->stat.nmi_window_exits;
2706
2707         return 1;
2708 }
2709
2710 /*
2711  * The exit handlers return 1 if the exit was handled fully and guest execution
2712  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2713  * to be done to userspace and return 0.
2714  */
2715 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2716                                       struct kvm_run *kvm_run) = {
2717         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2718         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2719         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2720         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
2721         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2722         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2723         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2724         [EXIT_REASON_CPUID]                   = handle_cpuid,
2725         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2726         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2727         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2728         [EXIT_REASON_HLT]                     = handle_halt,
2729         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2730         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2731         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2732         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2733         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
2734         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
2735 };
2736
2737 static const int kvm_vmx_max_exit_handlers =
2738         ARRAY_SIZE(kvm_vmx_exit_handlers);
2739
2740 /*
2741  * The guest has exited.  See if we can fix it or if we need userspace
2742  * assistance.
2743  */
2744 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2745 {
2746         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2747         struct vcpu_vmx *vmx = to_vmx(vcpu);
2748         u32 vectoring_info = vmx->idt_vectoring_info;
2749
2750         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
2751                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2752
2753         /* Access CR3 don't cause VMExit in paging mode, so we need
2754          * to sync with guest real CR3. */
2755         if (vm_need_ept() && is_paging(vcpu)) {
2756                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2757                 ept_load_pdptrs(vcpu);
2758         }
2759
2760         if (unlikely(vmx->fail)) {
2761                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2762                 kvm_run->fail_entry.hardware_entry_failure_reason
2763                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2764                 return 0;
2765         }
2766
2767         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2768                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2769                         exit_reason != EXIT_REASON_EPT_VIOLATION))
2770                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2771                        "exit reason is 0x%x\n", __func__, exit_reason);
2772         if (exit_reason < kvm_vmx_max_exit_handlers
2773             && kvm_vmx_exit_handlers[exit_reason])
2774                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2775         else {
2776                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2777                 kvm_run->hw.hardware_exit_reason = exit_reason;
2778         }
2779         return 0;
2780 }
2781
2782 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2783 {
2784         int max_irr, tpr;
2785
2786         if (!vm_need_tpr_shadow(vcpu->kvm))
2787                 return;
2788
2789         if (!kvm_lapic_enabled(vcpu) ||
2790             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2791                 vmcs_write32(TPR_THRESHOLD, 0);
2792                 return;
2793         }
2794
2795         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2796         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2797 }
2798
2799 static void enable_irq_window(struct kvm_vcpu *vcpu)
2800 {
2801         u32 cpu_based_vm_exec_control;
2802
2803         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2804         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2805         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2806 }
2807
2808 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2809 {
2810         u32 cpu_based_vm_exec_control;
2811
2812         if (!cpu_has_virtual_nmis())
2813                 return;
2814
2815         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2816         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2817         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2818 }
2819
2820 static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
2821 {
2822         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2823         return !(guest_intr & (GUEST_INTR_STATE_NMI |
2824                                GUEST_INTR_STATE_MOV_SS |
2825                                GUEST_INTR_STATE_STI));
2826 }
2827
2828 static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
2829 {
2830         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2831         return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
2832                                GUEST_INTR_STATE_STI)) &&
2833                 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2834 }
2835
2836 static void enable_intr_window(struct kvm_vcpu *vcpu)
2837 {
2838         if (vcpu->arch.nmi_pending)
2839                 enable_nmi_window(vcpu);
2840         else if (kvm_cpu_has_interrupt(vcpu))
2841                 enable_irq_window(vcpu);
2842 }
2843
2844 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
2845 {
2846         u32 exit_intr_info;
2847         u32 idt_vectoring_info;
2848         bool unblock_nmi;
2849         u8 vector;
2850         int type;
2851         bool idtv_info_valid;
2852         u32 error;
2853
2854         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2855         if (cpu_has_virtual_nmis()) {
2856                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
2857                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
2858                 /*
2859                  * SDM 3: 25.7.1.2
2860                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
2861                  * a guest IRET fault.
2862                  */
2863                 if (unblock_nmi && vector != DF_VECTOR)
2864                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2865                                       GUEST_INTR_STATE_NMI);
2866         }
2867
2868         idt_vectoring_info = vmx->idt_vectoring_info;
2869         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
2870         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
2871         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
2872         if (vmx->vcpu.arch.nmi_injected) {
2873                 /*
2874                  * SDM 3: 25.7.1.2
2875                  * Clear bit "block by NMI" before VM entry if a NMI delivery
2876                  * faulted.
2877                  */
2878                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
2879                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2880                                         GUEST_INTR_STATE_NMI);
2881                 else
2882                         vmx->vcpu.arch.nmi_injected = false;
2883         }
2884         kvm_clear_exception_queue(&vmx->vcpu);
2885         if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
2886                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
2887                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
2888                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
2889                 } else
2890                         kvm_queue_exception(&vmx->vcpu, vector);
2891                 vmx->idt_vectoring_info = 0;
2892         }
2893         kvm_clear_interrupt_queue(&vmx->vcpu);
2894         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
2895                 kvm_queue_interrupt(&vmx->vcpu, vector);
2896                 vmx->idt_vectoring_info = 0;
2897         }
2898 }
2899
2900 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2901 {
2902         u32 intr_info_field;
2903
2904         update_tpr_threshold(vcpu);
2905
2906         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2907         if (cpu_has_virtual_nmis()) {
2908                 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2909                         if (vmx_nmi_enabled(vcpu)) {
2910                                 vcpu->arch.nmi_pending = false;
2911                                 vcpu->arch.nmi_injected = true;
2912                         } else {
2913                                 enable_intr_window(vcpu);
2914                                 return;
2915                         }
2916                 }
2917                 if (vcpu->arch.nmi_injected) {
2918                         vmx_inject_nmi(vcpu);
2919                         enable_intr_window(vcpu);
2920                         return;
2921                 }
2922         }
2923         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
2924                 if (vmx_irq_enabled(vcpu))
2925                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
2926                 else
2927                         enable_irq_window(vcpu);
2928         }
2929         if (vcpu->arch.interrupt.pending) {
2930                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2931                 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
2932         }
2933 }
2934
2935 /*
2936  * Failure to inject an interrupt should give us the information
2937  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2938  * when fetching the interrupt redirection bitmap in the real-mode
2939  * tss, this doesn't happen.  So we do it ourselves.
2940  */
2941 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2942 {
2943         vmx->rmode.irq.pending = 0;
2944         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
2945                 return;
2946         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
2947         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2948                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2949                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2950                 return;
2951         }
2952         vmx->idt_vectoring_info =
2953                 VECTORING_INFO_VALID_MASK
2954                 | INTR_TYPE_EXT_INTR
2955                 | vmx->rmode.irq.vector;
2956 }
2957
2958 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2959 {
2960         struct vcpu_vmx *vmx = to_vmx(vcpu);
2961         u32 intr_info;
2962
2963         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
2964                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
2965         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
2966                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
2967
2968         /*
2969          * Loading guest fpu may have cleared host cr0.ts
2970          */
2971         vmcs_writel(HOST_CR0, read_cr0());
2972
2973         asm(
2974                 /* Store host registers */
2975 #ifdef CONFIG_X86_64
2976                 "push %%rdx; push %%rbp;"
2977                 "push %%rcx \n\t"
2978 #else
2979                 "push %%edx; push %%ebp;"
2980                 "push %%ecx \n\t"
2981 #endif
2982                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
2983                 /* Check if vmlaunch of vmresume is needed */
2984                 "cmpl $0, %c[launched](%0) \n\t"
2985                 /* Load guest registers.  Don't clobber flags. */
2986 #ifdef CONFIG_X86_64
2987                 "mov %c[cr2](%0), %%rax \n\t"
2988                 "mov %%rax, %%cr2 \n\t"
2989                 "mov %c[rax](%0), %%rax \n\t"
2990                 "mov %c[rbx](%0), %%rbx \n\t"
2991                 "mov %c[rdx](%0), %%rdx \n\t"
2992                 "mov %c[rsi](%0), %%rsi \n\t"
2993                 "mov %c[rdi](%0), %%rdi \n\t"
2994                 "mov %c[rbp](%0), %%rbp \n\t"
2995                 "mov %c[r8](%0),  %%r8  \n\t"
2996                 "mov %c[r9](%0),  %%r9  \n\t"
2997                 "mov %c[r10](%0), %%r10 \n\t"
2998                 "mov %c[r11](%0), %%r11 \n\t"
2999                 "mov %c[r12](%0), %%r12 \n\t"
3000                 "mov %c[r13](%0), %%r13 \n\t"
3001                 "mov %c[r14](%0), %%r14 \n\t"
3002                 "mov %c[r15](%0), %%r15 \n\t"
3003                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
3004 #else
3005                 "mov %c[cr2](%0), %%eax \n\t"
3006                 "mov %%eax,   %%cr2 \n\t"
3007                 "mov %c[rax](%0), %%eax \n\t"
3008                 "mov %c[rbx](%0), %%ebx \n\t"
3009                 "mov %c[rdx](%0), %%edx \n\t"
3010                 "mov %c[rsi](%0), %%esi \n\t"
3011                 "mov %c[rdi](%0), %%edi \n\t"
3012                 "mov %c[rbp](%0), %%ebp \n\t"
3013                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
3014 #endif
3015                 /* Enter guest mode */
3016                 "jne .Llaunched \n\t"
3017                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3018                 "jmp .Lkvm_vmx_return \n\t"
3019                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3020                 ".Lkvm_vmx_return: "
3021                 /* Save guest registers, load host registers, keep flags */
3022 #ifdef CONFIG_X86_64
3023                 "xchg %0,     (%%rsp) \n\t"
3024                 "mov %%rax, %c[rax](%0) \n\t"
3025                 "mov %%rbx, %c[rbx](%0) \n\t"
3026                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
3027                 "mov %%rdx, %c[rdx](%0) \n\t"
3028                 "mov %%rsi, %c[rsi](%0) \n\t"
3029                 "mov %%rdi, %c[rdi](%0) \n\t"
3030                 "mov %%rbp, %c[rbp](%0) \n\t"
3031                 "mov %%r8,  %c[r8](%0) \n\t"
3032                 "mov %%r9,  %c[r9](%0) \n\t"
3033                 "mov %%r10, %c[r10](%0) \n\t"
3034                 "mov %%r11, %c[r11](%0) \n\t"
3035                 "mov %%r12, %c[r12](%0) \n\t"
3036                 "mov %%r13, %c[r13](%0) \n\t"
3037                 "mov %%r14, %c[r14](%0) \n\t"
3038                 "mov %%r15, %c[r15](%0) \n\t"
3039                 "mov %%cr2, %%rax   \n\t"
3040                 "mov %%rax, %c[cr2](%0) \n\t"
3041
3042                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
3043 #else
3044                 "xchg %0, (%%esp) \n\t"
3045                 "mov %%eax, %c[rax](%0) \n\t"
3046                 "mov %%ebx, %c[rbx](%0) \n\t"
3047                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
3048                 "mov %%edx, %c[rdx](%0) \n\t"
3049                 "mov %%esi, %c[rsi](%0) \n\t"
3050                 "mov %%edi, %c[rdi](%0) \n\t"
3051                 "mov %%ebp, %c[rbp](%0) \n\t"
3052                 "mov %%cr2, %%eax  \n\t"
3053                 "mov %%eax, %c[cr2](%0) \n\t"
3054
3055                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
3056 #endif
3057                 "setbe %c[fail](%0) \n\t"
3058               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3059                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3060                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3061                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3062                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3063                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3064                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3065                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3066                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3067                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3068 #ifdef CONFIG_X86_64
3069                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3070                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3071                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3072                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3073                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3074                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3075                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3076                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3077 #endif
3078                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3079               : "cc", "memory"
3080 #ifdef CONFIG_X86_64
3081                 , "rbx", "rdi", "rsi"
3082                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3083 #else
3084                 , "ebx", "edi", "rsi"
3085 #endif
3086               );
3087
3088         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3089         vcpu->arch.regs_dirty = 0;
3090
3091         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3092         if (vmx->rmode.irq.pending)
3093                 fixup_rmode_irq(vmx);
3094
3095         vcpu->arch.interrupt_window_open =
3096                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3097                  (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
3098
3099         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3100         vmx->launched = 1;
3101
3102         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3103
3104         /* We need to handle NMIs before interrupts are enabled */
3105         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3106             (intr_info & INTR_INFO_VALID_MASK)) {
3107                 KVMTRACE_0D(NMI, vcpu, handler);
3108                 asm("int $2");
3109         }
3110
3111         vmx_complete_interrupts(vmx);
3112 }
3113
3114 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3115 {
3116         struct vcpu_vmx *vmx = to_vmx(vcpu);
3117
3118         if (vmx->vmcs) {
3119                 vcpu_clear(vmx);
3120                 free_vmcs(vmx->vmcs);
3121                 vmx->vmcs = NULL;
3122         }
3123 }
3124
3125 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3126 {
3127         struct vcpu_vmx *vmx = to_vmx(vcpu);
3128
3129         spin_lock(&vmx_vpid_lock);
3130         if (vmx->vpid != 0)
3131                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3132         spin_unlock(&vmx_vpid_lock);
3133         vmx_free_vmcs(vcpu);
3134         kfree(vmx->host_msrs);
3135         kfree(vmx->guest_msrs);
3136         kvm_vcpu_uninit(vcpu);
3137         kmem_cache_free(kvm_vcpu_cache, vmx);
3138 }
3139
3140 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3141 {
3142         int err;
3143         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3144         int cpu;
3145
3146         if (!vmx)
3147                 return ERR_PTR(-ENOMEM);
3148
3149         allocate_vpid(vmx);
3150
3151         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3152         if (err)
3153                 goto free_vcpu;
3154
3155         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3156         if (!vmx->guest_msrs) {
3157                 err = -ENOMEM;
3158                 goto uninit_vcpu;
3159         }
3160
3161         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3162         if (!vmx->host_msrs)
3163                 goto free_guest_msrs;
3164
3165         vmx->vmcs = alloc_vmcs();
3166         if (!vmx->vmcs)
3167                 goto free_msrs;
3168
3169         vmcs_clear(vmx->vmcs);
3170
3171         cpu = get_cpu();
3172         vmx_vcpu_load(&vmx->vcpu, cpu);
3173         err = vmx_vcpu_setup(vmx);
3174         vmx_vcpu_put(&vmx->vcpu);
3175         put_cpu();
3176         if (err)
3177                 goto free_vmcs;
3178         if (vm_need_virtualize_apic_accesses(kvm))
3179                 if (alloc_apic_access_page(kvm) != 0)
3180                         goto free_vmcs;
3181
3182         if (vm_need_ept())
3183                 if (alloc_identity_pagetable(kvm) != 0)
3184                         goto free_vmcs;
3185
3186         return &vmx->vcpu;
3187
3188 free_vmcs:
3189         free_vmcs(vmx->vmcs);
3190 free_msrs:
3191         kfree(vmx->host_msrs);
3192 free_guest_msrs:
3193         kfree(vmx->guest_msrs);
3194 uninit_vcpu:
3195         kvm_vcpu_uninit(&vmx->vcpu);
3196 free_vcpu:
3197         kmem_cache_free(kvm_vcpu_cache, vmx);
3198         return ERR_PTR(err);
3199 }
3200
3201 static void __init vmx_check_processor_compat(void *rtn)
3202 {
3203         struct vmcs_config vmcs_conf;
3204
3205         *(int *)rtn = 0;
3206         if (setup_vmcs_config(&vmcs_conf) < 0)
3207                 *(int *)rtn = -EIO;
3208         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3209                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3210                                 smp_processor_id());
3211                 *(int *)rtn = -EIO;
3212         }
3213 }
3214
3215 static int get_ept_level(void)
3216 {
3217         return VMX_EPT_DEFAULT_GAW + 1;
3218 }
3219
3220 static struct kvm_x86_ops vmx_x86_ops = {
3221         .cpu_has_kvm_support = cpu_has_kvm_support,
3222         .disabled_by_bios = vmx_disabled_by_bios,
3223         .hardware_setup = hardware_setup,
3224         .hardware_unsetup = hardware_unsetup,
3225         .check_processor_compatibility = vmx_check_processor_compat,
3226         .hardware_enable = hardware_enable,
3227         .hardware_disable = hardware_disable,
3228         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3229
3230         .vcpu_create = vmx_create_vcpu,
3231         .vcpu_free = vmx_free_vcpu,
3232         .vcpu_reset = vmx_vcpu_reset,
3233
3234         .prepare_guest_switch = vmx_save_host_state,
3235         .vcpu_load = vmx_vcpu_load,
3236         .vcpu_put = vmx_vcpu_put,
3237
3238         .set_guest_debug = set_guest_debug,
3239         .guest_debug_pre = kvm_guest_debug_pre,
3240         .get_msr = vmx_get_msr,
3241         .set_msr = vmx_set_msr,
3242         .get_segment_base = vmx_get_segment_base,
3243         .get_segment = vmx_get_segment,
3244         .set_segment = vmx_set_segment,
3245         .get_cpl = vmx_get_cpl,
3246         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3247         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3248         .set_cr0 = vmx_set_cr0,
3249         .set_cr3 = vmx_set_cr3,
3250         .set_cr4 = vmx_set_cr4,
3251         .set_efer = vmx_set_efer,
3252         .get_idt = vmx_get_idt,
3253         .set_idt = vmx_set_idt,
3254         .get_gdt = vmx_get_gdt,
3255         .set_gdt = vmx_set_gdt,
3256         .cache_reg = vmx_cache_reg,
3257         .get_rflags = vmx_get_rflags,
3258         .set_rflags = vmx_set_rflags,
3259
3260         .tlb_flush = vmx_flush_tlb,
3261
3262         .run = vmx_vcpu_run,
3263         .handle_exit = kvm_handle_exit,
3264         .skip_emulated_instruction = skip_emulated_instruction,
3265         .patch_hypercall = vmx_patch_hypercall,
3266         .get_irq = vmx_get_irq,
3267         .set_irq = vmx_inject_irq,
3268         .queue_exception = vmx_queue_exception,
3269         .exception_injected = vmx_exception_injected,
3270         .inject_pending_irq = vmx_intr_assist,
3271         .inject_pending_vectors = do_interrupt_requests,
3272
3273         .set_tss_addr = vmx_set_tss_addr,
3274         .get_tdp_level = get_ept_level,
3275 };
3276
3277 static int __init vmx_init(void)
3278 {
3279         void *va;
3280         int r;
3281
3282         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3283         if (!vmx_io_bitmap_a)
3284                 return -ENOMEM;
3285
3286         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3287         if (!vmx_io_bitmap_b) {
3288                 r = -ENOMEM;
3289                 goto out;
3290         }
3291
3292         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3293         if (!vmx_msr_bitmap) {
3294                 r = -ENOMEM;
3295                 goto out1;
3296         }
3297
3298         /*
3299          * Allow direct access to the PC debug port (it is often used for I/O
3300          * delays, but the vmexits simply slow things down).
3301          */
3302         va = kmap(vmx_io_bitmap_a);
3303         memset(va, 0xff, PAGE_SIZE);
3304         clear_bit(0x80, va);
3305         kunmap(vmx_io_bitmap_a);
3306
3307         va = kmap(vmx_io_bitmap_b);
3308         memset(va, 0xff, PAGE_SIZE);
3309         kunmap(vmx_io_bitmap_b);
3310
3311         va = kmap(vmx_msr_bitmap);
3312         memset(va, 0xff, PAGE_SIZE);
3313         kunmap(vmx_msr_bitmap);
3314
3315         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3316
3317         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3318         if (r)
3319                 goto out2;
3320
3321         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3322         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3323         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3324         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3325         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3326
3327         if (vm_need_ept()) {
3328                 bypass_guest_pf = 0;
3329                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3330                         VMX_EPT_WRITABLE_MASK |
3331                         VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3332                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3333                                 VMX_EPT_EXECUTABLE_MASK);
3334                 kvm_enable_tdp();
3335         } else
3336                 kvm_disable_tdp();
3337
3338         if (bypass_guest_pf)
3339                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3340
3341         ept_sync_global();
3342
3343         return 0;
3344
3345 out2:
3346         __free_page(vmx_msr_bitmap);
3347 out1:
3348         __free_page(vmx_io_bitmap_b);
3349 out:
3350         __free_page(vmx_io_bitmap_a);
3351         return r;
3352 }
3353
3354 static void __exit vmx_exit(void)
3355 {
3356         __free_page(vmx_msr_bitmap);
3357         __free_page(vmx_io_bitmap_b);
3358         __free_page(vmx_io_bitmap_a);
3359
3360         kvm_exit();
3361 }
3362
3363 module_init(vmx_init)
3364 module_exit(vmx_exit)