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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  65         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  66 #define KVM_GUEST_CR0_MASK                                              \
  67         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  69         (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
  70 #define KVM_VM_CR0_ALWAYS_ON                                            \
  71         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  72 #define KVM_GUEST_CR4_MASK                                              \
  73         (X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE)
  74 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  75 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  76
  77 /*
  78  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  79  * ple_gap:    upper bound on the amount of time between two successive
  80  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  81  *             According to test, this time is usually small than 41 cycles.
  82  * ple_window: upper bound on the amount of time a guest is allowed to execute
  83  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  84  *             less than 2^12 cycles
  85  * Time is measured based on a counter that runs at the same rate as the TSC,
  86  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  87  */
  88 #define KVM_VMX_DEFAULT_PLE_GAP    41
  89 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  90 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  91 module_param(ple_gap, int, S_IRUGO);
  92
  93 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  94 module_param(ple_window, int, S_IRUGO);
  95
  96 struct vmcs {
  97         u32 revision_id;
  98         u32 abort;
  99         char data[0];
 100 };
 101
 102 struct shared_msr_entry {
 103         unsigned index;
 104         u64 data;
 105         u64 mask;
 106 };
 107
 108 struct vcpu_vmx {
 109         struct kvm_vcpu       vcpu;
 110         struct list_head      local_vcpus_link;
 111         unsigned long         host_rsp;
 112         int                   launched;
 113         u8                    fail;
 114         u32                   idt_vectoring_info;
 115         struct shared_msr_entry *guest_msrs;
 116         int                   nmsrs;
 117         int                   save_nmsrs;
 118 #ifdef CONFIG_X86_64
 119         u64                   msr_host_kernel_gs_base;
 120         u64                   msr_guest_kernel_gs_base;
 121 #endif
 122         struct vmcs          *vmcs;
 123         struct {
 124                 int           loaded;
 125                 u16           fs_sel, gs_sel, ldt_sel;
 126                 int           gs_ldt_reload_needed;
 127                 int           fs_reload_needed;
 128         } host_state;
 129         struct {
 130                 int vm86_active;
 131                 u8 save_iopl;
 132                 struct kvm_save_segment {
 133                         u16 selector;
 134                         unsigned long base;
 135                         u32 limit;
 136                         u32 ar;
 137                 } tr, es, ds, fs, gs;
 138                 struct {
 139                         bool pending;
 140                         u8 vector;
 141                         unsigned rip;
 142                 } irq;
 143         } rmode;
 144         int vpid;
 145         bool emulation_required;
 146
 147         /* Support for vnmi-less CPUs */
 148         int soft_vnmi_blocked;
 149         ktime_t entry_time;
 150         s64 vnmi_blocked_time;
 151         u32 exit_reason;
 152 };
 153
 154 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 155 {
 156         return container_of(vcpu, struct vcpu_vmx, vcpu);
 157 }
 158
 159 static int init_rmode(struct kvm *kvm);
 160 static u64 construct_eptp(unsigned long root_hpa);
 161
 162 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 163 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 164 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 165
 166 static unsigned long *vmx_io_bitmap_a;
 167 static unsigned long *vmx_io_bitmap_b;
 168 static unsigned long *vmx_msr_bitmap_legacy;
 169 static unsigned long *vmx_msr_bitmap_longmode;
 170
 171 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 172 static DEFINE_SPINLOCK(vmx_vpid_lock);
 173
 174 static struct vmcs_config {
 175         int size;
 176         int order;
 177         u32 revision_id;
 178         u32 pin_based_exec_ctrl;
 179         u32 cpu_based_exec_ctrl;
 180         u32 cpu_based_2nd_exec_ctrl;
 181         u32 vmexit_ctrl;
 182         u32 vmentry_ctrl;
 183 } vmcs_config;
 184
 185 static struct vmx_capability {
 186         u32 ept;
 187         u32 vpid;
 188 } vmx_capability;
 189
 190 #define VMX_SEGMENT_FIELD(seg)                                  \
 191         [VCPU_SREG_##seg] = {                                   \
 192                 .selector = GUEST_##seg##_SELECTOR,             \
 193                 .base = GUEST_##seg##_BASE,                     \
 194                 .limit = GUEST_##seg##_LIMIT,                   \
 195                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 196         }
 197
 198 static struct kvm_vmx_segment_field {
 199         unsigned selector;
 200         unsigned base;
 201         unsigned limit;
 202         unsigned ar_bytes;
 203 } kvm_vmx_segment_fields[] = {
 204         VMX_SEGMENT_FIELD(CS),
 205         VMX_SEGMENT_FIELD(DS),
 206         VMX_SEGMENT_FIELD(ES),
 207         VMX_SEGMENT_FIELD(FS),
 208         VMX_SEGMENT_FIELD(GS),
 209         VMX_SEGMENT_FIELD(SS),
 210         VMX_SEGMENT_FIELD(TR),
 211         VMX_SEGMENT_FIELD(LDTR),
 212 };
 213
 214 static u64 host_efer;
 215
 216 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 217
 218 /*
 219  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 220  * away by decrementing the array size.
 221  */
 222 static const u32 vmx_msr_index[] = {
 223 #ifdef CONFIG_X86_64
 224         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 225 #endif
 226         MSR_EFER, MSR_K6_STAR,
 227 };
 228 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 229
 230 static inline int is_page_fault(u32 intr_info)
 231 {
 232         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 233                              INTR_INFO_VALID_MASK)) ==
 234                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 235 }
 236
 237 static inline int is_no_device(u32 intr_info)
 238 {
 239         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 240                              INTR_INFO_VALID_MASK)) ==
 241                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 242 }
 243
 244 static inline int is_invalid_opcode(u32 intr_info)
 245 {
 246         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 247                              INTR_INFO_VALID_MASK)) ==
 248                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 249 }
 250
 251 static inline int is_external_interrupt(u32 intr_info)
 252 {
 253         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 254                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 255 }
 256
 257 static inline int is_machine_check(u32 intr_info)
 258 {
 259         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 260                              INTR_INFO_VALID_MASK)) ==
 261                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 262 }
 263
 264 static inline int cpu_has_vmx_msr_bitmap(void)
 265 {
 266         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 267 }
 268
 269 static inline int cpu_has_vmx_tpr_shadow(void)
 270 {
 271         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 272 }
 273
 274 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 275 {
 276         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 277 }
 278
 279 static inline int cpu_has_secondary_exec_ctrls(void)
 280 {
 281         return vmcs_config.cpu_based_exec_ctrl &
 282                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 283 }
 284
 285 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 286 {
 287         return vmcs_config.cpu_based_2nd_exec_ctrl &
 288                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 289 }
 290
 291 static inline bool cpu_has_vmx_flexpriority(void)
 292 {
 293         return cpu_has_vmx_tpr_shadow() &&
 294                 cpu_has_vmx_virtualize_apic_accesses();
 295 }
 296
 297 static inline bool cpu_has_vmx_ept_execute_only(void)
 298 {
 299         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 300 }
 301
 302 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 303 {
 304         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 305 }
 306
 307 static inline bool cpu_has_vmx_eptp_writeback(void)
 308 {
 309         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 310 }
 311
 312 static inline bool cpu_has_vmx_ept_2m_page(void)
 313 {
 314         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 315 }
 316
 317 static inline int cpu_has_vmx_invept_individual_addr(void)
 318 {
 319         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 320 }
 321
 322 static inline int cpu_has_vmx_invept_context(void)
 323 {
 324         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 325 }
 326
 327 static inline int cpu_has_vmx_invept_global(void)
 328 {
 329         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 330 }
 331
 332 static inline int cpu_has_vmx_ept(void)
 333 {
 334         return vmcs_config.cpu_based_2nd_exec_ctrl &
 335                 SECONDARY_EXEC_ENABLE_EPT;
 336 }
 337
 338 static inline int cpu_has_vmx_unrestricted_guest(void)
 339 {
 340         return vmcs_config.cpu_based_2nd_exec_ctrl &
 341                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 342 }
 343
 344 static inline int cpu_has_vmx_ple(void)
 345 {
 346         return vmcs_config.cpu_based_2nd_exec_ctrl &
 347                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 348 }
 349
 350 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 351 {
 352         return flexpriority_enabled &&
 353                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 354                 (irqchip_in_kernel(kvm));
 355 }
 356
 357 static inline int cpu_has_vmx_vpid(void)
 358 {
 359         return vmcs_config.cpu_based_2nd_exec_ctrl &
 360                 SECONDARY_EXEC_ENABLE_VPID;
 361 }
 362
 363 static inline int cpu_has_virtual_nmis(void)
 364 {
 365         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 366 }
 367
 368 static inline bool report_flexpriority(void)
 369 {
 370         return flexpriority_enabled;
 371 }
 372
 373 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 374 {
 375         int i;
 376
 377         for (i = 0; i < vmx->nmsrs; ++i)
 378                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 379                         return i;
 380         return -1;
 381 }
 382
 383 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 384 {
 385     struct {
 386         u64 vpid : 16;
 387         u64 rsvd : 48;
 388         u64 gva;
 389     } operand = { vpid, 0, gva };
 390
 391     asm volatile (__ex(ASM_VMX_INVVPID)
 392                   /* CF==1 or ZF==1 --> rc = -1 */
 393                   "; ja 1f ; ud2 ; 1:"
 394                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 395 }
 396
 397 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 398 {
 399         struct {
 400                 u64 eptp, gpa;
 401         } operand = {eptp, gpa};
 402
 403         asm volatile (__ex(ASM_VMX_INVEPT)
 404                         /* CF==1 or ZF==1 --> rc = -1 */
 405                         "; ja 1f ; ud2 ; 1:\n"
 406                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 407 }
 408
 409 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 410 {
 411         int i;
 412
 413         i = __find_msr_index(vmx, msr);
 414         if (i >= 0)
 415                 return &vmx->guest_msrs[i];
 416         return NULL;
 417 }
 418
 419 static void vmcs_clear(struct vmcs *vmcs)
 420 {
 421         u64 phys_addr = __pa(vmcs);
 422         u8 error;
 423
 424         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 425                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 426                       : "cc", "memory");
 427         if (error)
 428                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 429                        vmcs, phys_addr);
 430 }
 431
 432 static void __vcpu_clear(void *arg)
 433 {
 434         struct vcpu_vmx *vmx = arg;
 435         int cpu = raw_smp_processor_id();
 436
 437         if (vmx->vcpu.cpu == cpu)
 438                 vmcs_clear(vmx->vmcs);
 439         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 440                 per_cpu(current_vmcs, cpu) = NULL;
 441         rdtscll(vmx->vcpu.arch.host_tsc);
 442         list_del(&vmx->local_vcpus_link);
 443         vmx->vcpu.cpu = -1;
 444         vmx->launched = 0;
 445 }
 446
 447 static void vcpu_clear(struct vcpu_vmx *vmx)
 448 {
 449         if (vmx->vcpu.cpu == -1)
 450                 return;
 451         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 452 }
 453
 454 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 455 {
 456         if (vmx->vpid == 0)
 457                 return;
 458
 459         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 460 }
 461
 462 static inline void ept_sync_global(void)
 463 {
 464         if (cpu_has_vmx_invept_global())
 465                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 466 }
 467
 468 static inline void ept_sync_context(u64 eptp)
 469 {
 470         if (enable_ept) {
 471                 if (cpu_has_vmx_invept_context())
 472                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 473                 else
 474                         ept_sync_global();
 475         }
 476 }
 477
 478 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 479 {
 480         if (enable_ept) {
 481                 if (cpu_has_vmx_invept_individual_addr())
 482                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 483                                         eptp, gpa);
 484                 else
 485                         ept_sync_context(eptp);
 486         }
 487 }
 488
 489 static unsigned long vmcs_readl(unsigned long field)
 490 {
 491         unsigned long value;
 492
 493         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 494                       : "=a"(value) : "d"(field) : "cc");
 495         return value;
 496 }
 497
 498 static u16 vmcs_read16(unsigned long field)
 499 {
 500         return vmcs_readl(field);
 501 }
 502
 503 static u32 vmcs_read32(unsigned long field)
 504 {
 505         return vmcs_readl(field);
 506 }
 507
 508 static u64 vmcs_read64(unsigned long field)
 509 {
 510 #ifdef CONFIG_X86_64
 511         return vmcs_readl(field);
 512 #else
 513         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 514 #endif
 515 }
 516
 517 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 518 {
 519         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 520                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 521         dump_stack();
 522 }
 523
 524 static void vmcs_writel(unsigned long field, unsigned long value)
 525 {
 526         u8 error;
 527
 528         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 529                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 530         if (unlikely(error))
 531                 vmwrite_error(field, value);
 532 }
 533
 534 static void vmcs_write16(unsigned long field, u16 value)
 535 {
 536         vmcs_writel(field, value);
 537 }
 538
 539 static void vmcs_write32(unsigned long field, u32 value)
 540 {
 541         vmcs_writel(field, value);
 542 }
 543
 544 static void vmcs_write64(unsigned long field, u64 value)
 545 {
 546         vmcs_writel(field, value);
 547 #ifndef CONFIG_X86_64
 548         asm volatile ("");
 549         vmcs_writel(field+1, value >> 32);
 550 #endif
 551 }
 552
 553 static void vmcs_clear_bits(unsigned long field, u32 mask)
 554 {
 555         vmcs_writel(field, vmcs_readl(field) & ~mask);
 556 }
 557
 558 static void vmcs_set_bits(unsigned long field, u32 mask)
 559 {
 560         vmcs_writel(field, vmcs_readl(field) | mask);
 561 }
 562
 563 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 564 {
 565         u32 eb;
 566
 567         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 568         if (!vcpu->fpu_active)
 569                 eb |= 1u << NM_VECTOR;
 570         /*
 571          * Unconditionally intercept #DB so we can maintain dr6 without
 572          * reading it every exit.
 573          */
 574         eb |= 1u << DB_VECTOR;
 575         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 576                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 577                         eb |= 1u << BP_VECTOR;
 578         }
 579         if (to_vmx(vcpu)->rmode.vm86_active)
 580                 eb = ~0;
 581         if (enable_ept)
 582                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 583         vmcs_write32(EXCEPTION_BITMAP, eb);
 584 }
 585
 586 static void reload_tss(void)
 587 {
 588         /*
 589          * VT restores TR but not its size.  Useless.
 590          */
 591         struct descriptor_table gdt;
 592         struct desc_struct *descs;
 593
 594         kvm_get_gdt(&gdt);
 595         descs = (void *)gdt.base;
 596         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 597         load_TR_desc();
 598 }
 599
 600 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 601 {
 602         u64 guest_efer;
 603         u64 ignore_bits;
 604
 605         guest_efer = vmx->vcpu.arch.shadow_efer;
 606
 607         /*
 608          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 609          * outside long mode
 610          */
 611         ignore_bits = EFER_NX | EFER_SCE;
 612 #ifdef CONFIG_X86_64
 613         ignore_bits |= EFER_LMA | EFER_LME;
 614         /* SCE is meaningful only in long mode on Intel */
 615         if (guest_efer & EFER_LMA)
 616                 ignore_bits &= ~(u64)EFER_SCE;
 617 #endif
 618         guest_efer &= ~ignore_bits;
 619         guest_efer |= host_efer & ignore_bits;
 620         vmx->guest_msrs[efer_offset].data = guest_efer;
 621         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 622         return true;
 623 }
 624
 625 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 626 {
 627         struct vcpu_vmx *vmx = to_vmx(vcpu);
 628         int i;
 629
 630         if (vmx->host_state.loaded)
 631                 return;
 632
 633         vmx->host_state.loaded = 1;
 634         /*
 635          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 636          * allow segment selectors with cpl > 0 or ti == 1.
 637          */
 638         vmx->host_state.ldt_sel = kvm_read_ldt();
 639         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 640         vmx->host_state.fs_sel = kvm_read_fs();
 641         if (!(vmx->host_state.fs_sel & 7)) {
 642                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 643                 vmx->host_state.fs_reload_needed = 0;
 644         } else {
 645                 vmcs_write16(HOST_FS_SELECTOR, 0);
 646                 vmx->host_state.fs_reload_needed = 1;
 647         }
 648         vmx->host_state.gs_sel = kvm_read_gs();
 649         if (!(vmx->host_state.gs_sel & 7))
 650                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 651         else {
 652                 vmcs_write16(HOST_GS_SELECTOR, 0);
 653                 vmx->host_state.gs_ldt_reload_needed = 1;
 654         }
 655
 656 #ifdef CONFIG_X86_64
 657         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 658         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 659 #else
 660         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 661         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 662 #endif
 663
 664 #ifdef CONFIG_X86_64
 665         if (is_long_mode(&vmx->vcpu)) {
 666                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 667                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 668         }
 669 #endif
 670         for (i = 0; i < vmx->save_nmsrs; ++i)
 671                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 672                                    vmx->guest_msrs[i].data,
 673                                    vmx->guest_msrs[i].mask);
 674 }
 675
 676 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 677 {
 678         unsigned long flags;
 679
 680         if (!vmx->host_state.loaded)
 681                 return;
 682
 683         ++vmx->vcpu.stat.host_state_reload;
 684         vmx->host_state.loaded = 0;
 685         if (vmx->host_state.fs_reload_needed)
 686                 kvm_load_fs(vmx->host_state.fs_sel);
 687         if (vmx->host_state.gs_ldt_reload_needed) {
 688                 kvm_load_ldt(vmx->host_state.ldt_sel);
 689                 /*
 690                  * If we have to reload gs, we must take care to
 691                  * preserve our gs base.
 692                  */
 693                 local_irq_save(flags);
 694                 kvm_load_gs(vmx->host_state.gs_sel);
 695 #ifdef CONFIG_X86_64
 696                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 697 #endif
 698                 local_irq_restore(flags);
 699         }
 700         reload_tss();
 701 #ifdef CONFIG_X86_64
 702         if (is_long_mode(&vmx->vcpu)) {
 703                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 704                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 705         }
 706 #endif
 707 }
 708
 709 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 710 {
 711         preempt_disable();
 712         __vmx_load_host_state(vmx);
 713         preempt_enable();
 714 }
 715
 716 /*
 717  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 718  * vcpu mutex is already taken.
 719  */
 720 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 721 {
 722         struct vcpu_vmx *vmx = to_vmx(vcpu);
 723         u64 phys_addr = __pa(vmx->vmcs);
 724         u64 tsc_this, delta, new_offset;
 725
 726         if (vcpu->cpu != cpu) {
 727                 vcpu_clear(vmx);
 728                 kvm_migrate_timers(vcpu);
 729                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 730                 local_irq_disable();
 731                 list_add(&vmx->local_vcpus_link,
 732                          &per_cpu(vcpus_on_cpu, cpu));
 733                 local_irq_enable();
 734         }
 735
 736         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 737                 u8 error;
 738
 739                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 740                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 741                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 742                               : "cc");
 743                 if (error)
 744                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 745                                vmx->vmcs, phys_addr);
 746         }
 747
 748         if (vcpu->cpu != cpu) {
 749                 struct descriptor_table dt;
 750                 unsigned long sysenter_esp;
 751
 752                 vcpu->cpu = cpu;
 753                 /*
 754                  * Linux uses per-cpu TSS and GDT, so set these when switching
 755                  * processors.
 756                  */
 757                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 758                 kvm_get_gdt(&dt);
 759                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 760
 761                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 762                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 763
 764                 /*
 765                  * Make sure the time stamp counter is monotonous.
 766                  */
 767                 rdtscll(tsc_this);
 768                 if (tsc_this < vcpu->arch.host_tsc) {
 769                         delta = vcpu->arch.host_tsc - tsc_this;
 770                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 771                         vmcs_write64(TSC_OFFSET, new_offset);
 772                 }
 773         }
 774 }
 775
 776 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 777 {
 778         __vmx_load_host_state(to_vmx(vcpu));
 779 }
 780
 781 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 782 {
 783         if (vcpu->fpu_active)
 784                 return;
 785         vcpu->fpu_active = 1;
 786         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 787         if (vcpu->arch.cr0 & X86_CR0_TS)
 788                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 789         update_exception_bitmap(vcpu);
 790 }
 791
 792 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 793 {
 794         if (!vcpu->fpu_active)
 795                 return;
 796         vcpu->fpu_active = 0;
 797         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 798         update_exception_bitmap(vcpu);
 799 }
 800
 801 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 802 {
 803         unsigned long rflags;
 804
 805         rflags = vmcs_readl(GUEST_RFLAGS);
 806         if (to_vmx(vcpu)->rmode.vm86_active)
 807                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 808         return rflags;
 809 }
 810
 811 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 812 {
 813         if (to_vmx(vcpu)->rmode.vm86_active)
 814                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 815         vmcs_writel(GUEST_RFLAGS, rflags);
 816 }
 817
 818 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 819 {
 820         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 821         int ret = 0;
 822
 823         if (interruptibility & GUEST_INTR_STATE_STI)
 824                 ret |= X86_SHADOW_INT_STI;
 825         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 826                 ret |= X86_SHADOW_INT_MOV_SS;
 827
 828         return ret & mask;
 829 }
 830
 831 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 832 {
 833         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 834         u32 interruptibility = interruptibility_old;
 835
 836         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 837
 838         if (mask & X86_SHADOW_INT_MOV_SS)
 839                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 840         if (mask & X86_SHADOW_INT_STI)
 841                 interruptibility |= GUEST_INTR_STATE_STI;
 842
 843         if ((interruptibility != interruptibility_old))
 844                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 845 }
 846
 847 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 848 {
 849         unsigned long rip;
 850
 851         rip = kvm_rip_read(vcpu);
 852         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 853         kvm_rip_write(vcpu, rip);
 854
 855         /* skipping an emulated instruction also counts */
 856         vmx_set_interrupt_shadow(vcpu, 0);
 857 }
 858
 859 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 860                                 bool has_error_code, u32 error_code)
 861 {
 862         struct vcpu_vmx *vmx = to_vmx(vcpu);
 863         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 864
 865         if (has_error_code) {
 866                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 867                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 868         }
 869
 870         if (vmx->rmode.vm86_active) {
 871                 vmx->rmode.irq.pending = true;
 872                 vmx->rmode.irq.vector = nr;
 873                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 874                 if (kvm_exception_is_soft(nr))
 875                         vmx->rmode.irq.rip +=
 876                                 vmx->vcpu.arch.event_exit_inst_len;
 877                 intr_info |= INTR_TYPE_SOFT_INTR;
 878                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 879                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 880                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 881                 return;
 882         }
 883
 884         if (kvm_exception_is_soft(nr)) {
 885                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 886                              vmx->vcpu.arch.event_exit_inst_len);
 887                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 888         } else
 889                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 890
 891         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 892 }
 893
 894 /*
 895  * Swap MSR entry in host/guest MSR entry array.
 896  */
 897 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 898 {
 899         struct shared_msr_entry tmp;
 900
 901         tmp = vmx->guest_msrs[to];
 902         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 903         vmx->guest_msrs[from] = tmp;
 904 }
 905
 906 /*
 907  * Set up the vmcs to automatically save and restore system
 908  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 909  * mode, as fiddling with msrs is very expensive.
 910  */
 911 static void setup_msrs(struct vcpu_vmx *vmx)
 912 {
 913         int save_nmsrs, index;
 914         unsigned long *msr_bitmap;
 915
 916         vmx_load_host_state(vmx);
 917         save_nmsrs = 0;
 918 #ifdef CONFIG_X86_64
 919         if (is_long_mode(&vmx->vcpu)) {
 920                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 921                 if (index >= 0)
 922                         move_msr_up(vmx, index, save_nmsrs++);
 923                 index = __find_msr_index(vmx, MSR_LSTAR);
 924                 if (index >= 0)
 925                         move_msr_up(vmx, index, save_nmsrs++);
 926                 index = __find_msr_index(vmx, MSR_CSTAR);
 927                 if (index >= 0)
 928                         move_msr_up(vmx, index, save_nmsrs++);
 929                 /*
 930                  * MSR_K6_STAR is only needed on long mode guests, and only
 931                  * if efer.sce is enabled.
 932                  */
 933                 index = __find_msr_index(vmx, MSR_K6_STAR);
 934                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 935                         move_msr_up(vmx, index, save_nmsrs++);
 936         }
 937 #endif
 938         index = __find_msr_index(vmx, MSR_EFER);
 939         if (index >= 0 && update_transition_efer(vmx, index))
 940                 move_msr_up(vmx, index, save_nmsrs++);
 941
 942         vmx->save_nmsrs = save_nmsrs;
 943
 944         if (cpu_has_vmx_msr_bitmap()) {
 945                 if (is_long_mode(&vmx->vcpu))
 946                         msr_bitmap = vmx_msr_bitmap_longmode;
 947                 else
 948                         msr_bitmap = vmx_msr_bitmap_legacy;
 949
 950                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 951         }
 952 }
 953
 954 /*
 955  * reads and returns guest's timestamp counter "register"
 956  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 957  */
 958 static u64 guest_read_tsc(void)
 959 {
 960         u64 host_tsc, tsc_offset;
 961
 962         rdtscll(host_tsc);
 963         tsc_offset = vmcs_read64(TSC_OFFSET);
 964         return host_tsc + tsc_offset;
 965 }
 966
 967 /*
 968  * writes 'guest_tsc' into guest's timestamp counter "register"
 969  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 970  */
 971 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 972 {
 973         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 974 }
 975
 976 /*
 977  * Reads an msr value (of 'msr_index') into 'pdata'.
 978  * Returns 0 on success, non-0 otherwise.
 979  * Assumes vcpu_load() was already called.
 980  */
 981 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 982 {
 983         u64 data;
 984         struct shared_msr_entry *msr;
 985
 986         if (!pdata) {
 987                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 988                 return -EINVAL;
 989         }
 990
 991         switch (msr_index) {
 992 #ifdef CONFIG_X86_64
 993         case MSR_FS_BASE:
 994                 data = vmcs_readl(GUEST_FS_BASE);
 995                 break;
 996         case MSR_GS_BASE:
 997                 data = vmcs_readl(GUEST_GS_BASE);
 998                 break;
 999         case MSR_KERNEL_GS_BASE:
1000                 vmx_load_host_state(to_vmx(vcpu));
1001                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1002                 break;
1003 #endif
1004         case MSR_EFER:
1005                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1006         case MSR_IA32_TSC:
1007                 data = guest_read_tsc();
1008                 break;
1009         case MSR_IA32_SYSENTER_CS:
1010                 data = vmcs_read32(GUEST_SYSENTER_CS);
1011                 break;
1012         case MSR_IA32_SYSENTER_EIP:
1013                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1014                 break;
1015         case MSR_IA32_SYSENTER_ESP:
1016                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1017                 break;
1018         default:
1019                 vmx_load_host_state(to_vmx(vcpu));
1020                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1021                 if (msr) {
1022                         vmx_load_host_state(to_vmx(vcpu));
1023                         data = msr->data;
1024                         break;
1025                 }
1026                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1027         }
1028
1029         *pdata = data;
1030         return 0;
1031 }
1032
1033 /*
1034  * Writes msr value into into the appropriate "register".
1035  * Returns 0 on success, non-0 otherwise.
1036  * Assumes vcpu_load() was already called.
1037  */
1038 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1039 {
1040         struct vcpu_vmx *vmx = to_vmx(vcpu);
1041         struct shared_msr_entry *msr;
1042         u64 host_tsc;
1043         int ret = 0;
1044
1045         switch (msr_index) {
1046         case MSR_EFER:
1047                 vmx_load_host_state(vmx);
1048                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1049                 break;
1050 #ifdef CONFIG_X86_64
1051         case MSR_FS_BASE:
1052                 vmcs_writel(GUEST_FS_BASE, data);
1053                 break;
1054         case MSR_GS_BASE:
1055                 vmcs_writel(GUEST_GS_BASE, data);
1056                 break;
1057         case MSR_KERNEL_GS_BASE:
1058                 vmx_load_host_state(vmx);
1059                 vmx->msr_guest_kernel_gs_base = data;
1060                 break;
1061 #endif
1062         case MSR_IA32_SYSENTER_CS:
1063                 vmcs_write32(GUEST_SYSENTER_CS, data);
1064                 break;
1065         case MSR_IA32_SYSENTER_EIP:
1066                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1067                 break;
1068         case MSR_IA32_SYSENTER_ESP:
1069                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1070                 break;
1071         case MSR_IA32_TSC:
1072                 rdtscll(host_tsc);
1073                 guest_write_tsc(data, host_tsc);
1074                 break;
1075         case MSR_IA32_CR_PAT:
1076                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1077                         vmcs_write64(GUEST_IA32_PAT, data);
1078                         vcpu->arch.pat = data;
1079                         break;
1080                 }
1081                 /* Otherwise falls through to kvm_set_msr_common */
1082         default:
1083                 msr = find_msr_entry(vmx, msr_index);
1084                 if (msr) {
1085                         vmx_load_host_state(vmx);
1086                         msr->data = data;
1087                         break;
1088                 }
1089                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1090         }
1091
1092         return ret;
1093 }
1094
1095 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1096 {
1097         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1098         switch (reg) {
1099         case VCPU_REGS_RSP:
1100                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1101                 break;
1102         case VCPU_REGS_RIP:
1103                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1104                 break;
1105         case VCPU_EXREG_PDPTR:
1106                 if (enable_ept)
1107                         ept_save_pdptrs(vcpu);
1108                 break;
1109         default:
1110                 break;
1111         }
1112 }
1113
1114 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1115 {
1116         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1118         else
1119                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1120
1121         update_exception_bitmap(vcpu);
1122 }
1123
1124 static __init int cpu_has_kvm_support(void)
1125 {
1126         return cpu_has_vmx();
1127 }
1128
1129 static __init int vmx_disabled_by_bios(void)
1130 {
1131         u64 msr;
1132
1133         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1134         return (msr & (FEATURE_CONTROL_LOCKED |
1135                        FEATURE_CONTROL_VMXON_ENABLED))
1136             == FEATURE_CONTROL_LOCKED;
1137         /* locked but not enabled */
1138 }
1139
1140 static int hardware_enable(void *garbage)
1141 {
1142         int cpu = raw_smp_processor_id();
1143         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1144         u64 old;
1145
1146         if (read_cr4() & X86_CR4_VMXE)
1147                 return -EBUSY;
1148
1149         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1150         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1151         if ((old & (FEATURE_CONTROL_LOCKED |
1152                     FEATURE_CONTROL_VMXON_ENABLED))
1153             != (FEATURE_CONTROL_LOCKED |
1154                 FEATURE_CONTROL_VMXON_ENABLED))
1155                 /* enable and lock */
1156                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1157                        FEATURE_CONTROL_LOCKED |
1158                        FEATURE_CONTROL_VMXON_ENABLED);
1159         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1160         asm volatile (ASM_VMX_VMXON_RAX
1161                       : : "a"(&phys_addr), "m"(phys_addr)
1162                       : "memory", "cc");
1163
1164         ept_sync_global();
1165
1166         return 0;
1167 }
1168
1169 static void vmclear_local_vcpus(void)
1170 {
1171         int cpu = raw_smp_processor_id();
1172         struct vcpu_vmx *vmx, *n;
1173
1174         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1175                                  local_vcpus_link)
1176                 __vcpu_clear(vmx);
1177 }
1178
1179
1180 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1181  * tricks.
1182  */
1183 static void kvm_cpu_vmxoff(void)
1184 {
1185         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1186         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1187 }
1188
1189 static void hardware_disable(void *garbage)
1190 {
1191         vmclear_local_vcpus();
1192         kvm_cpu_vmxoff();
1193 }
1194
1195 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1196                                       u32 msr, u32 *result)
1197 {
1198         u32 vmx_msr_low, vmx_msr_high;
1199         u32 ctl = ctl_min | ctl_opt;
1200
1201         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1202
1203         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1204         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1205
1206         /* Ensure minimum (required) set of control bits are supported. */
1207         if (ctl_min & ~ctl)
1208                 return -EIO;
1209
1210         *result = ctl;
1211         return 0;
1212 }
1213
1214 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1215 {
1216         u32 vmx_msr_low, vmx_msr_high;
1217         u32 min, opt, min2, opt2;
1218         u32 _pin_based_exec_control = 0;
1219         u32 _cpu_based_exec_control = 0;
1220         u32 _cpu_based_2nd_exec_control = 0;
1221         u32 _vmexit_control = 0;
1222         u32 _vmentry_control = 0;
1223
1224         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1225         opt = PIN_BASED_VIRTUAL_NMIS;
1226         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1227                                 &_pin_based_exec_control) < 0)
1228                 return -EIO;
1229
1230         min = CPU_BASED_HLT_EXITING |
1231 #ifdef CONFIG_X86_64
1232               CPU_BASED_CR8_LOAD_EXITING |
1233               CPU_BASED_CR8_STORE_EXITING |
1234 #endif
1235               CPU_BASED_CR3_LOAD_EXITING |
1236               CPU_BASED_CR3_STORE_EXITING |
1237               CPU_BASED_USE_IO_BITMAPS |
1238               CPU_BASED_MOV_DR_EXITING |
1239               CPU_BASED_USE_TSC_OFFSETING |
1240               CPU_BASED_MWAIT_EXITING |
1241               CPU_BASED_MONITOR_EXITING |
1242               CPU_BASED_INVLPG_EXITING;
1243         opt = CPU_BASED_TPR_SHADOW |
1244               CPU_BASED_USE_MSR_BITMAPS |
1245               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1246         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1247                                 &_cpu_based_exec_control) < 0)
1248                 return -EIO;
1249 #ifdef CONFIG_X86_64
1250         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1251                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1252                                            ~CPU_BASED_CR8_STORE_EXITING;
1253 #endif
1254         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1255                 min2 = 0;
1256                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1257                         SECONDARY_EXEC_WBINVD_EXITING |
1258                         SECONDARY_EXEC_ENABLE_VPID |
1259                         SECONDARY_EXEC_ENABLE_EPT |
1260                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1261                         SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262                 if (adjust_vmx_controls(min2, opt2,
1263                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1264                                         &_cpu_based_2nd_exec_control) < 0)
1265                         return -EIO;
1266         }
1267 #ifndef CONFIG_X86_64
1268         if (!(_cpu_based_2nd_exec_control &
1269                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1270                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1271 #endif
1272         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1273                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1274                    enabled */
1275                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1276                                              CPU_BASED_CR3_STORE_EXITING |
1277                                              CPU_BASED_INVLPG_EXITING);
1278                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1279                       vmx_capability.ept, vmx_capability.vpid);
1280         }
1281
1282         min = 0;
1283 #ifdef CONFIG_X86_64
1284         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1285 #endif
1286         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1287         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1288                                 &_vmexit_control) < 0)
1289                 return -EIO;
1290
1291         min = 0;
1292         opt = VM_ENTRY_LOAD_IA32_PAT;
1293         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1294                                 &_vmentry_control) < 0)
1295                 return -EIO;
1296
1297         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1298
1299         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1300         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1301                 return -EIO;
1302
1303 #ifdef CONFIG_X86_64
1304         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1305         if (vmx_msr_high & (1u<<16))
1306                 return -EIO;
1307 #endif
1308
1309         /* Require Write-Back (WB) memory type for VMCS accesses. */
1310         if (((vmx_msr_high >> 18) & 15) != 6)
1311                 return -EIO;
1312
1313         vmcs_conf->size = vmx_msr_high & 0x1fff;
1314         vmcs_conf->order = get_order(vmcs_config.size);
1315         vmcs_conf->revision_id = vmx_msr_low;
1316
1317         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1318         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1319         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1320         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1321         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1322
1323         return 0;
1324 }
1325
1326 static struct vmcs *alloc_vmcs_cpu(int cpu)
1327 {
1328         int node = cpu_to_node(cpu);
1329         struct page *pages;
1330         struct vmcs *vmcs;
1331
1332         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1333         if (!pages)
1334                 return NULL;
1335         vmcs = page_address(pages);
1336         memset(vmcs, 0, vmcs_config.size);
1337         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1338         return vmcs;
1339 }
1340
1341 static struct vmcs *alloc_vmcs(void)
1342 {
1343         return alloc_vmcs_cpu(raw_smp_processor_id());
1344 }
1345
1346 static void free_vmcs(struct vmcs *vmcs)
1347 {
1348         free_pages((unsigned long)vmcs, vmcs_config.order);
1349 }
1350
1351 static void free_kvm_area(void)
1352 {
1353         int cpu;
1354
1355         for_each_possible_cpu(cpu) {
1356                 free_vmcs(per_cpu(vmxarea, cpu));
1357                 per_cpu(vmxarea, cpu) = NULL;
1358         }
1359 }
1360
1361 static __init int alloc_kvm_area(void)
1362 {
1363         int cpu;
1364
1365         for_each_possible_cpu(cpu) {
1366                 struct vmcs *vmcs;
1367
1368                 vmcs = alloc_vmcs_cpu(cpu);
1369                 if (!vmcs) {
1370                         free_kvm_area();
1371                         return -ENOMEM;
1372                 }
1373
1374                 per_cpu(vmxarea, cpu) = vmcs;
1375         }
1376         return 0;
1377 }
1378
1379 static __init int hardware_setup(void)
1380 {
1381         if (setup_vmcs_config(&vmcs_config) < 0)
1382                 return -EIO;
1383
1384         if (boot_cpu_has(X86_FEATURE_NX))
1385                 kvm_enable_efer_bits(EFER_NX);
1386
1387         if (!cpu_has_vmx_vpid())
1388                 enable_vpid = 0;
1389
1390         if (!cpu_has_vmx_ept()) {
1391                 enable_ept = 0;
1392                 enable_unrestricted_guest = 0;
1393         }
1394
1395         if (!cpu_has_vmx_unrestricted_guest())
1396                 enable_unrestricted_guest = 0;
1397
1398         if (!cpu_has_vmx_flexpriority())
1399                 flexpriority_enabled = 0;
1400
1401         if (!cpu_has_vmx_tpr_shadow())
1402                 kvm_x86_ops->update_cr8_intercept = NULL;
1403
1404         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1405                 kvm_disable_largepages();
1406
1407         if (!cpu_has_vmx_ple())
1408                 ple_gap = 0;
1409
1410         return alloc_kvm_area();
1411 }
1412
1413 static __exit void hardware_unsetup(void)
1414 {
1415         free_kvm_area();
1416 }
1417
1418 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1419 {
1420         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1421
1422         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1423                 vmcs_write16(sf->selector, save->selector);
1424                 vmcs_writel(sf->base, save->base);
1425                 vmcs_write32(sf->limit, save->limit);
1426                 vmcs_write32(sf->ar_bytes, save->ar);
1427         } else {
1428                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1429                         << AR_DPL_SHIFT;
1430                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1431         }
1432 }
1433
1434 static void enter_pmode(struct kvm_vcpu *vcpu)
1435 {
1436         unsigned long flags;
1437         struct vcpu_vmx *vmx = to_vmx(vcpu);
1438
1439         vmx->emulation_required = 1;
1440         vmx->rmode.vm86_active = 0;
1441
1442         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1443         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1444         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1445
1446         flags = vmcs_readl(GUEST_RFLAGS);
1447         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1448         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1449         vmcs_writel(GUEST_RFLAGS, flags);
1450
1451         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1452                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1453
1454         update_exception_bitmap(vcpu);
1455
1456         if (emulate_invalid_guest_state)
1457                 return;
1458
1459         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1460         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1461         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1462         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1463
1464         vmcs_write16(GUEST_SS_SELECTOR, 0);
1465         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1466
1467         vmcs_write16(GUEST_CS_SELECTOR,
1468                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1469         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1470 }
1471
1472 static gva_t rmode_tss_base(struct kvm *kvm)
1473 {
1474         if (!kvm->arch.tss_addr) {
1475                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1476                                  kvm->memslots[0].npages - 3;
1477                 return base_gfn << PAGE_SHIFT;
1478         }
1479         return kvm->arch.tss_addr;
1480 }
1481
1482 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1483 {
1484         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1485
1486         save->selector = vmcs_read16(sf->selector);
1487         save->base = vmcs_readl(sf->base);
1488         save->limit = vmcs_read32(sf->limit);
1489         save->ar = vmcs_read32(sf->ar_bytes);
1490         vmcs_write16(sf->selector, save->base >> 4);
1491         vmcs_write32(sf->base, save->base & 0xfffff);
1492         vmcs_write32(sf->limit, 0xffff);
1493         vmcs_write32(sf->ar_bytes, 0xf3);
1494 }
1495
1496 static void enter_rmode(struct kvm_vcpu *vcpu)
1497 {
1498         unsigned long flags;
1499         struct vcpu_vmx *vmx = to_vmx(vcpu);
1500
1501         if (enable_unrestricted_guest)
1502                 return;
1503
1504         vmx->emulation_required = 1;
1505         vmx->rmode.vm86_active = 1;
1506
1507         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1508         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1509
1510         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1511         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1512
1513         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1514         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1515
1516         flags = vmcs_readl(GUEST_RFLAGS);
1517         vmx->rmode.save_iopl
1518                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1519
1520         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1521
1522         vmcs_writel(GUEST_RFLAGS, flags);
1523         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1524         update_exception_bitmap(vcpu);
1525
1526         if (emulate_invalid_guest_state)
1527                 goto continue_rmode;
1528
1529         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1530         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1531         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1532
1533         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1534         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1535         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1536                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1537         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1538
1539         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1540         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1541         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1542         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1543
1544 continue_rmode:
1545         kvm_mmu_reset_context(vcpu);
1546         init_rmode(vcpu->kvm);
1547 }
1548
1549 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1550 {
1551         struct vcpu_vmx *vmx = to_vmx(vcpu);
1552         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1553
1554         if (!msr)
1555                 return;
1556
1557         /*
1558          * Force kernel_gs_base reloading before EFER changes, as control
1559          * of this msr depends on is_long_mode().
1560          */
1561         vmx_load_host_state(to_vmx(vcpu));
1562         vcpu->arch.shadow_efer = efer;
1563         if (!msr)
1564                 return;
1565         if (efer & EFER_LMA) {
1566                 vmcs_write32(VM_ENTRY_CONTROLS,
1567                              vmcs_read32(VM_ENTRY_CONTROLS) |
1568                              VM_ENTRY_IA32E_MODE);
1569                 msr->data = efer;
1570         } else {
1571                 vmcs_write32(VM_ENTRY_CONTROLS,
1572                              vmcs_read32(VM_ENTRY_CONTROLS) &
1573                              ~VM_ENTRY_IA32E_MODE);
1574
1575                 msr->data = efer & ~EFER_LME;
1576         }
1577         setup_msrs(vmx);
1578 }
1579
1580 #ifdef CONFIG_X86_64
1581
1582 static void enter_lmode(struct kvm_vcpu *vcpu)
1583 {
1584         u32 guest_tr_ar;
1585
1586         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1587         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1588                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1589                        __func__);
1590                 vmcs_write32(GUEST_TR_AR_BYTES,
1591                              (guest_tr_ar & ~AR_TYPE_MASK)
1592                              | AR_TYPE_BUSY_64_TSS);
1593         }
1594         vcpu->arch.shadow_efer |= EFER_LMA;
1595         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1596 }
1597
1598 static void exit_lmode(struct kvm_vcpu *vcpu)
1599 {
1600         vcpu->arch.shadow_efer &= ~EFER_LMA;
1601
1602         vmcs_write32(VM_ENTRY_CONTROLS,
1603                      vmcs_read32(VM_ENTRY_CONTROLS)
1604                      & ~VM_ENTRY_IA32E_MODE);
1605 }
1606
1607 #endif
1608
1609 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1610 {
1611         vpid_sync_vcpu_all(to_vmx(vcpu));
1612         if (enable_ept)
1613                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1614 }
1615
1616 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1617 {
1618         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1619
1620         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1621         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1622 }
1623
1624 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1625 {
1626         if (!test_bit(VCPU_EXREG_PDPTR,
1627                       (unsigned long *)&vcpu->arch.regs_dirty))
1628                 return;
1629
1630         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1631                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1632                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1633                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1634                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1635         }
1636 }
1637
1638 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1639 {
1640         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1641                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1642                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1643                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1644                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1645         }
1646
1647         __set_bit(VCPU_EXREG_PDPTR,
1648                   (unsigned long *)&vcpu->arch.regs_avail);
1649         __set_bit(VCPU_EXREG_PDPTR,
1650                   (unsigned long *)&vcpu->arch.regs_dirty);
1651 }
1652
1653 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1654
1655 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1656                                         unsigned long cr0,
1657                                         struct kvm_vcpu *vcpu)
1658 {
1659         if (!(cr0 & X86_CR0_PG)) {
1660                 /* From paging/starting to nonpaging */
1661                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1662                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1663                              (CPU_BASED_CR3_LOAD_EXITING |
1664                               CPU_BASED_CR3_STORE_EXITING));
1665                 vcpu->arch.cr0 = cr0;
1666                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1667         } else if (!is_paging(vcpu)) {
1668                 /* From nonpaging to paging */
1669                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1670                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1671                              ~(CPU_BASED_CR3_LOAD_EXITING |
1672                                CPU_BASED_CR3_STORE_EXITING));
1673                 vcpu->arch.cr0 = cr0;
1674                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1675         }
1676
1677         if (!(cr0 & X86_CR0_WP))
1678                 *hw_cr0 &= ~X86_CR0_WP;
1679 }
1680
1681 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1682                                         struct kvm_vcpu *vcpu)
1683 {
1684         if (!is_paging(vcpu)) {
1685                 *hw_cr4 &= ~X86_CR4_PAE;
1686                 *hw_cr4 |= X86_CR4_PSE;
1687         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1688                 *hw_cr4 &= ~X86_CR4_PAE;
1689 }
1690
1691 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1692 {
1693         struct vcpu_vmx *vmx = to_vmx(vcpu);
1694         unsigned long hw_cr0;
1695
1696         if (enable_unrestricted_guest)
1697                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1698                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1699         else
1700                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1701
1702         vmx_fpu_deactivate(vcpu);
1703
1704         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1705                 enter_pmode(vcpu);
1706
1707         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1708                 enter_rmode(vcpu);
1709
1710 #ifdef CONFIG_X86_64
1711         if (vcpu->arch.shadow_efer & EFER_LME) {
1712                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1713                         enter_lmode(vcpu);
1714                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1715                         exit_lmode(vcpu);
1716         }
1717 #endif
1718
1719         if (enable_ept)
1720                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1721
1722         vmcs_writel(CR0_READ_SHADOW, cr0);
1723         vmcs_writel(GUEST_CR0, hw_cr0);
1724         vcpu->arch.cr0 = cr0;
1725
1726         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1727                 vmx_fpu_activate(vcpu);
1728 }
1729
1730 static u64 construct_eptp(unsigned long root_hpa)
1731 {
1732         u64 eptp;
1733
1734         /* TODO write the value reading from MSR */
1735         eptp = VMX_EPT_DEFAULT_MT |
1736                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1737         eptp |= (root_hpa & PAGE_MASK);
1738
1739         return eptp;
1740 }
1741
1742 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1743 {
1744         unsigned long guest_cr3;
1745         u64 eptp;
1746
1747         guest_cr3 = cr3;
1748         if (enable_ept) {
1749                 eptp = construct_eptp(cr3);
1750                 vmcs_write64(EPT_POINTER, eptp);
1751                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1752                         vcpu->kvm->arch.ept_identity_map_addr;
1753                 ept_load_pdptrs(vcpu);
1754         }
1755
1756         vmx_flush_tlb(vcpu);
1757         vmcs_writel(GUEST_CR3, guest_cr3);
1758         if (vcpu->arch.cr0 & X86_CR0_PE)
1759                 vmx_fpu_deactivate(vcpu);
1760 }
1761
1762 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1763 {
1764         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1765                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1766
1767         vcpu->arch.cr4 = cr4;
1768         if (enable_ept)
1769                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1770
1771         vmcs_writel(CR4_READ_SHADOW, cr4);
1772         vmcs_writel(GUEST_CR4, hw_cr4);
1773 }
1774
1775 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1776 {
1777         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1778
1779         return vmcs_readl(sf->base);
1780 }
1781
1782 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1783                             struct kvm_segment *var, int seg)
1784 {
1785         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1786         u32 ar;
1787
1788         var->base = vmcs_readl(sf->base);
1789         var->limit = vmcs_read32(sf->limit);
1790         var->selector = vmcs_read16(sf->selector);
1791         ar = vmcs_read32(sf->ar_bytes);
1792         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1793                 ar = 0;
1794         var->type = ar & 15;
1795         var->s = (ar >> 4) & 1;
1796         var->dpl = (ar >> 5) & 3;
1797         var->present = (ar >> 7) & 1;
1798         var->avl = (ar >> 12) & 1;
1799         var->l = (ar >> 13) & 1;
1800         var->db = (ar >> 14) & 1;
1801         var->g = (ar >> 15) & 1;
1802         var->unusable = (ar >> 16) & 1;
1803 }
1804
1805 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1806 {
1807         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1808                 return 0;
1809
1810         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1811                 return 3;
1812
1813         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1814 }
1815
1816 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1817 {
1818         u32 ar;
1819
1820         if (var->unusable)
1821                 ar = 1 << 16;
1822         else {
1823                 ar = var->type & 15;
1824                 ar |= (var->s & 1) << 4;
1825                 ar |= (var->dpl & 3) << 5;
1826                 ar |= (var->present & 1) << 7;
1827                 ar |= (var->avl & 1) << 12;
1828                 ar |= (var->l & 1) << 13;
1829                 ar |= (var->db & 1) << 14;
1830                 ar |= (var->g & 1) << 15;
1831         }
1832         if (ar == 0) /* a 0 value means unusable */
1833                 ar = AR_UNUSABLE_MASK;
1834
1835         return ar;
1836 }
1837
1838 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1839                             struct kvm_segment *var, int seg)
1840 {
1841         struct vcpu_vmx *vmx = to_vmx(vcpu);
1842         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1843         u32 ar;
1844
1845         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1846                 vmx->rmode.tr.selector = var->selector;
1847                 vmx->rmode.tr.base = var->base;
1848                 vmx->rmode.tr.limit = var->limit;
1849                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1850                 return;
1851         }
1852         vmcs_writel(sf->base, var->base);
1853         vmcs_write32(sf->limit, var->limit);
1854         vmcs_write16(sf->selector, var->selector);
1855         if (vmx->rmode.vm86_active && var->s) {
1856                 /*
1857                  * Hack real-mode segments into vm86 compatibility.
1858                  */
1859                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1860                         vmcs_writel(sf->base, 0xf0000);
1861                 ar = 0xf3;
1862         } else
1863                 ar = vmx_segment_access_rights(var);
1864
1865         /*
1866          *   Fix the "Accessed" bit in AR field of segment registers for older
1867          * qemu binaries.
1868          *   IA32 arch specifies that at the time of processor reset the
1869          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1870          * is setting it to 0 in the usedland code. This causes invalid guest
1871          * state vmexit when "unrestricted guest" mode is turned on.
1872          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1873          * tree. Newer qemu binaries with that qemu fix would not need this
1874          * kvm hack.
1875          */
1876         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1877                 ar |= 0x1; /* Accessed */
1878
1879         vmcs_write32(sf->ar_bytes, ar);
1880 }
1881
1882 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1883 {
1884         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1885
1886         *db = (ar >> 14) & 1;
1887         *l = (ar >> 13) & 1;
1888 }
1889
1890 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1891 {
1892         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1893         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1894 }
1895
1896 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1897 {
1898         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1899         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1900 }
1901
1902 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1903 {
1904         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1905         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1906 }
1907
1908 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1909 {
1910         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1911         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1912 }
1913
1914 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1915 {
1916         struct kvm_segment var;
1917         u32 ar;
1918
1919         vmx_get_segment(vcpu, &var, seg);
1920         ar = vmx_segment_access_rights(&var);
1921
1922         if (var.base != (var.selector << 4))
1923                 return false;
1924         if (var.limit != 0xffff)
1925                 return false;
1926         if (ar != 0xf3)
1927                 return false;
1928
1929         return true;
1930 }
1931
1932 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1933 {
1934         struct kvm_segment cs;
1935         unsigned int cs_rpl;
1936
1937         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1938         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1939
1940         if (cs.unusable)
1941                 return false;
1942         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1943                 return false;
1944         if (!cs.s)
1945                 return false;
1946         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1947                 if (cs.dpl > cs_rpl)
1948                         return false;
1949         } else {
1950                 if (cs.dpl != cs_rpl)
1951                         return false;
1952         }
1953         if (!cs.present)
1954                 return false;
1955
1956         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1957         return true;
1958 }
1959
1960 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1961 {
1962         struct kvm_segment ss;
1963         unsigned int ss_rpl;
1964
1965         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1966         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1967
1968         if (ss.unusable)
1969                 return true;
1970         if (ss.type != 3 && ss.type != 7)
1971                 return false;
1972         if (!ss.s)
1973                 return false;
1974         if (ss.dpl != ss_rpl) /* DPL != RPL */
1975                 return false;
1976         if (!ss.present)
1977                 return false;
1978
1979         return true;
1980 }
1981
1982 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1983 {
1984         struct kvm_segment var;
1985         unsigned int rpl;
1986
1987         vmx_get_segment(vcpu, &var, seg);
1988         rpl = var.selector & SELECTOR_RPL_MASK;
1989
1990         if (var.unusable)
1991                 return true;
1992         if (!var.s)
1993                 return false;
1994         if (!var.present)
1995                 return false;
1996         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1997                 if (var.dpl < rpl) /* DPL < RPL */
1998                         return false;
1999         }
2000
2001         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2002          * rights flags
2003          */
2004         return true;
2005 }
2006
2007 static bool tr_valid(struct kvm_vcpu *vcpu)
2008 {
2009         struct kvm_segment tr;
2010
2011         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2012
2013         if (tr.unusable)
2014                 return false;
2015         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2016                 return false;
2017         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2018                 return false;
2019         if (!tr.present)
2020                 return false;
2021
2022         return true;
2023 }
2024
2025 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2026 {
2027         struct kvm_segment ldtr;
2028
2029         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2030
2031         if (ldtr.unusable)
2032                 return true;
2033         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2034                 return false;
2035         if (ldtr.type != 2)
2036                 return false;
2037         if (!ldtr.present)
2038                 return false;
2039
2040         return true;
2041 }
2042
2043 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2044 {
2045         struct kvm_segment cs, ss;
2046
2047         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2048         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2049
2050         return ((cs.selector & SELECTOR_RPL_MASK) ==
2051                  (ss.selector & SELECTOR_RPL_MASK));
2052 }
2053
2054 /*
2055  * Check if guest state is valid. Returns true if valid, false if
2056  * not.
2057  * We assume that registers are always usable
2058  */
2059 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2060 {
2061         /* real mode guest state checks */
2062         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2063                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2064                         return false;
2065                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2066                         return false;
2067                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2068                         return false;
2069                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2070                         return false;
2071                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2072                         return false;
2073                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2074                         return false;
2075         } else {
2076         /* protected mode guest state checks */
2077                 if (!cs_ss_rpl_check(vcpu))
2078                         return false;
2079                 if (!code_segment_valid(vcpu))
2080                         return false;
2081                 if (!stack_segment_valid(vcpu))
2082                         return false;
2083                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2084                         return false;
2085                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2086                         return false;
2087                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2088                         return false;
2089                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2090                         return false;
2091                 if (!tr_valid(vcpu))
2092                         return false;
2093                 if (!ldtr_valid(vcpu))
2094                         return false;
2095         }
2096         /* TODO:
2097          * - Add checks on RIP
2098          * - Add checks on RFLAGS
2099          */
2100
2101         return true;
2102 }
2103
2104 static int init_rmode_tss(struct kvm *kvm)
2105 {
2106         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2107         u16 data = 0;
2108         int ret = 0;
2109         int r;
2110
2111         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2112         if (r < 0)
2113                 goto out;
2114         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2115         r = kvm_write_guest_page(kvm, fn++, &data,
2116                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2117         if (r < 0)
2118                 goto out;
2119         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2120         if (r < 0)
2121                 goto out;
2122         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2123         if (r < 0)
2124                 goto out;
2125         data = ~0;
2126         r = kvm_write_guest_page(kvm, fn, &data,
2127                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2128                                  sizeof(u8));
2129         if (r < 0)
2130                 goto out;
2131
2132         ret = 1;
2133 out:
2134         return ret;
2135 }
2136
2137 static int init_rmode_identity_map(struct kvm *kvm)
2138 {
2139         int i, r, ret;
2140         pfn_t identity_map_pfn;
2141         u32 tmp;
2142
2143         if (!enable_ept)
2144                 return 1;
2145         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2146                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2147                         "haven't been allocated!\n");
2148                 return 0;
2149         }
2150         if (likely(kvm->arch.ept_identity_pagetable_done))
2151                 return 1;
2152         ret = 0;
2153         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2154         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2155         if (r < 0)
2156                 goto out;
2157         /* Set up identity-mapping pagetable for EPT in real mode */
2158         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2159                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2160                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2161                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2162                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2163                 if (r < 0)
2164                         goto out;
2165         }
2166         kvm->arch.ept_identity_pagetable_done = true;
2167         ret = 1;
2168 out:
2169         return ret;
2170 }
2171
2172 static void seg_setup(int seg)
2173 {
2174         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2175         unsigned int ar;
2176
2177         vmcs_write16(sf->selector, 0);
2178         vmcs_writel(sf->base, 0);
2179         vmcs_write32(sf->limit, 0xffff);
2180         if (enable_unrestricted_guest) {
2181                 ar = 0x93;
2182                 if (seg == VCPU_SREG_CS)
2183                         ar |= 0x08; /* code segment */
2184         } else
2185                 ar = 0xf3;
2186
2187         vmcs_write32(sf->ar_bytes, ar);
2188 }
2189
2190 static int alloc_apic_access_page(struct kvm *kvm)
2191 {
2192         struct kvm_userspace_memory_region kvm_userspace_mem;
2193         int r = 0;
2194
2195         down_write(&kvm->slots_lock);
2196         if (kvm->arch.apic_access_page)
2197                 goto out;
2198         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2199         kvm_userspace_mem.flags = 0;
2200         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2201         kvm_userspace_mem.memory_size = PAGE_SIZE;
2202         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2203         if (r)
2204                 goto out;
2205
2206         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2207 out:
2208         up_write(&kvm->slots_lock);
2209         return r;
2210 }
2211
2212 static int alloc_identity_pagetable(struct kvm *kvm)
2213 {
2214         struct kvm_userspace_memory_region kvm_userspace_mem;
2215         int r = 0;
2216
2217         down_write(&kvm->slots_lock);
2218         if (kvm->arch.ept_identity_pagetable)
2219                 goto out;
2220         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2221         kvm_userspace_mem.flags = 0;
2222         kvm_userspace_mem.guest_phys_addr =
2223                 kvm->arch.ept_identity_map_addr;
2224         kvm_userspace_mem.memory_size = PAGE_SIZE;
2225         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2226         if (r)
2227                 goto out;
2228
2229         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2230                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2231 out:
2232         up_write(&kvm->slots_lock);
2233         return r;
2234 }
2235
2236 static void allocate_vpid(struct vcpu_vmx *vmx)
2237 {
2238         int vpid;
2239
2240         vmx->vpid = 0;
2241         if (!enable_vpid)
2242                 return;
2243         spin_lock(&vmx_vpid_lock);
2244         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2245         if (vpid < VMX_NR_VPIDS) {
2246                 vmx->vpid = vpid;
2247                 __set_bit(vpid, vmx_vpid_bitmap);
2248         }
2249         spin_unlock(&vmx_vpid_lock);
2250 }
2251
2252 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2253 {
2254         int f = sizeof(unsigned long);
2255
2256         if (!cpu_has_vmx_msr_bitmap())
2257                 return;
2258
2259         /*
2260          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2261          * have the write-low and read-high bitmap offsets the wrong way round.
2262          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2263          */
2264         if (msr <= 0x1fff) {
2265                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2266                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2267         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2268                 msr &= 0x1fff;
2269                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2270                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2271         }
2272 }
2273
2274 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2275 {
2276         if (!longmode_only)
2277                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2278         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2279 }
2280
2281 /*
2282  * Sets up the vmcs for emulated real mode.
2283  */
2284 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2285 {
2286         u32 host_sysenter_cs, msr_low, msr_high;
2287         u32 junk;
2288         u64 host_pat, tsc_this, tsc_base;
2289         unsigned long a;
2290         struct descriptor_table dt;
2291         int i;
2292         unsigned long kvm_vmx_return;
2293         u32 exec_control;
2294
2295         /* I/O */
2296         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2297         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2298
2299         if (cpu_has_vmx_msr_bitmap())
2300                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2301
2302         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2303
2304         /* Control */
2305         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2306                 vmcs_config.pin_based_exec_ctrl);
2307
2308         exec_control = vmcs_config.cpu_based_exec_ctrl;
2309         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2310                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2311 #ifdef CONFIG_X86_64
2312                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2313                                 CPU_BASED_CR8_LOAD_EXITING;
2314 #endif
2315         }
2316         if (!enable_ept)
2317                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2318                                 CPU_BASED_CR3_LOAD_EXITING  |
2319                                 CPU_BASED_INVLPG_EXITING;
2320         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2321
2322         if (cpu_has_secondary_exec_ctrls()) {
2323                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2324                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2325                         exec_control &=
2326                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2327                 if (vmx->vpid == 0)
2328                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2329                 if (!enable_ept) {
2330                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2331                         enable_unrestricted_guest = 0;
2332                 }
2333                 if (!enable_unrestricted_guest)
2334                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2335                 if (!ple_gap)
2336                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2337                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2338         }
2339
2340         if (ple_gap) {
2341                 vmcs_write32(PLE_GAP, ple_gap);
2342                 vmcs_write32(PLE_WINDOW, ple_window);
2343         }
2344
2345         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2346         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2347         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2348
2349         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2350         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2351         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2352
2353         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2354         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2355         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2356         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2357         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2358         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2359 #ifdef CONFIG_X86_64
2360         rdmsrl(MSR_FS_BASE, a);
2361         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2362         rdmsrl(MSR_GS_BASE, a);
2363         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2364 #else
2365         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2366         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2367 #endif
2368
2369         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2370
2371         kvm_get_idt(&dt);
2372         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2373
2374         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2375         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2376         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2377         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2378         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2379
2380         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2381         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2382         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2383         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2384         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2385         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2386
2387         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2388                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2389                 host_pat = msr_low | ((u64) msr_high << 32);
2390                 vmcs_write64(HOST_IA32_PAT, host_pat);
2391         }
2392         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2393                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2394                 host_pat = msr_low | ((u64) msr_high << 32);
2395                 /* Write the default value follow host pat */
2396                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2397                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2398                 vmx->vcpu.arch.pat = host_pat;
2399         }
2400
2401         for (i = 0; i < NR_VMX_MSR; ++i) {
2402                 u32 index = vmx_msr_index[i];
2403                 u32 data_low, data_high;
2404                 u64 data;
2405                 int j = vmx->nmsrs;
2406
2407                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2408                         continue;
2409                 if (wrmsr_safe(index, data_low, data_high) < 0)
2410                         continue;
2411                 data = data_low | ((u64)data_high << 32);
2412                 vmx->guest_msrs[j].index = i;
2413                 vmx->guest_msrs[j].data = 0;
2414                 vmx->guest_msrs[j].mask = -1ull;
2415                 ++vmx->nmsrs;
2416         }
2417
2418         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2419
2420         /* 22.2.1, 20.8.1 */
2421         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2422
2423         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2424         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2425         vmx->vcpu.arch.cr4_guest_owned_bits = ~KVM_GUEST_CR4_MASK;
2426
2427         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2428         rdtscll(tsc_this);
2429         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2430                 tsc_base = tsc_this;
2431
2432         guest_write_tsc(0, tsc_base);
2433
2434         return 0;
2435 }
2436
2437 static int init_rmode(struct kvm *kvm)
2438 {
2439         if (!init_rmode_tss(kvm))
2440                 return 0;
2441         if (!init_rmode_identity_map(kvm))
2442                 return 0;
2443         return 1;
2444 }
2445
2446 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2447 {
2448         struct vcpu_vmx *vmx = to_vmx(vcpu);
2449         u64 msr;
2450         int ret;
2451
2452         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2453         down_read(&vcpu->kvm->slots_lock);
2454         if (!init_rmode(vmx->vcpu.kvm)) {
2455                 ret = -ENOMEM;
2456                 goto out;
2457         }
2458
2459         vmx->rmode.vm86_active = 0;
2460
2461         vmx->soft_vnmi_blocked = 0;
2462
2463         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2464         kvm_set_cr8(&vmx->vcpu, 0);
2465         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2466         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2467                 msr |= MSR_IA32_APICBASE_BSP;
2468         kvm_set_apic_base(&vmx->vcpu, msr);
2469
2470         fx_init(&vmx->vcpu);
2471
2472         seg_setup(VCPU_SREG_CS);
2473         /*
2474          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2475          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2476          */
2477         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2478                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2479                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2480         } else {
2481                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2482                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2483         }
2484
2485         seg_setup(VCPU_SREG_DS);
2486         seg_setup(VCPU_SREG_ES);
2487         seg_setup(VCPU_SREG_FS);
2488         seg_setup(VCPU_SREG_GS);
2489         seg_setup(VCPU_SREG_SS);
2490
2491         vmcs_write16(GUEST_TR_SELECTOR, 0);
2492         vmcs_writel(GUEST_TR_BASE, 0);
2493         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2494         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2495
2496         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2497         vmcs_writel(GUEST_LDTR_BASE, 0);
2498         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2499         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2500
2501         vmcs_write32(GUEST_SYSENTER_CS, 0);
2502         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2503         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2504
2505         vmcs_writel(GUEST_RFLAGS, 0x02);
2506         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2507                 kvm_rip_write(vcpu, 0xfff0);
2508         else
2509                 kvm_rip_write(vcpu, 0);
2510         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2511
2512         vmcs_writel(GUEST_DR7, 0x400);
2513
2514         vmcs_writel(GUEST_GDTR_BASE, 0);
2515         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2516
2517         vmcs_writel(GUEST_IDTR_BASE, 0);
2518         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2519
2520         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2521         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2522         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2523
2524         /* Special registers */
2525         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2526
2527         setup_msrs(vmx);
2528
2529         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2530
2531         if (cpu_has_vmx_tpr_shadow()) {
2532                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2533                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2534                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2535                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2536                 vmcs_write32(TPR_THRESHOLD, 0);
2537         }
2538
2539         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2540                 vmcs_write64(APIC_ACCESS_ADDR,
2541                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2542
2543         if (vmx->vpid != 0)
2544                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2545
2546         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2547         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2548         vmx_set_cr4(&vmx->vcpu, 0);
2549         vmx_set_efer(&vmx->vcpu, 0);
2550         vmx_fpu_activate(&vmx->vcpu);
2551         update_exception_bitmap(&vmx->vcpu);
2552
2553         vpid_sync_vcpu_all(vmx);
2554
2555         ret = 0;
2556
2557         /* HACK: Don't enable emulation on guest boot/reset */
2558         vmx->emulation_required = 0;
2559
2560 out:
2561         up_read(&vcpu->kvm->slots_lock);
2562         return ret;
2563 }
2564
2565 static void enable_irq_window(struct kvm_vcpu *vcpu)
2566 {
2567         u32 cpu_based_vm_exec_control;
2568
2569         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2570         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2571         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2572 }
2573
2574 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2575 {
2576         u32 cpu_based_vm_exec_control;
2577
2578         if (!cpu_has_virtual_nmis()) {
2579                 enable_irq_window(vcpu);
2580                 return;
2581         }
2582
2583         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2584         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2585         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2586 }
2587
2588 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2589 {
2590         struct vcpu_vmx *vmx = to_vmx(vcpu);
2591         uint32_t intr;
2592         int irq = vcpu->arch.interrupt.nr;
2593
2594         trace_kvm_inj_virq(irq);
2595
2596         ++vcpu->stat.irq_injections;
2597         if (vmx->rmode.vm86_active) {
2598                 vmx->rmode.irq.pending = true;
2599                 vmx->rmode.irq.vector = irq;
2600                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2601                 if (vcpu->arch.interrupt.soft)
2602                         vmx->rmode.irq.rip +=
2603                                 vmx->vcpu.arch.event_exit_inst_len;
2604                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2605                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2606                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2607                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2608                 return;
2609         }
2610         intr = irq | INTR_INFO_VALID_MASK;
2611         if (vcpu->arch.interrupt.soft) {
2612                 intr |= INTR_TYPE_SOFT_INTR;
2613                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2614                              vmx->vcpu.arch.event_exit_inst_len);
2615         } else
2616                 intr |= INTR_TYPE_EXT_INTR;
2617         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2618 }
2619
2620 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2621 {
2622         struct vcpu_vmx *vmx = to_vmx(vcpu);
2623
2624         if (!cpu_has_virtual_nmis()) {
2625                 /*
2626                  * Tracking the NMI-blocked state in software is built upon
2627                  * finding the next open IRQ window. This, in turn, depends on
2628                  * well-behaving guests: They have to keep IRQs disabled at
2629                  * least as long as the NMI handler runs. Otherwise we may
2630                  * cause NMI nesting, maybe breaking the guest. But as this is
2631                  * highly unlikely, we can live with the residual risk.
2632                  */
2633                 vmx->soft_vnmi_blocked = 1;
2634                 vmx->vnmi_blocked_time = 0;
2635         }
2636
2637         ++vcpu->stat.nmi_injections;
2638         if (vmx->rmode.vm86_active) {
2639                 vmx->rmode.irq.pending = true;
2640                 vmx->rmode.irq.vector = NMI_VECTOR;
2641                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2642                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2643                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2644                              INTR_INFO_VALID_MASK);
2645                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2646                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2647                 return;
2648         }
2649         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2650                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2651 }
2652
2653 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2654 {
2655         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2656                 return 0;
2657
2658         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2659                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2660                                 GUEST_INTR_STATE_NMI));
2661 }
2662
2663 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2664 {
2665         if (!cpu_has_virtual_nmis())
2666                 return to_vmx(vcpu)->soft_vnmi_blocked;
2667         else
2668                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2669                           GUEST_INTR_STATE_NMI);
2670 }
2671
2672 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2673 {
2674         struct vcpu_vmx *vmx = to_vmx(vcpu);
2675
2676         if (!cpu_has_virtual_nmis()) {
2677                 if (vmx->soft_vnmi_blocked != masked) {
2678                         vmx->soft_vnmi_blocked = masked;
2679                         vmx->vnmi_blocked_time = 0;
2680                 }
2681         } else {
2682                 if (masked)
2683                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2684                                       GUEST_INTR_STATE_NMI);
2685                 else
2686                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2687                                         GUEST_INTR_STATE_NMI);
2688         }
2689 }
2690
2691 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2692 {
2693         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2694                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2695                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2696 }
2697
2698 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2699 {
2700         int ret;
2701         struct kvm_userspace_memory_region tss_mem = {
2702                 .slot = TSS_PRIVATE_MEMSLOT,
2703                 .guest_phys_addr = addr,
2704                 .memory_size = PAGE_SIZE * 3,
2705                 .flags = 0,
2706         };
2707
2708         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2709         if (ret)
2710                 return ret;
2711         kvm->arch.tss_addr = addr;
2712         return 0;
2713 }
2714
2715 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2716                                   int vec, u32 err_code)
2717 {
2718         /*
2719          * Instruction with address size override prefix opcode 0x67
2720          * Cause the #SS fault with 0 error code in VM86 mode.
2721          */
2722         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2723                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2724                         return 1;
2725         /*
2726          * Forward all other exceptions that are valid in real mode.
2727          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2728          *        the required debugging infrastructure rework.
2729          */
2730         switch (vec) {
2731         case DB_VECTOR:
2732                 if (vcpu->guest_debug &
2733                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2734                         return 0;
2735                 kvm_queue_exception(vcpu, vec);
2736                 return 1;
2737         case BP_VECTOR:
2738                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2739                         return 0;
2740                 /* fall through */
2741         case DE_VECTOR:
2742         case OF_VECTOR:
2743         case BR_VECTOR:
2744         case UD_VECTOR:
2745         case DF_VECTOR:
2746         case SS_VECTOR:
2747         case GP_VECTOR:
2748         case MF_VECTOR:
2749                 kvm_queue_exception(vcpu, vec);
2750                 return 1;
2751         }
2752         return 0;
2753 }
2754
2755 /*
2756  * Trigger machine check on the host. We assume all the MSRs are already set up
2757  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2758  * We pass a fake environment to the machine check handler because we want
2759  * the guest to be always treated like user space, no matter what context
2760  * it used internally.
2761  */
2762 static void kvm_machine_check(void)
2763 {
2764 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2765         struct pt_regs regs = {
2766                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2767                 .flags = X86_EFLAGS_IF,
2768         };
2769
2770         do_machine_check(&regs, 0);
2771 #endif
2772 }
2773
2774 static int handle_machine_check(struct kvm_vcpu *vcpu)
2775 {
2776         /* already handled by vcpu_run */
2777         return 1;
2778 }
2779
2780 static int handle_exception(struct kvm_vcpu *vcpu)
2781 {
2782         struct vcpu_vmx *vmx = to_vmx(vcpu);
2783         struct kvm_run *kvm_run = vcpu->run;
2784         u32 intr_info, ex_no, error_code;
2785         unsigned long cr2, rip, dr6;
2786         u32 vect_info;
2787         enum emulation_result er;
2788
2789         vect_info = vmx->idt_vectoring_info;
2790         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2791
2792         if (is_machine_check(intr_info))
2793                 return handle_machine_check(vcpu);
2794
2795         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2796             !is_page_fault(intr_info)) {
2797                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2798                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2799                 vcpu->run->internal.ndata = 2;
2800                 vcpu->run->internal.data[0] = vect_info;
2801                 vcpu->run->internal.data[1] = intr_info;
2802                 return 0;
2803         }
2804
2805         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2806                 return 1;  /* already handled by vmx_vcpu_run() */
2807
2808         if (is_no_device(intr_info)) {
2809                 vmx_fpu_activate(vcpu);
2810                 return 1;
2811         }
2812
2813         if (is_invalid_opcode(intr_info)) {
2814                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2815                 if (er != EMULATE_DONE)
2816                         kvm_queue_exception(vcpu, UD_VECTOR);
2817                 return 1;
2818         }
2819
2820         error_code = 0;
2821         rip = kvm_rip_read(vcpu);
2822         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2823                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2824         if (is_page_fault(intr_info)) {
2825                 /* EPT won't cause page fault directly */
2826                 if (enable_ept)
2827                         BUG();
2828                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2829                 trace_kvm_page_fault(cr2, error_code);
2830
2831                 if (kvm_event_needs_reinjection(vcpu))
2832                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2833                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2834         }
2835
2836         if (vmx->rmode.vm86_active &&
2837             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2838                                                                 error_code)) {
2839                 if (vcpu->arch.halt_request) {
2840                         vcpu->arch.halt_request = 0;
2841                         return kvm_emulate_halt(vcpu);
2842                 }
2843                 return 1;
2844         }
2845
2846         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2847         switch (ex_no) {
2848         case DB_VECTOR:
2849                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2850                 if (!(vcpu->guest_debug &
2851                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2852                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2853                         kvm_queue_exception(vcpu, DB_VECTOR);
2854                         return 1;
2855                 }
2856                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2857                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2858                 /* fall through */
2859         case BP_VECTOR:
2860                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2861                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2862                 kvm_run->debug.arch.exception = ex_no;
2863                 break;
2864         default:
2865                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2866                 kvm_run->ex.exception = ex_no;
2867                 kvm_run->ex.error_code = error_code;
2868                 break;
2869         }
2870         return 0;
2871 }
2872
2873 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2874 {
2875         ++vcpu->stat.irq_exits;
2876         return 1;
2877 }
2878
2879 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2880 {
2881         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2882         return 0;
2883 }
2884
2885 static int handle_io(struct kvm_vcpu *vcpu)
2886 {
2887         unsigned long exit_qualification;
2888         int size, in, string;
2889         unsigned port;
2890
2891         ++vcpu->stat.io_exits;
2892         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2893         string = (exit_qualification & 16) != 0;
2894
2895         if (string) {
2896                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2897                         return 0;
2898                 return 1;
2899         }
2900
2901         size = (exit_qualification & 7) + 1;
2902         in = (exit_qualification & 8) != 0;
2903         port = exit_qualification >> 16;
2904
2905         skip_emulated_instruction(vcpu);
2906         return kvm_emulate_pio(vcpu, in, size, port);
2907 }
2908
2909 static void
2910 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2911 {
2912         /*
2913          * Patch in the VMCALL instruction:
2914          */
2915         hypercall[0] = 0x0f;
2916         hypercall[1] = 0x01;
2917         hypercall[2] = 0xc1;
2918 }
2919
2920 static int handle_cr(struct kvm_vcpu *vcpu)
2921 {
2922         unsigned long exit_qualification, val;
2923         int cr;
2924         int reg;
2925
2926         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2927         cr = exit_qualification & 15;
2928         reg = (exit_qualification >> 8) & 15;
2929         switch ((exit_qualification >> 4) & 3) {
2930         case 0: /* mov to cr */
2931                 val = kvm_register_read(vcpu, reg);
2932                 trace_kvm_cr_write(cr, val);
2933                 switch (cr) {
2934                 case 0:
2935                         kvm_set_cr0(vcpu, val);
2936                         skip_emulated_instruction(vcpu);
2937                         return 1;
2938                 case 3:
2939                         kvm_set_cr3(vcpu, val);
2940                         skip_emulated_instruction(vcpu);
2941                         return 1;
2942                 case 4:
2943                         kvm_set_cr4(vcpu, val);
2944                         skip_emulated_instruction(vcpu);
2945                         return 1;
2946                 case 8: {
2947                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2948                                 u8 cr8 = kvm_register_read(vcpu, reg);
2949                                 kvm_set_cr8(vcpu, cr8);
2950                                 skip_emulated_instruction(vcpu);
2951                                 if (irqchip_in_kernel(vcpu->kvm))
2952                                         return 1;
2953                                 if (cr8_prev <= cr8)
2954                                         return 1;
2955                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2956                                 return 0;
2957                         }
2958                 };
2959                 break;
2960         case 2: /* clts */
2961                 vmx_fpu_deactivate(vcpu);
2962                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2963                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2964                 vmx_fpu_activate(vcpu);
2965                 skip_emulated_instruction(vcpu);
2966                 return 1;
2967         case 1: /*mov from cr*/
2968                 switch (cr) {
2969                 case 3:
2970                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2971                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2972                         skip_emulated_instruction(vcpu);
2973                         return 1;
2974                 case 8:
2975                         val = kvm_get_cr8(vcpu);
2976                         kvm_register_write(vcpu, reg, val);
2977                         trace_kvm_cr_read(cr, val);
2978                         skip_emulated_instruction(vcpu);
2979                         return 1;
2980                 }
2981                 break;
2982         case 3: /* lmsw */
2983                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2984
2985                 skip_emulated_instruction(vcpu);
2986                 return 1;
2987         default:
2988                 break;
2989         }
2990         vcpu->run->exit_reason = 0;
2991         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2992                (int)(exit_qualification >> 4) & 3, cr);
2993         return 0;
2994 }
2995
2996 static int handle_dr(struct kvm_vcpu *vcpu)
2997 {
2998         unsigned long exit_qualification;
2999         unsigned long val;
3000         int dr, reg;
3001
3002         if (!kvm_require_cpl(vcpu, 0))
3003                 return 1;
3004         dr = vmcs_readl(GUEST_DR7);
3005         if (dr & DR7_GD) {
3006                 /*
3007                  * As the vm-exit takes precedence over the debug trap, we
3008                  * need to emulate the latter, either for the host or the
3009                  * guest debugging itself.
3010                  */
3011                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3012                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3013                         vcpu->run->debug.arch.dr7 = dr;
3014                         vcpu->run->debug.arch.pc =
3015                                 vmcs_readl(GUEST_CS_BASE) +
3016                                 vmcs_readl(GUEST_RIP);
3017                         vcpu->run->debug.arch.exception = DB_VECTOR;
3018                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3019                         return 0;
3020                 } else {
3021                         vcpu->arch.dr7 &= ~DR7_GD;
3022                         vcpu->arch.dr6 |= DR6_BD;
3023                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3024                         kvm_queue_exception(vcpu, DB_VECTOR);
3025                         return 1;
3026                 }
3027         }
3028
3029         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3030         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3031         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3032         if (exit_qualification & TYPE_MOV_FROM_DR) {
3033                 switch (dr) {
3034                 case 0 ... 3:
3035                         val = vcpu->arch.db[dr];
3036                         break;
3037                 case 6:
3038                         val = vcpu->arch.dr6;
3039                         break;
3040                 case 7:
3041                         val = vcpu->arch.dr7;
3042                         break;
3043                 default:
3044                         val = 0;
3045                 }
3046                 kvm_register_write(vcpu, reg, val);
3047         } else {
3048                 val = vcpu->arch.regs[reg];
3049                 switch (dr) {
3050                 case 0 ... 3:
3051                         vcpu->arch.db[dr] = val;
3052                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3053                                 vcpu->arch.eff_db[dr] = val;
3054                         break;
3055                 case 4 ... 5:
3056                         if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
3057                                 kvm_queue_exception(vcpu, UD_VECTOR);
3058                         break;
3059                 case 6:
3060                         if (val & 0xffffffff00000000ULL) {
3061                                 kvm_queue_exception(vcpu, GP_VECTOR);
3062                                 break;
3063                         }
3064                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3065                         break;
3066                 case 7:
3067                         if (val & 0xffffffff00000000ULL) {
3068                                 kvm_queue_exception(vcpu, GP_VECTOR);
3069                                 break;
3070                         }
3071                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3072                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3073                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3074                                 vcpu->arch.switch_db_regs =
3075                                         (val & DR7_BP_EN_MASK);
3076                         }
3077                         break;
3078                 }
3079         }
3080         skip_emulated_instruction(vcpu);
3081         return 1;
3082 }
3083
3084 static int handle_cpuid(struct kvm_vcpu *vcpu)
3085 {
3086         kvm_emulate_cpuid(vcpu);
3087         return 1;
3088 }
3089
3090 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3091 {
3092         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3093         u64 data;
3094
3095         if (vmx_get_msr(vcpu, ecx, &data)) {
3096                 kvm_inject_gp(vcpu, 0);
3097                 return 1;
3098         }
3099
3100         trace_kvm_msr_read(ecx, data);
3101
3102         /* FIXME: handling of bits 32:63 of rax, rdx */
3103         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3104         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3105         skip_emulated_instruction(vcpu);
3106         return 1;
3107 }
3108
3109 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3110 {
3111         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3112         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3113                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3114
3115         trace_kvm_msr_write(ecx, data);
3116
3117         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3118                 kvm_inject_gp(vcpu, 0);
3119                 return 1;
3120         }
3121
3122         skip_emulated_instruction(vcpu);
3123         return 1;
3124 }
3125
3126 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3127 {
3128         return 1;
3129 }
3130
3131 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3132 {
3133         u32 cpu_based_vm_exec_control;
3134
3135         /* clear pending irq */
3136         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3137         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3138         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3139
3140         ++vcpu->stat.irq_window_exits;
3141
3142         /*
3143          * If the user space waits to inject interrupts, exit as soon as
3144          * possible
3145          */
3146         if (!irqchip_in_kernel(vcpu->kvm) &&
3147             vcpu->run->request_interrupt_window &&
3148             !kvm_cpu_has_interrupt(vcpu)) {
3149                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3150                 return 0;
3151         }
3152         return 1;
3153 }
3154
3155 static int handle_halt(struct kvm_vcpu *vcpu)
3156 {
3157         skip_emulated_instruction(vcpu);
3158         return kvm_emulate_halt(vcpu);
3159 }
3160
3161 static int handle_vmcall(struct kvm_vcpu *vcpu)
3162 {
3163         skip_emulated_instruction(vcpu);
3164         kvm_emulate_hypercall(vcpu);
3165         return 1;
3166 }
3167
3168 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3169 {
3170         kvm_queue_exception(vcpu, UD_VECTOR);
3171         return 1;
3172 }
3173
3174 static int handle_invlpg(struct kvm_vcpu *vcpu)
3175 {
3176         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3177
3178         kvm_mmu_invlpg(vcpu, exit_qualification);
3179         skip_emulated_instruction(vcpu);
3180         return 1;
3181 }
3182
3183 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3184 {
3185         skip_emulated_instruction(vcpu);
3186         /* TODO: Add support for VT-d/pass-through device */
3187         return 1;
3188 }
3189
3190 static int handle_apic_access(struct kvm_vcpu *vcpu)
3191 {
3192         unsigned long exit_qualification;
3193         enum emulation_result er;
3194         unsigned long offset;
3195
3196         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3197         offset = exit_qualification & 0xffful;
3198
3199         er = emulate_instruction(vcpu, 0, 0, 0);
3200
3201         if (er !=  EMULATE_DONE) {
3202                 printk(KERN_ERR
3203                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3204                        offset);
3205                 return -ENOEXEC;
3206         }
3207         return 1;
3208 }
3209
3210 static int handle_task_switch(struct kvm_vcpu *vcpu)
3211 {
3212         struct vcpu_vmx *vmx = to_vmx(vcpu);
3213         unsigned long exit_qualification;
3214         u16 tss_selector;
3215         int reason, type, idt_v;
3216
3217         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3218         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3219
3220         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3221
3222         reason = (u32)exit_qualification >> 30;
3223         if (reason == TASK_SWITCH_GATE && idt_v) {
3224                 switch (type) {
3225                 case INTR_TYPE_NMI_INTR:
3226                         vcpu->arch.nmi_injected = false;
3227                         if (cpu_has_virtual_nmis())
3228                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3229                                               GUEST_INTR_STATE_NMI);
3230                         break;
3231                 case INTR_TYPE_EXT_INTR:
3232                 case INTR_TYPE_SOFT_INTR:
3233                         kvm_clear_interrupt_queue(vcpu);
3234                         break;
3235                 case INTR_TYPE_HARD_EXCEPTION:
3236                 case INTR_TYPE_SOFT_EXCEPTION:
3237                         kvm_clear_exception_queue(vcpu);
3238                         break;
3239                 default:
3240                         break;
3241                 }
3242         }
3243         tss_selector = exit_qualification;
3244
3245         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3246                        type != INTR_TYPE_EXT_INTR &&
3247                        type != INTR_TYPE_NMI_INTR))
3248                 skip_emulated_instruction(vcpu);
3249
3250         if (!kvm_task_switch(vcpu, tss_selector, reason))
3251                 return 0;
3252
3253         /* clear all local breakpoint enable flags */
3254         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3255
3256         /*
3257          * TODO: What about debug traps on tss switch?
3258          *       Are we supposed to inject them and update dr6?
3259          */
3260
3261         return 1;
3262 }
3263
3264 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3265 {
3266         unsigned long exit_qualification;
3267         gpa_t gpa;
3268         int gla_validity;
3269
3270         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3271
3272         if (exit_qualification & (1 << 6)) {
3273                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3274                 return -EINVAL;
3275         }
3276
3277         gla_validity = (exit_qualification >> 7) & 0x3;
3278         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3279                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3280                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3281                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3282                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3283                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3284                         (long unsigned int)exit_qualification);
3285                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3286                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3287                 return 0;
3288         }
3289
3290         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3291         trace_kvm_page_fault(gpa, exit_qualification);
3292         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3293 }
3294
3295 static u64 ept_rsvd_mask(u64 spte, int level)
3296 {
3297         int i;
3298         u64 mask = 0;
3299
3300         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3301                 mask |= (1ULL << i);
3302
3303         if (level > 2)
3304                 /* bits 7:3 reserved */
3305                 mask |= 0xf8;
3306         else if (level == 2) {
3307                 if (spte & (1ULL << 7))
3308                         /* 2MB ref, bits 20:12 reserved */
3309                         mask |= 0x1ff000;
3310                 else
3311                         /* bits 6:3 reserved */
3312                         mask |= 0x78;
3313         }
3314
3315         return mask;
3316 }
3317
3318 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3319                                        int level)
3320 {
3321         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3322
3323         /* 010b (write-only) */
3324         WARN_ON((spte & 0x7) == 0x2);
3325
3326         /* 110b (write/execute) */
3327         WARN_ON((spte & 0x7) == 0x6);
3328
3329         /* 100b (execute-only) and value not supported by logical processor */
3330         if (!cpu_has_vmx_ept_execute_only())
3331                 WARN_ON((spte & 0x7) == 0x4);
3332
3333         /* not 000b */
3334         if ((spte & 0x7)) {
3335                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3336
3337                 if (rsvd_bits != 0) {
3338                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3339                                          __func__, rsvd_bits);
3340                         WARN_ON(1);
3341                 }
3342
3343                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3344                         u64 ept_mem_type = (spte & 0x38) >> 3;
3345
3346                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3347                             ept_mem_type == 7) {
3348                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3349                                                 __func__, ept_mem_type);
3350                                 WARN_ON(1);
3351                         }
3352                 }
3353         }
3354 }
3355
3356 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3357 {
3358         u64 sptes[4];
3359         int nr_sptes, i;
3360         gpa_t gpa;
3361
3362         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3363
3364         printk(KERN_ERR "EPT: Misconfiguration.\n");
3365         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3366
3367         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3368
3369         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3370                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3371
3372         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3373         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3374
3375         return 0;
3376 }
3377
3378 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3379 {
3380         u32 cpu_based_vm_exec_control;
3381
3382         /* clear pending NMI */
3383         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3384         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3385         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3386         ++vcpu->stat.nmi_window_exits;
3387
3388         return 1;
3389 }
3390
3391 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3392 {
3393         struct vcpu_vmx *vmx = to_vmx(vcpu);
3394         enum emulation_result err = EMULATE_DONE;
3395         int ret = 1;
3396
3397         while (!guest_state_valid(vcpu)) {
3398                 err = emulate_instruction(vcpu, 0, 0, 0);
3399
3400                 if (err == EMULATE_DO_MMIO) {
3401                         ret = 0;
3402                         goto out;
3403                 }
3404
3405                 if (err != EMULATE_DONE) {
3406                         kvm_report_emulation_failure(vcpu, "emulation failure");
3407                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3408                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3409                         vcpu->run->internal.ndata = 0;
3410                         ret = 0;
3411                         goto out;
3412                 }
3413
3414                 if (signal_pending(current))
3415                         goto out;
3416                 if (need_resched())
3417                         schedule();
3418         }
3419
3420         vmx->emulation_required = 0;
3421 out:
3422         return ret;
3423 }
3424
3425 /*
3426  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3427  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3428  */
3429 static int handle_pause(struct kvm_vcpu *vcpu)
3430 {
3431         skip_emulated_instruction(vcpu);
3432         kvm_vcpu_on_spin(vcpu);
3433
3434         return 1;
3435 }
3436
3437 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3438 {
3439         kvm_queue_exception(vcpu, UD_VECTOR);
3440         return 1;
3441 }
3442
3443 /*
3444  * The exit handlers return 1 if the exit was handled fully and guest execution
3445  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3446  * to be done to userspace and return 0.
3447  */
3448 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3449         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3450         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3451         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3452         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3453         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3454         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3455         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3456         [EXIT_REASON_CPUID]                   = handle_cpuid,
3457         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3458         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3459         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3460         [EXIT_REASON_HLT]                     = handle_halt,
3461         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3462         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3463         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3464         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3465         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3466         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3467         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3468         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3469         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3470         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3471         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3472         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3473         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3474         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3475         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3476         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3477         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3478         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3479         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3480         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3481         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3482 };
3483
3484 static const int kvm_vmx_max_exit_handlers =
3485         ARRAY_SIZE(kvm_vmx_exit_handlers);
3486
3487 /*
3488  * The guest has exited.  See if we can fix it or if we need userspace
3489  * assistance.
3490  */
3491 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3492 {
3493         struct vcpu_vmx *vmx = to_vmx(vcpu);
3494         u32 exit_reason = vmx->exit_reason;
3495         u32 vectoring_info = vmx->idt_vectoring_info;
3496
3497         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3498
3499         /* If guest state is invalid, start emulating */
3500         if (vmx->emulation_required && emulate_invalid_guest_state)
3501                 return handle_invalid_guest_state(vcpu);
3502
3503         /* Access CR3 don't cause VMExit in paging mode, so we need
3504          * to sync with guest real CR3. */
3505         if (enable_ept && is_paging(vcpu))
3506                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3507
3508         if (unlikely(vmx->fail)) {
3509                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3510                 vcpu->run->fail_entry.hardware_entry_failure_reason
3511                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3512                 return 0;
3513         }
3514
3515         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3516                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3517                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3518                         exit_reason != EXIT_REASON_TASK_SWITCH))
3519                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3520                        "(0x%x) and exit reason is 0x%x\n",
3521                        __func__, vectoring_info, exit_reason);
3522
3523         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3524                 if (vmx_interrupt_allowed(vcpu)) {
3525                         vmx->soft_vnmi_blocked = 0;
3526                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3527                            vcpu->arch.nmi_pending) {
3528                         /*
3529                          * This CPU don't support us in finding the end of an
3530                          * NMI-blocked window if the guest runs with IRQs
3531                          * disabled. So we pull the trigger after 1 s of
3532                          * futile waiting, but inform the user about this.
3533                          */
3534                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3535                                "state on VCPU %d after 1 s timeout\n",
3536                                __func__, vcpu->vcpu_id);
3537                         vmx->soft_vnmi_blocked = 0;
3538                 }
3539         }
3540
3541         if (exit_reason < kvm_vmx_max_exit_handlers
3542             && kvm_vmx_exit_handlers[exit_reason])
3543                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3544         else {
3545                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3546                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3547         }
3548         return 0;
3549 }
3550
3551 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3552 {
3553         if (irr == -1 || tpr < irr) {
3554                 vmcs_write32(TPR_THRESHOLD, 0);
3555                 return;
3556         }
3557
3558         vmcs_write32(TPR_THRESHOLD, irr);
3559 }
3560
3561 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3562 {
3563         u32 exit_intr_info;
3564         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3565         bool unblock_nmi;
3566         u8 vector;
3567         int type;
3568         bool idtv_info_valid;
3569
3570         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3571
3572         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3573
3574         /* Handle machine checks before interrupts are enabled */
3575         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3576             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3577                 && is_machine_check(exit_intr_info)))
3578                 kvm_machine_check();
3579
3580         /* We need to handle NMIs before interrupts are enabled */
3581         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3582             (exit_intr_info & INTR_INFO_VALID_MASK))
3583                 asm("int $2");
3584
3585         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3586
3587         if (cpu_has_virtual_nmis()) {
3588                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3589                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3590                 /*
3591                  * SDM 3: 27.7.1.2 (September 2008)
3592                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3593                  * a guest IRET fault.
3594                  * SDM 3: 23.2.2 (September 2008)
3595                  * Bit 12 is undefined in any of the following cases:
3596                  *  If the VM exit sets the valid bit in the IDT-vectoring
3597                  *   information field.
3598                  *  If the VM exit is due to a double fault.
3599                  */
3600                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3601                     vector != DF_VECTOR && !idtv_info_valid)
3602                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3603                                       GUEST_INTR_STATE_NMI);
3604         } else if (unlikely(vmx->soft_vnmi_blocked))
3605                 vmx->vnmi_blocked_time +=
3606                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3607
3608         vmx->vcpu.arch.nmi_injected = false;
3609         kvm_clear_exception_queue(&vmx->vcpu);
3610         kvm_clear_interrupt_queue(&vmx->vcpu);
3611
3612         if (!idtv_info_valid)
3613                 return;
3614
3615         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3616         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3617
3618         switch (type) {
3619         case INTR_TYPE_NMI_INTR:
3620                 vmx->vcpu.arch.nmi_injected = true;
3621                 /*
3622                  * SDM 3: 27.7.1.2 (September 2008)
3623                  * Clear bit "block by NMI" before VM entry if a NMI
3624                  * delivery faulted.
3625                  */
3626                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3627                                 GUEST_INTR_STATE_NMI);
3628                 break;
3629         case INTR_TYPE_SOFT_EXCEPTION:
3630                 vmx->vcpu.arch.event_exit_inst_len =
3631                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3632                 /* fall through */
3633         case INTR_TYPE_HARD_EXCEPTION:
3634                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3635                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3636                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3637                 } else
3638                         kvm_queue_exception(&vmx->vcpu, vector);
3639                 break;
3640         case INTR_TYPE_SOFT_INTR:
3641                 vmx->vcpu.arch.event_exit_inst_len =
3642                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3643                 /* fall through */
3644         case INTR_TYPE_EXT_INTR:
3645                 kvm_queue_interrupt(&vmx->vcpu, vector,
3646                         type == INTR_TYPE_SOFT_INTR);
3647                 break;
3648         default:
3649                 break;
3650         }
3651 }
3652
3653 /*
3654  * Failure to inject an interrupt should give us the information
3655  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3656  * when fetching the interrupt redirection bitmap in the real-mode
3657  * tss, this doesn't happen.  So we do it ourselves.
3658  */
3659 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3660 {
3661         vmx->rmode.irq.pending = 0;
3662         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3663                 return;
3664         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3665         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3666                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3667                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3668                 return;
3669         }
3670         vmx->idt_vectoring_info =
3671                 VECTORING_INFO_VALID_MASK
3672                 | INTR_TYPE_EXT_INTR
3673                 | vmx->rmode.irq.vector;
3674 }
3675
3676 #ifdef CONFIG_X86_64
3677 #define R "r"
3678 #define Q "q"
3679 #else
3680 #define R "e"
3681 #define Q "l"
3682 #endif
3683
3684 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3685 {
3686         struct vcpu_vmx *vmx = to_vmx(vcpu);
3687
3688         /* Record the guest's net vcpu time for enforced NMI injections. */
3689         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3690                 vmx->entry_time = ktime_get();
3691
3692         /* Don't enter VMX if guest state is invalid, let the exit handler
3693            start emulation until we arrive back to a valid state */
3694         if (vmx->emulation_required && emulate_invalid_guest_state)
3695                 return;
3696
3697         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3698                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3699         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3700                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3701
3702         /* When single-stepping over STI and MOV SS, we must clear the
3703          * corresponding interruptibility bits in the guest state. Otherwise
3704          * vmentry fails as it then expects bit 14 (BS) in pending debug
3705          * exceptions being set, but that's not correct for the guest debugging
3706          * case. */
3707         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3708                 vmx_set_interrupt_shadow(vcpu, 0);
3709
3710         /*
3711          * Loading guest fpu may have cleared host cr0.ts
3712          */
3713         vmcs_writel(HOST_CR0, read_cr0());
3714
3715         if (vcpu->arch.switch_db_regs)
3716                 set_debugreg(vcpu->arch.dr6, 6);
3717
3718         asm(
3719                 /* Store host registers */
3720                 "push %%"R"dx; push %%"R"bp;"
3721                 "push %%"R"cx \n\t"
3722                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3723                 "je 1f \n\t"
3724                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3725                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3726                 "1: \n\t"
3727                 /* Reload cr2 if changed */
3728                 "mov %c[cr2](%0), %%"R"ax \n\t"
3729                 "mov %%cr2, %%"R"dx \n\t"
3730                 "cmp %%"R"ax, %%"R"dx \n\t"
3731                 "je 2f \n\t"
3732                 "mov %%"R"ax, %%cr2 \n\t"
3733                 "2: \n\t"
3734                 /* Check if vmlaunch of vmresume is needed */
3735                 "cmpl $0, %c[launched](%0) \n\t"
3736                 /* Load guest registers.  Don't clobber flags. */
3737                 "mov %c[rax](%0), %%"R"ax \n\t"
3738                 "mov %c[rbx](%0), %%"R"bx \n\t"
3739                 "mov %c[rdx](%0), %%"R"dx \n\t"
3740                 "mov %c[rsi](%0), %%"R"si \n\t"
3741                 "mov %c[rdi](%0), %%"R"di \n\t"
3742                 "mov %c[rbp](%0), %%"R"bp \n\t"
3743 #ifdef CONFIG_X86_64
3744                 "mov %c[r8](%0),  %%r8  \n\t"
3745                 "mov %c[r9](%0),  %%r9  \n\t"
3746                 "mov %c[r10](%0), %%r10 \n\t"
3747                 "mov %c[r11](%0), %%r11 \n\t"
3748                 "mov %c[r12](%0), %%r12 \n\t"
3749                 "mov %c[r13](%0), %%r13 \n\t"
3750                 "mov %c[r14](%0), %%r14 \n\t"
3751                 "mov %c[r15](%0), %%r15 \n\t"
3752 #endif
3753                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3754
3755                 /* Enter guest mode */
3756                 "jne .Llaunched \n\t"
3757                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3758                 "jmp .Lkvm_vmx_return \n\t"
3759                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3760                 ".Lkvm_vmx_return: "
3761                 /* Save guest registers, load host registers, keep flags */
3762                 "xchg %0,     (%%"R"sp) \n\t"
3763                 "mov %%"R"ax, %c[rax](%0) \n\t"
3764                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3765                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3766                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3767                 "mov %%"R"si, %c[rsi](%0) \n\t"
3768                 "mov %%"R"di, %c[rdi](%0) \n\t"
3769                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3770 #ifdef CONFIG_X86_64
3771                 "mov %%r8,  %c[r8](%0) \n\t"
3772                 "mov %%r9,  %c[r9](%0) \n\t"
3773                 "mov %%r10, %c[r10](%0) \n\t"
3774                 "mov %%r11, %c[r11](%0) \n\t"
3775                 "mov %%r12, %c[r12](%0) \n\t"
3776                 "mov %%r13, %c[r13](%0) \n\t"
3777                 "mov %%r14, %c[r14](%0) \n\t"
3778                 "mov %%r15, %c[r15](%0) \n\t"
3779 #endif
3780                 "mov %%cr2, %%"R"ax   \n\t"
3781                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3782
3783                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3784                 "setbe %c[fail](%0) \n\t"
3785               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3786                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3787                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3788                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3789                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3790                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3791                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3792                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3793                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3794                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3795                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3796 #ifdef CONFIG_X86_64
3797                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3798                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3799                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3800                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3801                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3802                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3803                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3804                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3805 #endif
3806                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3807               : "cc", "memory"
3808                 , R"bx", R"di", R"si"
3809 #ifdef CONFIG_X86_64
3810                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3811 #endif
3812               );
3813
3814         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3815                                   | (1 << VCPU_EXREG_PDPTR));
3816         vcpu->arch.regs_dirty = 0;
3817
3818         if (vcpu->arch.switch_db_regs)
3819                 get_debugreg(vcpu->arch.dr6, 6);
3820
3821         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3822         if (vmx->rmode.irq.pending)
3823                 fixup_rmode_irq(vmx);
3824
3825         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3826         vmx->launched = 1;
3827
3828         vmx_complete_interrupts(vmx);
3829 }
3830
3831 #undef R
3832 #undef Q
3833
3834 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3835 {
3836         struct vcpu_vmx *vmx = to_vmx(vcpu);
3837
3838         if (vmx->vmcs) {
3839                 vcpu_clear(vmx);
3840                 free_vmcs(vmx->vmcs);
3841                 vmx->vmcs = NULL;
3842         }
3843 }
3844
3845 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3846 {
3847         struct vcpu_vmx *vmx = to_vmx(vcpu);
3848
3849         spin_lock(&vmx_vpid_lock);
3850         if (vmx->vpid != 0)
3851                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3852         spin_unlock(&vmx_vpid_lock);
3853         vmx_free_vmcs(vcpu);
3854         kfree(vmx->guest_msrs);
3855         kvm_vcpu_uninit(vcpu);
3856         kmem_cache_free(kvm_vcpu_cache, vmx);
3857 }
3858
3859 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3860 {
3861         int err;
3862         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3863         int cpu;
3864
3865         if (!vmx)
3866                 return ERR_PTR(-ENOMEM);
3867
3868         allocate_vpid(vmx);
3869
3870         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3871         if (err)
3872                 goto free_vcpu;
3873
3874         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3875         if (!vmx->guest_msrs) {
3876                 err = -ENOMEM;
3877                 goto uninit_vcpu;
3878         }
3879
3880         vmx->vmcs = alloc_vmcs();
3881         if (!vmx->vmcs)
3882                 goto free_msrs;
3883
3884         vmcs_clear(vmx->vmcs);
3885
3886         cpu = get_cpu();
3887         vmx_vcpu_load(&vmx->vcpu, cpu);
3888         err = vmx_vcpu_setup(vmx);
3889         vmx_vcpu_put(&vmx->vcpu);
3890         put_cpu();
3891         if (err)
3892                 goto free_vmcs;
3893         if (vm_need_virtualize_apic_accesses(kvm))
3894                 if (alloc_apic_access_page(kvm) != 0)
3895                         goto free_vmcs;
3896
3897         if (enable_ept) {
3898                 if (!kvm->arch.ept_identity_map_addr)
3899                         kvm->arch.ept_identity_map_addr =
3900                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3901                 if (alloc_identity_pagetable(kvm) != 0)
3902                         goto free_vmcs;
3903         }
3904
3905         return &vmx->vcpu;
3906
3907 free_vmcs:
3908         free_vmcs(vmx->vmcs);
3909 free_msrs:
3910         kfree(vmx->guest_msrs);
3911 uninit_vcpu:
3912         kvm_vcpu_uninit(&vmx->vcpu);
3913 free_vcpu:
3914         kmem_cache_free(kvm_vcpu_cache, vmx);
3915         return ERR_PTR(err);
3916 }
3917
3918 static void __init vmx_check_processor_compat(void *rtn)
3919 {
3920         struct vmcs_config vmcs_conf;
3921
3922         *(int *)rtn = 0;
3923         if (setup_vmcs_config(&vmcs_conf) < 0)
3924                 *(int *)rtn = -EIO;
3925         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3926                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3927                                 smp_processor_id());
3928                 *(int *)rtn = -EIO;
3929         }
3930 }
3931
3932 static int get_ept_level(void)
3933 {
3934         return VMX_EPT_DEFAULT_GAW + 1;
3935 }
3936
3937 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3938 {
3939         u64 ret;
3940
3941         /* For VT-d and EPT combination
3942          * 1. MMIO: always map as UC
3943          * 2. EPT with VT-d:
3944          *   a. VT-d without snooping control feature: can't guarantee the
3945          *      result, try to trust guest.
3946          *   b. VT-d with snooping control feature: snooping control feature of
3947          *      VT-d engine can guarantee the cache correctness. Just set it
3948          *      to WB to keep consistent with host. So the same as item 3.
3949          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3950          *    consistent with host MTRR
3951          */
3952         if (is_mmio)
3953                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3954         else if (vcpu->kvm->arch.iommu_domain &&
3955                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3956                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3957                       VMX_EPT_MT_EPTE_SHIFT;
3958         else
3959                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3960                         | VMX_EPT_IGMT_BIT;
3961
3962         return ret;
3963 }
3964
3965 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3966         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3967         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3968         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3969         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3970         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3971         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3972         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3973         { EXIT_REASON_CPUID,                   "cpuid" },
3974         { EXIT_REASON_MSR_READ,                "rdmsr" },
3975         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3976         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3977         { EXIT_REASON_HLT,                     "halt" },
3978         { EXIT_REASON_INVLPG,                  "invlpg" },
3979         { EXIT_REASON_VMCALL,                  "hypercall" },
3980         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3981         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3982         { EXIT_REASON_WBINVD,                  "wbinvd" },
3983         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3984         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3985         { -1, NULL }
3986 };
3987
3988 static bool vmx_gb_page_enable(void)
3989 {
3990         return false;
3991 }
3992
3993 static struct kvm_x86_ops vmx_x86_ops = {
3994         .cpu_has_kvm_support = cpu_has_kvm_support,
3995         .disabled_by_bios = vmx_disabled_by_bios,
3996         .hardware_setup = hardware_setup,
3997         .hardware_unsetup = hardware_unsetup,
3998         .check_processor_compatibility = vmx_check_processor_compat,
3999         .hardware_enable = hardware_enable,
4000         .hardware_disable = hardware_disable,
4001         .cpu_has_accelerated_tpr = report_flexpriority,
4002
4003         .vcpu_create = vmx_create_vcpu,
4004         .vcpu_free = vmx_free_vcpu,
4005         .vcpu_reset = vmx_vcpu_reset,
4006
4007         .prepare_guest_switch = vmx_save_host_state,
4008         .vcpu_load = vmx_vcpu_load,
4009         .vcpu_put = vmx_vcpu_put,
4010
4011         .set_guest_debug = set_guest_debug,
4012         .get_msr = vmx_get_msr,
4013         .set_msr = vmx_set_msr,
4014         .get_segment_base = vmx_get_segment_base,
4015         .get_segment = vmx_get_segment,
4016         .set_segment = vmx_set_segment,
4017         .get_cpl = vmx_get_cpl,
4018         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4019         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4020         .set_cr0 = vmx_set_cr0,
4021         .set_cr3 = vmx_set_cr3,
4022         .set_cr4 = vmx_set_cr4,
4023         .set_efer = vmx_set_efer,
4024         .get_idt = vmx_get_idt,
4025         .set_idt = vmx_set_idt,
4026         .get_gdt = vmx_get_gdt,
4027         .set_gdt = vmx_set_gdt,
4028         .cache_reg = vmx_cache_reg,
4029         .get_rflags = vmx_get_rflags,
4030         .set_rflags = vmx_set_rflags,
4031
4032         .tlb_flush = vmx_flush_tlb,
4033
4034         .run = vmx_vcpu_run,
4035         .handle_exit = vmx_handle_exit,
4036         .skip_emulated_instruction = skip_emulated_instruction,
4037         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4038         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4039         .patch_hypercall = vmx_patch_hypercall,
4040         .set_irq = vmx_inject_irq,
4041         .set_nmi = vmx_inject_nmi,
4042         .queue_exception = vmx_queue_exception,
4043         .interrupt_allowed = vmx_interrupt_allowed,
4044         .nmi_allowed = vmx_nmi_allowed,
4045         .get_nmi_mask = vmx_get_nmi_mask,
4046         .set_nmi_mask = vmx_set_nmi_mask,
4047         .enable_nmi_window = enable_nmi_window,
4048         .enable_irq_window = enable_irq_window,
4049         .update_cr8_intercept = update_cr8_intercept,
4050
4051         .set_tss_addr = vmx_set_tss_addr,
4052         .get_tdp_level = get_ept_level,
4053         .get_mt_mask = vmx_get_mt_mask,
4054
4055         .exit_reasons_str = vmx_exit_reasons_str,
4056         .gb_page_enable = vmx_gb_page_enable,
4057 };
4058
4059 static int __init vmx_init(void)
4060 {
4061         int r, i;
4062
4063         rdmsrl_safe(MSR_EFER, &host_efer);
4064
4065         for (i = 0; i < NR_VMX_MSR; ++i)
4066                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4067
4068         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4069         if (!vmx_io_bitmap_a)
4070                 return -ENOMEM;
4071
4072         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4073         if (!vmx_io_bitmap_b) {
4074                 r = -ENOMEM;
4075                 goto out;
4076         }
4077
4078         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4079         if (!vmx_msr_bitmap_legacy) {
4080                 r = -ENOMEM;
4081                 goto out1;
4082         }
4083
4084         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4085         if (!vmx_msr_bitmap_longmode) {
4086                 r = -ENOMEM;
4087                 goto out2;
4088         }
4089
4090         /*
4091          * Allow direct access to the PC debug port (it is often used for I/O
4092          * delays, but the vmexits simply slow things down).
4093          */
4094         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4095         clear_bit(0x80, vmx_io_bitmap_a);
4096
4097         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4098
4099         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4100         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4101
4102         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4103
4104         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4105         if (r)
4106                 goto out3;
4107
4108         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4109         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4110         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4111         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4112         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4113         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4114
4115         if (enable_ept) {
4116                 bypass_guest_pf = 0;
4117                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4118                         VMX_EPT_WRITABLE_MASK);
4119                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4120                                 VMX_EPT_EXECUTABLE_MASK);
4121                 kvm_enable_tdp();
4122         } else
4123                 kvm_disable_tdp();
4124
4125         if (bypass_guest_pf)
4126                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4127
4128         return 0;
4129
4130 out3:
4131         free_page((unsigned long)vmx_msr_bitmap_longmode);
4132 out2:
4133         free_page((unsigned long)vmx_msr_bitmap_legacy);
4134 out1:
4135         free_page((unsigned long)vmx_io_bitmap_b);
4136 out:
4137         free_page((unsigned long)vmx_io_bitmap_a);
4138         return r;
4139 }
4140
4141 static void __exit vmx_exit(void)
4142 {
4143         free_page((unsigned long)vmx_msr_bitmap_legacy);
4144         free_page((unsigned long)vmx_msr_bitmap_longmode);
4145         free_page((unsigned long)vmx_io_bitmap_b);
4146         free_page((unsigned long)vmx_io_bitmap_a);
4147
4148         kvm_exit();
4149 }
4150
4151 module_init(vmx_init)
4152 module_exit(vmx_exit)