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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  51
  52 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  53 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  54 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  55
  56 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  57
  58 static const u32 host_save_user_msrs[] = {
  59 #ifdef CONFIG_X86_64
  60         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  61         MSR_FS_BASE,
  62 #endif
  63         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  64 };
  65
  66 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  67
  68 struct kvm_vcpu;
  69
  70 struct nested_state {
  71         struct vmcb *hsave;
  72         u64 hsave_msr;
  73         u64 vmcb;
  74
  75         /* These are the merged vectors */
  76         u32 *msrpm;
  77
  78         /* gpa pointers to the real vectors */
  79         u64 vmcb_msrpm;
  80
  81         /* A VMEXIT is required but not yet emulated */
  82         bool exit_required;
  83
  84         /* cache for intercepts of the guest */
  85         u16 intercept_cr_read;
  86         u16 intercept_cr_write;
  87         u16 intercept_dr_read;
  88         u16 intercept_dr_write;
  89         u32 intercept_exceptions;
  90         u64 intercept;
  91
  92 };
  93
  94 struct vcpu_svm {
  95         struct kvm_vcpu vcpu;
  96         struct vmcb *vmcb;
  97         unsigned long vmcb_pa;
  98         struct svm_cpu_data *svm_data;
  99         uint64_t asid_generation;
 100         uint64_t sysenter_esp;
 101         uint64_t sysenter_eip;
 102
 103         u64 next_rip;
 104
 105         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 106         u64 host_gs_base;
 107
 108         u32 *msrpm;
 109
 110         struct nested_state nested;
 111
 112         bool nmi_singlestep;
 113 };
 114
 115 /* enable NPT for AMD64 and X86 with PAE */
 116 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 117 static bool npt_enabled = true;
 118 #else
 119 static bool npt_enabled = false;
 120 #endif
 121 static int npt = 1;
 122
 123 module_param(npt, int, S_IRUGO);
 124
 125 static int nested = 1;
 126 module_param(nested, int, S_IRUGO);
 127
 128 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 129 static void svm_complete_interrupts(struct vcpu_svm *svm);
 130
 131 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 132 static int nested_svm_intercept(struct vcpu_svm *svm);
 133 static int nested_svm_vmexit(struct vcpu_svm *svm);
 134 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 135                                       bool has_error_code, u32 error_code);
 136
 137 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 138 {
 139         return container_of(vcpu, struct vcpu_svm, vcpu);
 140 }
 141
 142 static inline bool is_nested(struct vcpu_svm *svm)
 143 {
 144         return svm->nested.vmcb;
 145 }
 146
 147 static inline void enable_gif(struct vcpu_svm *svm)
 148 {
 149         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 150 }
 151
 152 static inline void disable_gif(struct vcpu_svm *svm)
 153 {
 154         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 155 }
 156
 157 static inline bool gif_set(struct vcpu_svm *svm)
 158 {
 159         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 160 }
 161
 162 static unsigned long iopm_base;
 163
 164 struct kvm_ldttss_desc {
 165         u16 limit0;
 166         u16 base0;
 167         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 168         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 169         u32 base3;
 170         u32 zero1;
 171 } __attribute__((packed));
 172
 173 struct svm_cpu_data {
 174         int cpu;
 175
 176         u64 asid_generation;
 177         u32 max_asid;
 178         u32 next_asid;
 179         struct kvm_ldttss_desc *tss_desc;
 180
 181         struct page *save_area;
 182 };
 183
 184 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 185 static uint32_t svm_features;
 186
 187 struct svm_init_data {
 188         int cpu;
 189         int r;
 190 };
 191
 192 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 193
 194 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 195 #define MSRS_RANGE_SIZE 2048
 196 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 197
 198 #define MAX_INST_SIZE 15
 199
 200 static inline u32 svm_has(u32 feat)
 201 {
 202         return svm_features & feat;
 203 }
 204
 205 static inline void clgi(void)
 206 {
 207         asm volatile (__ex(SVM_CLGI));
 208 }
 209
 210 static inline void stgi(void)
 211 {
 212         asm volatile (__ex(SVM_STGI));
 213 }
 214
 215 static inline void invlpga(unsigned long addr, u32 asid)
 216 {
 217         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 218 }
 219
 220 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 221 {
 222         to_svm(vcpu)->asid_generation--;
 223 }
 224
 225 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 226 {
 227         force_new_asid(vcpu);
 228 }
 229
 230 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 231 {
 232         if (!npt_enabled && !(efer & EFER_LMA))
 233                 efer &= ~EFER_LME;
 234
 235         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 236         vcpu->arch.efer = efer;
 237 }
 238
 239 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 240                                 bool has_error_code, u32 error_code)
 241 {
 242         struct vcpu_svm *svm = to_svm(vcpu);
 243
 244         /* If we are within a nested VM we'd better #VMEXIT and let the
 245            guest handle the exception */
 246         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 247                 return;
 248
 249         svm->vmcb->control.event_inj = nr
 250                 | SVM_EVTINJ_VALID
 251                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 252                 | SVM_EVTINJ_TYPE_EXEPT;
 253         svm->vmcb->control.event_inj_err = error_code;
 254 }
 255
 256 static int is_external_interrupt(u32 info)
 257 {
 258         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 259         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 260 }
 261
 262 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 263 {
 264         struct vcpu_svm *svm = to_svm(vcpu);
 265         u32 ret = 0;
 266
 267         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 268                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 269         return ret & mask;
 270 }
 271
 272 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 273 {
 274         struct vcpu_svm *svm = to_svm(vcpu);
 275
 276         if (mask == 0)
 277                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 278         else
 279                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 280
 281 }
 282
 283 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 284 {
 285         struct vcpu_svm *svm = to_svm(vcpu);
 286
 287         if (!svm->next_rip) {
 288                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 289                                 EMULATE_DONE)
 290                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 291                 return;
 292         }
 293         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 294                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 295                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 296
 297         kvm_rip_write(vcpu, svm->next_rip);
 298         svm_set_interrupt_shadow(vcpu, 0);
 299 }
 300
 301 static int has_svm(void)
 302 {
 303         const char *msg;
 304
 305         if (!cpu_has_svm(&msg)) {
 306                 printk(KERN_INFO "has_svm: %s\n", msg);
 307                 return 0;
 308         }
 309
 310         return 1;
 311 }
 312
 313 static void svm_hardware_disable(void *garbage)
 314 {
 315         cpu_svm_disable();
 316 }
 317
 318 static int svm_hardware_enable(void *garbage)
 319 {
 320
 321         struct svm_cpu_data *sd;
 322         uint64_t efer;
 323         struct desc_ptr gdt_descr;
 324         struct desc_struct *gdt;
 325         int me = raw_smp_processor_id();
 326
 327         rdmsrl(MSR_EFER, efer);
 328         if (efer & EFER_SVME)
 329                 return -EBUSY;
 330
 331         if (!has_svm()) {
 332                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 333                        me);
 334                 return -EINVAL;
 335         }
 336         sd = per_cpu(svm_data, me);
 337
 338         if (!sd) {
 339                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 340                        me);
 341                 return -EINVAL;
 342         }
 343
 344         sd->asid_generation = 1;
 345         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 346         sd->next_asid = sd->max_asid + 1;
 347
 348         kvm_get_gdt(&gdt_descr);
 349         gdt = (struct desc_struct *)gdt_descr.address;
 350         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 351
 352         wrmsrl(MSR_EFER, efer | EFER_SVME);
 353
 354         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 355
 356         return 0;
 357 }
 358
 359 static void svm_cpu_uninit(int cpu)
 360 {
 361         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 362
 363         if (!sd)
 364                 return;
 365
 366         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 367         __free_page(sd->save_area);
 368         kfree(sd);
 369 }
 370
 371 static int svm_cpu_init(int cpu)
 372 {
 373         struct svm_cpu_data *sd;
 374         int r;
 375
 376         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 377         if (!sd)
 378                 return -ENOMEM;
 379         sd->cpu = cpu;
 380         sd->save_area = alloc_page(GFP_KERNEL);
 381         r = -ENOMEM;
 382         if (!sd->save_area)
 383                 goto err_1;
 384
 385         per_cpu(svm_data, cpu) = sd;
 386
 387         return 0;
 388
 389 err_1:
 390         kfree(sd);
 391         return r;
 392
 393 }
 394
 395 static void set_msr_interception(u32 *msrpm, unsigned msr,
 396                                  int read, int write)
 397 {
 398         int i;
 399
 400         for (i = 0; i < NUM_MSR_MAPS; i++) {
 401                 if (msr >= msrpm_ranges[i] &&
 402                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 403                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 404                                           msrpm_ranges[i]) * 2;
 405
 406                         u32 *base = msrpm + (msr_offset / 32);
 407                         u32 msr_shift = msr_offset % 32;
 408                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 409                         *base = (*base & ~(0x3 << msr_shift)) |
 410                                 (mask << msr_shift);
 411                         return;
 412                 }
 413         }
 414         BUG();
 415 }
 416
 417 static void svm_vcpu_init_msrpm(u32 *msrpm)
 418 {
 419         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 420
 421 #ifdef CONFIG_X86_64
 422         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 423         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 424         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 425         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 426         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 427         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 428 #endif
 429         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 430         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 431 }
 432
 433 static void svm_enable_lbrv(struct vcpu_svm *svm)
 434 {
 435         u32 *msrpm = svm->msrpm;
 436
 437         svm->vmcb->control.lbr_ctl = 1;
 438         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 439         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 440         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 441         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 442 }
 443
 444 static void svm_disable_lbrv(struct vcpu_svm *svm)
 445 {
 446         u32 *msrpm = svm->msrpm;
 447
 448         svm->vmcb->control.lbr_ctl = 0;
 449         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 450         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 451         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 452         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 453 }
 454
 455 static __init int svm_hardware_setup(void)
 456 {
 457         int cpu;
 458         struct page *iopm_pages;
 459         void *iopm_va;
 460         int r;
 461
 462         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 463
 464         if (!iopm_pages)
 465                 return -ENOMEM;
 466
 467         iopm_va = page_address(iopm_pages);
 468         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 469         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 470
 471         if (boot_cpu_has(X86_FEATURE_NX))
 472                 kvm_enable_efer_bits(EFER_NX);
 473
 474         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 475                 kvm_enable_efer_bits(EFER_FFXSR);
 476
 477         if (nested) {
 478                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 479                 kvm_enable_efer_bits(EFER_SVME);
 480         }
 481
 482         for_each_possible_cpu(cpu) {
 483                 r = svm_cpu_init(cpu);
 484                 if (r)
 485                         goto err;
 486         }
 487
 488         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 489
 490         if (!svm_has(SVM_FEATURE_NPT))
 491                 npt_enabled = false;
 492
 493         if (npt_enabled && !npt) {
 494                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 495                 npt_enabled = false;
 496         }
 497
 498         if (npt_enabled) {
 499                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 500                 kvm_enable_tdp();
 501         } else
 502                 kvm_disable_tdp();
 503
 504         return 0;
 505
 506 err:
 507         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 508         iopm_base = 0;
 509         return r;
 510 }
 511
 512 static __exit void svm_hardware_unsetup(void)
 513 {
 514         int cpu;
 515
 516         for_each_possible_cpu(cpu)
 517                 svm_cpu_uninit(cpu);
 518
 519         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 520         iopm_base = 0;
 521 }
 522
 523 static void init_seg(struct vmcb_seg *seg)
 524 {
 525         seg->selector = 0;
 526         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 527                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 528         seg->limit = 0xffff;
 529         seg->base = 0;
 530 }
 531
 532 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 533 {
 534         seg->selector = 0;
 535         seg->attrib = SVM_SELECTOR_P_MASK | type;
 536         seg->limit = 0xffff;
 537         seg->base = 0;
 538 }
 539
 540 static void init_vmcb(struct vcpu_svm *svm)
 541 {
 542         struct vmcb_control_area *control = &svm->vmcb->control;
 543         struct vmcb_save_area *save = &svm->vmcb->save;
 544
 545         svm->vcpu.fpu_active = 1;
 546
 547         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 548                                         INTERCEPT_CR3_MASK |
 549                                         INTERCEPT_CR4_MASK;
 550
 551         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 552                                         INTERCEPT_CR3_MASK |
 553                                         INTERCEPT_CR4_MASK |
 554                                         INTERCEPT_CR8_MASK;
 555
 556         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 557                                         INTERCEPT_DR1_MASK |
 558                                         INTERCEPT_DR2_MASK |
 559                                         INTERCEPT_DR3_MASK |
 560                                         INTERCEPT_DR4_MASK |
 561                                         INTERCEPT_DR5_MASK |
 562                                         INTERCEPT_DR6_MASK |
 563                                         INTERCEPT_DR7_MASK;
 564
 565         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 566                                         INTERCEPT_DR1_MASK |
 567                                         INTERCEPT_DR2_MASK |
 568                                         INTERCEPT_DR3_MASK |
 569                                         INTERCEPT_DR4_MASK |
 570                                         INTERCEPT_DR5_MASK |
 571                                         INTERCEPT_DR6_MASK |
 572                                         INTERCEPT_DR7_MASK;
 573
 574         control->intercept_exceptions = (1 << PF_VECTOR) |
 575                                         (1 << UD_VECTOR) |
 576                                         (1 << MC_VECTOR);
 577
 578
 579         control->intercept =    (1ULL << INTERCEPT_INTR) |
 580                                 (1ULL << INTERCEPT_NMI) |
 581                                 (1ULL << INTERCEPT_SMI) |
 582                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 583                                 (1ULL << INTERCEPT_CPUID) |
 584                                 (1ULL << INTERCEPT_INVD) |
 585                                 (1ULL << INTERCEPT_HLT) |
 586                                 (1ULL << INTERCEPT_INVLPG) |
 587                                 (1ULL << INTERCEPT_INVLPGA) |
 588                                 (1ULL << INTERCEPT_IOIO_PROT) |
 589                                 (1ULL << INTERCEPT_MSR_PROT) |
 590                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 591                                 (1ULL << INTERCEPT_SHUTDOWN) |
 592                                 (1ULL << INTERCEPT_VMRUN) |
 593                                 (1ULL << INTERCEPT_VMMCALL) |
 594                                 (1ULL << INTERCEPT_VMLOAD) |
 595                                 (1ULL << INTERCEPT_VMSAVE) |
 596                                 (1ULL << INTERCEPT_STGI) |
 597                                 (1ULL << INTERCEPT_CLGI) |
 598                                 (1ULL << INTERCEPT_SKINIT) |
 599                                 (1ULL << INTERCEPT_WBINVD) |
 600                                 (1ULL << INTERCEPT_MONITOR) |
 601                                 (1ULL << INTERCEPT_MWAIT);
 602
 603         control->iopm_base_pa = iopm_base;
 604         control->msrpm_base_pa = __pa(svm->msrpm);
 605         control->tsc_offset = 0;
 606         control->int_ctl = V_INTR_MASKING_MASK;
 607
 608         init_seg(&save->es);
 609         init_seg(&save->ss);
 610         init_seg(&save->ds);
 611         init_seg(&save->fs);
 612         init_seg(&save->gs);
 613
 614         save->cs.selector = 0xf000;
 615         /* Executable/Readable Code Segment */
 616         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 617                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 618         save->cs.limit = 0xffff;
 619         /*
 620          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 621          * be consistent with it.
 622          *
 623          * Replace when we have real mode working for vmx.
 624          */
 625         save->cs.base = 0xf0000;
 626
 627         save->gdtr.limit = 0xffff;
 628         save->idtr.limit = 0xffff;
 629
 630         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 631         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 632
 633         save->efer = EFER_SVME;
 634         save->dr6 = 0xffff0ff0;
 635         save->dr7 = 0x400;
 636         save->rflags = 2;
 637         save->rip = 0x0000fff0;
 638         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 639
 640         /* This is the guest-visible cr0 value.
 641          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 642          */
 643         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 644         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 645
 646         save->cr4 = X86_CR4_PAE;
 647         /* rdx = ?? */
 648
 649         if (npt_enabled) {
 650                 /* Setup VMCB for Nested Paging */
 651                 control->nested_ctl = 1;
 652                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 653                                         (1ULL << INTERCEPT_INVLPG));
 654                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 655                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 656                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 657                 save->g_pat = 0x0007040600070406ULL;
 658                 save->cr3 = 0;
 659                 save->cr4 = 0;
 660         }
 661         force_new_asid(&svm->vcpu);
 662
 663         svm->nested.vmcb = 0;
 664         svm->vcpu.arch.hflags = 0;
 665
 666         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 667                 control->pause_filter_count = 3000;
 668                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 669         }
 670
 671         enable_gif(svm);
 672 }
 673
 674 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 675 {
 676         struct vcpu_svm *svm = to_svm(vcpu);
 677
 678         init_vmcb(svm);
 679
 680         if (!kvm_vcpu_is_bsp(vcpu)) {
 681                 kvm_rip_write(vcpu, 0);
 682                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 683                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 684         }
 685         vcpu->arch.regs_avail = ~0;
 686         vcpu->arch.regs_dirty = ~0;
 687
 688         return 0;
 689 }
 690
 691 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 692 {
 693         struct vcpu_svm *svm;
 694         struct page *page;
 695         struct page *msrpm_pages;
 696         struct page *hsave_page;
 697         struct page *nested_msrpm_pages;
 698         int err;
 699
 700         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 701         if (!svm) {
 702                 err = -ENOMEM;
 703                 goto out;
 704         }
 705
 706         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 707         if (err)
 708                 goto free_svm;
 709
 710         err = -ENOMEM;
 711         page = alloc_page(GFP_KERNEL);
 712         if (!page)
 713                 goto uninit;
 714
 715         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 716         if (!msrpm_pages)
 717                 goto free_page1;
 718
 719         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 720         if (!nested_msrpm_pages)
 721                 goto free_page2;
 722
 723         hsave_page = alloc_page(GFP_KERNEL);
 724         if (!hsave_page)
 725                 goto free_page3;
 726
 727         svm->nested.hsave = page_address(hsave_page);
 728
 729         svm->msrpm = page_address(msrpm_pages);
 730         svm_vcpu_init_msrpm(svm->msrpm);
 731
 732         svm->nested.msrpm = page_address(nested_msrpm_pages);
 733
 734         svm->vmcb = page_address(page);
 735         clear_page(svm->vmcb);
 736         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 737         svm->asid_generation = 0;
 738         init_vmcb(svm);
 739
 740         fx_init(&svm->vcpu);
 741         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 742         if (kvm_vcpu_is_bsp(&svm->vcpu))
 743                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 744
 745         return &svm->vcpu;
 746
 747 free_page3:
 748         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 749 free_page2:
 750         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 751 free_page1:
 752         __free_page(page);
 753 uninit:
 754         kvm_vcpu_uninit(&svm->vcpu);
 755 free_svm:
 756         kmem_cache_free(kvm_vcpu_cache, svm);
 757 out:
 758         return ERR_PTR(err);
 759 }
 760
 761 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764
 765         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 766         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 767         __free_page(virt_to_page(svm->nested.hsave));
 768         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 769         kvm_vcpu_uninit(vcpu);
 770         kmem_cache_free(kvm_vcpu_cache, svm);
 771 }
 772
 773 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 774 {
 775         struct vcpu_svm *svm = to_svm(vcpu);
 776         int i;
 777
 778         if (unlikely(cpu != vcpu->cpu)) {
 779                 u64 delta;
 780
 781                 if (check_tsc_unstable()) {
 782                         /*
 783                          * Make sure that the guest sees a monotonically
 784                          * increasing TSC.
 785                          */
 786                         delta = vcpu->arch.host_tsc - native_read_tsc();
 787                         svm->vmcb->control.tsc_offset += delta;
 788                         if (is_nested(svm))
 789                                 svm->nested.hsave->control.tsc_offset += delta;
 790                 }
 791                 vcpu->cpu = cpu;
 792                 kvm_migrate_timers(vcpu);
 793                 svm->asid_generation = 0;
 794         }
 795
 796         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 797                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 798 }
 799
 800 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 801 {
 802         struct vcpu_svm *svm = to_svm(vcpu);
 803         int i;
 804
 805         ++vcpu->stat.host_state_reload;
 806         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 807                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 808
 809         vcpu->arch.host_tsc = native_read_tsc();
 810 }
 811
 812 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 813 {
 814         return to_svm(vcpu)->vmcb->save.rflags;
 815 }
 816
 817 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 818 {
 819         to_svm(vcpu)->vmcb->save.rflags = rflags;
 820 }
 821
 822 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 823 {
 824         switch (reg) {
 825         case VCPU_EXREG_PDPTR:
 826                 BUG_ON(!npt_enabled);
 827                 load_pdptrs(vcpu, vcpu->arch.cr3);
 828                 break;
 829         default:
 830                 BUG();
 831         }
 832 }
 833
 834 static void svm_set_vintr(struct vcpu_svm *svm)
 835 {
 836         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 837 }
 838
 839 static void svm_clear_vintr(struct vcpu_svm *svm)
 840 {
 841         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 842 }
 843
 844 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 845 {
 846         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 847
 848         switch (seg) {
 849         case VCPU_SREG_CS: return &save->cs;
 850         case VCPU_SREG_DS: return &save->ds;
 851         case VCPU_SREG_ES: return &save->es;
 852         case VCPU_SREG_FS: return &save->fs;
 853         case VCPU_SREG_GS: return &save->gs;
 854         case VCPU_SREG_SS: return &save->ss;
 855         case VCPU_SREG_TR: return &save->tr;
 856         case VCPU_SREG_LDTR: return &save->ldtr;
 857         }
 858         BUG();
 859         return NULL;
 860 }
 861
 862 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 863 {
 864         struct vmcb_seg *s = svm_seg(vcpu, seg);
 865
 866         return s->base;
 867 }
 868
 869 static void svm_get_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg)
 871 {
 872         struct vmcb_seg *s = svm_seg(vcpu, seg);
 873
 874         var->base = s->base;
 875         var->limit = s->limit;
 876         var->selector = s->selector;
 877         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 878         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 879         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 880         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 881         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 882         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 883         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 884         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 885
 886         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 887          * for cross vendor migration purposes by "not present"
 888          */
 889         var->unusable = !var->present || (var->type == 0);
 890
 891         switch (seg) {
 892         case VCPU_SREG_CS:
 893                 /*
 894                  * SVM always stores 0 for the 'G' bit in the CS selector in
 895                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 896                  * Intel's VMENTRY has a check on the 'G' bit.
 897                  */
 898                 var->g = s->limit > 0xfffff;
 899                 break;
 900         case VCPU_SREG_TR:
 901                 /*
 902                  * Work around a bug where the busy flag in the tr selector
 903                  * isn't exposed
 904                  */
 905                 var->type |= 0x2;
 906                 break;
 907         case VCPU_SREG_DS:
 908         case VCPU_SREG_ES:
 909         case VCPU_SREG_FS:
 910         case VCPU_SREG_GS:
 911                 /*
 912                  * The accessed bit must always be set in the segment
 913                  * descriptor cache, although it can be cleared in the
 914                  * descriptor, the cached bit always remains at 1. Since
 915                  * Intel has a check on this, set it here to support
 916                  * cross-vendor migration.
 917                  */
 918                 if (!var->unusable)
 919                         var->type |= 0x1;
 920                 break;
 921         case VCPU_SREG_SS:
 922                 /* On AMD CPUs sometimes the DB bit in the segment
 923                  * descriptor is left as 1, although the whole segment has
 924                  * been made unusable. Clear it here to pass an Intel VMX
 925                  * entry check when cross vendor migrating.
 926                  */
 927                 if (var->unusable)
 928                         var->db = 0;
 929                 break;
 930         }
 931 }
 932
 933 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 934 {
 935         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 936
 937         return save->cpl;
 938 }
 939
 940 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 941 {
 942         struct vcpu_svm *svm = to_svm(vcpu);
 943
 944         dt->size = svm->vmcb->save.idtr.limit;
 945         dt->address = svm->vmcb->save.idtr.base;
 946 }
 947
 948 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 949 {
 950         struct vcpu_svm *svm = to_svm(vcpu);
 951
 952         svm->vmcb->save.idtr.limit = dt->size;
 953         svm->vmcb->save.idtr.base = dt->address ;
 954 }
 955
 956 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 957 {
 958         struct vcpu_svm *svm = to_svm(vcpu);
 959
 960         dt->size = svm->vmcb->save.gdtr.limit;
 961         dt->address = svm->vmcb->save.gdtr.base;
 962 }
 963
 964 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 965 {
 966         struct vcpu_svm *svm = to_svm(vcpu);
 967
 968         svm->vmcb->save.gdtr.limit = dt->size;
 969         svm->vmcb->save.gdtr.base = dt->address ;
 970 }
 971
 972 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 973 {
 974 }
 975
 976 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 977 {
 978 }
 979
 980 static void update_cr0_intercept(struct vcpu_svm *svm)
 981 {
 982         struct vmcb *vmcb = svm->vmcb;
 983         ulong gcr0 = svm->vcpu.arch.cr0;
 984         u64 *hcr0 = &svm->vmcb->save.cr0;
 985
 986         if (!svm->vcpu.fpu_active)
 987                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
 988         else
 989                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
 990                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
 991
 992
 993         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
 994                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
 995                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
 996                 if (is_nested(svm)) {
 997                         struct vmcb *hsave = svm->nested.hsave;
 998
 999                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1000                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1001                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1002                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1003                 }
1004         } else {
1005                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1006                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1007                 if (is_nested(svm)) {
1008                         struct vmcb *hsave = svm->nested.hsave;
1009
1010                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1011                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1012                 }
1013         }
1014 }
1015
1016 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1017 {
1018         struct vcpu_svm *svm = to_svm(vcpu);
1019
1020 #ifdef CONFIG_X86_64
1021         if (vcpu->arch.efer & EFER_LME) {
1022                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1023                         vcpu->arch.efer |= EFER_LMA;
1024                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1025                 }
1026
1027                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1028                         vcpu->arch.efer &= ~EFER_LMA;
1029                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1030                 }
1031         }
1032 #endif
1033         vcpu->arch.cr0 = cr0;
1034
1035         if (!npt_enabled)
1036                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1037
1038         if (!vcpu->fpu_active)
1039                 cr0 |= X86_CR0_TS;
1040         /*
1041          * re-enable caching here because the QEMU bios
1042          * does not do it - this results in some delay at
1043          * reboot
1044          */
1045         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1046         svm->vmcb->save.cr0 = cr0;
1047         update_cr0_intercept(svm);
1048 }
1049
1050 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1051 {
1052         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1053         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1054
1055         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1056                 force_new_asid(vcpu);
1057
1058         vcpu->arch.cr4 = cr4;
1059         if (!npt_enabled)
1060                 cr4 |= X86_CR4_PAE;
1061         cr4 |= host_cr4_mce;
1062         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1063 }
1064
1065 static void svm_set_segment(struct kvm_vcpu *vcpu,
1066                             struct kvm_segment *var, int seg)
1067 {
1068         struct vcpu_svm *svm = to_svm(vcpu);
1069         struct vmcb_seg *s = svm_seg(vcpu, seg);
1070
1071         s->base = var->base;
1072         s->limit = var->limit;
1073         s->selector = var->selector;
1074         if (var->unusable)
1075                 s->attrib = 0;
1076         else {
1077                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1078                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1079                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1080                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1081                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1082                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1083                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1084                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1085         }
1086         if (seg == VCPU_SREG_CS)
1087                 svm->vmcb->save.cpl
1088                         = (svm->vmcb->save.cs.attrib
1089                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1090
1091 }
1092
1093 static void update_db_intercept(struct kvm_vcpu *vcpu)
1094 {
1095         struct vcpu_svm *svm = to_svm(vcpu);
1096
1097         svm->vmcb->control.intercept_exceptions &=
1098                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1099
1100         if (svm->nmi_singlestep)
1101                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1102
1103         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1104                 if (vcpu->guest_debug &
1105                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1106                         svm->vmcb->control.intercept_exceptions |=
1107                                 1 << DB_VECTOR;
1108                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1109                         svm->vmcb->control.intercept_exceptions |=
1110                                 1 << BP_VECTOR;
1111         } else
1112                 vcpu->guest_debug = 0;
1113 }
1114
1115 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1116 {
1117         struct vcpu_svm *svm = to_svm(vcpu);
1118
1119         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1120                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1121         else
1122                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1123
1124         update_db_intercept(vcpu);
1125 }
1126
1127 static void load_host_msrs(struct kvm_vcpu *vcpu)
1128 {
1129 #ifdef CONFIG_X86_64
1130         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1131 #endif
1132 }
1133
1134 static void save_host_msrs(struct kvm_vcpu *vcpu)
1135 {
1136 #ifdef CONFIG_X86_64
1137         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1138 #endif
1139 }
1140
1141 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1142 {
1143         if (sd->next_asid > sd->max_asid) {
1144                 ++sd->asid_generation;
1145                 sd->next_asid = 1;
1146                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1147         }
1148
1149         svm->asid_generation = sd->asid_generation;
1150         svm->vmcb->control.asid = sd->next_asid++;
1151 }
1152
1153 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1154 {
1155         struct vcpu_svm *svm = to_svm(vcpu);
1156
1157         switch (dr) {
1158         case 0 ... 3:
1159                 *dest = vcpu->arch.db[dr];
1160                 break;
1161         case 4:
1162                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1163                         return EMULATE_FAIL; /* will re-inject UD */
1164                 /* fall through */
1165         case 6:
1166                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1167                         *dest = vcpu->arch.dr6;
1168                 else
1169                         *dest = svm->vmcb->save.dr6;
1170                 break;
1171         case 5:
1172                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1173                         return EMULATE_FAIL; /* will re-inject UD */
1174                 /* fall through */
1175         case 7:
1176                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1177                         *dest = vcpu->arch.dr7;
1178                 else
1179                         *dest = svm->vmcb->save.dr7;
1180                 break;
1181         }
1182
1183         return EMULATE_DONE;
1184 }
1185
1186 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1187 {
1188         struct vcpu_svm *svm = to_svm(vcpu);
1189
1190         switch (dr) {
1191         case 0 ... 3:
1192                 vcpu->arch.db[dr] = value;
1193                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1194                         vcpu->arch.eff_db[dr] = value;
1195                 break;
1196         case 4:
1197                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1198                         return EMULATE_FAIL; /* will re-inject UD */
1199                 /* fall through */
1200         case 6:
1201                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1202                 break;
1203         case 5:
1204                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1205                         return EMULATE_FAIL; /* will re-inject UD */
1206                 /* fall through */
1207         case 7:
1208                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1209                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1210                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1211                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1212                 }
1213                 break;
1214         }
1215
1216         return EMULATE_DONE;
1217 }
1218
1219 static int pf_interception(struct vcpu_svm *svm)
1220 {
1221         u64 fault_address;
1222         u32 error_code;
1223
1224         fault_address  = svm->vmcb->control.exit_info_2;
1225         error_code = svm->vmcb->control.exit_info_1;
1226
1227         trace_kvm_page_fault(fault_address, error_code);
1228         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1229                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1230         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1231 }
1232
1233 static int db_interception(struct vcpu_svm *svm)
1234 {
1235         struct kvm_run *kvm_run = svm->vcpu.run;
1236
1237         if (!(svm->vcpu.guest_debug &
1238               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1239                 !svm->nmi_singlestep) {
1240                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1241                 return 1;
1242         }
1243
1244         if (svm->nmi_singlestep) {
1245                 svm->nmi_singlestep = false;
1246                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1247                         svm->vmcb->save.rflags &=
1248                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1249                 update_db_intercept(&svm->vcpu);
1250         }
1251
1252         if (svm->vcpu.guest_debug &
1253             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1254                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1255                 kvm_run->debug.arch.pc =
1256                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1257                 kvm_run->debug.arch.exception = DB_VECTOR;
1258                 return 0;
1259         }
1260
1261         return 1;
1262 }
1263
1264 static int bp_interception(struct vcpu_svm *svm)
1265 {
1266         struct kvm_run *kvm_run = svm->vcpu.run;
1267
1268         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1269         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1270         kvm_run->debug.arch.exception = BP_VECTOR;
1271         return 0;
1272 }
1273
1274 static int ud_interception(struct vcpu_svm *svm)
1275 {
1276         int er;
1277
1278         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1279         if (er != EMULATE_DONE)
1280                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1281         return 1;
1282 }
1283
1284 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1285 {
1286         struct vcpu_svm *svm = to_svm(vcpu);
1287         u32 excp;
1288
1289         if (is_nested(svm)) {
1290                 u32 h_excp, n_excp;
1291
1292                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1293                 n_excp  = svm->nested.intercept_exceptions;
1294                 h_excp &= ~(1 << NM_VECTOR);
1295                 excp    = h_excp | n_excp;
1296         } else {
1297                 excp  = svm->vmcb->control.intercept_exceptions;
1298                 excp &= ~(1 << NM_VECTOR);
1299         }
1300
1301         svm->vmcb->control.intercept_exceptions = excp;
1302
1303         svm->vcpu.fpu_active = 1;
1304         update_cr0_intercept(svm);
1305 }
1306
1307 static int nm_interception(struct vcpu_svm *svm)
1308 {
1309         svm_fpu_activate(&svm->vcpu);
1310         return 1;
1311 }
1312
1313 static int mc_interception(struct vcpu_svm *svm)
1314 {
1315         /*
1316          * On an #MC intercept the MCE handler is not called automatically in
1317          * the host. So do it by hand here.
1318          */
1319         asm volatile (
1320                 "int $0x12\n");
1321         /* not sure if we ever come back to this point */
1322
1323         return 1;
1324 }
1325
1326 static int shutdown_interception(struct vcpu_svm *svm)
1327 {
1328         struct kvm_run *kvm_run = svm->vcpu.run;
1329
1330         /*
1331          * VMCB is undefined after a SHUTDOWN intercept
1332          * so reinitialize it.
1333          */
1334         clear_page(svm->vmcb);
1335         init_vmcb(svm);
1336
1337         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1338         return 0;
1339 }
1340
1341 static int io_interception(struct vcpu_svm *svm)
1342 {
1343         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1344         int size, in, string;
1345         unsigned port;
1346
1347         ++svm->vcpu.stat.io_exits;
1348
1349         svm->next_rip = svm->vmcb->control.exit_info_2;
1350
1351         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1352
1353         if (string) {
1354                 if (emulate_instruction(&svm->vcpu,
1355                                         0, 0, 0) == EMULATE_DO_MMIO)
1356                         return 0;
1357                 return 1;
1358         }
1359
1360         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1361         port = io_info >> 16;
1362         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1363
1364         skip_emulated_instruction(&svm->vcpu);
1365         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1366 }
1367
1368 static int nmi_interception(struct vcpu_svm *svm)
1369 {
1370         return 1;
1371 }
1372
1373 static int intr_interception(struct vcpu_svm *svm)
1374 {
1375         ++svm->vcpu.stat.irq_exits;
1376         return 1;
1377 }
1378
1379 static int nop_on_interception(struct vcpu_svm *svm)
1380 {
1381         return 1;
1382 }
1383
1384 static int halt_interception(struct vcpu_svm *svm)
1385 {
1386         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1387         skip_emulated_instruction(&svm->vcpu);
1388         return kvm_emulate_halt(&svm->vcpu);
1389 }
1390
1391 static int vmmcall_interception(struct vcpu_svm *svm)
1392 {
1393         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1394         skip_emulated_instruction(&svm->vcpu);
1395         kvm_emulate_hypercall(&svm->vcpu);
1396         return 1;
1397 }
1398
1399 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1400 {
1401         if (!(svm->vcpu.arch.efer & EFER_SVME)
1402             || !is_paging(&svm->vcpu)) {
1403                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1404                 return 1;
1405         }
1406
1407         if (svm->vmcb->save.cpl) {
1408                 kvm_inject_gp(&svm->vcpu, 0);
1409                 return 1;
1410         }
1411
1412        return 0;
1413 }
1414
1415 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1416                                       bool has_error_code, u32 error_code)
1417 {
1418         int vmexit;
1419
1420         if (!is_nested(svm))
1421                 return 0;
1422
1423         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1424         svm->vmcb->control.exit_code_hi = 0;
1425         svm->vmcb->control.exit_info_1 = error_code;
1426         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1427
1428         vmexit = nested_svm_intercept(svm);
1429         if (vmexit == NESTED_EXIT_DONE)
1430                 svm->nested.exit_required = true;
1431
1432         return vmexit;
1433 }
1434
1435 /* This function returns true if it is save to enable the irq window */
1436 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1437 {
1438         if (!is_nested(svm))
1439                 return true;
1440
1441         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1442                 return true;
1443
1444         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1445                 return false;
1446
1447         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1448
1449         if (svm->nested.intercept & 1ULL) {
1450                 /*
1451                  * The #vmexit can't be emulated here directly because this
1452                  * code path runs with irqs and preemtion disabled. A
1453                  * #vmexit emulation might sleep. Only signal request for
1454                  * the #vmexit here.
1455                  */
1456                 svm->nested.exit_required = true;
1457                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1458                 return false;
1459         }
1460
1461         return true;
1462 }
1463
1464 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1465 {
1466         struct page *page;
1467
1468         might_sleep();
1469
1470         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1471         if (is_error_page(page))
1472                 goto error;
1473
1474         *_page = page;
1475
1476         return kmap(page);
1477
1478 error:
1479         kvm_release_page_clean(page);
1480         kvm_inject_gp(&svm->vcpu, 0);
1481
1482         return NULL;
1483 }
1484
1485 static void nested_svm_unmap(struct page *page)
1486 {
1487         kunmap(page);
1488         kvm_release_page_dirty(page);
1489 }
1490
1491 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1492 {
1493         u32 param = svm->vmcb->control.exit_info_1 & 1;
1494         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1495         bool ret = false;
1496         u32 t0, t1;
1497         u8 val;
1498
1499         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1500                 return false;
1501
1502         switch (msr) {
1503         case 0 ... 0x1fff:
1504                 t0 = (msr * 2) % 8;
1505                 t1 = msr / 8;
1506                 break;
1507         case 0xc0000000 ... 0xc0001fff:
1508                 t0 = (8192 + msr - 0xc0000000) * 2;
1509                 t1 = (t0 / 8);
1510                 t0 %= 8;
1511                 break;
1512         case 0xc0010000 ... 0xc0011fff:
1513                 t0 = (16384 + msr - 0xc0010000) * 2;
1514                 t1 = (t0 / 8);
1515                 t0 %= 8;
1516                 break;
1517         default:
1518                 ret = true;
1519                 goto out;
1520         }
1521
1522         if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1523                 ret = val & ((1 << param) << t0);
1524
1525 out:
1526         return ret;
1527 }
1528
1529 static int nested_svm_exit_special(struct vcpu_svm *svm)
1530 {
1531         u32 exit_code = svm->vmcb->control.exit_code;
1532
1533         switch (exit_code) {
1534         case SVM_EXIT_INTR:
1535         case SVM_EXIT_NMI:
1536                 return NESTED_EXIT_HOST;
1537                 /* For now we are always handling NPFs when using them */
1538         case SVM_EXIT_NPF:
1539                 if (npt_enabled)
1540                         return NESTED_EXIT_HOST;
1541                 break;
1542         /* When we're shadowing, trap PFs */
1543         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1544                 if (!npt_enabled)
1545                         return NESTED_EXIT_HOST;
1546                 break;
1547         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1548                 nm_interception(svm);
1549                 break;
1550         default:
1551                 break;
1552         }
1553
1554         return NESTED_EXIT_CONTINUE;
1555 }
1556
1557 /*
1558  * If this function returns true, this #vmexit was already handled
1559  */
1560 static int nested_svm_intercept(struct vcpu_svm *svm)
1561 {
1562         u32 exit_code = svm->vmcb->control.exit_code;
1563         int vmexit = NESTED_EXIT_HOST;
1564
1565         switch (exit_code) {
1566         case SVM_EXIT_MSR:
1567                 vmexit = nested_svm_exit_handled_msr(svm);
1568                 break;
1569         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1570                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1571                 if (svm->nested.intercept_cr_read & cr_bits)
1572                         vmexit = NESTED_EXIT_DONE;
1573                 break;
1574         }
1575         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1576                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1577                 if (svm->nested.intercept_cr_write & cr_bits)
1578                         vmexit = NESTED_EXIT_DONE;
1579                 break;
1580         }
1581         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1582                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1583                 if (svm->nested.intercept_dr_read & dr_bits)
1584                         vmexit = NESTED_EXIT_DONE;
1585                 break;
1586         }
1587         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1588                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1589                 if (svm->nested.intercept_dr_write & dr_bits)
1590                         vmexit = NESTED_EXIT_DONE;
1591                 break;
1592         }
1593         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1594                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1595                 if (svm->nested.intercept_exceptions & excp_bits)
1596                         vmexit = NESTED_EXIT_DONE;
1597                 break;
1598         }
1599         default: {
1600                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1601                 if (svm->nested.intercept & exit_bits)
1602                         vmexit = NESTED_EXIT_DONE;
1603         }
1604         }
1605
1606         return vmexit;
1607 }
1608
1609 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1610 {
1611         int vmexit;
1612
1613         vmexit = nested_svm_intercept(svm);
1614
1615         if (vmexit == NESTED_EXIT_DONE)
1616                 nested_svm_vmexit(svm);
1617
1618         return vmexit;
1619 }
1620
1621 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1622 {
1623         struct vmcb_control_area *dst  = &dst_vmcb->control;
1624         struct vmcb_control_area *from = &from_vmcb->control;
1625
1626         dst->intercept_cr_read    = from->intercept_cr_read;
1627         dst->intercept_cr_write   = from->intercept_cr_write;
1628         dst->intercept_dr_read    = from->intercept_dr_read;
1629         dst->intercept_dr_write   = from->intercept_dr_write;
1630         dst->intercept_exceptions = from->intercept_exceptions;
1631         dst->intercept            = from->intercept;
1632         dst->iopm_base_pa         = from->iopm_base_pa;
1633         dst->msrpm_base_pa        = from->msrpm_base_pa;
1634         dst->tsc_offset           = from->tsc_offset;
1635         dst->asid                 = from->asid;
1636         dst->tlb_ctl              = from->tlb_ctl;
1637         dst->int_ctl              = from->int_ctl;
1638         dst->int_vector           = from->int_vector;
1639         dst->int_state            = from->int_state;
1640         dst->exit_code            = from->exit_code;
1641         dst->exit_code_hi         = from->exit_code_hi;
1642         dst->exit_info_1          = from->exit_info_1;
1643         dst->exit_info_2          = from->exit_info_2;
1644         dst->exit_int_info        = from->exit_int_info;
1645         dst->exit_int_info_err    = from->exit_int_info_err;
1646         dst->nested_ctl           = from->nested_ctl;
1647         dst->event_inj            = from->event_inj;
1648         dst->event_inj_err        = from->event_inj_err;
1649         dst->nested_cr3           = from->nested_cr3;
1650         dst->lbr_ctl              = from->lbr_ctl;
1651 }
1652
1653 static int nested_svm_vmexit(struct vcpu_svm *svm)
1654 {
1655         struct vmcb *nested_vmcb;
1656         struct vmcb *hsave = svm->nested.hsave;
1657         struct vmcb *vmcb = svm->vmcb;
1658         struct page *page;
1659
1660         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1661                                        vmcb->control.exit_info_1,
1662                                        vmcb->control.exit_info_2,
1663                                        vmcb->control.exit_int_info,
1664                                        vmcb->control.exit_int_info_err);
1665
1666         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1667         if (!nested_vmcb)
1668                 return 1;
1669
1670         /* Exit nested SVM mode */
1671         svm->nested.vmcb = 0;
1672
1673         /* Give the current vmcb to the guest */
1674         disable_gif(svm);
1675
1676         nested_vmcb->save.es     = vmcb->save.es;
1677         nested_vmcb->save.cs     = vmcb->save.cs;
1678         nested_vmcb->save.ss     = vmcb->save.ss;
1679         nested_vmcb->save.ds     = vmcb->save.ds;
1680         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1681         nested_vmcb->save.idtr   = vmcb->save.idtr;
1682         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1683         if (npt_enabled)
1684                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1685         else
1686                 nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1687         nested_vmcb->save.cr2    = vmcb->save.cr2;
1688         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1689         nested_vmcb->save.rflags = vmcb->save.rflags;
1690         nested_vmcb->save.rip    = vmcb->save.rip;
1691         nested_vmcb->save.rsp    = vmcb->save.rsp;
1692         nested_vmcb->save.rax    = vmcb->save.rax;
1693         nested_vmcb->save.dr7    = vmcb->save.dr7;
1694         nested_vmcb->save.dr6    = vmcb->save.dr6;
1695         nested_vmcb->save.cpl    = vmcb->save.cpl;
1696
1697         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1698         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1699         nested_vmcb->control.int_state         = vmcb->control.int_state;
1700         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1701         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1702         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1703         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1704         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1705         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1706
1707         /*
1708          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1709          * to make sure that we do not lose injected events. So check event_inj
1710          * here and copy it to exit_int_info if it is valid.
1711          * Exit_int_info and event_inj can't be both valid because the case
1712          * below only happens on a VMRUN instruction intercept which has
1713          * no valid exit_int_info set.
1714          */
1715         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1716                 struct vmcb_control_area *nc = &nested_vmcb->control;
1717
1718                 nc->exit_int_info     = vmcb->control.event_inj;
1719                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1720         }
1721
1722         nested_vmcb->control.tlb_ctl           = 0;
1723         nested_vmcb->control.event_inj         = 0;
1724         nested_vmcb->control.event_inj_err     = 0;
1725
1726         /* We always set V_INTR_MASKING and remember the old value in hflags */
1727         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1728                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1729
1730         /* Restore the original control entries */
1731         copy_vmcb_control_area(vmcb, hsave);
1732
1733         kvm_clear_exception_queue(&svm->vcpu);
1734         kvm_clear_interrupt_queue(&svm->vcpu);
1735
1736         /* Restore selected save entries */
1737         svm->vmcb->save.es = hsave->save.es;
1738         svm->vmcb->save.cs = hsave->save.cs;
1739         svm->vmcb->save.ss = hsave->save.ss;
1740         svm->vmcb->save.ds = hsave->save.ds;
1741         svm->vmcb->save.gdtr = hsave->save.gdtr;
1742         svm->vmcb->save.idtr = hsave->save.idtr;
1743         svm->vmcb->save.rflags = hsave->save.rflags;
1744         svm_set_efer(&svm->vcpu, hsave->save.efer);
1745         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1746         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1747         if (npt_enabled) {
1748                 svm->vmcb->save.cr3 = hsave->save.cr3;
1749                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1750         } else {
1751                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1752         }
1753         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1754         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1755         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1756         svm->vmcb->save.dr7 = 0;
1757         svm->vmcb->save.cpl = 0;
1758         svm->vmcb->control.exit_int_info = 0;
1759
1760         nested_svm_unmap(page);
1761
1762         kvm_mmu_reset_context(&svm->vcpu);
1763         kvm_mmu_load(&svm->vcpu);
1764
1765         return 0;
1766 }
1767
1768 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1769 {
1770         u32 *nested_msrpm;
1771         struct page *page;
1772         int i;
1773
1774         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
1775         if (!nested_msrpm)
1776                 return false;
1777
1778         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1779                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1780
1781         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1782
1783         nested_svm_unmap(page);
1784
1785         return true;
1786 }
1787
1788 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1789 {
1790         struct vmcb *nested_vmcb;
1791         struct vmcb *hsave = svm->nested.hsave;
1792         struct vmcb *vmcb = svm->vmcb;
1793         struct page *page;
1794         u64 vmcb_gpa;
1795
1796         vmcb_gpa = svm->vmcb->save.rax;
1797
1798         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1799         if (!nested_vmcb)
1800                 return false;
1801
1802         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1803                                nested_vmcb->save.rip,
1804                                nested_vmcb->control.int_ctl,
1805                                nested_vmcb->control.event_inj,
1806                                nested_vmcb->control.nested_ctl);
1807
1808         /* Clear internal status */
1809         kvm_clear_exception_queue(&svm->vcpu);
1810         kvm_clear_interrupt_queue(&svm->vcpu);
1811
1812         /* Save the old vmcb, so we don't need to pick what we save, but
1813            can restore everything when a VMEXIT occurs */
1814         hsave->save.es     = vmcb->save.es;
1815         hsave->save.cs     = vmcb->save.cs;
1816         hsave->save.ss     = vmcb->save.ss;
1817         hsave->save.ds     = vmcb->save.ds;
1818         hsave->save.gdtr   = vmcb->save.gdtr;
1819         hsave->save.idtr   = vmcb->save.idtr;
1820         hsave->save.efer   = svm->vcpu.arch.efer;
1821         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1822         hsave->save.cr4    = svm->vcpu.arch.cr4;
1823         hsave->save.rflags = vmcb->save.rflags;
1824         hsave->save.rip    = svm->next_rip;
1825         hsave->save.rsp    = vmcb->save.rsp;
1826         hsave->save.rax    = vmcb->save.rax;
1827         if (npt_enabled)
1828                 hsave->save.cr3    = vmcb->save.cr3;
1829         else
1830                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1831
1832         copy_vmcb_control_area(hsave, vmcb);
1833
1834         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1835                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1836         else
1837                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1838
1839         /* Load the nested guest state */
1840         svm->vmcb->save.es = nested_vmcb->save.es;
1841         svm->vmcb->save.cs = nested_vmcb->save.cs;
1842         svm->vmcb->save.ss = nested_vmcb->save.ss;
1843         svm->vmcb->save.ds = nested_vmcb->save.ds;
1844         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1845         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1846         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1847         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1848         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1849         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1850         if (npt_enabled) {
1851                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1852                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1853         } else {
1854                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1855                 kvm_mmu_reset_context(&svm->vcpu);
1856         }
1857         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1858         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1859         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1860         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1861         /* In case we don't even reach vcpu_run, the fields are not updated */
1862         svm->vmcb->save.rax = nested_vmcb->save.rax;
1863         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1864         svm->vmcb->save.rip = nested_vmcb->save.rip;
1865         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1866         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1867         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1868
1869         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1870
1871         /* cache intercepts */
1872         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1873         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1874         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1875         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1876         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1877         svm->nested.intercept            = nested_vmcb->control.intercept;
1878
1879         force_new_asid(&svm->vcpu);
1880         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1881         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1882                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1883         else
1884                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1885
1886         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1887                 /* We only want the cr8 intercept bits of the guest */
1888                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1889                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1890         }
1891
1892         /* We don't want a nested guest to be more powerful than the guest,
1893            so all intercepts are ORed */
1894         svm->vmcb->control.intercept_cr_read |=
1895                 nested_vmcb->control.intercept_cr_read;
1896         svm->vmcb->control.intercept_cr_write |=
1897                 nested_vmcb->control.intercept_cr_write;
1898         svm->vmcb->control.intercept_dr_read |=
1899                 nested_vmcb->control.intercept_dr_read;
1900         svm->vmcb->control.intercept_dr_write |=
1901                 nested_vmcb->control.intercept_dr_write;
1902         svm->vmcb->control.intercept_exceptions |=
1903                 nested_vmcb->control.intercept_exceptions;
1904
1905         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1906
1907         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
1908         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1909         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1910         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1911         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1912         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1913
1914         nested_svm_unmap(page);
1915
1916         /* nested_vmcb is our indicator if nested SVM is activated */
1917         svm->nested.vmcb = vmcb_gpa;
1918
1919         enable_gif(svm);
1920
1921         return true;
1922 }
1923
1924 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1925 {
1926         to_vmcb->save.fs = from_vmcb->save.fs;
1927         to_vmcb->save.gs = from_vmcb->save.gs;
1928         to_vmcb->save.tr = from_vmcb->save.tr;
1929         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1930         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1931         to_vmcb->save.star = from_vmcb->save.star;
1932         to_vmcb->save.lstar = from_vmcb->save.lstar;
1933         to_vmcb->save.cstar = from_vmcb->save.cstar;
1934         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1935         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1936         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1937         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1938 }
1939
1940 static int vmload_interception(struct vcpu_svm *svm)
1941 {
1942         struct vmcb *nested_vmcb;
1943         struct page *page;
1944
1945         if (nested_svm_check_permissions(svm))
1946                 return 1;
1947
1948         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1949         skip_emulated_instruction(&svm->vcpu);
1950
1951         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1952         if (!nested_vmcb)
1953                 return 1;
1954
1955         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1956         nested_svm_unmap(page);
1957
1958         return 1;
1959 }
1960
1961 static int vmsave_interception(struct vcpu_svm *svm)
1962 {
1963         struct vmcb *nested_vmcb;
1964         struct page *page;
1965
1966         if (nested_svm_check_permissions(svm))
1967                 return 1;
1968
1969         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1970         skip_emulated_instruction(&svm->vcpu);
1971
1972         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1973         if (!nested_vmcb)
1974                 return 1;
1975
1976         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1977         nested_svm_unmap(page);
1978
1979         return 1;
1980 }
1981
1982 static int vmrun_interception(struct vcpu_svm *svm)
1983 {
1984         if (nested_svm_check_permissions(svm))
1985                 return 1;
1986
1987         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1988         skip_emulated_instruction(&svm->vcpu);
1989
1990         if (!nested_svm_vmrun(svm))
1991                 return 1;
1992
1993         if (!nested_svm_vmrun_msrpm(svm))
1994                 goto failed;
1995
1996         return 1;
1997
1998 failed:
1999
2000         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2001         svm->vmcb->control.exit_code_hi = 0;
2002         svm->vmcb->control.exit_info_1  = 0;
2003         svm->vmcb->control.exit_info_2  = 0;
2004
2005         nested_svm_vmexit(svm);
2006
2007         return 1;
2008 }
2009
2010 static int stgi_interception(struct vcpu_svm *svm)
2011 {
2012         if (nested_svm_check_permissions(svm))
2013                 return 1;
2014
2015         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2016         skip_emulated_instruction(&svm->vcpu);
2017
2018         enable_gif(svm);
2019
2020         return 1;
2021 }
2022
2023 static int clgi_interception(struct vcpu_svm *svm)
2024 {
2025         if (nested_svm_check_permissions(svm))
2026                 return 1;
2027
2028         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2029         skip_emulated_instruction(&svm->vcpu);
2030
2031         disable_gif(svm);
2032
2033         /* After a CLGI no interrupts should come */
2034         svm_clear_vintr(svm);
2035         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2036
2037         return 1;
2038 }
2039
2040 static int invlpga_interception(struct vcpu_svm *svm)
2041 {
2042         struct kvm_vcpu *vcpu = &svm->vcpu;
2043
2044         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2045                           vcpu->arch.regs[VCPU_REGS_RAX]);
2046
2047         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2048         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2049
2050         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2051         skip_emulated_instruction(&svm->vcpu);
2052         return 1;
2053 }
2054
2055 static int skinit_interception(struct vcpu_svm *svm)
2056 {
2057         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2058
2059         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2060         return 1;
2061 }
2062
2063 static int invalid_op_interception(struct vcpu_svm *svm)
2064 {
2065         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2066         return 1;
2067 }
2068
2069 static int task_switch_interception(struct vcpu_svm *svm)
2070 {
2071         u16 tss_selector;
2072         int reason;
2073         int int_type = svm->vmcb->control.exit_int_info &
2074                 SVM_EXITINTINFO_TYPE_MASK;
2075         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2076         uint32_t type =
2077                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2078         uint32_t idt_v =
2079                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2080
2081         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2082
2083         if (svm->vmcb->control.exit_info_2 &
2084             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2085                 reason = TASK_SWITCH_IRET;
2086         else if (svm->vmcb->control.exit_info_2 &
2087                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2088                 reason = TASK_SWITCH_JMP;
2089         else if (idt_v)
2090                 reason = TASK_SWITCH_GATE;
2091         else
2092                 reason = TASK_SWITCH_CALL;
2093
2094         if (reason == TASK_SWITCH_GATE) {
2095                 switch (type) {
2096                 case SVM_EXITINTINFO_TYPE_NMI:
2097                         svm->vcpu.arch.nmi_injected = false;
2098                         break;
2099                 case SVM_EXITINTINFO_TYPE_EXEPT:
2100                         kvm_clear_exception_queue(&svm->vcpu);
2101                         break;
2102                 case SVM_EXITINTINFO_TYPE_INTR:
2103                         kvm_clear_interrupt_queue(&svm->vcpu);
2104                         break;
2105                 default:
2106                         break;
2107                 }
2108         }
2109
2110         if (reason != TASK_SWITCH_GATE ||
2111             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2112             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2113              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2114                 skip_emulated_instruction(&svm->vcpu);
2115
2116         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2117 }
2118
2119 static int cpuid_interception(struct vcpu_svm *svm)
2120 {
2121         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2122         kvm_emulate_cpuid(&svm->vcpu);
2123         return 1;
2124 }
2125
2126 static int iret_interception(struct vcpu_svm *svm)
2127 {
2128         ++svm->vcpu.stat.nmi_window_exits;
2129         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2130         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2131         return 1;
2132 }
2133
2134 static int invlpg_interception(struct vcpu_svm *svm)
2135 {
2136         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2137                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2138         return 1;
2139 }
2140
2141 static int emulate_on_interception(struct vcpu_svm *svm)
2142 {
2143         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2144                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2145         return 1;
2146 }
2147
2148 static int cr8_write_interception(struct vcpu_svm *svm)
2149 {
2150         struct kvm_run *kvm_run = svm->vcpu.run;
2151
2152         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2153         /* instruction emulation calls kvm_set_cr8() */
2154         emulate_instruction(&svm->vcpu, 0, 0, 0);
2155         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2156                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2157                 return 1;
2158         }
2159         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2160                 return 1;
2161         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2162         return 0;
2163 }
2164
2165 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2166 {
2167         struct vcpu_svm *svm = to_svm(vcpu);
2168
2169         switch (ecx) {
2170         case MSR_IA32_TSC: {
2171                 u64 tsc_offset;
2172
2173                 if (is_nested(svm))
2174                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2175                 else
2176                         tsc_offset = svm->vmcb->control.tsc_offset;
2177
2178                 *data = tsc_offset + native_read_tsc();
2179                 break;
2180         }
2181         case MSR_K6_STAR:
2182                 *data = svm->vmcb->save.star;
2183                 break;
2184 #ifdef CONFIG_X86_64
2185         case MSR_LSTAR:
2186                 *data = svm->vmcb->save.lstar;
2187                 break;
2188         case MSR_CSTAR:
2189                 *data = svm->vmcb->save.cstar;
2190                 break;
2191         case MSR_KERNEL_GS_BASE:
2192                 *data = svm->vmcb->save.kernel_gs_base;
2193                 break;
2194         case MSR_SYSCALL_MASK:
2195                 *data = svm->vmcb->save.sfmask;
2196                 break;
2197 #endif
2198         case MSR_IA32_SYSENTER_CS:
2199                 *data = svm->vmcb->save.sysenter_cs;
2200                 break;
2201         case MSR_IA32_SYSENTER_EIP:
2202                 *data = svm->sysenter_eip;
2203                 break;
2204         case MSR_IA32_SYSENTER_ESP:
2205                 *data = svm->sysenter_esp;
2206                 break;
2207         /* Nobody will change the following 5 values in the VMCB so
2208            we can safely return them on rdmsr. They will always be 0
2209            until LBRV is implemented. */
2210         case MSR_IA32_DEBUGCTLMSR:
2211                 *data = svm->vmcb->save.dbgctl;
2212                 break;
2213         case MSR_IA32_LASTBRANCHFROMIP:
2214                 *data = svm->vmcb->save.br_from;
2215                 break;
2216         case MSR_IA32_LASTBRANCHTOIP:
2217                 *data = svm->vmcb->save.br_to;
2218                 break;
2219         case MSR_IA32_LASTINTFROMIP:
2220                 *data = svm->vmcb->save.last_excp_from;
2221                 break;
2222         case MSR_IA32_LASTINTTOIP:
2223                 *data = svm->vmcb->save.last_excp_to;
2224                 break;
2225         case MSR_VM_HSAVE_PA:
2226                 *data = svm->nested.hsave_msr;
2227                 break;
2228         case MSR_VM_CR:
2229                 *data = 0;
2230                 break;
2231         case MSR_IA32_UCODE_REV:
2232                 *data = 0x01000065;
2233                 break;
2234         default:
2235                 return kvm_get_msr_common(vcpu, ecx, data);
2236         }
2237         return 0;
2238 }
2239
2240 static int rdmsr_interception(struct vcpu_svm *svm)
2241 {
2242         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2243         u64 data;
2244
2245         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2246                 trace_kvm_msr_read_ex(ecx);
2247                 kvm_inject_gp(&svm->vcpu, 0);
2248         } else {
2249                 trace_kvm_msr_read(ecx, data);
2250
2251                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2252                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2253                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2254                 skip_emulated_instruction(&svm->vcpu);
2255         }
2256         return 1;
2257 }
2258
2259 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2260 {
2261         struct vcpu_svm *svm = to_svm(vcpu);
2262
2263         switch (ecx) {
2264         case MSR_IA32_TSC: {
2265                 u64 tsc_offset = data - native_read_tsc();
2266                 u64 g_tsc_offset = 0;
2267
2268                 if (is_nested(svm)) {
2269                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2270                                        svm->nested.hsave->control.tsc_offset;
2271                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2272                 }
2273
2274                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2275
2276                 break;
2277         }
2278         case MSR_K6_STAR:
2279                 svm->vmcb->save.star = data;
2280                 break;
2281 #ifdef CONFIG_X86_64
2282         case MSR_LSTAR:
2283                 svm->vmcb->save.lstar = data;
2284                 break;
2285         case MSR_CSTAR:
2286                 svm->vmcb->save.cstar = data;
2287                 break;
2288         case MSR_KERNEL_GS_BASE:
2289                 svm->vmcb->save.kernel_gs_base = data;
2290                 break;
2291         case MSR_SYSCALL_MASK:
2292                 svm->vmcb->save.sfmask = data;
2293                 break;
2294 #endif
2295         case MSR_IA32_SYSENTER_CS:
2296                 svm->vmcb->save.sysenter_cs = data;
2297                 break;
2298         case MSR_IA32_SYSENTER_EIP:
2299                 svm->sysenter_eip = data;
2300                 svm->vmcb->save.sysenter_eip = data;
2301                 break;
2302         case MSR_IA32_SYSENTER_ESP:
2303                 svm->sysenter_esp = data;
2304                 svm->vmcb->save.sysenter_esp = data;
2305                 break;
2306         case MSR_IA32_DEBUGCTLMSR:
2307                 if (!svm_has(SVM_FEATURE_LBRV)) {
2308                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2309                                         __func__, data);
2310                         break;
2311                 }
2312                 if (data & DEBUGCTL_RESERVED_BITS)
2313                         return 1;
2314
2315                 svm->vmcb->save.dbgctl = data;
2316                 if (data & (1ULL<<0))
2317                         svm_enable_lbrv(svm);
2318                 else
2319                         svm_disable_lbrv(svm);
2320                 break;
2321         case MSR_VM_HSAVE_PA:
2322                 svm->nested.hsave_msr = data;
2323                 break;
2324         case MSR_VM_CR:
2325         case MSR_VM_IGNNE:
2326                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2327                 break;
2328         default:
2329                 return kvm_set_msr_common(vcpu, ecx, data);
2330         }
2331         return 0;
2332 }
2333
2334 static int wrmsr_interception(struct vcpu_svm *svm)
2335 {
2336         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2337         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2338                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2339
2340
2341         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2342         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2343                 trace_kvm_msr_write_ex(ecx, data);
2344                 kvm_inject_gp(&svm->vcpu, 0);
2345         } else {
2346                 trace_kvm_msr_write(ecx, data);
2347                 skip_emulated_instruction(&svm->vcpu);
2348         }
2349         return 1;
2350 }
2351
2352 static int msr_interception(struct vcpu_svm *svm)
2353 {
2354         if (svm->vmcb->control.exit_info_1)
2355                 return wrmsr_interception(svm);
2356         else
2357                 return rdmsr_interception(svm);
2358 }
2359
2360 static int interrupt_window_interception(struct vcpu_svm *svm)
2361 {
2362         struct kvm_run *kvm_run = svm->vcpu.run;
2363
2364         svm_clear_vintr(svm);
2365         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2366         /*
2367          * If the user space waits to inject interrupts, exit as soon as
2368          * possible
2369          */
2370         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2371             kvm_run->request_interrupt_window &&
2372             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2373                 ++svm->vcpu.stat.irq_window_exits;
2374                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2375                 return 0;
2376         }
2377
2378         return 1;
2379 }
2380
2381 static int pause_interception(struct vcpu_svm *svm)
2382 {
2383         kvm_vcpu_on_spin(&(svm->vcpu));
2384         return 1;
2385 }
2386
2387 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2388         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2389         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2390         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2391         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2392         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2393         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2394         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2395         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2396         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2397         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2398         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2399         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2400         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2401         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2402         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2403         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2404         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2405         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2406         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2407         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2408         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2409         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2410         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2411         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2412         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2413         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2414         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2415         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2416         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2417         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2418         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2419         [SVM_EXIT_INTR]                         = intr_interception,
2420         [SVM_EXIT_NMI]                          = nmi_interception,
2421         [SVM_EXIT_SMI]                          = nop_on_interception,
2422         [SVM_EXIT_INIT]                         = nop_on_interception,
2423         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2424         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2425         [SVM_EXIT_CPUID]                        = cpuid_interception,
2426         [SVM_EXIT_IRET]                         = iret_interception,
2427         [SVM_EXIT_INVD]                         = emulate_on_interception,
2428         [SVM_EXIT_PAUSE]                        = pause_interception,
2429         [SVM_EXIT_HLT]                          = halt_interception,
2430         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2431         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2432         [SVM_EXIT_IOIO]                         = io_interception,
2433         [SVM_EXIT_MSR]                          = msr_interception,
2434         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2435         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2436         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2437         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2438         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2439         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2440         [SVM_EXIT_STGI]                         = stgi_interception,
2441         [SVM_EXIT_CLGI]                         = clgi_interception,
2442         [SVM_EXIT_SKINIT]                       = skinit_interception,
2443         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2444         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2445         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2446         [SVM_EXIT_NPF]                          = pf_interception,
2447 };
2448
2449 static int handle_exit(struct kvm_vcpu *vcpu)
2450 {
2451         struct vcpu_svm *svm = to_svm(vcpu);
2452         struct kvm_run *kvm_run = vcpu->run;
2453         u32 exit_code = svm->vmcb->control.exit_code;
2454
2455         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2456
2457         if (unlikely(svm->nested.exit_required)) {
2458                 nested_svm_vmexit(svm);
2459                 svm->nested.exit_required = false;
2460
2461                 return 1;
2462         }
2463
2464         if (is_nested(svm)) {
2465                 int vmexit;
2466
2467                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2468                                         svm->vmcb->control.exit_info_1,
2469                                         svm->vmcb->control.exit_info_2,
2470                                         svm->vmcb->control.exit_int_info,
2471                                         svm->vmcb->control.exit_int_info_err);
2472
2473                 vmexit = nested_svm_exit_special(svm);
2474
2475                 if (vmexit == NESTED_EXIT_CONTINUE)
2476                         vmexit = nested_svm_exit_handled(svm);
2477
2478                 if (vmexit == NESTED_EXIT_DONE)
2479                         return 1;
2480         }
2481
2482         svm_complete_interrupts(svm);
2483
2484         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2485                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2486         if (npt_enabled)
2487                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2488
2489         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2490                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2491                 kvm_run->fail_entry.hardware_entry_failure_reason
2492                         = svm->vmcb->control.exit_code;
2493                 return 0;
2494         }
2495
2496         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2497             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2498             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2499                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2500                        "exit_code 0x%x\n",
2501                        __func__, svm->vmcb->control.exit_int_info,
2502                        exit_code);
2503
2504         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2505             || !svm_exit_handlers[exit_code]) {
2506                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2507                 kvm_run->hw.hardware_exit_reason = exit_code;
2508                 return 0;
2509         }
2510
2511         return svm_exit_handlers[exit_code](svm);
2512 }
2513
2514 static void reload_tss(struct kvm_vcpu *vcpu)
2515 {
2516         int cpu = raw_smp_processor_id();
2517
2518         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2519         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2520         load_TR_desc();
2521 }
2522
2523 static void pre_svm_run(struct vcpu_svm *svm)
2524 {
2525         int cpu = raw_smp_processor_id();
2526
2527         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2528
2529         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2530         /* FIXME: handle wraparound of asid_generation */
2531         if (svm->asid_generation != sd->asid_generation)
2532                 new_asid(svm, sd);
2533 }
2534
2535 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2536 {
2537         struct vcpu_svm *svm = to_svm(vcpu);
2538
2539         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2540         vcpu->arch.hflags |= HF_NMI_MASK;
2541         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2542         ++vcpu->stat.nmi_injections;
2543 }
2544
2545 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2546 {
2547         struct vmcb_control_area *control;
2548
2549         trace_kvm_inj_virq(irq);
2550
2551         ++svm->vcpu.stat.irq_injections;
2552         control = &svm->vmcb->control;
2553         control->int_vector = irq;
2554         control->int_ctl &= ~V_INTR_PRIO_MASK;
2555         control->int_ctl |= V_IRQ_MASK |
2556                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2557 }
2558
2559 static void svm_set_irq(struct kvm_vcpu *vcpu)
2560 {
2561         struct vcpu_svm *svm = to_svm(vcpu);
2562
2563         BUG_ON(!(gif_set(svm)));
2564
2565         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2566                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2567 }
2568
2569 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2570 {
2571         struct vcpu_svm *svm = to_svm(vcpu);
2572
2573         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2574                 return;
2575
2576         if (irr == -1)
2577                 return;
2578
2579         if (tpr >= irr)
2580                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2581 }
2582
2583 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2584 {
2585         struct vcpu_svm *svm = to_svm(vcpu);
2586         struct vmcb *vmcb = svm->vmcb;
2587         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2588                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2589 }
2590
2591 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2592 {
2593         struct vcpu_svm *svm = to_svm(vcpu);
2594
2595         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2596 }
2597
2598 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2599 {
2600         struct vcpu_svm *svm = to_svm(vcpu);
2601
2602         if (masked) {
2603                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2604                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2605         } else {
2606                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2607                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2608         }
2609 }
2610
2611 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2612 {
2613         struct vcpu_svm *svm = to_svm(vcpu);
2614         struct vmcb *vmcb = svm->vmcb;
2615         int ret;
2616
2617         if (!gif_set(svm) ||
2618              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2619                 return 0;
2620
2621         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2622
2623         if (is_nested(svm))
2624                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2625
2626         return ret;
2627 }
2628
2629 static void enable_irq_window(struct kvm_vcpu *vcpu)
2630 {
2631         struct vcpu_svm *svm = to_svm(vcpu);
2632
2633         /* In case GIF=0 we can't rely on the CPU to tell us when
2634          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2635          * The next time we get that intercept, this function will be
2636          * called again though and we'll get the vintr intercept. */
2637         if (gif_set(svm) && nested_svm_intr(svm)) {
2638                 svm_set_vintr(svm);
2639                 svm_inject_irq(svm, 0x0);
2640         }
2641 }
2642
2643 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2644 {
2645         struct vcpu_svm *svm = to_svm(vcpu);
2646
2647         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2648             == HF_NMI_MASK)
2649                 return; /* IRET will cause a vm exit */
2650
2651         /* Something prevents NMI from been injected. Single step over
2652            possible problem (IRET or exception injection or interrupt
2653            shadow) */
2654         svm->nmi_singlestep = true;
2655         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2656         update_db_intercept(vcpu);
2657 }
2658
2659 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2660 {
2661         return 0;
2662 }
2663
2664 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2665 {
2666         force_new_asid(vcpu);
2667 }
2668
2669 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2670 {
2671 }
2672
2673 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2674 {
2675         struct vcpu_svm *svm = to_svm(vcpu);
2676
2677         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2678                 return;
2679
2680         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2681                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2682                 kvm_set_cr8(vcpu, cr8);
2683         }
2684 }
2685
2686 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2687 {
2688         struct vcpu_svm *svm = to_svm(vcpu);
2689         u64 cr8;
2690
2691         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2692                 return;
2693
2694         cr8 = kvm_get_cr8(vcpu);
2695         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2696         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2697 }
2698
2699 static void svm_complete_interrupts(struct vcpu_svm *svm)
2700 {
2701         u8 vector;
2702         int type;
2703         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2704
2705         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2706                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2707
2708         svm->vcpu.arch.nmi_injected = false;
2709         kvm_clear_exception_queue(&svm->vcpu);
2710         kvm_clear_interrupt_queue(&svm->vcpu);
2711
2712         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2713                 return;
2714
2715         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2716         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2717
2718         switch (type) {
2719         case SVM_EXITINTINFO_TYPE_NMI:
2720                 svm->vcpu.arch.nmi_injected = true;
2721                 break;
2722         case SVM_EXITINTINFO_TYPE_EXEPT:
2723                 /* In case of software exception do not reinject an exception
2724                    vector, but re-execute and instruction instead */
2725                 if (is_nested(svm))
2726                         break;
2727                 if (kvm_exception_is_soft(vector))
2728                         break;
2729                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2730                         u32 err = svm->vmcb->control.exit_int_info_err;
2731                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2732
2733                 } else
2734                         kvm_queue_exception(&svm->vcpu, vector);
2735                 break;
2736         case SVM_EXITINTINFO_TYPE_INTR:
2737                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2738                 break;
2739         default:
2740                 break;
2741         }
2742 }
2743
2744 #ifdef CONFIG_X86_64
2745 #define R "r"
2746 #else
2747 #define R "e"
2748 #endif
2749
2750 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2751 {
2752         struct vcpu_svm *svm = to_svm(vcpu);
2753         u16 fs_selector;
2754         u16 gs_selector;
2755         u16 ldt_selector;
2756
2757         /*
2758          * A vmexit emulation is required before the vcpu can be executed
2759          * again.
2760          */
2761         if (unlikely(svm->nested.exit_required))
2762                 return;
2763
2764         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2765         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2766         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2767
2768         pre_svm_run(svm);
2769
2770         sync_lapic_to_cr8(vcpu);
2771
2772         save_host_msrs(vcpu);
2773         fs_selector = kvm_read_fs();
2774         gs_selector = kvm_read_gs();
2775         ldt_selector = kvm_read_ldt();
2776         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2777         /* required for live migration with NPT */
2778         if (npt_enabled)
2779                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2780
2781         clgi();
2782
2783         local_irq_enable();
2784
2785         asm volatile (
2786                 "push %%"R"bp; \n\t"
2787                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2788                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2789                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2790                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2791                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2792                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2793 #ifdef CONFIG_X86_64
2794                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2795                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2796                 "mov %c[r10](%[svm]), %%r10 \n\t"
2797                 "mov %c[r11](%[svm]), %%r11 \n\t"
2798                 "mov %c[r12](%[svm]), %%r12 \n\t"
2799                 "mov %c[r13](%[svm]), %%r13 \n\t"
2800                 "mov %c[r14](%[svm]), %%r14 \n\t"
2801                 "mov %c[r15](%[svm]), %%r15 \n\t"
2802 #endif
2803
2804                 /* Enter guest mode */
2805                 "push %%"R"ax \n\t"
2806                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2807                 __ex(SVM_VMLOAD) "\n\t"
2808                 __ex(SVM_VMRUN) "\n\t"
2809                 __ex(SVM_VMSAVE) "\n\t"
2810                 "pop %%"R"ax \n\t"
2811
2812                 /* Save guest registers, load host registers */
2813                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2814                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2815                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2816                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2817                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2818                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2819 #ifdef CONFIG_X86_64
2820                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2821                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2822                 "mov %%r10, %c[r10](%[svm]) \n\t"
2823                 "mov %%r11, %c[r11](%[svm]) \n\t"
2824                 "mov %%r12, %c[r12](%[svm]) \n\t"
2825                 "mov %%r13, %c[r13](%[svm]) \n\t"
2826                 "mov %%r14, %c[r14](%[svm]) \n\t"
2827                 "mov %%r15, %c[r15](%[svm]) \n\t"
2828 #endif
2829                 "pop %%"R"bp"
2830                 :
2831                 : [svm]"a"(svm),
2832                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2833                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2834                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2835                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2836                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2837                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2838                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2839 #ifdef CONFIG_X86_64
2840                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2841                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2842                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2843                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2844                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2845                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2846                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2847                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2848 #endif
2849                 : "cc", "memory"
2850                 , R"bx", R"cx", R"dx", R"si", R"di"
2851 #ifdef CONFIG_X86_64
2852                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2853 #endif
2854                 );
2855
2856         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2857         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2858         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2859         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2860
2861         kvm_load_fs(fs_selector);
2862         kvm_load_gs(gs_selector);
2863         kvm_load_ldt(ldt_selector);
2864         load_host_msrs(vcpu);
2865
2866         reload_tss(vcpu);
2867
2868         local_irq_disable();
2869
2870         stgi();
2871
2872         sync_cr8_to_lapic(vcpu);
2873
2874         svm->next_rip = 0;
2875
2876         if (npt_enabled) {
2877                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2878                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2879         }
2880 }
2881
2882 #undef R
2883
2884 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2885 {
2886         struct vcpu_svm *svm = to_svm(vcpu);
2887
2888         if (npt_enabled) {
2889                 svm->vmcb->control.nested_cr3 = root;
2890                 force_new_asid(vcpu);
2891                 return;
2892         }
2893
2894         svm->vmcb->save.cr3 = root;
2895         force_new_asid(vcpu);
2896 }
2897
2898 static int is_disabled(void)
2899 {
2900         u64 vm_cr;
2901
2902         rdmsrl(MSR_VM_CR, vm_cr);
2903         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2904                 return 1;
2905
2906         return 0;
2907 }
2908
2909 static void
2910 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2911 {
2912         /*
2913          * Patch in the VMMCALL instruction:
2914          */
2915         hypercall[0] = 0x0f;
2916         hypercall[1] = 0x01;
2917         hypercall[2] = 0xd9;
2918 }
2919
2920 static void svm_check_processor_compat(void *rtn)
2921 {
2922         *(int *)rtn = 0;
2923 }
2924
2925 static bool svm_cpu_has_accelerated_tpr(void)
2926 {
2927         return false;
2928 }
2929
2930 static int get_npt_level(void)
2931 {
2932 #ifdef CONFIG_X86_64
2933         return PT64_ROOT_LEVEL;
2934 #else
2935         return PT32E_ROOT_LEVEL;
2936 #endif
2937 }
2938
2939 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2940 {
2941         return 0;
2942 }
2943
2944 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2945 {
2946 }
2947
2948 static const struct trace_print_flags svm_exit_reasons_str[] = {
2949         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2950         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2951         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2952         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2953         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2954         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2955         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2956         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2957         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2958         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2959         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2960         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2961         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2962         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2963         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2964         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2965         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2966         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2967         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2968         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2969         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2970         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2971         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2972         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2973         { SVM_EXIT_INTR,                        "interrupt" },
2974         { SVM_EXIT_NMI,                         "nmi" },
2975         { SVM_EXIT_SMI,                         "smi" },
2976         { SVM_EXIT_INIT,                        "init" },
2977         { SVM_EXIT_VINTR,                       "vintr" },
2978         { SVM_EXIT_CPUID,                       "cpuid" },
2979         { SVM_EXIT_INVD,                        "invd" },
2980         { SVM_EXIT_HLT,                         "hlt" },
2981         { SVM_EXIT_INVLPG,                      "invlpg" },
2982         { SVM_EXIT_INVLPGA,                     "invlpga" },
2983         { SVM_EXIT_IOIO,                        "io" },
2984         { SVM_EXIT_MSR,                         "msr" },
2985         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2986         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2987         { SVM_EXIT_VMRUN,                       "vmrun" },
2988         { SVM_EXIT_VMMCALL,                     "hypercall" },
2989         { SVM_EXIT_VMLOAD,                      "vmload" },
2990         { SVM_EXIT_VMSAVE,                      "vmsave" },
2991         { SVM_EXIT_STGI,                        "stgi" },
2992         { SVM_EXIT_CLGI,                        "clgi" },
2993         { SVM_EXIT_SKINIT,                      "skinit" },
2994         { SVM_EXIT_WBINVD,                      "wbinvd" },
2995         { SVM_EXIT_MONITOR,                     "monitor" },
2996         { SVM_EXIT_MWAIT,                       "mwait" },
2997         { SVM_EXIT_NPF,                         "npf" },
2998         { -1, NULL }
2999 };
3000
3001 static int svm_get_lpage_level(void)
3002 {
3003         return PT_PDPE_LEVEL;
3004 }
3005
3006 static bool svm_rdtscp_supported(void)
3007 {
3008         return false;
3009 }
3010
3011 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3012 {
3013         struct vcpu_svm *svm = to_svm(vcpu);
3014
3015         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3016         if (is_nested(svm))
3017                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3018         update_cr0_intercept(svm);
3019 }
3020
3021 static struct kvm_x86_ops svm_x86_ops = {
3022         .cpu_has_kvm_support = has_svm,
3023         .disabled_by_bios = is_disabled,
3024         .hardware_setup = svm_hardware_setup,
3025         .hardware_unsetup = svm_hardware_unsetup,
3026         .check_processor_compatibility = svm_check_processor_compat,
3027         .hardware_enable = svm_hardware_enable,
3028         .hardware_disable = svm_hardware_disable,
3029         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3030
3031         .vcpu_create = svm_create_vcpu,
3032         .vcpu_free = svm_free_vcpu,
3033         .vcpu_reset = svm_vcpu_reset,
3034
3035         .prepare_guest_switch = svm_prepare_guest_switch,
3036         .vcpu_load = svm_vcpu_load,
3037         .vcpu_put = svm_vcpu_put,
3038
3039         .set_guest_debug = svm_guest_debug,
3040         .get_msr = svm_get_msr,
3041         .set_msr = svm_set_msr,
3042         .get_segment_base = svm_get_segment_base,
3043         .get_segment = svm_get_segment,
3044         .set_segment = svm_set_segment,
3045         .get_cpl = svm_get_cpl,
3046         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3047         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3048         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3049         .set_cr0 = svm_set_cr0,
3050         .set_cr3 = svm_set_cr3,
3051         .set_cr4 = svm_set_cr4,
3052         .set_efer = svm_set_efer,
3053         .get_idt = svm_get_idt,
3054         .set_idt = svm_set_idt,
3055         .get_gdt = svm_get_gdt,
3056         .set_gdt = svm_set_gdt,
3057         .get_dr = svm_get_dr,
3058         .set_dr = svm_set_dr,
3059         .cache_reg = svm_cache_reg,
3060         .get_rflags = svm_get_rflags,
3061         .set_rflags = svm_set_rflags,
3062         .fpu_activate = svm_fpu_activate,
3063         .fpu_deactivate = svm_fpu_deactivate,
3064
3065         .tlb_flush = svm_flush_tlb,
3066
3067         .run = svm_vcpu_run,
3068         .handle_exit = handle_exit,
3069         .skip_emulated_instruction = skip_emulated_instruction,
3070         .set_interrupt_shadow = svm_set_interrupt_shadow,
3071         .get_interrupt_shadow = svm_get_interrupt_shadow,
3072         .patch_hypercall = svm_patch_hypercall,
3073         .set_irq = svm_set_irq,
3074         .set_nmi = svm_inject_nmi,
3075         .queue_exception = svm_queue_exception,
3076         .interrupt_allowed = svm_interrupt_allowed,
3077         .nmi_allowed = svm_nmi_allowed,
3078         .get_nmi_mask = svm_get_nmi_mask,
3079         .set_nmi_mask = svm_set_nmi_mask,
3080         .enable_nmi_window = enable_nmi_window,
3081         .enable_irq_window = enable_irq_window,
3082         .update_cr8_intercept = update_cr8_intercept,
3083
3084         .set_tss_addr = svm_set_tss_addr,
3085         .get_tdp_level = get_npt_level,
3086         .get_mt_mask = svm_get_mt_mask,
3087
3088         .exit_reasons_str = svm_exit_reasons_str,
3089         .get_lpage_level = svm_get_lpage_level,
3090
3091         .cpuid_update = svm_cpuid_update,
3092
3093         .rdtscp_supported = svm_rdtscp_supported,
3094 };
3095
3096 static int __init svm_init(void)
3097 {
3098         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3099                               THIS_MODULE);
3100 }
3101
3102 static void __exit svm_exit(void)
3103 {
3104         kvm_exit();
3105 }
3106
3107 module_init(svm_init)
3108 module_exit(svm_exit)