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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50 #define SVM_FEATURE_NRIP (1 << 3)
  51 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  52
  53 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  54 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  55 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  56
  57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  58
  59 static const u32 host_save_user_msrs[] = {
  60 #ifdef CONFIG_X86_64
  61         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  62         MSR_FS_BASE,
  63 #endif
  64         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  65 };
  66
  67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  68
  69 struct kvm_vcpu;
  70
  71 struct nested_state {
  72         struct vmcb *hsave;
  73         u64 hsave_msr;
  74         u64 vmcb;
  75
  76         /* These are the merged vectors */
  77         u32 *msrpm;
  78
  79         /* gpa pointers to the real vectors */
  80         u64 vmcb_msrpm;
  81
  82         /* A VMEXIT is required but not yet emulated */
  83         bool exit_required;
  84
  85         /* cache for intercepts of the guest */
  86         u16 intercept_cr_read;
  87         u16 intercept_cr_write;
  88         u16 intercept_dr_read;
  89         u16 intercept_dr_write;
  90         u32 intercept_exceptions;
  91         u64 intercept;
  92
  93 };
  94
  95 struct vcpu_svm {
  96         struct kvm_vcpu vcpu;
  97         struct vmcb *vmcb;
  98         unsigned long vmcb_pa;
  99         struct svm_cpu_data *svm_data;
 100         uint64_t asid_generation;
 101         uint64_t sysenter_esp;
 102         uint64_t sysenter_eip;
 103
 104         u64 next_rip;
 105
 106         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 107         u64 host_gs_base;
 108
 109         u32 *msrpm;
 110
 111         struct nested_state nested;
 112
 113         bool nmi_singlestep;
 114
 115         unsigned int3_injected;
 116         unsigned long int3_rip;
 117 };
 118
 119 /* enable NPT for AMD64 and X86 with PAE */
 120 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 121 static bool npt_enabled = true;
 122 #else
 123 static bool npt_enabled;
 124 #endif
 125 static int npt = 1;
 126
 127 module_param(npt, int, S_IRUGO);
 128
 129 static int nested = 1;
 130 module_param(nested, int, S_IRUGO);
 131
 132 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 133 static void svm_complete_interrupts(struct vcpu_svm *svm);
 134
 135 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 136 static int nested_svm_intercept(struct vcpu_svm *svm);
 137 static int nested_svm_vmexit(struct vcpu_svm *svm);
 138 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 139                                       bool has_error_code, u32 error_code);
 140
 141 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 142 {
 143         return container_of(vcpu, struct vcpu_svm, vcpu);
 144 }
 145
 146 static inline bool is_nested(struct vcpu_svm *svm)
 147 {
 148         return svm->nested.vmcb;
 149 }
 150
 151 static inline void enable_gif(struct vcpu_svm *svm)
 152 {
 153         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 154 }
 155
 156 static inline void disable_gif(struct vcpu_svm *svm)
 157 {
 158         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 159 }
 160
 161 static inline bool gif_set(struct vcpu_svm *svm)
 162 {
 163         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 164 }
 165
 166 static unsigned long iopm_base;
 167
 168 struct kvm_ldttss_desc {
 169         u16 limit0;
 170         u16 base0;
 171         unsigned base1:8, type:5, dpl:2, p:1;
 172         unsigned limit1:4, zero0:3, g:1, base2:8;
 173         u32 base3;
 174         u32 zero1;
 175 } __attribute__((packed));
 176
 177 struct svm_cpu_data {
 178         int cpu;
 179
 180         u64 asid_generation;
 181         u32 max_asid;
 182         u32 next_asid;
 183         struct kvm_ldttss_desc *tss_desc;
 184
 185         struct page *save_area;
 186 };
 187
 188 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 189 static uint32_t svm_features;
 190
 191 struct svm_init_data {
 192         int cpu;
 193         int r;
 194 };
 195
 196 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 197
 198 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 199 #define MSRS_RANGE_SIZE 2048
 200 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 201
 202 #define MAX_INST_SIZE 15
 203
 204 static inline u32 svm_has(u32 feat)
 205 {
 206         return svm_features & feat;
 207 }
 208
 209 static inline void clgi(void)
 210 {
 211         asm volatile (__ex(SVM_CLGI));
 212 }
 213
 214 static inline void stgi(void)
 215 {
 216         asm volatile (__ex(SVM_STGI));
 217 }
 218
 219 static inline void invlpga(unsigned long addr, u32 asid)
 220 {
 221         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 222 }
 223
 224 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 225 {
 226         to_svm(vcpu)->asid_generation--;
 227 }
 228
 229 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 230 {
 231         force_new_asid(vcpu);
 232 }
 233
 234 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 235 {
 236         if (!npt_enabled && !(efer & EFER_LMA))
 237                 efer &= ~EFER_LME;
 238
 239         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 240         vcpu->arch.efer = efer;
 241 }
 242
 243 static int is_external_interrupt(u32 info)
 244 {
 245         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 246         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 247 }
 248
 249 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 250 {
 251         struct vcpu_svm *svm = to_svm(vcpu);
 252         u32 ret = 0;
 253
 254         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 255                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 256         return ret & mask;
 257 }
 258
 259 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 260 {
 261         struct vcpu_svm *svm = to_svm(vcpu);
 262
 263         if (mask == 0)
 264                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 265         else
 266                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 267
 268 }
 269
 270 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273
 274         if (!svm->next_rip) {
 275                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 276                                 EMULATE_DONE)
 277                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 278                 return;
 279         }
 280         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 281                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 282                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 283
 284         kvm_rip_write(vcpu, svm->next_rip);
 285         svm_set_interrupt_shadow(vcpu, 0);
 286 }
 287
 288 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 289                                 bool has_error_code, u32 error_code)
 290 {
 291         struct vcpu_svm *svm = to_svm(vcpu);
 292
 293         /*
 294          * If we are within a nested VM we'd better #VMEXIT and let the guest
 295          * handle the exception
 296          */
 297         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 298                 return;
 299
 300         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 301                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 302
 303                 /*
 304                  * For guest debugging where we have to reinject #BP if some
 305                  * INT3 is guest-owned:
 306                  * Emulate nRIP by moving RIP forward. Will fail if injection
 307                  * raises a fault that is not intercepted. Still better than
 308                  * failing in all cases.
 309                  */
 310                 skip_emulated_instruction(&svm->vcpu);
 311                 rip = kvm_rip_read(&svm->vcpu);
 312                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 313                 svm->int3_injected = rip - old_rip;
 314         }
 315
 316         svm->vmcb->control.event_inj = nr
 317                 | SVM_EVTINJ_VALID
 318                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 319                 | SVM_EVTINJ_TYPE_EXEPT;
 320         svm->vmcb->control.event_inj_err = error_code;
 321 }
 322
 323 static int has_svm(void)
 324 {
 325         const char *msg;
 326
 327         if (!cpu_has_svm(&msg)) {
 328                 printk(KERN_INFO "has_svm: %s\n", msg);
 329                 return 0;
 330         }
 331
 332         return 1;
 333 }
 334
 335 static void svm_hardware_disable(void *garbage)
 336 {
 337         cpu_svm_disable();
 338 }
 339
 340 static int svm_hardware_enable(void *garbage)
 341 {
 342
 343         struct svm_cpu_data *sd;
 344         uint64_t efer;
 345         struct desc_ptr gdt_descr;
 346         struct desc_struct *gdt;
 347         int me = raw_smp_processor_id();
 348
 349         rdmsrl(MSR_EFER, efer);
 350         if (efer & EFER_SVME)
 351                 return -EBUSY;
 352
 353         if (!has_svm()) {
 354                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 355                        me);
 356                 return -EINVAL;
 357         }
 358         sd = per_cpu(svm_data, me);
 359
 360         if (!sd) {
 361                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 362                        me);
 363                 return -EINVAL;
 364         }
 365
 366         sd->asid_generation = 1;
 367         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 368         sd->next_asid = sd->max_asid + 1;
 369
 370         kvm_get_gdt(&gdt_descr);
 371         gdt = (struct desc_struct *)gdt_descr.address;
 372         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 373
 374         wrmsrl(MSR_EFER, efer | EFER_SVME);
 375
 376         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 377
 378         return 0;
 379 }
 380
 381 static void svm_cpu_uninit(int cpu)
 382 {
 383         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 384
 385         if (!sd)
 386                 return;
 387
 388         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 389         __free_page(sd->save_area);
 390         kfree(sd);
 391 }
 392
 393 static int svm_cpu_init(int cpu)
 394 {
 395         struct svm_cpu_data *sd;
 396         int r;
 397
 398         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 399         if (!sd)
 400                 return -ENOMEM;
 401         sd->cpu = cpu;
 402         sd->save_area = alloc_page(GFP_KERNEL);
 403         r = -ENOMEM;
 404         if (!sd->save_area)
 405                 goto err_1;
 406
 407         per_cpu(svm_data, cpu) = sd;
 408
 409         return 0;
 410
 411 err_1:
 412         kfree(sd);
 413         return r;
 414
 415 }
 416
 417 static void set_msr_interception(u32 *msrpm, unsigned msr,
 418                                  int read, int write)
 419 {
 420         int i;
 421
 422         for (i = 0; i < NUM_MSR_MAPS; i++) {
 423                 if (msr >= msrpm_ranges[i] &&
 424                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 425                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 426                                           msrpm_ranges[i]) * 2;
 427
 428                         u32 *base = msrpm + (msr_offset / 32);
 429                         u32 msr_shift = msr_offset % 32;
 430                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 431                         *base = (*base & ~(0x3 << msr_shift)) |
 432                                 (mask << msr_shift);
 433                         return;
 434                 }
 435         }
 436         BUG();
 437 }
 438
 439 static void svm_vcpu_init_msrpm(u32 *msrpm)
 440 {
 441         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 442
 443 #ifdef CONFIG_X86_64
 444         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 445         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 446         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 447         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 448         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 449         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 450 #endif
 451         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 452         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 453 }
 454
 455 static void svm_enable_lbrv(struct vcpu_svm *svm)
 456 {
 457         u32 *msrpm = svm->msrpm;
 458
 459         svm->vmcb->control.lbr_ctl = 1;
 460         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 461         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 462         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 463         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 464 }
 465
 466 static void svm_disable_lbrv(struct vcpu_svm *svm)
 467 {
 468         u32 *msrpm = svm->msrpm;
 469
 470         svm->vmcb->control.lbr_ctl = 0;
 471         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 472         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 473         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 474         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 475 }
 476
 477 static __init int svm_hardware_setup(void)
 478 {
 479         int cpu;
 480         struct page *iopm_pages;
 481         void *iopm_va;
 482         int r;
 483
 484         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 485
 486         if (!iopm_pages)
 487                 return -ENOMEM;
 488
 489         iopm_va = page_address(iopm_pages);
 490         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 491         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 492
 493         if (boot_cpu_has(X86_FEATURE_NX))
 494                 kvm_enable_efer_bits(EFER_NX);
 495
 496         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 497                 kvm_enable_efer_bits(EFER_FFXSR);
 498
 499         if (nested) {
 500                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 501                 kvm_enable_efer_bits(EFER_SVME);
 502         }
 503
 504         for_each_possible_cpu(cpu) {
 505                 r = svm_cpu_init(cpu);
 506                 if (r)
 507                         goto err;
 508         }
 509
 510         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 511
 512         if (!svm_has(SVM_FEATURE_NPT))
 513                 npt_enabled = false;
 514
 515         if (npt_enabled && !npt) {
 516                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 517                 npt_enabled = false;
 518         }
 519
 520         if (npt_enabled) {
 521                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 522                 kvm_enable_tdp();
 523         } else
 524                 kvm_disable_tdp();
 525
 526         return 0;
 527
 528 err:
 529         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 530         iopm_base = 0;
 531         return r;
 532 }
 533
 534 static __exit void svm_hardware_unsetup(void)
 535 {
 536         int cpu;
 537
 538         for_each_possible_cpu(cpu)
 539                 svm_cpu_uninit(cpu);
 540
 541         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 542         iopm_base = 0;
 543 }
 544
 545 static void init_seg(struct vmcb_seg *seg)
 546 {
 547         seg->selector = 0;
 548         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 549                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 550         seg->limit = 0xffff;
 551         seg->base = 0;
 552 }
 553
 554 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 555 {
 556         seg->selector = 0;
 557         seg->attrib = SVM_SELECTOR_P_MASK | type;
 558         seg->limit = 0xffff;
 559         seg->base = 0;
 560 }
 561
 562 static void init_vmcb(struct vcpu_svm *svm)
 563 {
 564         struct vmcb_control_area *control = &svm->vmcb->control;
 565         struct vmcb_save_area *save = &svm->vmcb->save;
 566
 567         svm->vcpu.fpu_active = 1;
 568
 569         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 570                                         INTERCEPT_CR3_MASK |
 571                                         INTERCEPT_CR4_MASK;
 572
 573         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 574                                         INTERCEPT_CR3_MASK |
 575                                         INTERCEPT_CR4_MASK |
 576                                         INTERCEPT_CR8_MASK;
 577
 578         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 579                                         INTERCEPT_DR1_MASK |
 580                                         INTERCEPT_DR2_MASK |
 581                                         INTERCEPT_DR3_MASK |
 582                                         INTERCEPT_DR4_MASK |
 583                                         INTERCEPT_DR5_MASK |
 584                                         INTERCEPT_DR6_MASK |
 585                                         INTERCEPT_DR7_MASK;
 586
 587         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 588                                         INTERCEPT_DR1_MASK |
 589                                         INTERCEPT_DR2_MASK |
 590                                         INTERCEPT_DR3_MASK |
 591                                         INTERCEPT_DR4_MASK |
 592                                         INTERCEPT_DR5_MASK |
 593                                         INTERCEPT_DR6_MASK |
 594                                         INTERCEPT_DR7_MASK;
 595
 596         control->intercept_exceptions = (1 << PF_VECTOR) |
 597                                         (1 << UD_VECTOR) |
 598                                         (1 << MC_VECTOR);
 599
 600
 601         control->intercept =    (1ULL << INTERCEPT_INTR) |
 602                                 (1ULL << INTERCEPT_NMI) |
 603                                 (1ULL << INTERCEPT_SMI) |
 604                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 605                                 (1ULL << INTERCEPT_CPUID) |
 606                                 (1ULL << INTERCEPT_INVD) |
 607                                 (1ULL << INTERCEPT_HLT) |
 608                                 (1ULL << INTERCEPT_INVLPG) |
 609                                 (1ULL << INTERCEPT_INVLPGA) |
 610                                 (1ULL << INTERCEPT_IOIO_PROT) |
 611                                 (1ULL << INTERCEPT_MSR_PROT) |
 612                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 613                                 (1ULL << INTERCEPT_SHUTDOWN) |
 614                                 (1ULL << INTERCEPT_VMRUN) |
 615                                 (1ULL << INTERCEPT_VMMCALL) |
 616                                 (1ULL << INTERCEPT_VMLOAD) |
 617                                 (1ULL << INTERCEPT_VMSAVE) |
 618                                 (1ULL << INTERCEPT_STGI) |
 619                                 (1ULL << INTERCEPT_CLGI) |
 620                                 (1ULL << INTERCEPT_SKINIT) |
 621                                 (1ULL << INTERCEPT_WBINVD) |
 622                                 (1ULL << INTERCEPT_MONITOR) |
 623                                 (1ULL << INTERCEPT_MWAIT);
 624
 625         control->iopm_base_pa = iopm_base;
 626         control->msrpm_base_pa = __pa(svm->msrpm);
 627         control->tsc_offset = 0;
 628         control->int_ctl = V_INTR_MASKING_MASK;
 629
 630         init_seg(&save->es);
 631         init_seg(&save->ss);
 632         init_seg(&save->ds);
 633         init_seg(&save->fs);
 634         init_seg(&save->gs);
 635
 636         save->cs.selector = 0xf000;
 637         /* Executable/Readable Code Segment */
 638         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 639                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 640         save->cs.limit = 0xffff;
 641         /*
 642          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 643          * be consistent with it.
 644          *
 645          * Replace when we have real mode working for vmx.
 646          */
 647         save->cs.base = 0xf0000;
 648
 649         save->gdtr.limit = 0xffff;
 650         save->idtr.limit = 0xffff;
 651
 652         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 653         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 654
 655         save->efer = EFER_SVME;
 656         save->dr6 = 0xffff0ff0;
 657         save->dr7 = 0x400;
 658         save->rflags = 2;
 659         save->rip = 0x0000fff0;
 660         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 661
 662         /*
 663          * This is the guest-visible cr0 value.
 664          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 665          */
 666         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 667         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 668
 669         save->cr4 = X86_CR4_PAE;
 670         /* rdx = ?? */
 671
 672         if (npt_enabled) {
 673                 /* Setup VMCB for Nested Paging */
 674                 control->nested_ctl = 1;
 675                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 676                                         (1ULL << INTERCEPT_INVLPG));
 677                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 678                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 679                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 680                 save->g_pat = 0x0007040600070406ULL;
 681                 save->cr3 = 0;
 682                 save->cr4 = 0;
 683         }
 684         force_new_asid(&svm->vcpu);
 685
 686         svm->nested.vmcb = 0;
 687         svm->vcpu.arch.hflags = 0;
 688
 689         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 690                 control->pause_filter_count = 3000;
 691                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 692         }
 693
 694         enable_gif(svm);
 695 }
 696
 697 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 698 {
 699         struct vcpu_svm *svm = to_svm(vcpu);
 700
 701         init_vmcb(svm);
 702
 703         if (!kvm_vcpu_is_bsp(vcpu)) {
 704                 kvm_rip_write(vcpu, 0);
 705                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 706                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 707         }
 708         vcpu->arch.regs_avail = ~0;
 709         vcpu->arch.regs_dirty = ~0;
 710
 711         return 0;
 712 }
 713
 714 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 715 {
 716         struct vcpu_svm *svm;
 717         struct page *page;
 718         struct page *msrpm_pages;
 719         struct page *hsave_page;
 720         struct page *nested_msrpm_pages;
 721         int err;
 722
 723         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 724         if (!svm) {
 725                 err = -ENOMEM;
 726                 goto out;
 727         }
 728
 729         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 730         if (err)
 731                 goto free_svm;
 732
 733         err = -ENOMEM;
 734         page = alloc_page(GFP_KERNEL);
 735         if (!page)
 736                 goto uninit;
 737
 738         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 739         if (!msrpm_pages)
 740                 goto free_page1;
 741
 742         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 743         if (!nested_msrpm_pages)
 744                 goto free_page2;
 745
 746         hsave_page = alloc_page(GFP_KERNEL);
 747         if (!hsave_page)
 748                 goto free_page3;
 749
 750         svm->nested.hsave = page_address(hsave_page);
 751
 752         svm->msrpm = page_address(msrpm_pages);
 753         svm_vcpu_init_msrpm(svm->msrpm);
 754
 755         svm->nested.msrpm = page_address(nested_msrpm_pages);
 756
 757         svm->vmcb = page_address(page);
 758         clear_page(svm->vmcb);
 759         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 760         svm->asid_generation = 0;
 761         init_vmcb(svm);
 762
 763         fx_init(&svm->vcpu);
 764         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 765         if (kvm_vcpu_is_bsp(&svm->vcpu))
 766                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 767
 768         return &svm->vcpu;
 769
 770 free_page3:
 771         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 772 free_page2:
 773         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 774 free_page1:
 775         __free_page(page);
 776 uninit:
 777         kvm_vcpu_uninit(&svm->vcpu);
 778 free_svm:
 779         kmem_cache_free(kvm_vcpu_cache, svm);
 780 out:
 781         return ERR_PTR(err);
 782 }
 783
 784 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 785 {
 786         struct vcpu_svm *svm = to_svm(vcpu);
 787
 788         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 789         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 790         __free_page(virt_to_page(svm->nested.hsave));
 791         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 792         kvm_vcpu_uninit(vcpu);
 793         kmem_cache_free(kvm_vcpu_cache, svm);
 794 }
 795
 796 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 797 {
 798         struct vcpu_svm *svm = to_svm(vcpu);
 799         int i;
 800
 801         if (unlikely(cpu != vcpu->cpu)) {
 802                 u64 delta;
 803
 804                 if (check_tsc_unstable()) {
 805                         /*
 806                          * Make sure that the guest sees a monotonically
 807                          * increasing TSC.
 808                          */
 809                         delta = vcpu->arch.host_tsc - native_read_tsc();
 810                         svm->vmcb->control.tsc_offset += delta;
 811                         if (is_nested(svm))
 812                                 svm->nested.hsave->control.tsc_offset += delta;
 813                 }
 814                 vcpu->cpu = cpu;
 815                 kvm_migrate_timers(vcpu);
 816                 svm->asid_generation = 0;
 817         }
 818
 819         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 820                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 821 }
 822
 823 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 824 {
 825         struct vcpu_svm *svm = to_svm(vcpu);
 826         int i;
 827
 828         ++vcpu->stat.host_state_reload;
 829         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 830                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 831
 832         vcpu->arch.host_tsc = native_read_tsc();
 833 }
 834
 835 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 836 {
 837         return to_svm(vcpu)->vmcb->save.rflags;
 838 }
 839
 840 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 841 {
 842         to_svm(vcpu)->vmcb->save.rflags = rflags;
 843 }
 844
 845 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 846 {
 847         switch (reg) {
 848         case VCPU_EXREG_PDPTR:
 849                 BUG_ON(!npt_enabled);
 850                 load_pdptrs(vcpu, vcpu->arch.cr3);
 851                 break;
 852         default:
 853                 BUG();
 854         }
 855 }
 856
 857 static void svm_set_vintr(struct vcpu_svm *svm)
 858 {
 859         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 860 }
 861
 862 static void svm_clear_vintr(struct vcpu_svm *svm)
 863 {
 864         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 865 }
 866
 867 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 868 {
 869         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 870
 871         switch (seg) {
 872         case VCPU_SREG_CS: return &save->cs;
 873         case VCPU_SREG_DS: return &save->ds;
 874         case VCPU_SREG_ES: return &save->es;
 875         case VCPU_SREG_FS: return &save->fs;
 876         case VCPU_SREG_GS: return &save->gs;
 877         case VCPU_SREG_SS: return &save->ss;
 878         case VCPU_SREG_TR: return &save->tr;
 879         case VCPU_SREG_LDTR: return &save->ldtr;
 880         }
 881         BUG();
 882         return NULL;
 883 }
 884
 885 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 886 {
 887         struct vmcb_seg *s = svm_seg(vcpu, seg);
 888
 889         return s->base;
 890 }
 891
 892 static void svm_get_segment(struct kvm_vcpu *vcpu,
 893                             struct kvm_segment *var, int seg)
 894 {
 895         struct vmcb_seg *s = svm_seg(vcpu, seg);
 896
 897         var->base = s->base;
 898         var->limit = s->limit;
 899         var->selector = s->selector;
 900         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 901         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 902         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 903         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 904         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 905         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 906         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 907         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 908
 909         /*
 910          * AMD's VMCB does not have an explicit unusable field, so emulate it
 911          * for cross vendor migration purposes by "not present"
 912          */
 913         var->unusable = !var->present || (var->type == 0);
 914
 915         switch (seg) {
 916         case VCPU_SREG_CS:
 917                 /*
 918                  * SVM always stores 0 for the 'G' bit in the CS selector in
 919                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 920                  * Intel's VMENTRY has a check on the 'G' bit.
 921                  */
 922                 var->g = s->limit > 0xfffff;
 923                 break;
 924         case VCPU_SREG_TR:
 925                 /*
 926                  * Work around a bug where the busy flag in the tr selector
 927                  * isn't exposed
 928                  */
 929                 var->type |= 0x2;
 930                 break;
 931         case VCPU_SREG_DS:
 932         case VCPU_SREG_ES:
 933         case VCPU_SREG_FS:
 934         case VCPU_SREG_GS:
 935                 /*
 936                  * The accessed bit must always be set in the segment
 937                  * descriptor cache, although it can be cleared in the
 938                  * descriptor, the cached bit always remains at 1. Since
 939                  * Intel has a check on this, set it here to support
 940                  * cross-vendor migration.
 941                  */
 942                 if (!var->unusable)
 943                         var->type |= 0x1;
 944                 break;
 945         case VCPU_SREG_SS:
 946                 /*
 947                  * On AMD CPUs sometimes the DB bit in the segment
 948                  * descriptor is left as 1, although the whole segment has
 949                  * been made unusable. Clear it here to pass an Intel VMX
 950                  * entry check when cross vendor migrating.
 951                  */
 952                 if (var->unusable)
 953                         var->db = 0;
 954                 break;
 955         }
 956 }
 957
 958 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 959 {
 960         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 961
 962         return save->cpl;
 963 }
 964
 965 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 966 {
 967         struct vcpu_svm *svm = to_svm(vcpu);
 968
 969         dt->size = svm->vmcb->save.idtr.limit;
 970         dt->address = svm->vmcb->save.idtr.base;
 971 }
 972
 973 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 974 {
 975         struct vcpu_svm *svm = to_svm(vcpu);
 976
 977         svm->vmcb->save.idtr.limit = dt->size;
 978         svm->vmcb->save.idtr.base = dt->address ;
 979 }
 980
 981 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 982 {
 983         struct vcpu_svm *svm = to_svm(vcpu);
 984
 985         dt->size = svm->vmcb->save.gdtr.limit;
 986         dt->address = svm->vmcb->save.gdtr.base;
 987 }
 988
 989 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 990 {
 991         struct vcpu_svm *svm = to_svm(vcpu);
 992
 993         svm->vmcb->save.gdtr.limit = dt->size;
 994         svm->vmcb->save.gdtr.base = dt->address ;
 995 }
 996
 997 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 998 {
 999 }
1000
1001 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1002 {
1003 }
1004
1005 static void update_cr0_intercept(struct vcpu_svm *svm)
1006 {
1007         struct vmcb *vmcb = svm->vmcb;
1008         ulong gcr0 = svm->vcpu.arch.cr0;
1009         u64 *hcr0 = &svm->vmcb->save.cr0;
1010
1011         if (!svm->vcpu.fpu_active)
1012                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1013         else
1014                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1015                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1016
1017
1018         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1019                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1020                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1021                 if (is_nested(svm)) {
1022                         struct vmcb *hsave = svm->nested.hsave;
1023
1024                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1025                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1026                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1027                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1028                 }
1029         } else {
1030                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1031                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1032                 if (is_nested(svm)) {
1033                         struct vmcb *hsave = svm->nested.hsave;
1034
1035                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1036                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1037                 }
1038         }
1039 }
1040
1041 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1042 {
1043         struct vcpu_svm *svm = to_svm(vcpu);
1044
1045 #ifdef CONFIG_X86_64
1046         if (vcpu->arch.efer & EFER_LME) {
1047                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1048                         vcpu->arch.efer |= EFER_LMA;
1049                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1050                 }
1051
1052                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1053                         vcpu->arch.efer &= ~EFER_LMA;
1054                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1055                 }
1056         }
1057 #endif
1058         vcpu->arch.cr0 = cr0;
1059
1060         if (!npt_enabled)
1061                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1062
1063         if (!vcpu->fpu_active)
1064                 cr0 |= X86_CR0_TS;
1065         /*
1066          * re-enable caching here because the QEMU bios
1067          * does not do it - this results in some delay at
1068          * reboot
1069          */
1070         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1071         svm->vmcb->save.cr0 = cr0;
1072         update_cr0_intercept(svm);
1073 }
1074
1075 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1076 {
1077         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1078         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1079
1080         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1081                 force_new_asid(vcpu);
1082
1083         vcpu->arch.cr4 = cr4;
1084         if (!npt_enabled)
1085                 cr4 |= X86_CR4_PAE;
1086         cr4 |= host_cr4_mce;
1087         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1088 }
1089
1090 static void svm_set_segment(struct kvm_vcpu *vcpu,
1091                             struct kvm_segment *var, int seg)
1092 {
1093         struct vcpu_svm *svm = to_svm(vcpu);
1094         struct vmcb_seg *s = svm_seg(vcpu, seg);
1095
1096         s->base = var->base;
1097         s->limit = var->limit;
1098         s->selector = var->selector;
1099         if (var->unusable)
1100                 s->attrib = 0;
1101         else {
1102                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1103                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1104                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1105                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1106                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1107                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1108                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1109                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1110         }
1111         if (seg == VCPU_SREG_CS)
1112                 svm->vmcb->save.cpl
1113                         = (svm->vmcb->save.cs.attrib
1114                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1115
1116 }
1117
1118 static void update_db_intercept(struct kvm_vcpu *vcpu)
1119 {
1120         struct vcpu_svm *svm = to_svm(vcpu);
1121
1122         svm->vmcb->control.intercept_exceptions &=
1123                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1124
1125         if (svm->nmi_singlestep)
1126                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1127
1128         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1129                 if (vcpu->guest_debug &
1130                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1131                         svm->vmcb->control.intercept_exceptions |=
1132                                 1 << DB_VECTOR;
1133                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1134                         svm->vmcb->control.intercept_exceptions |=
1135                                 1 << BP_VECTOR;
1136         } else
1137                 vcpu->guest_debug = 0;
1138 }
1139
1140 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1141 {
1142         struct vcpu_svm *svm = to_svm(vcpu);
1143
1144         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1145                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1146         else
1147                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1148
1149         update_db_intercept(vcpu);
1150 }
1151
1152 static void load_host_msrs(struct kvm_vcpu *vcpu)
1153 {
1154 #ifdef CONFIG_X86_64
1155         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1156 #endif
1157 }
1158
1159 static void save_host_msrs(struct kvm_vcpu *vcpu)
1160 {
1161 #ifdef CONFIG_X86_64
1162         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1163 #endif
1164 }
1165
1166 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1167 {
1168         if (sd->next_asid > sd->max_asid) {
1169                 ++sd->asid_generation;
1170                 sd->next_asid = 1;
1171                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1172         }
1173
1174         svm->asid_generation = sd->asid_generation;
1175         svm->vmcb->control.asid = sd->next_asid++;
1176 }
1177
1178 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1179 {
1180         struct vcpu_svm *svm = to_svm(vcpu);
1181
1182         switch (dr) {
1183         case 0 ... 3:
1184                 *dest = vcpu->arch.db[dr];
1185                 break;
1186         case 4:
1187                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1188                         return EMULATE_FAIL; /* will re-inject UD */
1189                 /* fall through */
1190         case 6:
1191                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1192                         *dest = vcpu->arch.dr6;
1193                 else
1194                         *dest = svm->vmcb->save.dr6;
1195                 break;
1196         case 5:
1197                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1198                         return EMULATE_FAIL; /* will re-inject UD */
1199                 /* fall through */
1200         case 7:
1201                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1202                         *dest = vcpu->arch.dr7;
1203                 else
1204                         *dest = svm->vmcb->save.dr7;
1205                 break;
1206         }
1207
1208         return EMULATE_DONE;
1209 }
1210
1211 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1212 {
1213         struct vcpu_svm *svm = to_svm(vcpu);
1214
1215         switch (dr) {
1216         case 0 ... 3:
1217                 vcpu->arch.db[dr] = value;
1218                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1219                         vcpu->arch.eff_db[dr] = value;
1220                 break;
1221         case 4:
1222                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1223                         return EMULATE_FAIL; /* will re-inject UD */
1224                 /* fall through */
1225         case 6:
1226                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1227                 break;
1228         case 5:
1229                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1230                         return EMULATE_FAIL; /* will re-inject UD */
1231                 /* fall through */
1232         case 7:
1233                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1234                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1235                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1236                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1237                 }
1238                 break;
1239         }
1240
1241         return EMULATE_DONE;
1242 }
1243
1244 static int pf_interception(struct vcpu_svm *svm)
1245 {
1246         u64 fault_address;
1247         u32 error_code;
1248
1249         fault_address  = svm->vmcb->control.exit_info_2;
1250         error_code = svm->vmcb->control.exit_info_1;
1251
1252         trace_kvm_page_fault(fault_address, error_code);
1253         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1254                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1255         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1256 }
1257
1258 static int db_interception(struct vcpu_svm *svm)
1259 {
1260         struct kvm_run *kvm_run = svm->vcpu.run;
1261
1262         if (!(svm->vcpu.guest_debug &
1263               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1264                 !svm->nmi_singlestep) {
1265                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1266                 return 1;
1267         }
1268
1269         if (svm->nmi_singlestep) {
1270                 svm->nmi_singlestep = false;
1271                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1272                         svm->vmcb->save.rflags &=
1273                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1274                 update_db_intercept(&svm->vcpu);
1275         }
1276
1277         if (svm->vcpu.guest_debug &
1278             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1279                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1280                 kvm_run->debug.arch.pc =
1281                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1282                 kvm_run->debug.arch.exception = DB_VECTOR;
1283                 return 0;
1284         }
1285
1286         return 1;
1287 }
1288
1289 static int bp_interception(struct vcpu_svm *svm)
1290 {
1291         struct kvm_run *kvm_run = svm->vcpu.run;
1292
1293         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1294         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1295         kvm_run->debug.arch.exception = BP_VECTOR;
1296         return 0;
1297 }
1298
1299 static int ud_interception(struct vcpu_svm *svm)
1300 {
1301         int er;
1302
1303         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1304         if (er != EMULATE_DONE)
1305                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1306         return 1;
1307 }
1308
1309 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1310 {
1311         struct vcpu_svm *svm = to_svm(vcpu);
1312         u32 excp;
1313
1314         if (is_nested(svm)) {
1315                 u32 h_excp, n_excp;
1316
1317                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1318                 n_excp  = svm->nested.intercept_exceptions;
1319                 h_excp &= ~(1 << NM_VECTOR);
1320                 excp    = h_excp | n_excp;
1321         } else {
1322                 excp  = svm->vmcb->control.intercept_exceptions;
1323                 excp &= ~(1 << NM_VECTOR);
1324         }
1325
1326         svm->vmcb->control.intercept_exceptions = excp;
1327
1328         svm->vcpu.fpu_active = 1;
1329         update_cr0_intercept(svm);
1330 }
1331
1332 static int nm_interception(struct vcpu_svm *svm)
1333 {
1334         svm_fpu_activate(&svm->vcpu);
1335         return 1;
1336 }
1337
1338 static int mc_interception(struct vcpu_svm *svm)
1339 {
1340         /*
1341          * On an #MC intercept the MCE handler is not called automatically in
1342          * the host. So do it by hand here.
1343          */
1344         asm volatile (
1345                 "int $0x12\n");
1346         /* not sure if we ever come back to this point */
1347
1348         return 1;
1349 }
1350
1351 static int shutdown_interception(struct vcpu_svm *svm)
1352 {
1353         struct kvm_run *kvm_run = svm->vcpu.run;
1354
1355         /*
1356          * VMCB is undefined after a SHUTDOWN intercept
1357          * so reinitialize it.
1358          */
1359         clear_page(svm->vmcb);
1360         init_vmcb(svm);
1361
1362         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1363         return 0;
1364 }
1365
1366 static int io_interception(struct vcpu_svm *svm)
1367 {
1368         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1369         int size, in, string;
1370         unsigned port;
1371
1372         ++svm->vcpu.stat.io_exits;
1373
1374         svm->next_rip = svm->vmcb->control.exit_info_2;
1375
1376         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1377
1378         if (string) {
1379                 if (emulate_instruction(&svm->vcpu,
1380                                         0, 0, 0) == EMULATE_DO_MMIO)
1381                         return 0;
1382                 return 1;
1383         }
1384
1385         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1386         port = io_info >> 16;
1387         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1388
1389         skip_emulated_instruction(&svm->vcpu);
1390         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1391 }
1392
1393 static int nmi_interception(struct vcpu_svm *svm)
1394 {
1395         return 1;
1396 }
1397
1398 static int intr_interception(struct vcpu_svm *svm)
1399 {
1400         ++svm->vcpu.stat.irq_exits;
1401         return 1;
1402 }
1403
1404 static int nop_on_interception(struct vcpu_svm *svm)
1405 {
1406         return 1;
1407 }
1408
1409 static int halt_interception(struct vcpu_svm *svm)
1410 {
1411         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1412         skip_emulated_instruction(&svm->vcpu);
1413         return kvm_emulate_halt(&svm->vcpu);
1414 }
1415
1416 static int vmmcall_interception(struct vcpu_svm *svm)
1417 {
1418         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1419         skip_emulated_instruction(&svm->vcpu);
1420         kvm_emulate_hypercall(&svm->vcpu);
1421         return 1;
1422 }
1423
1424 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1425 {
1426         if (!(svm->vcpu.arch.efer & EFER_SVME)
1427             || !is_paging(&svm->vcpu)) {
1428                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1429                 return 1;
1430         }
1431
1432         if (svm->vmcb->save.cpl) {
1433                 kvm_inject_gp(&svm->vcpu, 0);
1434                 return 1;
1435         }
1436
1437        return 0;
1438 }
1439
1440 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1441                                       bool has_error_code, u32 error_code)
1442 {
1443         int vmexit;
1444
1445         if (!is_nested(svm))
1446                 return 0;
1447
1448         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1449         svm->vmcb->control.exit_code_hi = 0;
1450         svm->vmcb->control.exit_info_1 = error_code;
1451         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1452
1453         vmexit = nested_svm_intercept(svm);
1454         if (vmexit == NESTED_EXIT_DONE)
1455                 svm->nested.exit_required = true;
1456
1457         return vmexit;
1458 }
1459
1460 /* This function returns true if it is save to enable the irq window */
1461 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1462 {
1463         if (!is_nested(svm))
1464                 return true;
1465
1466         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1467                 return true;
1468
1469         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1470                 return false;
1471
1472         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1473
1474         if (svm->nested.intercept & 1ULL) {
1475                 /*
1476                  * The #vmexit can't be emulated here directly because this
1477                  * code path runs with irqs and preemtion disabled. A
1478                  * #vmexit emulation might sleep. Only signal request for
1479                  * the #vmexit here.
1480                  */
1481                 svm->nested.exit_required = true;
1482                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1483                 return false;
1484         }
1485
1486         return true;
1487 }
1488
1489 /* This function returns true if it is save to enable the nmi window */
1490 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1491 {
1492         if (!is_nested(svm))
1493                 return true;
1494
1495         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1496                 return true;
1497
1498         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1499         svm->nested.exit_required = true;
1500
1501         return false;
1502 }
1503
1504 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1505 {
1506         struct page *page;
1507
1508         might_sleep();
1509
1510         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1511         if (is_error_page(page))
1512                 goto error;
1513
1514         *_page = page;
1515
1516         return kmap(page);
1517
1518 error:
1519         kvm_release_page_clean(page);
1520         kvm_inject_gp(&svm->vcpu, 0);
1521
1522         return NULL;
1523 }
1524
1525 static void nested_svm_unmap(struct page *page)
1526 {
1527         kunmap(page);
1528         kvm_release_page_dirty(page);
1529 }
1530
1531 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1532 {
1533         u32 param = svm->vmcb->control.exit_info_1 & 1;
1534         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1535         bool ret = false;
1536         u32 t0, t1;
1537         u8 val;
1538
1539         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1540                 return false;
1541
1542         switch (msr) {
1543         case 0 ... 0x1fff:
1544                 t0 = (msr * 2) % 8;
1545                 t1 = msr / 8;
1546                 break;
1547         case 0xc0000000 ... 0xc0001fff:
1548                 t0 = (8192 + msr - 0xc0000000) * 2;
1549                 t1 = (t0 / 8);
1550                 t0 %= 8;
1551                 break;
1552         case 0xc0010000 ... 0xc0011fff:
1553                 t0 = (16384 + msr - 0xc0010000) * 2;
1554                 t1 = (t0 / 8);
1555                 t0 %= 8;
1556                 break;
1557         default:
1558                 ret = true;
1559                 goto out;
1560         }
1561
1562         if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1563                 ret = val & ((1 << param) << t0);
1564
1565 out:
1566         return ret;
1567 }
1568
1569 static int nested_svm_exit_special(struct vcpu_svm *svm)
1570 {
1571         u32 exit_code = svm->vmcb->control.exit_code;
1572
1573         switch (exit_code) {
1574         case SVM_EXIT_INTR:
1575         case SVM_EXIT_NMI:
1576                 return NESTED_EXIT_HOST;
1577         case SVM_EXIT_NPF:
1578                 /* For now we are always handling NPFs when using them */
1579                 if (npt_enabled)
1580                         return NESTED_EXIT_HOST;
1581                 break;
1582         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1583                 /* When we're shadowing, trap PFs */
1584                 if (!npt_enabled)
1585                         return NESTED_EXIT_HOST;
1586                 break;
1587         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1588                 nm_interception(svm);
1589                 break;
1590         default:
1591                 break;
1592         }
1593
1594         return NESTED_EXIT_CONTINUE;
1595 }
1596
1597 /*
1598  * If this function returns true, this #vmexit was already handled
1599  */
1600 static int nested_svm_intercept(struct vcpu_svm *svm)
1601 {
1602         u32 exit_code = svm->vmcb->control.exit_code;
1603         int vmexit = NESTED_EXIT_HOST;
1604
1605         switch (exit_code) {
1606         case SVM_EXIT_MSR:
1607                 vmexit = nested_svm_exit_handled_msr(svm);
1608                 break;
1609         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1610                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1611                 if (svm->nested.intercept_cr_read & cr_bits)
1612                         vmexit = NESTED_EXIT_DONE;
1613                 break;
1614         }
1615         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1616                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1617                 if (svm->nested.intercept_cr_write & cr_bits)
1618                         vmexit = NESTED_EXIT_DONE;
1619                 break;
1620         }
1621         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1622                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1623                 if (svm->nested.intercept_dr_read & dr_bits)
1624                         vmexit = NESTED_EXIT_DONE;
1625                 break;
1626         }
1627         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1628                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1629                 if (svm->nested.intercept_dr_write & dr_bits)
1630                         vmexit = NESTED_EXIT_DONE;
1631                 break;
1632         }
1633         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1634                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1635                 if (svm->nested.intercept_exceptions & excp_bits)
1636                         vmexit = NESTED_EXIT_DONE;
1637                 break;
1638         }
1639         default: {
1640                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1641                 if (svm->nested.intercept & exit_bits)
1642                         vmexit = NESTED_EXIT_DONE;
1643         }
1644         }
1645
1646         return vmexit;
1647 }
1648
1649 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1650 {
1651         int vmexit;
1652
1653         vmexit = nested_svm_intercept(svm);
1654
1655         if (vmexit == NESTED_EXIT_DONE)
1656                 nested_svm_vmexit(svm);
1657
1658         return vmexit;
1659 }
1660
1661 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1662 {
1663         struct vmcb_control_area *dst  = &dst_vmcb->control;
1664         struct vmcb_control_area *from = &from_vmcb->control;
1665
1666         dst->intercept_cr_read    = from->intercept_cr_read;
1667         dst->intercept_cr_write   = from->intercept_cr_write;
1668         dst->intercept_dr_read    = from->intercept_dr_read;
1669         dst->intercept_dr_write   = from->intercept_dr_write;
1670         dst->intercept_exceptions = from->intercept_exceptions;
1671         dst->intercept            = from->intercept;
1672         dst->iopm_base_pa         = from->iopm_base_pa;
1673         dst->msrpm_base_pa        = from->msrpm_base_pa;
1674         dst->tsc_offset           = from->tsc_offset;
1675         dst->asid                 = from->asid;
1676         dst->tlb_ctl              = from->tlb_ctl;
1677         dst->int_ctl              = from->int_ctl;
1678         dst->int_vector           = from->int_vector;
1679         dst->int_state            = from->int_state;
1680         dst->exit_code            = from->exit_code;
1681         dst->exit_code_hi         = from->exit_code_hi;
1682         dst->exit_info_1          = from->exit_info_1;
1683         dst->exit_info_2          = from->exit_info_2;
1684         dst->exit_int_info        = from->exit_int_info;
1685         dst->exit_int_info_err    = from->exit_int_info_err;
1686         dst->nested_ctl           = from->nested_ctl;
1687         dst->event_inj            = from->event_inj;
1688         dst->event_inj_err        = from->event_inj_err;
1689         dst->nested_cr3           = from->nested_cr3;
1690         dst->lbr_ctl              = from->lbr_ctl;
1691 }
1692
1693 static int nested_svm_vmexit(struct vcpu_svm *svm)
1694 {
1695         struct vmcb *nested_vmcb;
1696         struct vmcb *hsave = svm->nested.hsave;
1697         struct vmcb *vmcb = svm->vmcb;
1698         struct page *page;
1699
1700         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1701                                        vmcb->control.exit_info_1,
1702                                        vmcb->control.exit_info_2,
1703                                        vmcb->control.exit_int_info,
1704                                        vmcb->control.exit_int_info_err);
1705
1706         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1707         if (!nested_vmcb)
1708                 return 1;
1709
1710         /* Exit nested SVM mode */
1711         svm->nested.vmcb = 0;
1712
1713         /* Give the current vmcb to the guest */
1714         disable_gif(svm);
1715
1716         nested_vmcb->save.es     = vmcb->save.es;
1717         nested_vmcb->save.cs     = vmcb->save.cs;
1718         nested_vmcb->save.ss     = vmcb->save.ss;
1719         nested_vmcb->save.ds     = vmcb->save.ds;
1720         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1721         nested_vmcb->save.idtr   = vmcb->save.idtr;
1722         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1723         if (npt_enabled)
1724                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1725         else
1726                 nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1727         nested_vmcb->save.cr2    = vmcb->save.cr2;
1728         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1729         nested_vmcb->save.rflags = vmcb->save.rflags;
1730         nested_vmcb->save.rip    = vmcb->save.rip;
1731         nested_vmcb->save.rsp    = vmcb->save.rsp;
1732         nested_vmcb->save.rax    = vmcb->save.rax;
1733         nested_vmcb->save.dr7    = vmcb->save.dr7;
1734         nested_vmcb->save.dr6    = vmcb->save.dr6;
1735         nested_vmcb->save.cpl    = vmcb->save.cpl;
1736
1737         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1738         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1739         nested_vmcb->control.int_state         = vmcb->control.int_state;
1740         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1741         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1742         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1743         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1744         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1745         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1746
1747         /*
1748          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1749          * to make sure that we do not lose injected events. So check event_inj
1750          * here and copy it to exit_int_info if it is valid.
1751          * Exit_int_info and event_inj can't be both valid because the case
1752          * below only happens on a VMRUN instruction intercept which has
1753          * no valid exit_int_info set.
1754          */
1755         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1756                 struct vmcb_control_area *nc = &nested_vmcb->control;
1757
1758                 nc->exit_int_info     = vmcb->control.event_inj;
1759                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1760         }
1761
1762         nested_vmcb->control.tlb_ctl           = 0;
1763         nested_vmcb->control.event_inj         = 0;
1764         nested_vmcb->control.event_inj_err     = 0;
1765
1766         /* We always set V_INTR_MASKING and remember the old value in hflags */
1767         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1768                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1769
1770         /* Restore the original control entries */
1771         copy_vmcb_control_area(vmcb, hsave);
1772
1773         kvm_clear_exception_queue(&svm->vcpu);
1774         kvm_clear_interrupt_queue(&svm->vcpu);
1775
1776         /* Restore selected save entries */
1777         svm->vmcb->save.es = hsave->save.es;
1778         svm->vmcb->save.cs = hsave->save.cs;
1779         svm->vmcb->save.ss = hsave->save.ss;
1780         svm->vmcb->save.ds = hsave->save.ds;
1781         svm->vmcb->save.gdtr = hsave->save.gdtr;
1782         svm->vmcb->save.idtr = hsave->save.idtr;
1783         svm->vmcb->save.rflags = hsave->save.rflags;
1784         svm_set_efer(&svm->vcpu, hsave->save.efer);
1785         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1786         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1787         if (npt_enabled) {
1788                 svm->vmcb->save.cr3 = hsave->save.cr3;
1789                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1790         } else {
1791                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1792         }
1793         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1794         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1795         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1796         svm->vmcb->save.dr7 = 0;
1797         svm->vmcb->save.cpl = 0;
1798         svm->vmcb->control.exit_int_info = 0;
1799
1800         nested_svm_unmap(page);
1801
1802         kvm_mmu_reset_context(&svm->vcpu);
1803         kvm_mmu_load(&svm->vcpu);
1804
1805         return 0;
1806 }
1807
1808 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1809 {
1810         u32 *nested_msrpm;
1811         struct page *page;
1812         int i;
1813
1814         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
1815         if (!nested_msrpm)
1816                 return false;
1817
1818         for (i = 0; i < PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1819                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1820
1821         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1822
1823         nested_svm_unmap(page);
1824
1825         return true;
1826 }
1827
1828 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1829 {
1830         struct vmcb *nested_vmcb;
1831         struct vmcb *hsave = svm->nested.hsave;
1832         struct vmcb *vmcb = svm->vmcb;
1833         struct page *page;
1834         u64 vmcb_gpa;
1835
1836         vmcb_gpa = svm->vmcb->save.rax;
1837
1838         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1839         if (!nested_vmcb)
1840                 return false;
1841
1842         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1843                                nested_vmcb->save.rip,
1844                                nested_vmcb->control.int_ctl,
1845                                nested_vmcb->control.event_inj,
1846                                nested_vmcb->control.nested_ctl);
1847
1848         /* Clear internal status */
1849         kvm_clear_exception_queue(&svm->vcpu);
1850         kvm_clear_interrupt_queue(&svm->vcpu);
1851
1852         /*
1853          * Save the old vmcb, so we don't need to pick what we save, but can
1854          * restore everything when a VMEXIT occurs
1855          */
1856         hsave->save.es     = vmcb->save.es;
1857         hsave->save.cs     = vmcb->save.cs;
1858         hsave->save.ss     = vmcb->save.ss;
1859         hsave->save.ds     = vmcb->save.ds;
1860         hsave->save.gdtr   = vmcb->save.gdtr;
1861         hsave->save.idtr   = vmcb->save.idtr;
1862         hsave->save.efer   = svm->vcpu.arch.efer;
1863         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1864         hsave->save.cr4    = svm->vcpu.arch.cr4;
1865         hsave->save.rflags = vmcb->save.rflags;
1866         hsave->save.rip    = svm->next_rip;
1867         hsave->save.rsp    = vmcb->save.rsp;
1868         hsave->save.rax    = vmcb->save.rax;
1869         if (npt_enabled)
1870                 hsave->save.cr3    = vmcb->save.cr3;
1871         else
1872                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1873
1874         copy_vmcb_control_area(hsave, vmcb);
1875
1876         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1877                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1878         else
1879                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1880
1881         /* Load the nested guest state */
1882         svm->vmcb->save.es = nested_vmcb->save.es;
1883         svm->vmcb->save.cs = nested_vmcb->save.cs;
1884         svm->vmcb->save.ss = nested_vmcb->save.ss;
1885         svm->vmcb->save.ds = nested_vmcb->save.ds;
1886         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1887         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1888         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1889         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1890         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1891         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1892         if (npt_enabled) {
1893                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1894                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1895         } else
1896                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1897
1898         /* Guest paging mode is active - reset mmu */
1899         kvm_mmu_reset_context(&svm->vcpu);
1900
1901         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1902         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1903         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1904         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1905
1906         /* In case we don't even reach vcpu_run, the fields are not updated */
1907         svm->vmcb->save.rax = nested_vmcb->save.rax;
1908         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1909         svm->vmcb->save.rip = nested_vmcb->save.rip;
1910         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1911         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1912         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1913
1914         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1915
1916         /* cache intercepts */
1917         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1918         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1919         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1920         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1921         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1922         svm->nested.intercept            = nested_vmcb->control.intercept;
1923
1924         force_new_asid(&svm->vcpu);
1925         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1926         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1927                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1928         else
1929                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1930
1931         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1932                 /* We only want the cr8 intercept bits of the guest */
1933                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1934                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1935         }
1936
1937         /*
1938          * We don't want a nested guest to be more powerful than the guest, so
1939          * all intercepts are ORed
1940          */
1941         svm->vmcb->control.intercept_cr_read |=
1942                 nested_vmcb->control.intercept_cr_read;
1943         svm->vmcb->control.intercept_cr_write |=
1944                 nested_vmcb->control.intercept_cr_write;
1945         svm->vmcb->control.intercept_dr_read |=
1946                 nested_vmcb->control.intercept_dr_read;
1947         svm->vmcb->control.intercept_dr_write |=
1948                 nested_vmcb->control.intercept_dr_write;
1949         svm->vmcb->control.intercept_exceptions |=
1950                 nested_vmcb->control.intercept_exceptions;
1951
1952         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1953
1954         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
1955         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1956         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1957         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1958         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1959         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1960
1961         nested_svm_unmap(page);
1962
1963         /* nested_vmcb is our indicator if nested SVM is activated */
1964         svm->nested.vmcb = vmcb_gpa;
1965
1966         enable_gif(svm);
1967
1968         return true;
1969 }
1970
1971 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1972 {
1973         to_vmcb->save.fs = from_vmcb->save.fs;
1974         to_vmcb->save.gs = from_vmcb->save.gs;
1975         to_vmcb->save.tr = from_vmcb->save.tr;
1976         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1977         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1978         to_vmcb->save.star = from_vmcb->save.star;
1979         to_vmcb->save.lstar = from_vmcb->save.lstar;
1980         to_vmcb->save.cstar = from_vmcb->save.cstar;
1981         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1982         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1983         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1984         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1985 }
1986
1987 static int vmload_interception(struct vcpu_svm *svm)
1988 {
1989         struct vmcb *nested_vmcb;
1990         struct page *page;
1991
1992         if (nested_svm_check_permissions(svm))
1993                 return 1;
1994
1995         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1996         skip_emulated_instruction(&svm->vcpu);
1997
1998         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1999         if (!nested_vmcb)
2000                 return 1;
2001
2002         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2003         nested_svm_unmap(page);
2004
2005         return 1;
2006 }
2007
2008 static int vmsave_interception(struct vcpu_svm *svm)
2009 {
2010         struct vmcb *nested_vmcb;
2011         struct page *page;
2012
2013         if (nested_svm_check_permissions(svm))
2014                 return 1;
2015
2016         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2017         skip_emulated_instruction(&svm->vcpu);
2018
2019         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2020         if (!nested_vmcb)
2021                 return 1;
2022
2023         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2024         nested_svm_unmap(page);
2025
2026         return 1;
2027 }
2028
2029 static int vmrun_interception(struct vcpu_svm *svm)
2030 {
2031         if (nested_svm_check_permissions(svm))
2032                 return 1;
2033
2034         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2035         skip_emulated_instruction(&svm->vcpu);
2036
2037         if (!nested_svm_vmrun(svm))
2038                 return 1;
2039
2040         if (!nested_svm_vmrun_msrpm(svm))
2041                 goto failed;
2042
2043         return 1;
2044
2045 failed:
2046
2047         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2048         svm->vmcb->control.exit_code_hi = 0;
2049         svm->vmcb->control.exit_info_1  = 0;
2050         svm->vmcb->control.exit_info_2  = 0;
2051
2052         nested_svm_vmexit(svm);
2053
2054         return 1;
2055 }
2056
2057 static int stgi_interception(struct vcpu_svm *svm)
2058 {
2059         if (nested_svm_check_permissions(svm))
2060                 return 1;
2061
2062         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2063         skip_emulated_instruction(&svm->vcpu);
2064
2065         enable_gif(svm);
2066
2067         return 1;
2068 }
2069
2070 static int clgi_interception(struct vcpu_svm *svm)
2071 {
2072         if (nested_svm_check_permissions(svm))
2073                 return 1;
2074
2075         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2076         skip_emulated_instruction(&svm->vcpu);
2077
2078         disable_gif(svm);
2079
2080         /* After a CLGI no interrupts should come */
2081         svm_clear_vintr(svm);
2082         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2083
2084         return 1;
2085 }
2086
2087 static int invlpga_interception(struct vcpu_svm *svm)
2088 {
2089         struct kvm_vcpu *vcpu = &svm->vcpu;
2090
2091         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2092                           vcpu->arch.regs[VCPU_REGS_RAX]);
2093
2094         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2095         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2096
2097         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2098         skip_emulated_instruction(&svm->vcpu);
2099         return 1;
2100 }
2101
2102 static int skinit_interception(struct vcpu_svm *svm)
2103 {
2104         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2105
2106         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2107         return 1;
2108 }
2109
2110 static int invalid_op_interception(struct vcpu_svm *svm)
2111 {
2112         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2113         return 1;
2114 }
2115
2116 static int task_switch_interception(struct vcpu_svm *svm)
2117 {
2118         u16 tss_selector;
2119         int reason;
2120         int int_type = svm->vmcb->control.exit_int_info &
2121                 SVM_EXITINTINFO_TYPE_MASK;
2122         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2123         uint32_t type =
2124                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2125         uint32_t idt_v =
2126                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2127
2128         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2129
2130         if (svm->vmcb->control.exit_info_2 &
2131             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2132                 reason = TASK_SWITCH_IRET;
2133         else if (svm->vmcb->control.exit_info_2 &
2134                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2135                 reason = TASK_SWITCH_JMP;
2136         else if (idt_v)
2137                 reason = TASK_SWITCH_GATE;
2138         else
2139                 reason = TASK_SWITCH_CALL;
2140
2141         if (reason == TASK_SWITCH_GATE) {
2142                 switch (type) {
2143                 case SVM_EXITINTINFO_TYPE_NMI:
2144                         svm->vcpu.arch.nmi_injected = false;
2145                         break;
2146                 case SVM_EXITINTINFO_TYPE_EXEPT:
2147                         kvm_clear_exception_queue(&svm->vcpu);
2148                         break;
2149                 case SVM_EXITINTINFO_TYPE_INTR:
2150                         kvm_clear_interrupt_queue(&svm->vcpu);
2151                         break;
2152                 default:
2153                         break;
2154                 }
2155         }
2156
2157         if (reason != TASK_SWITCH_GATE ||
2158             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2159             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2160              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2161                 skip_emulated_instruction(&svm->vcpu);
2162
2163         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2164 }
2165
2166 static int cpuid_interception(struct vcpu_svm *svm)
2167 {
2168         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2169         kvm_emulate_cpuid(&svm->vcpu);
2170         return 1;
2171 }
2172
2173 static int iret_interception(struct vcpu_svm *svm)
2174 {
2175         ++svm->vcpu.stat.nmi_window_exits;
2176         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2177         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2178         return 1;
2179 }
2180
2181 static int invlpg_interception(struct vcpu_svm *svm)
2182 {
2183         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2184                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2185         return 1;
2186 }
2187
2188 static int emulate_on_interception(struct vcpu_svm *svm)
2189 {
2190         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2191                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2192         return 1;
2193 }
2194
2195 static int cr8_write_interception(struct vcpu_svm *svm)
2196 {
2197         struct kvm_run *kvm_run = svm->vcpu.run;
2198
2199         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2200         /* instruction emulation calls kvm_set_cr8() */
2201         emulate_instruction(&svm->vcpu, 0, 0, 0);
2202         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2203                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2204                 return 1;
2205         }
2206         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2207                 return 1;
2208         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2209         return 0;
2210 }
2211
2212 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2213 {
2214         struct vcpu_svm *svm = to_svm(vcpu);
2215
2216         switch (ecx) {
2217         case MSR_IA32_TSC: {
2218                 u64 tsc_offset;
2219
2220                 if (is_nested(svm))
2221                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2222                 else
2223                         tsc_offset = svm->vmcb->control.tsc_offset;
2224
2225                 *data = tsc_offset + native_read_tsc();
2226                 break;
2227         }
2228         case MSR_K6_STAR:
2229                 *data = svm->vmcb->save.star;
2230                 break;
2231 #ifdef CONFIG_X86_64
2232         case MSR_LSTAR:
2233                 *data = svm->vmcb->save.lstar;
2234                 break;
2235         case MSR_CSTAR:
2236                 *data = svm->vmcb->save.cstar;
2237                 break;
2238         case MSR_KERNEL_GS_BASE:
2239                 *data = svm->vmcb->save.kernel_gs_base;
2240                 break;
2241         case MSR_SYSCALL_MASK:
2242                 *data = svm->vmcb->save.sfmask;
2243                 break;
2244 #endif
2245         case MSR_IA32_SYSENTER_CS:
2246                 *data = svm->vmcb->save.sysenter_cs;
2247                 break;
2248         case MSR_IA32_SYSENTER_EIP:
2249                 *data = svm->sysenter_eip;
2250                 break;
2251         case MSR_IA32_SYSENTER_ESP:
2252                 *data = svm->sysenter_esp;
2253                 break;
2254         /*
2255          * Nobody will change the following 5 values in the VMCB so we can
2256          * safely return them on rdmsr. They will always be 0 until LBRV is
2257          * implemented.
2258          */
2259         case MSR_IA32_DEBUGCTLMSR:
2260                 *data = svm->vmcb->save.dbgctl;
2261                 break;
2262         case MSR_IA32_LASTBRANCHFROMIP:
2263                 *data = svm->vmcb->save.br_from;
2264                 break;
2265         case MSR_IA32_LASTBRANCHTOIP:
2266                 *data = svm->vmcb->save.br_to;
2267                 break;
2268         case MSR_IA32_LASTINTFROMIP:
2269                 *data = svm->vmcb->save.last_excp_from;
2270                 break;
2271         case MSR_IA32_LASTINTTOIP:
2272                 *data = svm->vmcb->save.last_excp_to;
2273                 break;
2274         case MSR_VM_HSAVE_PA:
2275                 *data = svm->nested.hsave_msr;
2276                 break;
2277         case MSR_VM_CR:
2278                 *data = 0;
2279                 break;
2280         case MSR_IA32_UCODE_REV:
2281                 *data = 0x01000065;
2282                 break;
2283         default:
2284                 return kvm_get_msr_common(vcpu, ecx, data);
2285         }
2286         return 0;
2287 }
2288
2289 static int rdmsr_interception(struct vcpu_svm *svm)
2290 {
2291         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2292         u64 data;
2293
2294         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2295                 trace_kvm_msr_read_ex(ecx);
2296                 kvm_inject_gp(&svm->vcpu, 0);
2297         } else {
2298                 trace_kvm_msr_read(ecx, data);
2299
2300                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2301                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2302                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2303                 skip_emulated_instruction(&svm->vcpu);
2304         }
2305         return 1;
2306 }
2307
2308 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2309 {
2310         struct vcpu_svm *svm = to_svm(vcpu);
2311
2312         switch (ecx) {
2313         case MSR_IA32_TSC: {
2314                 u64 tsc_offset = data - native_read_tsc();
2315                 u64 g_tsc_offset = 0;
2316
2317                 if (is_nested(svm)) {
2318                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2319                                        svm->nested.hsave->control.tsc_offset;
2320                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2321                 }
2322
2323                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2324
2325                 break;
2326         }
2327         case MSR_K6_STAR:
2328                 svm->vmcb->save.star = data;
2329                 break;
2330 #ifdef CONFIG_X86_64
2331         case MSR_LSTAR:
2332                 svm->vmcb->save.lstar = data;
2333                 break;
2334         case MSR_CSTAR:
2335                 svm->vmcb->save.cstar = data;
2336                 break;
2337         case MSR_KERNEL_GS_BASE:
2338                 svm->vmcb->save.kernel_gs_base = data;
2339                 break;
2340         case MSR_SYSCALL_MASK:
2341                 svm->vmcb->save.sfmask = data;
2342                 break;
2343 #endif
2344         case MSR_IA32_SYSENTER_CS:
2345                 svm->vmcb->save.sysenter_cs = data;
2346                 break;
2347         case MSR_IA32_SYSENTER_EIP:
2348                 svm->sysenter_eip = data;
2349                 svm->vmcb->save.sysenter_eip = data;
2350                 break;
2351         case MSR_IA32_SYSENTER_ESP:
2352                 svm->sysenter_esp = data;
2353                 svm->vmcb->save.sysenter_esp = data;
2354                 break;
2355         case MSR_IA32_DEBUGCTLMSR:
2356                 if (!svm_has(SVM_FEATURE_LBRV)) {
2357                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2358                                         __func__, data);
2359                         break;
2360                 }
2361                 if (data & DEBUGCTL_RESERVED_BITS)
2362                         return 1;
2363
2364                 svm->vmcb->save.dbgctl = data;
2365                 if (data & (1ULL<<0))
2366                         svm_enable_lbrv(svm);
2367                 else
2368                         svm_disable_lbrv(svm);
2369                 break;
2370         case MSR_VM_HSAVE_PA:
2371                 svm->nested.hsave_msr = data;
2372                 break;
2373         case MSR_VM_CR:
2374         case MSR_VM_IGNNE:
2375                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2376                 break;
2377         default:
2378                 return kvm_set_msr_common(vcpu, ecx, data);
2379         }
2380         return 0;
2381 }
2382
2383 static int wrmsr_interception(struct vcpu_svm *svm)
2384 {
2385         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2386         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2387                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2388
2389
2390         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2391         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2392                 trace_kvm_msr_write_ex(ecx, data);
2393                 kvm_inject_gp(&svm->vcpu, 0);
2394         } else {
2395                 trace_kvm_msr_write(ecx, data);
2396                 skip_emulated_instruction(&svm->vcpu);
2397         }
2398         return 1;
2399 }
2400
2401 static int msr_interception(struct vcpu_svm *svm)
2402 {
2403         if (svm->vmcb->control.exit_info_1)
2404                 return wrmsr_interception(svm);
2405         else
2406                 return rdmsr_interception(svm);
2407 }
2408
2409 static int interrupt_window_interception(struct vcpu_svm *svm)
2410 {
2411         struct kvm_run *kvm_run = svm->vcpu.run;
2412
2413         svm_clear_vintr(svm);
2414         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2415         /*
2416          * If the user space waits to inject interrupts, exit as soon as
2417          * possible
2418          */
2419         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2420             kvm_run->request_interrupt_window &&
2421             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2422                 ++svm->vcpu.stat.irq_window_exits;
2423                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2424                 return 0;
2425         }
2426
2427         return 1;
2428 }
2429
2430 static int pause_interception(struct vcpu_svm *svm)
2431 {
2432         kvm_vcpu_on_spin(&(svm->vcpu));
2433         return 1;
2434 }
2435
2436 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2437         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2438         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2439         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2440         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2441         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2442         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2443         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2444         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2445         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2446         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2447         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2448         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2449         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2450         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2451         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2452         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2453         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2454         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2455         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2456         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2457         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2458         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2459         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2460         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2461         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2462         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2463         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2464         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2465         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2466         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2467         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2468         [SVM_EXIT_INTR]                         = intr_interception,
2469         [SVM_EXIT_NMI]                          = nmi_interception,
2470         [SVM_EXIT_SMI]                          = nop_on_interception,
2471         [SVM_EXIT_INIT]                         = nop_on_interception,
2472         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2473         [SVM_EXIT_CPUID]                        = cpuid_interception,
2474         [SVM_EXIT_IRET]                         = iret_interception,
2475         [SVM_EXIT_INVD]                         = emulate_on_interception,
2476         [SVM_EXIT_PAUSE]                        = pause_interception,
2477         [SVM_EXIT_HLT]                          = halt_interception,
2478         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2479         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2480         [SVM_EXIT_IOIO]                         = io_interception,
2481         [SVM_EXIT_MSR]                          = msr_interception,
2482         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2483         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2484         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2485         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2486         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2487         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2488         [SVM_EXIT_STGI]                         = stgi_interception,
2489         [SVM_EXIT_CLGI]                         = clgi_interception,
2490         [SVM_EXIT_SKINIT]                       = skinit_interception,
2491         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2492         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2493         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2494         [SVM_EXIT_NPF]                          = pf_interception,
2495 };
2496
2497 static int handle_exit(struct kvm_vcpu *vcpu)
2498 {
2499         struct vcpu_svm *svm = to_svm(vcpu);
2500         struct kvm_run *kvm_run = vcpu->run;
2501         u32 exit_code = svm->vmcb->control.exit_code;
2502
2503         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2504
2505         if (unlikely(svm->nested.exit_required)) {
2506                 nested_svm_vmexit(svm);
2507                 svm->nested.exit_required = false;
2508
2509                 return 1;
2510         }
2511
2512         if (is_nested(svm)) {
2513                 int vmexit;
2514
2515                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2516                                         svm->vmcb->control.exit_info_1,
2517                                         svm->vmcb->control.exit_info_2,
2518                                         svm->vmcb->control.exit_int_info,
2519                                         svm->vmcb->control.exit_int_info_err);
2520
2521                 vmexit = nested_svm_exit_special(svm);
2522
2523                 if (vmexit == NESTED_EXIT_CONTINUE)
2524                         vmexit = nested_svm_exit_handled(svm);
2525
2526                 if (vmexit == NESTED_EXIT_DONE)
2527                         return 1;
2528         }
2529
2530         svm_complete_interrupts(svm);
2531
2532         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2533                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2534         if (npt_enabled)
2535                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2536
2537         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2538                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2539                 kvm_run->fail_entry.hardware_entry_failure_reason
2540                         = svm->vmcb->control.exit_code;
2541                 return 0;
2542         }
2543
2544         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2545             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2546             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2547                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2548                        "exit_code 0x%x\n",
2549                        __func__, svm->vmcb->control.exit_int_info,
2550                        exit_code);
2551
2552         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2553             || !svm_exit_handlers[exit_code]) {
2554                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2555                 kvm_run->hw.hardware_exit_reason = exit_code;
2556                 return 0;
2557         }
2558
2559         return svm_exit_handlers[exit_code](svm);
2560 }
2561
2562 static void reload_tss(struct kvm_vcpu *vcpu)
2563 {
2564         int cpu = raw_smp_processor_id();
2565
2566         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2567         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2568         load_TR_desc();
2569 }
2570
2571 static void pre_svm_run(struct vcpu_svm *svm)
2572 {
2573         int cpu = raw_smp_processor_id();
2574
2575         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2576
2577         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2578         /* FIXME: handle wraparound of asid_generation */
2579         if (svm->asid_generation != sd->asid_generation)
2580                 new_asid(svm, sd);
2581 }
2582
2583 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2584 {
2585         struct vcpu_svm *svm = to_svm(vcpu);
2586
2587         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2588         vcpu->arch.hflags |= HF_NMI_MASK;
2589         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2590         ++vcpu->stat.nmi_injections;
2591 }
2592
2593 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2594 {
2595         struct vmcb_control_area *control;
2596
2597         trace_kvm_inj_virq(irq);
2598
2599         ++svm->vcpu.stat.irq_injections;
2600         control = &svm->vmcb->control;
2601         control->int_vector = irq;
2602         control->int_ctl &= ~V_INTR_PRIO_MASK;
2603         control->int_ctl |= V_IRQ_MASK |
2604                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2605 }
2606
2607 static void svm_set_irq(struct kvm_vcpu *vcpu)
2608 {
2609         struct vcpu_svm *svm = to_svm(vcpu);
2610
2611         BUG_ON(!(gif_set(svm)));
2612
2613         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2614                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2615 }
2616
2617 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2618 {
2619         struct vcpu_svm *svm = to_svm(vcpu);
2620
2621         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2622                 return;
2623
2624         if (irr == -1)
2625                 return;
2626
2627         if (tpr >= irr)
2628                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2629 }
2630
2631 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2632 {
2633         struct vcpu_svm *svm = to_svm(vcpu);
2634         struct vmcb *vmcb = svm->vmcb;
2635         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2636                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2637 }
2638
2639 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2640 {
2641         struct vcpu_svm *svm = to_svm(vcpu);
2642
2643         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2644 }
2645
2646 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2647 {
2648         struct vcpu_svm *svm = to_svm(vcpu);
2649
2650         if (masked) {
2651                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2652                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2653         } else {
2654                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2655                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2656         }
2657 }
2658
2659 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2660 {
2661         struct vcpu_svm *svm = to_svm(vcpu);
2662         struct vmcb *vmcb = svm->vmcb;
2663         int ret;
2664
2665         if (!gif_set(svm) ||
2666              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2667                 return 0;
2668
2669         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2670
2671         if (is_nested(svm))
2672                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2673
2674         return ret;
2675 }
2676
2677 static void enable_irq_window(struct kvm_vcpu *vcpu)
2678 {
2679         struct vcpu_svm *svm = to_svm(vcpu);
2680
2681         /*
2682          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2683          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
2684          * get that intercept, this function will be called again though and
2685          * we'll get the vintr intercept.
2686          */
2687         if (gif_set(svm) && nested_svm_intr(svm)) {
2688                 svm_set_vintr(svm);
2689                 svm_inject_irq(svm, 0x0);
2690         }
2691 }
2692
2693 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2694 {
2695         struct vcpu_svm *svm = to_svm(vcpu);
2696
2697         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2698             == HF_NMI_MASK)
2699                 return; /* IRET will cause a vm exit */
2700
2701         /*
2702          * Something prevents NMI from been injected. Single step over possible
2703          * problem (IRET or exception injection or interrupt shadow)
2704          */
2705         if (gif_set(svm) && nested_svm_nmi(svm)) {
2706                 svm->nmi_singlestep = true;
2707                 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2708                 update_db_intercept(vcpu);
2709         }
2710 }
2711
2712 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2713 {
2714         return 0;
2715 }
2716
2717 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2718 {
2719         force_new_asid(vcpu);
2720 }
2721
2722 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2723 {
2724 }
2725
2726 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2727 {
2728         struct vcpu_svm *svm = to_svm(vcpu);
2729
2730         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2731                 return;
2732
2733         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2734                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2735                 kvm_set_cr8(vcpu, cr8);
2736         }
2737 }
2738
2739 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2740 {
2741         struct vcpu_svm *svm = to_svm(vcpu);
2742         u64 cr8;
2743
2744         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2745                 return;
2746
2747         cr8 = kvm_get_cr8(vcpu);
2748         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2749         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2750 }
2751
2752 static void svm_complete_interrupts(struct vcpu_svm *svm)
2753 {
2754         u8 vector;
2755         int type;
2756         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2757         unsigned int3_injected = svm->int3_injected;
2758
2759         svm->int3_injected = 0;
2760
2761         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2762                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2763
2764         svm->vcpu.arch.nmi_injected = false;
2765         kvm_clear_exception_queue(&svm->vcpu);
2766         kvm_clear_interrupt_queue(&svm->vcpu);
2767
2768         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2769                 return;
2770
2771         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2772         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2773
2774         switch (type) {
2775         case SVM_EXITINTINFO_TYPE_NMI:
2776                 svm->vcpu.arch.nmi_injected = true;
2777                 break;
2778         case SVM_EXITINTINFO_TYPE_EXEPT:
2779                 if (is_nested(svm))
2780                         break;
2781                 /*
2782                  * In case of software exceptions, do not reinject the vector,
2783                  * but re-execute the instruction instead. Rewind RIP first
2784                  * if we emulated INT3 before.
2785                  */
2786                 if (kvm_exception_is_soft(vector)) {
2787                         if (vector == BP_VECTOR && int3_injected &&
2788                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2789                                 kvm_rip_write(&svm->vcpu,
2790                                               kvm_rip_read(&svm->vcpu) -
2791                                               int3_injected);
2792                         break;
2793                 }
2794                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2795                         u32 err = svm->vmcb->control.exit_int_info_err;
2796                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2797
2798                 } else
2799                         kvm_queue_exception(&svm->vcpu, vector);
2800                 break;
2801         case SVM_EXITINTINFO_TYPE_INTR:
2802                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2803                 break;
2804         default:
2805                 break;
2806         }
2807 }
2808
2809 #ifdef CONFIG_X86_64
2810 #define R "r"
2811 #else
2812 #define R "e"
2813 #endif
2814
2815 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2816 {
2817         struct vcpu_svm *svm = to_svm(vcpu);
2818         u16 fs_selector;
2819         u16 gs_selector;
2820         u16 ldt_selector;
2821
2822         /*
2823          * A vmexit emulation is required before the vcpu can be executed
2824          * again.
2825          */
2826         if (unlikely(svm->nested.exit_required))
2827                 return;
2828
2829         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2830         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2831         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2832
2833         pre_svm_run(svm);
2834
2835         sync_lapic_to_cr8(vcpu);
2836
2837         save_host_msrs(vcpu);
2838         fs_selector = kvm_read_fs();
2839         gs_selector = kvm_read_gs();
2840         ldt_selector = kvm_read_ldt();
2841         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2842         /* required for live migration with NPT */
2843         if (npt_enabled)
2844                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2845
2846         clgi();
2847
2848         local_irq_enable();
2849
2850         asm volatile (
2851                 "push %%"R"bp; \n\t"
2852                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2853                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2854                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2855                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2856                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2857                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2858 #ifdef CONFIG_X86_64
2859                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2860                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2861                 "mov %c[r10](%[svm]), %%r10 \n\t"
2862                 "mov %c[r11](%[svm]), %%r11 \n\t"
2863                 "mov %c[r12](%[svm]), %%r12 \n\t"
2864                 "mov %c[r13](%[svm]), %%r13 \n\t"
2865                 "mov %c[r14](%[svm]), %%r14 \n\t"
2866                 "mov %c[r15](%[svm]), %%r15 \n\t"
2867 #endif
2868
2869                 /* Enter guest mode */
2870                 "push %%"R"ax \n\t"
2871                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2872                 __ex(SVM_VMLOAD) "\n\t"
2873                 __ex(SVM_VMRUN) "\n\t"
2874                 __ex(SVM_VMSAVE) "\n\t"
2875                 "pop %%"R"ax \n\t"
2876
2877                 /* Save guest registers, load host registers */
2878                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2879                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2880                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2881                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2882                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2883                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2884 #ifdef CONFIG_X86_64
2885                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2886                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2887                 "mov %%r10, %c[r10](%[svm]) \n\t"
2888                 "mov %%r11, %c[r11](%[svm]) \n\t"
2889                 "mov %%r12, %c[r12](%[svm]) \n\t"
2890                 "mov %%r13, %c[r13](%[svm]) \n\t"
2891                 "mov %%r14, %c[r14](%[svm]) \n\t"
2892                 "mov %%r15, %c[r15](%[svm]) \n\t"
2893 #endif
2894                 "pop %%"R"bp"
2895                 :
2896                 : [svm]"a"(svm),
2897                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2898                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2899                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2900                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2901                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2902                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2903                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2904 #ifdef CONFIG_X86_64
2905                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2906                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2907                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2908                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2909                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2910                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2911                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2912                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2913 #endif
2914                 : "cc", "memory"
2915                 , R"bx", R"cx", R"dx", R"si", R"di"
2916 #ifdef CONFIG_X86_64
2917                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2918 #endif
2919                 );
2920
2921         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2922         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2923         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2924         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2925
2926         kvm_load_fs(fs_selector);
2927         kvm_load_gs(gs_selector);
2928         kvm_load_ldt(ldt_selector);
2929         load_host_msrs(vcpu);
2930
2931         reload_tss(vcpu);
2932
2933         local_irq_disable();
2934
2935         stgi();
2936
2937         sync_cr8_to_lapic(vcpu);
2938
2939         svm->next_rip = 0;
2940
2941         if (npt_enabled) {
2942                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2943                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2944         }
2945 }
2946
2947 #undef R
2948
2949 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2950 {
2951         struct vcpu_svm *svm = to_svm(vcpu);
2952
2953         if (npt_enabled) {
2954                 svm->vmcb->control.nested_cr3 = root;
2955                 force_new_asid(vcpu);
2956                 return;
2957         }
2958
2959         svm->vmcb->save.cr3 = root;
2960         force_new_asid(vcpu);
2961 }
2962
2963 static int is_disabled(void)
2964 {
2965         u64 vm_cr;
2966
2967         rdmsrl(MSR_VM_CR, vm_cr);
2968         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2969                 return 1;
2970
2971         return 0;
2972 }
2973
2974 static void
2975 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2976 {
2977         /*
2978          * Patch in the VMMCALL instruction:
2979          */
2980         hypercall[0] = 0x0f;
2981         hypercall[1] = 0x01;
2982         hypercall[2] = 0xd9;
2983 }
2984
2985 static void svm_check_processor_compat(void *rtn)
2986 {
2987         *(int *)rtn = 0;
2988 }
2989
2990 static bool svm_cpu_has_accelerated_tpr(void)
2991 {
2992         return false;
2993 }
2994
2995 static int get_npt_level(void)
2996 {
2997 #ifdef CONFIG_X86_64
2998         return PT64_ROOT_LEVEL;
2999 #else
3000         return PT32E_ROOT_LEVEL;
3001 #endif
3002 }
3003
3004 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3005 {
3006         return 0;
3007 }
3008
3009 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3010 {
3011 }
3012
3013 static const struct trace_print_flags svm_exit_reasons_str[] = {
3014         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3015         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3016         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3017         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3018         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3019         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3020         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3021         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3022         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3023         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3024         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3025         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3026         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3027         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3028         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3029         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3030         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3031         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3032         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3033         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3034         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3035         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3036         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3037         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3038         { SVM_EXIT_INTR,                        "interrupt" },
3039         { SVM_EXIT_NMI,                         "nmi" },
3040         { SVM_EXIT_SMI,                         "smi" },
3041         { SVM_EXIT_INIT,                        "init" },
3042         { SVM_EXIT_VINTR,                       "vintr" },
3043         { SVM_EXIT_CPUID,                       "cpuid" },
3044         { SVM_EXIT_INVD,                        "invd" },
3045         { SVM_EXIT_HLT,                         "hlt" },
3046         { SVM_EXIT_INVLPG,                      "invlpg" },
3047         { SVM_EXIT_INVLPGA,                     "invlpga" },
3048         { SVM_EXIT_IOIO,                        "io" },
3049         { SVM_EXIT_MSR,                         "msr" },
3050         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3051         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3052         { SVM_EXIT_VMRUN,                       "vmrun" },
3053         { SVM_EXIT_VMMCALL,                     "hypercall" },
3054         { SVM_EXIT_VMLOAD,                      "vmload" },
3055         { SVM_EXIT_VMSAVE,                      "vmsave" },
3056         { SVM_EXIT_STGI,                        "stgi" },
3057         { SVM_EXIT_CLGI,                        "clgi" },
3058         { SVM_EXIT_SKINIT,                      "skinit" },
3059         { SVM_EXIT_WBINVD,                      "wbinvd" },
3060         { SVM_EXIT_MONITOR,                     "monitor" },
3061         { SVM_EXIT_MWAIT,                       "mwait" },
3062         { SVM_EXIT_NPF,                         "npf" },
3063         { -1, NULL }
3064 };
3065
3066 static int svm_get_lpage_level(void)
3067 {
3068         return PT_PDPE_LEVEL;
3069 }
3070
3071 static bool svm_rdtscp_supported(void)
3072 {
3073         return false;
3074 }
3075
3076 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3077 {
3078         struct vcpu_svm *svm = to_svm(vcpu);
3079
3080         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3081         if (is_nested(svm))
3082                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3083         update_cr0_intercept(svm);
3084 }
3085
3086 static struct kvm_x86_ops svm_x86_ops = {
3087         .cpu_has_kvm_support = has_svm,
3088         .disabled_by_bios = is_disabled,
3089         .hardware_setup = svm_hardware_setup,
3090         .hardware_unsetup = svm_hardware_unsetup,
3091         .check_processor_compatibility = svm_check_processor_compat,
3092         .hardware_enable = svm_hardware_enable,
3093         .hardware_disable = svm_hardware_disable,
3094         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3095
3096         .vcpu_create = svm_create_vcpu,
3097         .vcpu_free = svm_free_vcpu,
3098         .vcpu_reset = svm_vcpu_reset,
3099
3100         .prepare_guest_switch = svm_prepare_guest_switch,
3101         .vcpu_load = svm_vcpu_load,
3102         .vcpu_put = svm_vcpu_put,
3103
3104         .set_guest_debug = svm_guest_debug,
3105         .get_msr = svm_get_msr,
3106         .set_msr = svm_set_msr,
3107         .get_segment_base = svm_get_segment_base,
3108         .get_segment = svm_get_segment,
3109         .set_segment = svm_set_segment,
3110         .get_cpl = svm_get_cpl,
3111         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3112         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3113         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3114         .set_cr0 = svm_set_cr0,
3115         .set_cr3 = svm_set_cr3,
3116         .set_cr4 = svm_set_cr4,
3117         .set_efer = svm_set_efer,
3118         .get_idt = svm_get_idt,
3119         .set_idt = svm_set_idt,
3120         .get_gdt = svm_get_gdt,
3121         .set_gdt = svm_set_gdt,
3122         .get_dr = svm_get_dr,
3123         .set_dr = svm_set_dr,
3124         .cache_reg = svm_cache_reg,
3125         .get_rflags = svm_get_rflags,
3126         .set_rflags = svm_set_rflags,
3127         .fpu_activate = svm_fpu_activate,
3128         .fpu_deactivate = svm_fpu_deactivate,
3129
3130         .tlb_flush = svm_flush_tlb,
3131
3132         .run = svm_vcpu_run,
3133         .handle_exit = handle_exit,
3134         .skip_emulated_instruction = skip_emulated_instruction,
3135         .set_interrupt_shadow = svm_set_interrupt_shadow,
3136         .get_interrupt_shadow = svm_get_interrupt_shadow,
3137         .patch_hypercall = svm_patch_hypercall,
3138         .set_irq = svm_set_irq,
3139         .set_nmi = svm_inject_nmi,
3140         .queue_exception = svm_queue_exception,
3141         .interrupt_allowed = svm_interrupt_allowed,
3142         .nmi_allowed = svm_nmi_allowed,
3143         .get_nmi_mask = svm_get_nmi_mask,
3144         .set_nmi_mask = svm_set_nmi_mask,
3145         .enable_nmi_window = enable_nmi_window,
3146         .enable_irq_window = enable_irq_window,
3147         .update_cr8_intercept = update_cr8_intercept,
3148
3149         .set_tss_addr = svm_set_tss_addr,
3150         .get_tdp_level = get_npt_level,
3151         .get_mt_mask = svm_get_mt_mask,
3152
3153         .exit_reasons_str = svm_exit_reasons_str,
3154         .get_lpage_level = svm_get_lpage_level,
3155
3156         .cpuid_update = svm_cpuid_update,
3157
3158         .rdtscp_supported = svm_rdtscp_supported,
3159 };
3160
3161 static int __init svm_init(void)
3162 {
3163         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3164                               THIS_MODULE);
3165 }
3166
3167 static void __exit svm_exit(void)
3168 {
3169         kvm_exit();
3170 }
3171
3172 module_init(svm_init)
3173 module_exit(svm_exit)