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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49
  50 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  51 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  52 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  53
  54 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  55
  56 /* Turn on to get debugging output*/
  57 /* #define NESTED_DEBUG */
  58
  59 #ifdef NESTED_DEBUG
  60 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  61 #else
  62 #define nsvm_printk(fmt, args...) do {} while(0)
  63 #endif
  64
  65 static const u32 host_save_user_msrs[] = {
  66 #ifdef CONFIG_X86_64
  67         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  68         MSR_FS_BASE,
  69 #endif
  70         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  71 };
  72
  73 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  74
  75 struct kvm_vcpu;
  76
  77 struct nested_state {
  78         struct vmcb *hsave;
  79         u64 hsave_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87
  88         /* cache for intercepts of the guest */
  89         u16 intercept_cr_read;
  90         u16 intercept_cr_write;
  91         u16 intercept_dr_read;
  92         u16 intercept_dr_write;
  93         u32 intercept_exceptions;
  94         u64 intercept;
  95
  96 };
  97
  98 struct vcpu_svm {
  99         struct kvm_vcpu vcpu;
 100         struct vmcb *vmcb;
 101         unsigned long vmcb_pa;
 102         struct svm_cpu_data *svm_data;
 103         uint64_t asid_generation;
 104         uint64_t sysenter_esp;
 105         uint64_t sysenter_eip;
 106
 107         u64 next_rip;
 108
 109         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 110         u64 host_gs_base;
 111
 112         u32 *msrpm;
 113
 114         struct nested_state nested;
 115 };
 116
 117 /* enable NPT for AMD64 and X86 with PAE */
 118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 119 static bool npt_enabled = true;
 120 #else
 121 static bool npt_enabled = false;
 122 #endif
 123 static int npt = 1;
 124
 125 module_param(npt, int, S_IRUGO);
 126
 127 static int nested = 1;
 128 module_param(nested, int, S_IRUGO);
 129
 130 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 131 static void svm_complete_interrupts(struct vcpu_svm *svm);
 132
 133 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 134 static int nested_svm_vmexit(struct vcpu_svm *svm);
 135 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 136                                       bool has_error_code, u32 error_code);
 137
 138 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 139 {
 140         return container_of(vcpu, struct vcpu_svm, vcpu);
 141 }
 142
 143 static inline bool is_nested(struct vcpu_svm *svm)
 144 {
 145         return svm->nested.vmcb;
 146 }
 147
 148 static inline void enable_gif(struct vcpu_svm *svm)
 149 {
 150         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 151 }
 152
 153 static inline void disable_gif(struct vcpu_svm *svm)
 154 {
 155         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 156 }
 157
 158 static inline bool gif_set(struct vcpu_svm *svm)
 159 {
 160         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 161 }
 162
 163 static unsigned long iopm_base;
 164
 165 struct kvm_ldttss_desc {
 166         u16 limit0;
 167         u16 base0;
 168         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 169         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 170         u32 base3;
 171         u32 zero1;
 172 } __attribute__((packed));
 173
 174 struct svm_cpu_data {
 175         int cpu;
 176
 177         u64 asid_generation;
 178         u32 max_asid;
 179         u32 next_asid;
 180         struct kvm_ldttss_desc *tss_desc;
 181
 182         struct page *save_area;
 183 };
 184
 185 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 186 static uint32_t svm_features;
 187
 188 struct svm_init_data {
 189         int cpu;
 190         int r;
 191 };
 192
 193 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 194
 195 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 196 #define MSRS_RANGE_SIZE 2048
 197 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 198
 199 #define MAX_INST_SIZE 15
 200
 201 static inline u32 svm_has(u32 feat)
 202 {
 203         return svm_features & feat;
 204 }
 205
 206 static inline void clgi(void)
 207 {
 208         asm volatile (__ex(SVM_CLGI));
 209 }
 210
 211 static inline void stgi(void)
 212 {
 213         asm volatile (__ex(SVM_STGI));
 214 }
 215
 216 static inline void invlpga(unsigned long addr, u32 asid)
 217 {
 218         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 219 }
 220
 221 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 222 {
 223         to_svm(vcpu)->asid_generation--;
 224 }
 225
 226 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 227 {
 228         force_new_asid(vcpu);
 229 }
 230
 231 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 232 {
 233         if (!npt_enabled && !(efer & EFER_LMA))
 234                 efer &= ~EFER_LME;
 235
 236         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 237         vcpu->arch.shadow_efer = efer;
 238 }
 239
 240 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 241                                 bool has_error_code, u32 error_code)
 242 {
 243         struct vcpu_svm *svm = to_svm(vcpu);
 244
 245         /* If we are within a nested VM we'd better #VMEXIT and let the
 246            guest handle the exception */
 247         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 248                 return;
 249
 250         svm->vmcb->control.event_inj = nr
 251                 | SVM_EVTINJ_VALID
 252                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 253                 | SVM_EVTINJ_TYPE_EXEPT;
 254         svm->vmcb->control.event_inj_err = error_code;
 255 }
 256
 257 static int is_external_interrupt(u32 info)
 258 {
 259         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 260         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 261 }
 262
 263 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 264 {
 265         struct vcpu_svm *svm = to_svm(vcpu);
 266         u32 ret = 0;
 267
 268         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 269                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 270         return ret & mask;
 271 }
 272
 273 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 274 {
 275         struct vcpu_svm *svm = to_svm(vcpu);
 276
 277         if (mask == 0)
 278                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 279         else
 280                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 281
 282 }
 283
 284 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 285 {
 286         struct vcpu_svm *svm = to_svm(vcpu);
 287
 288         if (!svm->next_rip) {
 289                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 290                                 EMULATE_DONE)
 291                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 292                 return;
 293         }
 294         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 295                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 296                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 297
 298         kvm_rip_write(vcpu, svm->next_rip);
 299         svm_set_interrupt_shadow(vcpu, 0);
 300 }
 301
 302 static int has_svm(void)
 303 {
 304         const char *msg;
 305
 306         if (!cpu_has_svm(&msg)) {
 307                 printk(KERN_INFO "has_svm: %s\n", msg);
 308                 return 0;
 309         }
 310
 311         return 1;
 312 }
 313
 314 static void svm_hardware_disable(void *garbage)
 315 {
 316         cpu_svm_disable();
 317 }
 318
 319 static int svm_hardware_enable(void *garbage)
 320 {
 321
 322         struct svm_cpu_data *svm_data;
 323         uint64_t efer;
 324         struct descriptor_table gdt_descr;
 325         struct desc_struct *gdt;
 326         int me = raw_smp_processor_id();
 327
 328         rdmsrl(MSR_EFER, efer);
 329         if (efer & EFER_SVME)
 330                 return -EBUSY;
 331
 332         if (!has_svm()) {
 333                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 334                        me);
 335                 return -EINVAL;
 336         }
 337         svm_data = per_cpu(svm_data, me);
 338
 339         if (!svm_data) {
 340                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 341                        me);
 342                 return -EINVAL;
 343         }
 344
 345         svm_data->asid_generation = 1;
 346         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 347         svm_data->next_asid = svm_data->max_asid + 1;
 348
 349         kvm_get_gdt(&gdt_descr);
 350         gdt = (struct desc_struct *)gdt_descr.base;
 351         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 352
 353         wrmsrl(MSR_EFER, efer | EFER_SVME);
 354
 355         wrmsrl(MSR_VM_HSAVE_PA,
 356                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 357
 358         return 0;
 359 }
 360
 361 static void svm_cpu_uninit(int cpu)
 362 {
 363         struct svm_cpu_data *svm_data
 364                 = per_cpu(svm_data, raw_smp_processor_id());
 365
 366         if (!svm_data)
 367                 return;
 368
 369         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 370         __free_page(svm_data->save_area);
 371         kfree(svm_data);
 372 }
 373
 374 static int svm_cpu_init(int cpu)
 375 {
 376         struct svm_cpu_data *svm_data;
 377         int r;
 378
 379         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 380         if (!svm_data)
 381                 return -ENOMEM;
 382         svm_data->cpu = cpu;
 383         svm_data->save_area = alloc_page(GFP_KERNEL);
 384         r = -ENOMEM;
 385         if (!svm_data->save_area)
 386                 goto err_1;
 387
 388         per_cpu(svm_data, cpu) = svm_data;
 389
 390         return 0;
 391
 392 err_1:
 393         kfree(svm_data);
 394         return r;
 395
 396 }
 397
 398 static void set_msr_interception(u32 *msrpm, unsigned msr,
 399                                  int read, int write)
 400 {
 401         int i;
 402
 403         for (i = 0; i < NUM_MSR_MAPS; i++) {
 404                 if (msr >= msrpm_ranges[i] &&
 405                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 406                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 407                                           msrpm_ranges[i]) * 2;
 408
 409                         u32 *base = msrpm + (msr_offset / 32);
 410                         u32 msr_shift = msr_offset % 32;
 411                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 412                         *base = (*base & ~(0x3 << msr_shift)) |
 413                                 (mask << msr_shift);
 414                         return;
 415                 }
 416         }
 417         BUG();
 418 }
 419
 420 static void svm_vcpu_init_msrpm(u32 *msrpm)
 421 {
 422         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 423
 424 #ifdef CONFIG_X86_64
 425         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 426         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 427         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 428         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 429         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 430         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 431 #endif
 432         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 433         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 434 }
 435
 436 static void svm_enable_lbrv(struct vcpu_svm *svm)
 437 {
 438         u32 *msrpm = svm->msrpm;
 439
 440         svm->vmcb->control.lbr_ctl = 1;
 441         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 442         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 443         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 444         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 445 }
 446
 447 static void svm_disable_lbrv(struct vcpu_svm *svm)
 448 {
 449         u32 *msrpm = svm->msrpm;
 450
 451         svm->vmcb->control.lbr_ctl = 0;
 452         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 453         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 454         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 455         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 456 }
 457
 458 static __init int svm_hardware_setup(void)
 459 {
 460         int cpu;
 461         struct page *iopm_pages;
 462         void *iopm_va;
 463         int r;
 464
 465         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 466
 467         if (!iopm_pages)
 468                 return -ENOMEM;
 469
 470         iopm_va = page_address(iopm_pages);
 471         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 472         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 473
 474         if (boot_cpu_has(X86_FEATURE_NX))
 475                 kvm_enable_efer_bits(EFER_NX);
 476
 477         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 478                 kvm_enable_efer_bits(EFER_FFXSR);
 479
 480         if (nested) {
 481                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 482                 kvm_enable_efer_bits(EFER_SVME);
 483         }
 484
 485         for_each_possible_cpu(cpu) {
 486                 r = svm_cpu_init(cpu);
 487                 if (r)
 488                         goto err;
 489         }
 490
 491         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 492
 493         if (!svm_has(SVM_FEATURE_NPT))
 494                 npt_enabled = false;
 495
 496         if (npt_enabled && !npt) {
 497                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 498                 npt_enabled = false;
 499         }
 500
 501         if (npt_enabled) {
 502                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 503                 kvm_enable_tdp();
 504         } else
 505                 kvm_disable_tdp();
 506
 507         return 0;
 508
 509 err:
 510         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 511         iopm_base = 0;
 512         return r;
 513 }
 514
 515 static __exit void svm_hardware_unsetup(void)
 516 {
 517         int cpu;
 518
 519         for_each_possible_cpu(cpu)
 520                 svm_cpu_uninit(cpu);
 521
 522         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 523         iopm_base = 0;
 524 }
 525
 526 static void init_seg(struct vmcb_seg *seg)
 527 {
 528         seg->selector = 0;
 529         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 530                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 531         seg->limit = 0xffff;
 532         seg->base = 0;
 533 }
 534
 535 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 536 {
 537         seg->selector = 0;
 538         seg->attrib = SVM_SELECTOR_P_MASK | type;
 539         seg->limit = 0xffff;
 540         seg->base = 0;
 541 }
 542
 543 static void init_vmcb(struct vcpu_svm *svm)
 544 {
 545         struct vmcb_control_area *control = &svm->vmcb->control;
 546         struct vmcb_save_area *save = &svm->vmcb->save;
 547
 548         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 549                                         INTERCEPT_CR3_MASK |
 550                                         INTERCEPT_CR4_MASK;
 551
 552         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 553                                         INTERCEPT_CR3_MASK |
 554                                         INTERCEPT_CR4_MASK |
 555                                         INTERCEPT_CR8_MASK;
 556
 557         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 558                                         INTERCEPT_DR1_MASK |
 559                                         INTERCEPT_DR2_MASK |
 560                                         INTERCEPT_DR3_MASK;
 561
 562         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 563                                         INTERCEPT_DR1_MASK |
 564                                         INTERCEPT_DR2_MASK |
 565                                         INTERCEPT_DR3_MASK |
 566                                         INTERCEPT_DR5_MASK |
 567                                         INTERCEPT_DR7_MASK;
 568
 569         control->intercept_exceptions = (1 << PF_VECTOR) |
 570                                         (1 << UD_VECTOR) |
 571                                         (1 << MC_VECTOR);
 572
 573
 574         control->intercept =    (1ULL << INTERCEPT_INTR) |
 575                                 (1ULL << INTERCEPT_NMI) |
 576                                 (1ULL << INTERCEPT_SMI) |
 577                                 (1ULL << INTERCEPT_CPUID) |
 578                                 (1ULL << INTERCEPT_INVD) |
 579                                 (1ULL << INTERCEPT_HLT) |
 580                                 (1ULL << INTERCEPT_INVLPG) |
 581                                 (1ULL << INTERCEPT_INVLPGA) |
 582                                 (1ULL << INTERCEPT_IOIO_PROT) |
 583                                 (1ULL << INTERCEPT_MSR_PROT) |
 584                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 585                                 (1ULL << INTERCEPT_SHUTDOWN) |
 586                                 (1ULL << INTERCEPT_VMRUN) |
 587                                 (1ULL << INTERCEPT_VMMCALL) |
 588                                 (1ULL << INTERCEPT_VMLOAD) |
 589                                 (1ULL << INTERCEPT_VMSAVE) |
 590                                 (1ULL << INTERCEPT_STGI) |
 591                                 (1ULL << INTERCEPT_CLGI) |
 592                                 (1ULL << INTERCEPT_SKINIT) |
 593                                 (1ULL << INTERCEPT_WBINVD) |
 594                                 (1ULL << INTERCEPT_MONITOR) |
 595                                 (1ULL << INTERCEPT_MWAIT);
 596
 597         control->iopm_base_pa = iopm_base;
 598         control->msrpm_base_pa = __pa(svm->msrpm);
 599         control->tsc_offset = 0;
 600         control->int_ctl = V_INTR_MASKING_MASK;
 601
 602         init_seg(&save->es);
 603         init_seg(&save->ss);
 604         init_seg(&save->ds);
 605         init_seg(&save->fs);
 606         init_seg(&save->gs);
 607
 608         save->cs.selector = 0xf000;
 609         /* Executable/Readable Code Segment */
 610         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 611                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 612         save->cs.limit = 0xffff;
 613         /*
 614          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 615          * be consistent with it.
 616          *
 617          * Replace when we have real mode working for vmx.
 618          */
 619         save->cs.base = 0xf0000;
 620
 621         save->gdtr.limit = 0xffff;
 622         save->idtr.limit = 0xffff;
 623
 624         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 625         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 626
 627         save->efer = EFER_SVME;
 628         save->dr6 = 0xffff0ff0;
 629         save->dr7 = 0x400;
 630         save->rflags = 2;
 631         save->rip = 0x0000fff0;
 632         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 633
 634         /*
 635          * cr0 val on cpu init should be 0x60000010, we enable cpu
 636          * cache by default. the orderly way is to enable cache in bios.
 637          */
 638         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 639         save->cr4 = X86_CR4_PAE;
 640         /* rdx = ?? */
 641
 642         if (npt_enabled) {
 643                 /* Setup VMCB for Nested Paging */
 644                 control->nested_ctl = 1;
 645                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 646                                         (1ULL << INTERCEPT_INVLPG));
 647                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 648                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 649                                                 INTERCEPT_CR3_MASK);
 650                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 651                                                  INTERCEPT_CR3_MASK);
 652                 save->g_pat = 0x0007040600070406ULL;
 653                 /* enable caching because the QEMU Bios doesn't enable it */
 654                 save->cr0 = X86_CR0_ET;
 655                 save->cr3 = 0;
 656                 save->cr4 = 0;
 657         }
 658         force_new_asid(&svm->vcpu);
 659
 660         svm->nested.vmcb = 0;
 661         svm->vcpu.arch.hflags = 0;
 662
 663         enable_gif(svm);
 664 }
 665
 666 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 667 {
 668         struct vcpu_svm *svm = to_svm(vcpu);
 669
 670         init_vmcb(svm);
 671
 672         if (!kvm_vcpu_is_bsp(vcpu)) {
 673                 kvm_rip_write(vcpu, 0);
 674                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 675                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 676         }
 677         vcpu->arch.regs_avail = ~0;
 678         vcpu->arch.regs_dirty = ~0;
 679
 680         return 0;
 681 }
 682
 683 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 684 {
 685         struct vcpu_svm *svm;
 686         struct page *page;
 687         struct page *msrpm_pages;
 688         struct page *hsave_page;
 689         struct page *nested_msrpm_pages;
 690         int err;
 691
 692         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 693         if (!svm) {
 694                 err = -ENOMEM;
 695                 goto out;
 696         }
 697
 698         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 699         if (err)
 700                 goto free_svm;
 701
 702         page = alloc_page(GFP_KERNEL);
 703         if (!page) {
 704                 err = -ENOMEM;
 705                 goto uninit;
 706         }
 707
 708         err = -ENOMEM;
 709         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 710         if (!msrpm_pages)
 711                 goto uninit;
 712
 713         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 714         if (!nested_msrpm_pages)
 715                 goto uninit;
 716
 717         svm->msrpm = page_address(msrpm_pages);
 718         svm_vcpu_init_msrpm(svm->msrpm);
 719
 720         hsave_page = alloc_page(GFP_KERNEL);
 721         if (!hsave_page)
 722                 goto uninit;
 723         svm->nested.hsave = page_address(hsave_page);
 724
 725         svm->nested.msrpm = page_address(nested_msrpm_pages);
 726
 727         svm->vmcb = page_address(page);
 728         clear_page(svm->vmcb);
 729         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 730         svm->asid_generation = 0;
 731         init_vmcb(svm);
 732
 733         fx_init(&svm->vcpu);
 734         svm->vcpu.fpu_active = 1;
 735         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 736         if (kvm_vcpu_is_bsp(&svm->vcpu))
 737                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 738
 739         return &svm->vcpu;
 740
 741 uninit:
 742         kvm_vcpu_uninit(&svm->vcpu);
 743 free_svm:
 744         kmem_cache_free(kvm_vcpu_cache, svm);
 745 out:
 746         return ERR_PTR(err);
 747 }
 748
 749 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 750 {
 751         struct vcpu_svm *svm = to_svm(vcpu);
 752
 753         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 754         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 755         __free_page(virt_to_page(svm->nested.hsave));
 756         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 757         kvm_vcpu_uninit(vcpu);
 758         kmem_cache_free(kvm_vcpu_cache, svm);
 759 }
 760
 761 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764         int i;
 765
 766         if (unlikely(cpu != vcpu->cpu)) {
 767                 u64 delta;
 768
 769                 /*
 770                  * Make sure that the guest sees a monotonically
 771                  * increasing TSC.
 772                  */
 773                 delta = vcpu->arch.host_tsc - native_read_tsc();
 774                 svm->vmcb->control.tsc_offset += delta;
 775                 if (is_nested(svm))
 776                         svm->nested.hsave->control.tsc_offset += delta;
 777                 vcpu->cpu = cpu;
 778                 kvm_migrate_timers(vcpu);
 779                 svm->asid_generation = 0;
 780         }
 781
 782         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 783                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 784 }
 785
 786 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 787 {
 788         struct vcpu_svm *svm = to_svm(vcpu);
 789         int i;
 790
 791         ++vcpu->stat.host_state_reload;
 792         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 793                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 794
 795         vcpu->arch.host_tsc = native_read_tsc();
 796 }
 797
 798 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 799 {
 800         return to_svm(vcpu)->vmcb->save.rflags;
 801 }
 802
 803 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 804 {
 805         to_svm(vcpu)->vmcb->save.rflags = rflags;
 806 }
 807
 808 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 809 {
 810         switch (reg) {
 811         case VCPU_EXREG_PDPTR:
 812                 BUG_ON(!npt_enabled);
 813                 load_pdptrs(vcpu, vcpu->arch.cr3);
 814                 break;
 815         default:
 816                 BUG();
 817         }
 818 }
 819
 820 static void svm_set_vintr(struct vcpu_svm *svm)
 821 {
 822         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 823 }
 824
 825 static void svm_clear_vintr(struct vcpu_svm *svm)
 826 {
 827         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 828 }
 829
 830 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 831 {
 832         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 833
 834         switch (seg) {
 835         case VCPU_SREG_CS: return &save->cs;
 836         case VCPU_SREG_DS: return &save->ds;
 837         case VCPU_SREG_ES: return &save->es;
 838         case VCPU_SREG_FS: return &save->fs;
 839         case VCPU_SREG_GS: return &save->gs;
 840         case VCPU_SREG_SS: return &save->ss;
 841         case VCPU_SREG_TR: return &save->tr;
 842         case VCPU_SREG_LDTR: return &save->ldtr;
 843         }
 844         BUG();
 845         return NULL;
 846 }
 847
 848 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 849 {
 850         struct vmcb_seg *s = svm_seg(vcpu, seg);
 851
 852         return s->base;
 853 }
 854
 855 static void svm_get_segment(struct kvm_vcpu *vcpu,
 856                             struct kvm_segment *var, int seg)
 857 {
 858         struct vmcb_seg *s = svm_seg(vcpu, seg);
 859
 860         var->base = s->base;
 861         var->limit = s->limit;
 862         var->selector = s->selector;
 863         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 864         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 865         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 866         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 867         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 868         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 869         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 870         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 871
 872         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 873          * for cross vendor migration purposes by "not present"
 874          */
 875         var->unusable = !var->present || (var->type == 0);
 876
 877         switch (seg) {
 878         case VCPU_SREG_CS:
 879                 /*
 880                  * SVM always stores 0 for the 'G' bit in the CS selector in
 881                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 882                  * Intel's VMENTRY has a check on the 'G' bit.
 883                  */
 884                 var->g = s->limit > 0xfffff;
 885                 break;
 886         case VCPU_SREG_TR:
 887                 /*
 888                  * Work around a bug where the busy flag in the tr selector
 889                  * isn't exposed
 890                  */
 891                 var->type |= 0x2;
 892                 break;
 893         case VCPU_SREG_DS:
 894         case VCPU_SREG_ES:
 895         case VCPU_SREG_FS:
 896         case VCPU_SREG_GS:
 897                 /*
 898                  * The accessed bit must always be set in the segment
 899                  * descriptor cache, although it can be cleared in the
 900                  * descriptor, the cached bit always remains at 1. Since
 901                  * Intel has a check on this, set it here to support
 902                  * cross-vendor migration.
 903                  */
 904                 if (!var->unusable)
 905                         var->type |= 0x1;
 906                 break;
 907         case VCPU_SREG_SS:
 908                 /* On AMD CPUs sometimes the DB bit in the segment
 909                  * descriptor is left as 1, although the whole segment has
 910                  * been made unusable. Clear it here to pass an Intel VMX
 911                  * entry check when cross vendor migrating.
 912                  */
 913                 if (var->unusable)
 914                         var->db = 0;
 915                 break;
 916         }
 917 }
 918
 919 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 920 {
 921         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 922
 923         return save->cpl;
 924 }
 925
 926 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 927 {
 928         struct vcpu_svm *svm = to_svm(vcpu);
 929
 930         dt->limit = svm->vmcb->save.idtr.limit;
 931         dt->base = svm->vmcb->save.idtr.base;
 932 }
 933
 934 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937
 938         svm->vmcb->save.idtr.limit = dt->limit;
 939         svm->vmcb->save.idtr.base = dt->base ;
 940 }
 941
 942 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 943 {
 944         struct vcpu_svm *svm = to_svm(vcpu);
 945
 946         dt->limit = svm->vmcb->save.gdtr.limit;
 947         dt->base = svm->vmcb->save.gdtr.base;
 948 }
 949
 950 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 951 {
 952         struct vcpu_svm *svm = to_svm(vcpu);
 953
 954         svm->vmcb->save.gdtr.limit = dt->limit;
 955         svm->vmcb->save.gdtr.base = dt->base ;
 956 }
 957
 958 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 959 {
 960 }
 961
 962 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 963 {
 964         struct vcpu_svm *svm = to_svm(vcpu);
 965
 966 #ifdef CONFIG_X86_64
 967         if (vcpu->arch.shadow_efer & EFER_LME) {
 968                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 969                         vcpu->arch.shadow_efer |= EFER_LMA;
 970                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 971                 }
 972
 973                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 974                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 975                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 976                 }
 977         }
 978 #endif
 979         if (npt_enabled)
 980                 goto set;
 981
 982         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 983                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 984                 vcpu->fpu_active = 1;
 985         }
 986
 987         vcpu->arch.cr0 = cr0;
 988         cr0 |= X86_CR0_PG | X86_CR0_WP;
 989         if (!vcpu->fpu_active) {
 990                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 991                 cr0 |= X86_CR0_TS;
 992         }
 993 set:
 994         /*
 995          * re-enable caching here because the QEMU bios
 996          * does not do it - this results in some delay at
 997          * reboot
 998          */
 999         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1000         svm->vmcb->save.cr0 = cr0;
1001 }
1002
1003 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1004 {
1005         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1006         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1007
1008         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1009                 force_new_asid(vcpu);
1010
1011         vcpu->arch.cr4 = cr4;
1012         if (!npt_enabled)
1013                 cr4 |= X86_CR4_PAE;
1014         cr4 |= host_cr4_mce;
1015         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1016 }
1017
1018 static void svm_set_segment(struct kvm_vcpu *vcpu,
1019                             struct kvm_segment *var, int seg)
1020 {
1021         struct vcpu_svm *svm = to_svm(vcpu);
1022         struct vmcb_seg *s = svm_seg(vcpu, seg);
1023
1024         s->base = var->base;
1025         s->limit = var->limit;
1026         s->selector = var->selector;
1027         if (var->unusable)
1028                 s->attrib = 0;
1029         else {
1030                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1031                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1032                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1033                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1034                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1035                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1036                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1037                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1038         }
1039         if (seg == VCPU_SREG_CS)
1040                 svm->vmcb->save.cpl
1041                         = (svm->vmcb->save.cs.attrib
1042                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1043
1044 }
1045
1046 static void update_db_intercept(struct kvm_vcpu *vcpu)
1047 {
1048         struct vcpu_svm *svm = to_svm(vcpu);
1049
1050         svm->vmcb->control.intercept_exceptions &=
1051                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1052
1053         if (vcpu->arch.singlestep)
1054                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1055
1056         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1057                 if (vcpu->guest_debug &
1058                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1059                         svm->vmcb->control.intercept_exceptions |=
1060                                 1 << DB_VECTOR;
1061                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1062                         svm->vmcb->control.intercept_exceptions |=
1063                                 1 << BP_VECTOR;
1064         } else
1065                 vcpu->guest_debug = 0;
1066 }
1067
1068 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1069 {
1070         int old_debug = vcpu->guest_debug;
1071         struct vcpu_svm *svm = to_svm(vcpu);
1072
1073         vcpu->guest_debug = dbg->control;
1074
1075         update_db_intercept(vcpu);
1076
1077         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1078                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1079         else
1080                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1081
1082         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1083                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1084         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1085                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1086
1087         return 0;
1088 }
1089
1090 static void load_host_msrs(struct kvm_vcpu *vcpu)
1091 {
1092 #ifdef CONFIG_X86_64
1093         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1094 #endif
1095 }
1096
1097 static void save_host_msrs(struct kvm_vcpu *vcpu)
1098 {
1099 #ifdef CONFIG_X86_64
1100         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1101 #endif
1102 }
1103
1104 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1105 {
1106         if (svm_data->next_asid > svm_data->max_asid) {
1107                 ++svm_data->asid_generation;
1108                 svm_data->next_asid = 1;
1109                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1110         }
1111
1112         svm->asid_generation = svm_data->asid_generation;
1113         svm->vmcb->control.asid = svm_data->next_asid++;
1114 }
1115
1116 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1117 {
1118         struct vcpu_svm *svm = to_svm(vcpu);
1119         unsigned long val;
1120
1121         switch (dr) {
1122         case 0 ... 3:
1123                 val = vcpu->arch.db[dr];
1124                 break;
1125         case 6:
1126                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1127                         val = vcpu->arch.dr6;
1128                 else
1129                         val = svm->vmcb->save.dr6;
1130                 break;
1131         case 7:
1132                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1133                         val = vcpu->arch.dr7;
1134                 else
1135                         val = svm->vmcb->save.dr7;
1136                 break;
1137         default:
1138                 val = 0;
1139         }
1140
1141         return val;
1142 }
1143
1144 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1145                        int *exception)
1146 {
1147         struct vcpu_svm *svm = to_svm(vcpu);
1148
1149         *exception = 0;
1150
1151         switch (dr) {
1152         case 0 ... 3:
1153                 vcpu->arch.db[dr] = value;
1154                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1155                         vcpu->arch.eff_db[dr] = value;
1156                 return;
1157         case 4 ... 5:
1158                 if (vcpu->arch.cr4 & X86_CR4_DE)
1159                         *exception = UD_VECTOR;
1160                 return;
1161         case 6:
1162                 if (value & 0xffffffff00000000ULL) {
1163                         *exception = GP_VECTOR;
1164                         return;
1165                 }
1166                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1167                 return;
1168         case 7:
1169                 if (value & 0xffffffff00000000ULL) {
1170                         *exception = GP_VECTOR;
1171                         return;
1172                 }
1173                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1174                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1175                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1176                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1177                 }
1178                 return;
1179         default:
1180                 /* FIXME: Possible case? */
1181                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1182                        __func__, dr);
1183                 *exception = UD_VECTOR;
1184                 return;
1185         }
1186 }
1187
1188 static int pf_interception(struct vcpu_svm *svm)
1189 {
1190         u64 fault_address;
1191         u32 error_code;
1192
1193         fault_address  = svm->vmcb->control.exit_info_2;
1194         error_code = svm->vmcb->control.exit_info_1;
1195
1196         trace_kvm_page_fault(fault_address, error_code);
1197         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1198                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1199         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1200 }
1201
1202 static int db_interception(struct vcpu_svm *svm)
1203 {
1204         struct kvm_run *kvm_run = svm->vcpu.run;
1205
1206         if (!(svm->vcpu.guest_debug &
1207               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1208                 !svm->vcpu.arch.singlestep) {
1209                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1210                 return 1;
1211         }
1212
1213         if (svm->vcpu.arch.singlestep) {
1214                 svm->vcpu.arch.singlestep = false;
1215                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1216                         svm->vmcb->save.rflags &=
1217                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1218                 update_db_intercept(&svm->vcpu);
1219         }
1220
1221         if (svm->vcpu.guest_debug &
1222             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1223                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1224                 kvm_run->debug.arch.pc =
1225                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1226                 kvm_run->debug.arch.exception = DB_VECTOR;
1227                 return 0;
1228         }
1229
1230         return 1;
1231 }
1232
1233 static int bp_interception(struct vcpu_svm *svm)
1234 {
1235         struct kvm_run *kvm_run = svm->vcpu.run;
1236
1237         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1238         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1239         kvm_run->debug.arch.exception = BP_VECTOR;
1240         return 0;
1241 }
1242
1243 static int ud_interception(struct vcpu_svm *svm)
1244 {
1245         int er;
1246
1247         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1248         if (er != EMULATE_DONE)
1249                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1250         return 1;
1251 }
1252
1253 static int nm_interception(struct vcpu_svm *svm)
1254 {
1255         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1256         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1257                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1258         svm->vcpu.fpu_active = 1;
1259
1260         return 1;
1261 }
1262
1263 static int mc_interception(struct vcpu_svm *svm)
1264 {
1265         /*
1266          * On an #MC intercept the MCE handler is not called automatically in
1267          * the host. So do it by hand here.
1268          */
1269         asm volatile (
1270                 "int $0x12\n");
1271         /* not sure if we ever come back to this point */
1272
1273         return 1;
1274 }
1275
1276 static int shutdown_interception(struct vcpu_svm *svm)
1277 {
1278         struct kvm_run *kvm_run = svm->vcpu.run;
1279
1280         /*
1281          * VMCB is undefined after a SHUTDOWN intercept
1282          * so reinitialize it.
1283          */
1284         clear_page(svm->vmcb);
1285         init_vmcb(svm);
1286
1287         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1288         return 0;
1289 }
1290
1291 static int io_interception(struct vcpu_svm *svm)
1292 {
1293         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1294         int size, in, string;
1295         unsigned port;
1296
1297         ++svm->vcpu.stat.io_exits;
1298
1299         svm->next_rip = svm->vmcb->control.exit_info_2;
1300
1301         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1302
1303         if (string) {
1304                 if (emulate_instruction(&svm->vcpu,
1305                                         0, 0, 0) == EMULATE_DO_MMIO)
1306                         return 0;
1307                 return 1;
1308         }
1309
1310         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1311         port = io_info >> 16;
1312         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1313
1314         skip_emulated_instruction(&svm->vcpu);
1315         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1316 }
1317
1318 static int nmi_interception(struct vcpu_svm *svm)
1319 {
1320         return 1;
1321 }
1322
1323 static int intr_interception(struct vcpu_svm *svm)
1324 {
1325         ++svm->vcpu.stat.irq_exits;
1326         return 1;
1327 }
1328
1329 static int nop_on_interception(struct vcpu_svm *svm)
1330 {
1331         return 1;
1332 }
1333
1334 static int halt_interception(struct vcpu_svm *svm)
1335 {
1336         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1337         skip_emulated_instruction(&svm->vcpu);
1338         return kvm_emulate_halt(&svm->vcpu);
1339 }
1340
1341 static int vmmcall_interception(struct vcpu_svm *svm)
1342 {
1343         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1344         skip_emulated_instruction(&svm->vcpu);
1345         kvm_emulate_hypercall(&svm->vcpu);
1346         return 1;
1347 }
1348
1349 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1350 {
1351         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1352             || !is_paging(&svm->vcpu)) {
1353                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1354                 return 1;
1355         }
1356
1357         if (svm->vmcb->save.cpl) {
1358                 kvm_inject_gp(&svm->vcpu, 0);
1359                 return 1;
1360         }
1361
1362        return 0;
1363 }
1364
1365 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1366                                       bool has_error_code, u32 error_code)
1367 {
1368         if (!is_nested(svm))
1369                 return 0;
1370
1371         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1372         svm->vmcb->control.exit_code_hi = 0;
1373         svm->vmcb->control.exit_info_1 = error_code;
1374         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1375
1376         return nested_svm_exit_handled(svm);
1377 }
1378
1379 static inline int nested_svm_intr(struct vcpu_svm *svm)
1380 {
1381         if (!is_nested(svm))
1382                 return 0;
1383
1384         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1385                 return 0;
1386
1387         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1388                 return 0;
1389
1390         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1391
1392         if (nested_svm_exit_handled(svm)) {
1393                 nsvm_printk("VMexit -> INTR\n");
1394                 return 1;
1395         }
1396
1397         return 0;
1398 }
1399
1400 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1401 {
1402         struct page *page;
1403
1404         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1405         if (is_error_page(page))
1406                 goto error;
1407
1408         return kmap_atomic(page, idx);
1409
1410 error:
1411         kvm_release_page_clean(page);
1412         kvm_inject_gp(&svm->vcpu, 0);
1413
1414         return NULL;
1415 }
1416
1417 static void nested_svm_unmap(void *addr, enum km_type idx)
1418 {
1419         struct page *page;
1420
1421         if (!addr)
1422                 return;
1423
1424         page = kmap_atomic_to_page(addr);
1425
1426         kunmap_atomic(addr, idx);
1427         kvm_release_page_dirty(page);
1428 }
1429
1430 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1431 {
1432         u32 param = svm->vmcb->control.exit_info_1 & 1;
1433         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1434         bool ret = false;
1435         u32 t0, t1;
1436         u8 *msrpm;
1437
1438         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1439                 return false;
1440
1441         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1442
1443         if (!msrpm)
1444                 goto out;
1445
1446         switch (msr) {
1447         case 0 ... 0x1fff:
1448                 t0 = (msr * 2) % 8;
1449                 t1 = msr / 8;
1450                 break;
1451         case 0xc0000000 ... 0xc0001fff:
1452                 t0 = (8192 + msr - 0xc0000000) * 2;
1453                 t1 = (t0 / 8);
1454                 t0 %= 8;
1455                 break;
1456         case 0xc0010000 ... 0xc0011fff:
1457                 t0 = (16384 + msr - 0xc0010000) * 2;
1458                 t1 = (t0 / 8);
1459                 t0 %= 8;
1460                 break;
1461         default:
1462                 ret = true;
1463                 goto out;
1464         }
1465
1466         ret = msrpm[t1] & ((1 << param) << t0);
1467
1468 out:
1469         nested_svm_unmap(msrpm, KM_USER0);
1470
1471         return ret;
1472 }
1473
1474 static int nested_svm_exit_special(struct vcpu_svm *svm)
1475 {
1476         u32 exit_code = svm->vmcb->control.exit_code;
1477
1478         switch (exit_code) {
1479         case SVM_EXIT_INTR:
1480         case SVM_EXIT_NMI:
1481                 return NESTED_EXIT_HOST;
1482                 /* For now we are always handling NPFs when using them */
1483         case SVM_EXIT_NPF:
1484                 if (npt_enabled)
1485                         return NESTED_EXIT_HOST;
1486                 break;
1487         /* When we're shadowing, trap PFs */
1488         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1489                 if (!npt_enabled)
1490                         return NESTED_EXIT_HOST;
1491                 break;
1492         default:
1493                 break;
1494         }
1495
1496         return NESTED_EXIT_CONTINUE;
1497 }
1498
1499 /*
1500  * If this function returns true, this #vmexit was already handled
1501  */
1502 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1503 {
1504         u32 exit_code = svm->vmcb->control.exit_code;
1505         int vmexit = NESTED_EXIT_HOST;
1506
1507         switch (exit_code) {
1508         case SVM_EXIT_MSR:
1509                 vmexit = nested_svm_exit_handled_msr(svm);
1510                 break;
1511         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1512                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1513                 if (svm->nested.intercept_cr_read & cr_bits)
1514                         vmexit = NESTED_EXIT_DONE;
1515                 break;
1516         }
1517         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1518                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1519                 if (svm->nested.intercept_cr_write & cr_bits)
1520                         vmexit = NESTED_EXIT_DONE;
1521                 break;
1522         }
1523         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1524                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1525                 if (svm->nested.intercept_dr_read & dr_bits)
1526                         vmexit = NESTED_EXIT_DONE;
1527                 break;
1528         }
1529         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1530                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1531                 if (svm->nested.intercept_dr_write & dr_bits)
1532                         vmexit = NESTED_EXIT_DONE;
1533                 break;
1534         }
1535         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1536                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1537                 if (svm->nested.intercept_exceptions & excp_bits)
1538                         vmexit = NESTED_EXIT_DONE;
1539                 break;
1540         }
1541         default: {
1542                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1543                 nsvm_printk("exit code: 0x%x\n", exit_code);
1544                 if (svm->nested.intercept & exit_bits)
1545                         vmexit = NESTED_EXIT_DONE;
1546         }
1547         }
1548
1549         if (vmexit == NESTED_EXIT_DONE) {
1550                 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1551                 nested_svm_vmexit(svm);
1552         }
1553
1554         return vmexit;
1555 }
1556
1557 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1558 {
1559         struct vmcb_control_area *dst  = &dst_vmcb->control;
1560         struct vmcb_control_area *from = &from_vmcb->control;
1561
1562         dst->intercept_cr_read    = from->intercept_cr_read;
1563         dst->intercept_cr_write   = from->intercept_cr_write;
1564         dst->intercept_dr_read    = from->intercept_dr_read;
1565         dst->intercept_dr_write   = from->intercept_dr_write;
1566         dst->intercept_exceptions = from->intercept_exceptions;
1567         dst->intercept            = from->intercept;
1568         dst->iopm_base_pa         = from->iopm_base_pa;
1569         dst->msrpm_base_pa        = from->msrpm_base_pa;
1570         dst->tsc_offset           = from->tsc_offset;
1571         dst->asid                 = from->asid;
1572         dst->tlb_ctl              = from->tlb_ctl;
1573         dst->int_ctl              = from->int_ctl;
1574         dst->int_vector           = from->int_vector;
1575         dst->int_state            = from->int_state;
1576         dst->exit_code            = from->exit_code;
1577         dst->exit_code_hi         = from->exit_code_hi;
1578         dst->exit_info_1          = from->exit_info_1;
1579         dst->exit_info_2          = from->exit_info_2;
1580         dst->exit_int_info        = from->exit_int_info;
1581         dst->exit_int_info_err    = from->exit_int_info_err;
1582         dst->nested_ctl           = from->nested_ctl;
1583         dst->event_inj            = from->event_inj;
1584         dst->event_inj_err        = from->event_inj_err;
1585         dst->nested_cr3           = from->nested_cr3;
1586         dst->lbr_ctl              = from->lbr_ctl;
1587 }
1588
1589 static int nested_svm_vmexit(struct vcpu_svm *svm)
1590 {
1591         struct vmcb *nested_vmcb;
1592         struct vmcb *hsave = svm->nested.hsave;
1593         struct vmcb *vmcb = svm->vmcb;
1594
1595         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1596         if (!nested_vmcb)
1597                 return 1;
1598
1599         /* Give the current vmcb to the guest */
1600         disable_gif(svm);
1601
1602         nested_vmcb->save.es     = vmcb->save.es;
1603         nested_vmcb->save.cs     = vmcb->save.cs;
1604         nested_vmcb->save.ss     = vmcb->save.ss;
1605         nested_vmcb->save.ds     = vmcb->save.ds;
1606         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1607         nested_vmcb->save.idtr   = vmcb->save.idtr;
1608         if (npt_enabled)
1609                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1610         nested_vmcb->save.cr2    = vmcb->save.cr2;
1611         nested_vmcb->save.rflags = vmcb->save.rflags;
1612         nested_vmcb->save.rip    = vmcb->save.rip;
1613         nested_vmcb->save.rsp    = vmcb->save.rsp;
1614         nested_vmcb->save.rax    = vmcb->save.rax;
1615         nested_vmcb->save.dr7    = vmcb->save.dr7;
1616         nested_vmcb->save.dr6    = vmcb->save.dr6;
1617         nested_vmcb->save.cpl    = vmcb->save.cpl;
1618
1619         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1620         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1621         nested_vmcb->control.int_state         = vmcb->control.int_state;
1622         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1623         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1624         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1625         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1626         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1627         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1628         nested_vmcb->control.tlb_ctl           = 0;
1629         nested_vmcb->control.event_inj         = 0;
1630         nested_vmcb->control.event_inj_err     = 0;
1631
1632         /* We always set V_INTR_MASKING and remember the old value in hflags */
1633         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1634                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1635
1636         /* Restore the original control entries */
1637         copy_vmcb_control_area(vmcb, hsave);
1638
1639         /* Kill any pending exceptions */
1640         if (svm->vcpu.arch.exception.pending == true)
1641                 nsvm_printk("WARNING: Pending Exception\n");
1642
1643         kvm_clear_exception_queue(&svm->vcpu);
1644         kvm_clear_interrupt_queue(&svm->vcpu);
1645
1646         /* Restore selected save entries */
1647         svm->vmcb->save.es = hsave->save.es;
1648         svm->vmcb->save.cs = hsave->save.cs;
1649         svm->vmcb->save.ss = hsave->save.ss;
1650         svm->vmcb->save.ds = hsave->save.ds;
1651         svm->vmcb->save.gdtr = hsave->save.gdtr;
1652         svm->vmcb->save.idtr = hsave->save.idtr;
1653         svm->vmcb->save.rflags = hsave->save.rflags;
1654         svm_set_efer(&svm->vcpu, hsave->save.efer);
1655         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1656         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1657         if (npt_enabled) {
1658                 svm->vmcb->save.cr3 = hsave->save.cr3;
1659                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1660         } else {
1661                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1662         }
1663         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1664         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1665         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1666         svm->vmcb->save.dr7 = 0;
1667         svm->vmcb->save.cpl = 0;
1668         svm->vmcb->control.exit_int_info = 0;
1669
1670         /* Exit nested SVM mode */
1671         svm->nested.vmcb = 0;
1672
1673         nested_svm_unmap(nested_vmcb, KM_USER0);
1674
1675         kvm_mmu_reset_context(&svm->vcpu);
1676         kvm_mmu_load(&svm->vcpu);
1677
1678         return 0;
1679 }
1680
1681 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1682 {
1683         u32 *nested_msrpm;
1684         int i;
1685
1686         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1687         if (!nested_msrpm)
1688                 return false;
1689
1690         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1691                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1692
1693         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1694
1695         nested_svm_unmap(nested_msrpm, KM_USER0);
1696
1697         return true;
1698 }
1699
1700 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1701 {
1702         struct vmcb *nested_vmcb;
1703         struct vmcb *hsave = svm->nested.hsave;
1704         struct vmcb *vmcb = svm->vmcb;
1705
1706         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1707         if (!nested_vmcb)
1708                 return false;
1709
1710         /* nested_vmcb is our indicator if nested SVM is activated */
1711         svm->nested.vmcb = svm->vmcb->save.rax;
1712
1713         /* Clear internal status */
1714         kvm_clear_exception_queue(&svm->vcpu);
1715         kvm_clear_interrupt_queue(&svm->vcpu);
1716
1717         /* Save the old vmcb, so we don't need to pick what we save, but
1718            can restore everything when a VMEXIT occurs */
1719         hsave->save.es     = vmcb->save.es;
1720         hsave->save.cs     = vmcb->save.cs;
1721         hsave->save.ss     = vmcb->save.ss;
1722         hsave->save.ds     = vmcb->save.ds;
1723         hsave->save.gdtr   = vmcb->save.gdtr;
1724         hsave->save.idtr   = vmcb->save.idtr;
1725         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1726         hsave->save.cr0    = svm->vcpu.arch.cr0;
1727         hsave->save.cr4    = svm->vcpu.arch.cr4;
1728         hsave->save.rflags = vmcb->save.rflags;
1729         hsave->save.rip    = svm->next_rip;
1730         hsave->save.rsp    = vmcb->save.rsp;
1731         hsave->save.rax    = vmcb->save.rax;
1732         if (npt_enabled)
1733                 hsave->save.cr3    = vmcb->save.cr3;
1734         else
1735                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1736
1737         copy_vmcb_control_area(hsave, vmcb);
1738
1739         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1740                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1741         else
1742                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1743
1744         /* Load the nested guest state */
1745         svm->vmcb->save.es = nested_vmcb->save.es;
1746         svm->vmcb->save.cs = nested_vmcb->save.cs;
1747         svm->vmcb->save.ss = nested_vmcb->save.ss;
1748         svm->vmcb->save.ds = nested_vmcb->save.ds;
1749         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1750         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1751         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1752         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1753         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1754         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1755         if (npt_enabled) {
1756                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1757                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1758         } else {
1759                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1760                 kvm_mmu_reset_context(&svm->vcpu);
1761         }
1762         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1763         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1764         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1765         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1766         /* In case we don't even reach vcpu_run, the fields are not updated */
1767         svm->vmcb->save.rax = nested_vmcb->save.rax;
1768         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1769         svm->vmcb->save.rip = nested_vmcb->save.rip;
1770         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1771         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1772         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1773
1774         /* We don't want a nested guest to be more powerful than the guest,
1775            so all intercepts are ORed */
1776         svm->vmcb->control.intercept_cr_read |=
1777                 nested_vmcb->control.intercept_cr_read;
1778         svm->vmcb->control.intercept_cr_write |=
1779                 nested_vmcb->control.intercept_cr_write;
1780         svm->vmcb->control.intercept_dr_read |=
1781                 nested_vmcb->control.intercept_dr_read;
1782         svm->vmcb->control.intercept_dr_write |=
1783                 nested_vmcb->control.intercept_dr_write;
1784         svm->vmcb->control.intercept_exceptions |=
1785                 nested_vmcb->control.intercept_exceptions;
1786
1787         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1788
1789         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1790
1791         /* cache intercepts */
1792         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1793         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1794         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1795         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1796         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1797         svm->nested.intercept            = nested_vmcb->control.intercept;
1798
1799         force_new_asid(&svm->vcpu);
1800         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1801         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1802                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1803                                 nested_vmcb->control.int_ctl);
1804         }
1805         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1806                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1807         else
1808                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1809
1810         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1811                         nested_vmcb->control.exit_int_info,
1812                         nested_vmcb->control.int_state);
1813
1814         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1815         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1816         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1817         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1818                 nsvm_printk("Injecting Event: 0x%x\n",
1819                                 nested_vmcb->control.event_inj);
1820         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1821         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1822
1823         nested_svm_unmap(nested_vmcb, KM_USER0);
1824
1825         enable_gif(svm);
1826
1827         return true;
1828 }
1829
1830 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1831 {
1832         to_vmcb->save.fs = from_vmcb->save.fs;
1833         to_vmcb->save.gs = from_vmcb->save.gs;
1834         to_vmcb->save.tr = from_vmcb->save.tr;
1835         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1836         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1837         to_vmcb->save.star = from_vmcb->save.star;
1838         to_vmcb->save.lstar = from_vmcb->save.lstar;
1839         to_vmcb->save.cstar = from_vmcb->save.cstar;
1840         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1841         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1842         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1843         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1844 }
1845
1846 static int vmload_interception(struct vcpu_svm *svm)
1847 {
1848         struct vmcb *nested_vmcb;
1849
1850         if (nested_svm_check_permissions(svm))
1851                 return 1;
1852
1853         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1854         skip_emulated_instruction(&svm->vcpu);
1855
1856         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1857         if (!nested_vmcb)
1858                 return 1;
1859
1860         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1861         nested_svm_unmap(nested_vmcb, KM_USER0);
1862
1863         return 1;
1864 }
1865
1866 static int vmsave_interception(struct vcpu_svm *svm)
1867 {
1868         struct vmcb *nested_vmcb;
1869
1870         if (nested_svm_check_permissions(svm))
1871                 return 1;
1872
1873         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1874         skip_emulated_instruction(&svm->vcpu);
1875
1876         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1877         if (!nested_vmcb)
1878                 return 1;
1879
1880         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1881         nested_svm_unmap(nested_vmcb, KM_USER0);
1882
1883         return 1;
1884 }
1885
1886 static int vmrun_interception(struct vcpu_svm *svm)
1887 {
1888         nsvm_printk("VMrun\n");
1889
1890         if (nested_svm_check_permissions(svm))
1891                 return 1;
1892
1893         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1894         skip_emulated_instruction(&svm->vcpu);
1895
1896         if (!nested_svm_vmrun(svm))
1897                 return 1;
1898
1899         if (!nested_svm_vmrun_msrpm(svm))
1900                 goto failed;
1901
1902         return 1;
1903
1904 failed:
1905
1906         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1907         svm->vmcb->control.exit_code_hi = 0;
1908         svm->vmcb->control.exit_info_1  = 0;
1909         svm->vmcb->control.exit_info_2  = 0;
1910
1911         nested_svm_vmexit(svm);
1912
1913         return 1;
1914 }
1915
1916 static int stgi_interception(struct vcpu_svm *svm)
1917 {
1918         if (nested_svm_check_permissions(svm))
1919                 return 1;
1920
1921         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1922         skip_emulated_instruction(&svm->vcpu);
1923
1924         enable_gif(svm);
1925
1926         return 1;
1927 }
1928
1929 static int clgi_interception(struct vcpu_svm *svm)
1930 {
1931         if (nested_svm_check_permissions(svm))
1932                 return 1;
1933
1934         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1935         skip_emulated_instruction(&svm->vcpu);
1936
1937         disable_gif(svm);
1938
1939         /* After a CLGI no interrupts should come */
1940         svm_clear_vintr(svm);
1941         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1942
1943         return 1;
1944 }
1945
1946 static int invlpga_interception(struct vcpu_svm *svm)
1947 {
1948         struct kvm_vcpu *vcpu = &svm->vcpu;
1949         nsvm_printk("INVLPGA\n");
1950
1951         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1952         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1953
1954         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1955         skip_emulated_instruction(&svm->vcpu);
1956         return 1;
1957 }
1958
1959 static int invalid_op_interception(struct vcpu_svm *svm)
1960 {
1961         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1962         return 1;
1963 }
1964
1965 static int task_switch_interception(struct vcpu_svm *svm)
1966 {
1967         u16 tss_selector;
1968         int reason;
1969         int int_type = svm->vmcb->control.exit_int_info &
1970                 SVM_EXITINTINFO_TYPE_MASK;
1971         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1972         uint32_t type =
1973                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1974         uint32_t idt_v =
1975                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1976
1977         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1978
1979         if (svm->vmcb->control.exit_info_2 &
1980             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1981                 reason = TASK_SWITCH_IRET;
1982         else if (svm->vmcb->control.exit_info_2 &
1983                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1984                 reason = TASK_SWITCH_JMP;
1985         else if (idt_v)
1986                 reason = TASK_SWITCH_GATE;
1987         else
1988                 reason = TASK_SWITCH_CALL;
1989
1990         if (reason == TASK_SWITCH_GATE) {
1991                 switch (type) {
1992                 case SVM_EXITINTINFO_TYPE_NMI:
1993                         svm->vcpu.arch.nmi_injected = false;
1994                         break;
1995                 case SVM_EXITINTINFO_TYPE_EXEPT:
1996                         kvm_clear_exception_queue(&svm->vcpu);
1997                         break;
1998                 case SVM_EXITINTINFO_TYPE_INTR:
1999                         kvm_clear_interrupt_queue(&svm->vcpu);
2000                         break;
2001                 default:
2002                         break;
2003                 }
2004         }
2005
2006         if (reason != TASK_SWITCH_GATE ||
2007             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2008             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2009              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2010                 skip_emulated_instruction(&svm->vcpu);
2011
2012         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2013 }
2014
2015 static int cpuid_interception(struct vcpu_svm *svm)
2016 {
2017         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2018         kvm_emulate_cpuid(&svm->vcpu);
2019         return 1;
2020 }
2021
2022 static int iret_interception(struct vcpu_svm *svm)
2023 {
2024         ++svm->vcpu.stat.nmi_window_exits;
2025         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2026         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2027         return 1;
2028 }
2029
2030 static int invlpg_interception(struct vcpu_svm *svm)
2031 {
2032         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2033                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2034         return 1;
2035 }
2036
2037 static int emulate_on_interception(struct vcpu_svm *svm)
2038 {
2039         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2040                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2041         return 1;
2042 }
2043
2044 static int cr8_write_interception(struct vcpu_svm *svm)
2045 {
2046         struct kvm_run *kvm_run = svm->vcpu.run;
2047
2048         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2049         /* instruction emulation calls kvm_set_cr8() */
2050         emulate_instruction(&svm->vcpu, 0, 0, 0);
2051         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2052                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2053                 return 1;
2054         }
2055         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2056                 return 1;
2057         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2058         return 0;
2059 }
2060
2061 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2062 {
2063         struct vcpu_svm *svm = to_svm(vcpu);
2064
2065         switch (ecx) {
2066         case MSR_IA32_TSC: {
2067                 u64 tsc_offset;
2068
2069                 if (is_nested(svm))
2070                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2071                 else
2072                         tsc_offset = svm->vmcb->control.tsc_offset;
2073
2074                 *data = tsc_offset + native_read_tsc();
2075                 break;
2076         }
2077         case MSR_K6_STAR:
2078                 *data = svm->vmcb->save.star;
2079                 break;
2080 #ifdef CONFIG_X86_64
2081         case MSR_LSTAR:
2082                 *data = svm->vmcb->save.lstar;
2083                 break;
2084         case MSR_CSTAR:
2085                 *data = svm->vmcb->save.cstar;
2086                 break;
2087         case MSR_KERNEL_GS_BASE:
2088                 *data = svm->vmcb->save.kernel_gs_base;
2089                 break;
2090         case MSR_SYSCALL_MASK:
2091                 *data = svm->vmcb->save.sfmask;
2092                 break;
2093 #endif
2094         case MSR_IA32_SYSENTER_CS:
2095                 *data = svm->vmcb->save.sysenter_cs;
2096                 break;
2097         case MSR_IA32_SYSENTER_EIP:
2098                 *data = svm->sysenter_eip;
2099                 break;
2100         case MSR_IA32_SYSENTER_ESP:
2101                 *data = svm->sysenter_esp;
2102                 break;
2103         /* Nobody will change the following 5 values in the VMCB so
2104            we can safely return them on rdmsr. They will always be 0
2105            until LBRV is implemented. */
2106         case MSR_IA32_DEBUGCTLMSR:
2107                 *data = svm->vmcb->save.dbgctl;
2108                 break;
2109         case MSR_IA32_LASTBRANCHFROMIP:
2110                 *data = svm->vmcb->save.br_from;
2111                 break;
2112         case MSR_IA32_LASTBRANCHTOIP:
2113                 *data = svm->vmcb->save.br_to;
2114                 break;
2115         case MSR_IA32_LASTINTFROMIP:
2116                 *data = svm->vmcb->save.last_excp_from;
2117                 break;
2118         case MSR_IA32_LASTINTTOIP:
2119                 *data = svm->vmcb->save.last_excp_to;
2120                 break;
2121         case MSR_VM_HSAVE_PA:
2122                 *data = svm->nested.hsave_msr;
2123                 break;
2124         case MSR_VM_CR:
2125                 *data = 0;
2126                 break;
2127         case MSR_IA32_UCODE_REV:
2128                 *data = 0x01000065;
2129                 break;
2130         default:
2131                 return kvm_get_msr_common(vcpu, ecx, data);
2132         }
2133         return 0;
2134 }
2135
2136 static int rdmsr_interception(struct vcpu_svm *svm)
2137 {
2138         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2139         u64 data;
2140
2141         if (svm_get_msr(&svm->vcpu, ecx, &data))
2142                 kvm_inject_gp(&svm->vcpu, 0);
2143         else {
2144                 trace_kvm_msr_read(ecx, data);
2145
2146                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2147                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2148                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2149                 skip_emulated_instruction(&svm->vcpu);
2150         }
2151         return 1;
2152 }
2153
2154 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2155 {
2156         struct vcpu_svm *svm = to_svm(vcpu);
2157
2158         switch (ecx) {
2159         case MSR_IA32_TSC: {
2160                 u64 tsc_offset = data - native_read_tsc();
2161                 u64 g_tsc_offset = 0;
2162
2163                 if (is_nested(svm)) {
2164                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2165                                        svm->nested.hsave->control.tsc_offset;
2166                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2167                 }
2168
2169                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2170
2171                 break;
2172         }
2173         case MSR_K6_STAR:
2174                 svm->vmcb->save.star = data;
2175                 break;
2176 #ifdef CONFIG_X86_64
2177         case MSR_LSTAR:
2178                 svm->vmcb->save.lstar = data;
2179                 break;
2180         case MSR_CSTAR:
2181                 svm->vmcb->save.cstar = data;
2182                 break;
2183         case MSR_KERNEL_GS_BASE:
2184                 svm->vmcb->save.kernel_gs_base = data;
2185                 break;
2186         case MSR_SYSCALL_MASK:
2187                 svm->vmcb->save.sfmask = data;
2188                 break;
2189 #endif
2190         case MSR_IA32_SYSENTER_CS:
2191                 svm->vmcb->save.sysenter_cs = data;
2192                 break;
2193         case MSR_IA32_SYSENTER_EIP:
2194                 svm->sysenter_eip = data;
2195                 svm->vmcb->save.sysenter_eip = data;
2196                 break;
2197         case MSR_IA32_SYSENTER_ESP:
2198                 svm->sysenter_esp = data;
2199                 svm->vmcb->save.sysenter_esp = data;
2200                 break;
2201         case MSR_IA32_DEBUGCTLMSR:
2202                 if (!svm_has(SVM_FEATURE_LBRV)) {
2203                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2204                                         __func__, data);
2205                         break;
2206                 }
2207                 if (data & DEBUGCTL_RESERVED_BITS)
2208                         return 1;
2209
2210                 svm->vmcb->save.dbgctl = data;
2211                 if (data & (1ULL<<0))
2212                         svm_enable_lbrv(svm);
2213                 else
2214                         svm_disable_lbrv(svm);
2215                 break;
2216         case MSR_VM_HSAVE_PA:
2217                 svm->nested.hsave_msr = data;
2218                 break;
2219         case MSR_VM_CR:
2220         case MSR_VM_IGNNE:
2221                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2222                 break;
2223         default:
2224                 return kvm_set_msr_common(vcpu, ecx, data);
2225         }
2226         return 0;
2227 }
2228
2229 static int wrmsr_interception(struct vcpu_svm *svm)
2230 {
2231         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2232         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2233                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2234
2235         trace_kvm_msr_write(ecx, data);
2236
2237         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2238         if (svm_set_msr(&svm->vcpu, ecx, data))
2239                 kvm_inject_gp(&svm->vcpu, 0);
2240         else
2241                 skip_emulated_instruction(&svm->vcpu);
2242         return 1;
2243 }
2244
2245 static int msr_interception(struct vcpu_svm *svm)
2246 {
2247         if (svm->vmcb->control.exit_info_1)
2248                 return wrmsr_interception(svm);
2249         else
2250                 return rdmsr_interception(svm);
2251 }
2252
2253 static int interrupt_window_interception(struct vcpu_svm *svm)
2254 {
2255         struct kvm_run *kvm_run = svm->vcpu.run;
2256
2257         svm_clear_vintr(svm);
2258         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2259         /*
2260          * If the user space waits to inject interrupts, exit as soon as
2261          * possible
2262          */
2263         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2264             kvm_run->request_interrupt_window &&
2265             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2266                 ++svm->vcpu.stat.irq_window_exits;
2267                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2268                 return 0;
2269         }
2270
2271         return 1;
2272 }
2273
2274 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2275         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2276         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2277         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2278         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2279         /* for now: */
2280         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2281         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2282         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2283         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2284         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2285         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2286         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2287         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2288         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2289         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2290         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2291         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2292         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2293         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2294         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2295         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2296         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2297         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2298         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2299         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2300         [SVM_EXIT_INTR]                         = intr_interception,
2301         [SVM_EXIT_NMI]                          = nmi_interception,
2302         [SVM_EXIT_SMI]                          = nop_on_interception,
2303         [SVM_EXIT_INIT]                         = nop_on_interception,
2304         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2305         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2306         [SVM_EXIT_CPUID]                        = cpuid_interception,
2307         [SVM_EXIT_IRET]                         = iret_interception,
2308         [SVM_EXIT_INVD]                         = emulate_on_interception,
2309         [SVM_EXIT_HLT]                          = halt_interception,
2310         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2311         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2312         [SVM_EXIT_IOIO]                         = io_interception,
2313         [SVM_EXIT_MSR]                          = msr_interception,
2314         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2315         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2316         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2317         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2318         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2319         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2320         [SVM_EXIT_STGI]                         = stgi_interception,
2321         [SVM_EXIT_CLGI]                         = clgi_interception,
2322         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2323         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2324         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2325         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2326         [SVM_EXIT_NPF]                          = pf_interception,
2327 };
2328
2329 static int handle_exit(struct kvm_vcpu *vcpu)
2330 {
2331         struct vcpu_svm *svm = to_svm(vcpu);
2332         struct kvm_run *kvm_run = vcpu->run;
2333         u32 exit_code = svm->vmcb->control.exit_code;
2334
2335         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2336
2337         if (is_nested(svm)) {
2338                 int vmexit;
2339
2340                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2341                             exit_code, svm->vmcb->control.exit_info_1,
2342                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2343
2344                 vmexit = nested_svm_exit_special(svm);
2345
2346                 if (vmexit == NESTED_EXIT_CONTINUE)
2347                         vmexit = nested_svm_exit_handled(svm);
2348
2349                 if (vmexit == NESTED_EXIT_DONE)
2350                         return 1;
2351         }
2352
2353         svm_complete_interrupts(svm);
2354
2355         if (npt_enabled) {
2356                 int mmu_reload = 0;
2357                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2358                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2359                         mmu_reload = 1;
2360                 }
2361                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2362                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2363                 if (mmu_reload) {
2364                         kvm_mmu_reset_context(vcpu);
2365                         kvm_mmu_load(vcpu);
2366                 }
2367         }
2368
2369
2370         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2371                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2372                 kvm_run->fail_entry.hardware_entry_failure_reason
2373                         = svm->vmcb->control.exit_code;
2374                 return 0;
2375         }
2376
2377         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2378             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2379             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2380                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2381                        "exit_code 0x%x\n",
2382                        __func__, svm->vmcb->control.exit_int_info,
2383                        exit_code);
2384
2385         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2386             || !svm_exit_handlers[exit_code]) {
2387                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2388                 kvm_run->hw.hardware_exit_reason = exit_code;
2389                 return 0;
2390         }
2391
2392         return svm_exit_handlers[exit_code](svm);
2393 }
2394
2395 static void reload_tss(struct kvm_vcpu *vcpu)
2396 {
2397         int cpu = raw_smp_processor_id();
2398
2399         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2400         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2401         load_TR_desc();
2402 }
2403
2404 static void pre_svm_run(struct vcpu_svm *svm)
2405 {
2406         int cpu = raw_smp_processor_id();
2407
2408         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2409
2410         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2411         /* FIXME: handle wraparound of asid_generation */
2412         if (svm->asid_generation != svm_data->asid_generation)
2413                 new_asid(svm, svm_data);
2414 }
2415
2416 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2417 {
2418         struct vcpu_svm *svm = to_svm(vcpu);
2419
2420         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2421         vcpu->arch.hflags |= HF_NMI_MASK;
2422         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2423         ++vcpu->stat.nmi_injections;
2424 }
2425
2426 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2427 {
2428         struct vmcb_control_area *control;
2429
2430         trace_kvm_inj_virq(irq);
2431
2432         ++svm->vcpu.stat.irq_injections;
2433         control = &svm->vmcb->control;
2434         control->int_vector = irq;
2435         control->int_ctl &= ~V_INTR_PRIO_MASK;
2436         control->int_ctl |= V_IRQ_MASK |
2437                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2438 }
2439
2440 static void svm_set_irq(struct kvm_vcpu *vcpu)
2441 {
2442         struct vcpu_svm *svm = to_svm(vcpu);
2443
2444         BUG_ON(!(gif_set(svm)));
2445
2446         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2447                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2448 }
2449
2450 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2451 {
2452         struct vcpu_svm *svm = to_svm(vcpu);
2453
2454         if (irr == -1)
2455                 return;
2456
2457         if (tpr >= irr)
2458                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2459 }
2460
2461 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2462 {
2463         struct vcpu_svm *svm = to_svm(vcpu);
2464         struct vmcb *vmcb = svm->vmcb;
2465         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2466                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2467 }
2468
2469 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2470 {
2471         struct vcpu_svm *svm = to_svm(vcpu);
2472         struct vmcb *vmcb = svm->vmcb;
2473         int ret;
2474
2475         if (!gif_set(svm) ||
2476              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2477                 return 0;
2478
2479         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2480
2481         if (is_nested(svm))
2482                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2483
2484         return ret;
2485 }
2486
2487 static void enable_irq_window(struct kvm_vcpu *vcpu)
2488 {
2489         struct vcpu_svm *svm = to_svm(vcpu);
2490         nsvm_printk("Trying to open IRQ window\n");
2491
2492         nested_svm_intr(svm);
2493
2494         /* In case GIF=0 we can't rely on the CPU to tell us when
2495          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2496          * The next time we get that intercept, this function will be
2497          * called again though and we'll get the vintr intercept. */
2498         if (gif_set(svm)) {
2499                 svm_set_vintr(svm);
2500                 svm_inject_irq(svm, 0x0);
2501         }
2502 }
2503
2504 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2505 {
2506         struct vcpu_svm *svm = to_svm(vcpu);
2507
2508         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2509             == HF_NMI_MASK)
2510                 return; /* IRET will cause a vm exit */
2511
2512         /* Something prevents NMI from been injected. Single step over
2513            possible problem (IRET or exception injection or interrupt
2514            shadow) */
2515         vcpu->arch.singlestep = true;
2516         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2517         update_db_intercept(vcpu);
2518 }
2519
2520 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2521 {
2522         return 0;
2523 }
2524
2525 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2526 {
2527         force_new_asid(vcpu);
2528 }
2529
2530 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2531 {
2532 }
2533
2534 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2535 {
2536         struct vcpu_svm *svm = to_svm(vcpu);
2537
2538         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2539                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2540                 kvm_set_cr8(vcpu, cr8);
2541         }
2542 }
2543
2544 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2545 {
2546         struct vcpu_svm *svm = to_svm(vcpu);
2547         u64 cr8;
2548
2549         cr8 = kvm_get_cr8(vcpu);
2550         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2551         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2552 }
2553
2554 static void svm_complete_interrupts(struct vcpu_svm *svm)
2555 {
2556         u8 vector;
2557         int type;
2558         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2559
2560         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2561                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2562
2563         svm->vcpu.arch.nmi_injected = false;
2564         kvm_clear_exception_queue(&svm->vcpu);
2565         kvm_clear_interrupt_queue(&svm->vcpu);
2566
2567         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2568                 return;
2569
2570         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2571         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2572
2573         switch (type) {
2574         case SVM_EXITINTINFO_TYPE_NMI:
2575                 svm->vcpu.arch.nmi_injected = true;
2576                 break;
2577         case SVM_EXITINTINFO_TYPE_EXEPT:
2578                 /* In case of software exception do not reinject an exception
2579                    vector, but re-execute and instruction instead */
2580                 if (is_nested(svm))
2581                         break;
2582                 if (kvm_exception_is_soft(vector))
2583                         break;
2584                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2585                         u32 err = svm->vmcb->control.exit_int_info_err;
2586                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2587
2588                 } else
2589                         kvm_queue_exception(&svm->vcpu, vector);
2590                 break;
2591         case SVM_EXITINTINFO_TYPE_INTR:
2592                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2593                 break;
2594         default:
2595                 break;
2596         }
2597 }
2598
2599 #ifdef CONFIG_X86_64
2600 #define R "r"
2601 #else
2602 #define R "e"
2603 #endif
2604
2605 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2606 {
2607         struct vcpu_svm *svm = to_svm(vcpu);
2608         u16 fs_selector;
2609         u16 gs_selector;
2610         u16 ldt_selector;
2611
2612         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2613         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2614         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2615
2616         pre_svm_run(svm);
2617
2618         sync_lapic_to_cr8(vcpu);
2619
2620         save_host_msrs(vcpu);
2621         fs_selector = kvm_read_fs();
2622         gs_selector = kvm_read_gs();
2623         ldt_selector = kvm_read_ldt();
2624         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2625         /* required for live migration with NPT */
2626         if (npt_enabled)
2627                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2628
2629         clgi();
2630
2631         local_irq_enable();
2632
2633         asm volatile (
2634                 "push %%"R"bp; \n\t"
2635                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2636                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2637                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2638                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2639                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2640                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2641 #ifdef CONFIG_X86_64
2642                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2643                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2644                 "mov %c[r10](%[svm]), %%r10 \n\t"
2645                 "mov %c[r11](%[svm]), %%r11 \n\t"
2646                 "mov %c[r12](%[svm]), %%r12 \n\t"
2647                 "mov %c[r13](%[svm]), %%r13 \n\t"
2648                 "mov %c[r14](%[svm]), %%r14 \n\t"
2649                 "mov %c[r15](%[svm]), %%r15 \n\t"
2650 #endif
2651
2652                 /* Enter guest mode */
2653                 "push %%"R"ax \n\t"
2654                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2655                 __ex(SVM_VMLOAD) "\n\t"
2656                 __ex(SVM_VMRUN) "\n\t"
2657                 __ex(SVM_VMSAVE) "\n\t"
2658                 "pop %%"R"ax \n\t"
2659
2660                 /* Save guest registers, load host registers */
2661                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2662                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2663                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2664                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2665                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2666                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2667 #ifdef CONFIG_X86_64
2668                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2669                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2670                 "mov %%r10, %c[r10](%[svm]) \n\t"
2671                 "mov %%r11, %c[r11](%[svm]) \n\t"
2672                 "mov %%r12, %c[r12](%[svm]) \n\t"
2673                 "mov %%r13, %c[r13](%[svm]) \n\t"
2674                 "mov %%r14, %c[r14](%[svm]) \n\t"
2675                 "mov %%r15, %c[r15](%[svm]) \n\t"
2676 #endif
2677                 "pop %%"R"bp"
2678                 :
2679                 : [svm]"a"(svm),
2680                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2681                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2682                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2683                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2684                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2685                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2686                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2687 #ifdef CONFIG_X86_64
2688                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2689                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2690                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2691                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2692                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2693                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2694                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2695                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2696 #endif
2697                 : "cc", "memory"
2698                 , R"bx", R"cx", R"dx", R"si", R"di"
2699 #ifdef CONFIG_X86_64
2700                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2701 #endif
2702                 );
2703
2704         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2705         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2706         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2707         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2708
2709         kvm_load_fs(fs_selector);
2710         kvm_load_gs(gs_selector);
2711         kvm_load_ldt(ldt_selector);
2712         load_host_msrs(vcpu);
2713
2714         reload_tss(vcpu);
2715
2716         local_irq_disable();
2717
2718         stgi();
2719
2720         sync_cr8_to_lapic(vcpu);
2721
2722         svm->next_rip = 0;
2723
2724         if (npt_enabled) {
2725                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2726                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2727         }
2728 }
2729
2730 #undef R
2731
2732 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2733 {
2734         struct vcpu_svm *svm = to_svm(vcpu);
2735
2736         if (npt_enabled) {
2737                 svm->vmcb->control.nested_cr3 = root;
2738                 force_new_asid(vcpu);
2739                 return;
2740         }
2741
2742         svm->vmcb->save.cr3 = root;
2743         force_new_asid(vcpu);
2744
2745         if (vcpu->fpu_active) {
2746                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2747                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2748                 vcpu->fpu_active = 0;
2749         }
2750 }
2751
2752 static int is_disabled(void)
2753 {
2754         u64 vm_cr;
2755
2756         rdmsrl(MSR_VM_CR, vm_cr);
2757         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2758                 return 1;
2759
2760         return 0;
2761 }
2762
2763 static void
2764 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2765 {
2766         /*
2767          * Patch in the VMMCALL instruction:
2768          */
2769         hypercall[0] = 0x0f;
2770         hypercall[1] = 0x01;
2771         hypercall[2] = 0xd9;
2772 }
2773
2774 static void svm_check_processor_compat(void *rtn)
2775 {
2776         *(int *)rtn = 0;
2777 }
2778
2779 static bool svm_cpu_has_accelerated_tpr(void)
2780 {
2781         return false;
2782 }
2783
2784 static int get_npt_level(void)
2785 {
2786 #ifdef CONFIG_X86_64
2787         return PT64_ROOT_LEVEL;
2788 #else
2789         return PT32E_ROOT_LEVEL;
2790 #endif
2791 }
2792
2793 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2794 {
2795         return 0;
2796 }
2797
2798 static const struct trace_print_flags svm_exit_reasons_str[] = {
2799         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2800         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2801         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2802         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2803         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2804         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2805         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2806         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2807         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2808         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2809         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2810         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2811         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2812         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2813         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2814         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2815         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2816         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2817         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2818         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2819         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2820         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2821         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2822         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2823         { SVM_EXIT_INTR,                        "interrupt" },
2824         { SVM_EXIT_NMI,                         "nmi" },
2825         { SVM_EXIT_SMI,                         "smi" },
2826         { SVM_EXIT_INIT,                        "init" },
2827         { SVM_EXIT_VINTR,                       "vintr" },
2828         { SVM_EXIT_CPUID,                       "cpuid" },
2829         { SVM_EXIT_INVD,                        "invd" },
2830         { SVM_EXIT_HLT,                         "hlt" },
2831         { SVM_EXIT_INVLPG,                      "invlpg" },
2832         { SVM_EXIT_INVLPGA,                     "invlpga" },
2833         { SVM_EXIT_IOIO,                        "io" },
2834         { SVM_EXIT_MSR,                         "msr" },
2835         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2836         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2837         { SVM_EXIT_VMRUN,                       "vmrun" },
2838         { SVM_EXIT_VMMCALL,                     "hypercall" },
2839         { SVM_EXIT_VMLOAD,                      "vmload" },
2840         { SVM_EXIT_VMSAVE,                      "vmsave" },
2841         { SVM_EXIT_STGI,                        "stgi" },
2842         { SVM_EXIT_CLGI,                        "clgi" },
2843         { SVM_EXIT_SKINIT,                      "skinit" },
2844         { SVM_EXIT_WBINVD,                      "wbinvd" },
2845         { SVM_EXIT_MONITOR,                     "monitor" },
2846         { SVM_EXIT_MWAIT,                       "mwait" },
2847         { SVM_EXIT_NPF,                         "npf" },
2848         { -1, NULL }
2849 };
2850
2851 static bool svm_gb_page_enable(void)
2852 {
2853         return true;
2854 }
2855
2856 static struct kvm_x86_ops svm_x86_ops = {
2857         .cpu_has_kvm_support = has_svm,
2858         .disabled_by_bios = is_disabled,
2859         .hardware_setup = svm_hardware_setup,
2860         .hardware_unsetup = svm_hardware_unsetup,
2861         .check_processor_compatibility = svm_check_processor_compat,
2862         .hardware_enable = svm_hardware_enable,
2863         .hardware_disable = svm_hardware_disable,
2864         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2865
2866         .vcpu_create = svm_create_vcpu,
2867         .vcpu_free = svm_free_vcpu,
2868         .vcpu_reset = svm_vcpu_reset,
2869
2870         .prepare_guest_switch = svm_prepare_guest_switch,
2871         .vcpu_load = svm_vcpu_load,
2872         .vcpu_put = svm_vcpu_put,
2873
2874         .set_guest_debug = svm_guest_debug,
2875         .get_msr = svm_get_msr,
2876         .set_msr = svm_set_msr,
2877         .get_segment_base = svm_get_segment_base,
2878         .get_segment = svm_get_segment,
2879         .set_segment = svm_set_segment,
2880         .get_cpl = svm_get_cpl,
2881         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2882         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2883         .set_cr0 = svm_set_cr0,
2884         .set_cr3 = svm_set_cr3,
2885         .set_cr4 = svm_set_cr4,
2886         .set_efer = svm_set_efer,
2887         .get_idt = svm_get_idt,
2888         .set_idt = svm_set_idt,
2889         .get_gdt = svm_get_gdt,
2890         .set_gdt = svm_set_gdt,
2891         .get_dr = svm_get_dr,
2892         .set_dr = svm_set_dr,
2893         .cache_reg = svm_cache_reg,
2894         .get_rflags = svm_get_rflags,
2895         .set_rflags = svm_set_rflags,
2896
2897         .tlb_flush = svm_flush_tlb,
2898
2899         .run = svm_vcpu_run,
2900         .handle_exit = handle_exit,
2901         .skip_emulated_instruction = skip_emulated_instruction,
2902         .set_interrupt_shadow = svm_set_interrupt_shadow,
2903         .get_interrupt_shadow = svm_get_interrupt_shadow,
2904         .patch_hypercall = svm_patch_hypercall,
2905         .set_irq = svm_set_irq,
2906         .set_nmi = svm_inject_nmi,
2907         .queue_exception = svm_queue_exception,
2908         .interrupt_allowed = svm_interrupt_allowed,
2909         .nmi_allowed = svm_nmi_allowed,
2910         .enable_nmi_window = enable_nmi_window,
2911         .enable_irq_window = enable_irq_window,
2912         .update_cr8_intercept = update_cr8_intercept,
2913
2914         .set_tss_addr = svm_set_tss_addr,
2915         .get_tdp_level = get_npt_level,
2916         .get_mt_mask = svm_get_mt_mask,
2917
2918         .exit_reasons_str = svm_exit_reasons_str,
2919         .gb_page_enable = svm_gb_page_enable,
2920 };
2921
2922 static int __init svm_init(void)
2923 {
2924         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2925                               THIS_MODULE);
2926 }
2927
2928 static void __exit svm_exit(void)
2929 {
2930         kvm_exit();
2931 }
2932
2933 module_init(svm_init)
2934 module_exit(svm_exit)