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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 #define IOPM_ALLOC_ORDER 2
  40 #define MSRPM_ALLOC_ORDER 1
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* Turn on to get debugging output*/
  52 /* #define NESTED_DEBUG */
  53
  54 #ifdef NESTED_DEBUG
  55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  56 #else
  57 #define nsvm_printk(fmt, args...) do {} while(0)
  58 #endif
  59
  60 /* enable NPT for AMD64 and X86 with PAE */
  61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  62 static bool npt_enabled = true;
  63 #else
  64 static bool npt_enabled = false;
  65 #endif
  66 static int npt = 1;
  67
  68 module_param(npt, int, S_IRUGO);
  69
  70 static int nested = 0;
  71 module_param(nested, int, S_IRUGO);
  72
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline void clgi(void)
 136 {
 137         asm volatile (__ex(SVM_CLGI));
 138 }
 139
 140 static inline void stgi(void)
 141 {
 142         asm volatile (__ex(SVM_STGI));
 143 }
 144
 145 static inline void invlpga(unsigned long addr, u32 asid)
 146 {
 147         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 148 }
 149
 150 static inline unsigned long kvm_read_cr2(void)
 151 {
 152         unsigned long cr2;
 153
 154         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 155         return cr2;
 156 }
 157
 158 static inline void kvm_write_cr2(unsigned long val)
 159 {
 160         asm volatile ("mov %0, %%cr2" :: "r" (val));
 161 }
 162
 163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 164 {
 165         to_svm(vcpu)->asid_generation--;
 166 }
 167
 168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 169 {
 170         force_new_asid(vcpu);
 171 }
 172
 173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 174 {
 175         if (!npt_enabled && !(efer & EFER_LMA))
 176                 efer &= ~EFER_LME;
 177
 178         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 179         vcpu->arch.shadow_efer = efer;
 180 }
 181
 182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 183                                 bool has_error_code, u32 error_code)
 184 {
 185         struct vcpu_svm *svm = to_svm(vcpu);
 186
 187         /* If we are within a nested VM we'd better #VMEXIT and let the
 188            guest handle the exception */
 189         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 190                 return;
 191
 192         svm->vmcb->control.event_inj = nr
 193                 | SVM_EVTINJ_VALID
 194                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 195                 | SVM_EVTINJ_TYPE_EXEPT;
 196         svm->vmcb->control.event_inj_err = error_code;
 197 }
 198
 199 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 200 {
 201         return false;
 202 }
 203
 204 static int is_external_interrupt(u32 info)
 205 {
 206         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 207         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 208 }
 209
 210 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 211 {
 212         struct vcpu_svm *svm = to_svm(vcpu);
 213
 214         if (!svm->next_rip) {
 215                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 216                 return;
 217         }
 218         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 219                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 220                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 221
 222         kvm_rip_write(vcpu, svm->next_rip);
 223         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 224
 225         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 226 }
 227
 228 static int has_svm(void)
 229 {
 230         const char *msg;
 231
 232         if (!cpu_has_svm(&msg)) {
 233                 printk(KERN_INFO "has_svm: %s\n", msg);
 234                 return 0;
 235         }
 236
 237         return 1;
 238 }
 239
 240 static void svm_hardware_disable(void *garbage)
 241 {
 242         cpu_svm_disable();
 243 }
 244
 245 static void svm_hardware_enable(void *garbage)
 246 {
 247
 248         struct svm_cpu_data *svm_data;
 249         uint64_t efer;
 250         struct desc_ptr gdt_descr;
 251         struct desc_struct *gdt;
 252         int me = raw_smp_processor_id();
 253
 254         if (!has_svm()) {
 255                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 256                 return;
 257         }
 258         svm_data = per_cpu(svm_data, me);
 259
 260         if (!svm_data) {
 261                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 262                        me);
 263                 return;
 264         }
 265
 266         svm_data->asid_generation = 1;
 267         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 268         svm_data->next_asid = svm_data->max_asid + 1;
 269
 270         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 271         gdt = (struct desc_struct *)gdt_descr.address;
 272         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 273
 274         rdmsrl(MSR_EFER, efer);
 275         wrmsrl(MSR_EFER, efer | EFER_SVME);
 276
 277         wrmsrl(MSR_VM_HSAVE_PA,
 278                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 279 }
 280
 281 static void svm_cpu_uninit(int cpu)
 282 {
 283         struct svm_cpu_data *svm_data
 284                 = per_cpu(svm_data, raw_smp_processor_id());
 285
 286         if (!svm_data)
 287                 return;
 288
 289         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 290         __free_page(svm_data->save_area);
 291         kfree(svm_data);
 292 }
 293
 294 static int svm_cpu_init(int cpu)
 295 {
 296         struct svm_cpu_data *svm_data;
 297         int r;
 298
 299         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 300         if (!svm_data)
 301                 return -ENOMEM;
 302         svm_data->cpu = cpu;
 303         svm_data->save_area = alloc_page(GFP_KERNEL);
 304         r = -ENOMEM;
 305         if (!svm_data->save_area)
 306                 goto err_1;
 307
 308         per_cpu(svm_data, cpu) = svm_data;
 309
 310         return 0;
 311
 312 err_1:
 313         kfree(svm_data);
 314         return r;
 315
 316 }
 317
 318 static void set_msr_interception(u32 *msrpm, unsigned msr,
 319                                  int read, int write)
 320 {
 321         int i;
 322
 323         for (i = 0; i < NUM_MSR_MAPS; i++) {
 324                 if (msr >= msrpm_ranges[i] &&
 325                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 326                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 327                                           msrpm_ranges[i]) * 2;
 328
 329                         u32 *base = msrpm + (msr_offset / 32);
 330                         u32 msr_shift = msr_offset % 32;
 331                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 332                         *base = (*base & ~(0x3 << msr_shift)) |
 333                                 (mask << msr_shift);
 334                         return;
 335                 }
 336         }
 337         BUG();
 338 }
 339
 340 static void svm_vcpu_init_msrpm(u32 *msrpm)
 341 {
 342         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 343
 344 #ifdef CONFIG_X86_64
 345         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 346         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 347         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 348         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 349         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 350         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 351 #endif
 352         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 353         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 354         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 355         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 356 }
 357
 358 static void svm_enable_lbrv(struct vcpu_svm *svm)
 359 {
 360         u32 *msrpm = svm->msrpm;
 361
 362         svm->vmcb->control.lbr_ctl = 1;
 363         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 364         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 365         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 366         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 367 }
 368
 369 static void svm_disable_lbrv(struct vcpu_svm *svm)
 370 {
 371         u32 *msrpm = svm->msrpm;
 372
 373         svm->vmcb->control.lbr_ctl = 0;
 374         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 375         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 376         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 377         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 378 }
 379
 380 static __init int svm_hardware_setup(void)
 381 {
 382         int cpu;
 383         struct page *iopm_pages;
 384         void *iopm_va;
 385         int r;
 386
 387         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 388
 389         if (!iopm_pages)
 390                 return -ENOMEM;
 391
 392         iopm_va = page_address(iopm_pages);
 393         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 394         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 395
 396         if (boot_cpu_has(X86_FEATURE_NX))
 397                 kvm_enable_efer_bits(EFER_NX);
 398
 399         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 400                 kvm_enable_efer_bits(EFER_FFXSR);
 401
 402         if (nested) {
 403                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 404                 kvm_enable_efer_bits(EFER_SVME);
 405         }
 406
 407         for_each_online_cpu(cpu) {
 408                 r = svm_cpu_init(cpu);
 409                 if (r)
 410                         goto err;
 411         }
 412
 413         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 414
 415         if (!svm_has(SVM_FEATURE_NPT))
 416                 npt_enabled = false;
 417
 418         if (npt_enabled && !npt) {
 419                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 420                 npt_enabled = false;
 421         }
 422
 423         if (npt_enabled) {
 424                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 425                 kvm_enable_tdp();
 426         } else
 427                 kvm_disable_tdp();
 428
 429         return 0;
 430
 431 err:
 432         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 433         iopm_base = 0;
 434         return r;
 435 }
 436
 437 static __exit void svm_hardware_unsetup(void)
 438 {
 439         int cpu;
 440
 441         for_each_online_cpu(cpu)
 442                 svm_cpu_uninit(cpu);
 443
 444         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 445         iopm_base = 0;
 446 }
 447
 448 static void init_seg(struct vmcb_seg *seg)
 449 {
 450         seg->selector = 0;
 451         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 452                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 453         seg->limit = 0xffff;
 454         seg->base = 0;
 455 }
 456
 457 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 458 {
 459         seg->selector = 0;
 460         seg->attrib = SVM_SELECTOR_P_MASK | type;
 461         seg->limit = 0xffff;
 462         seg->base = 0;
 463 }
 464
 465 static void init_vmcb(struct vcpu_svm *svm)
 466 {
 467         struct vmcb_control_area *control = &svm->vmcb->control;
 468         struct vmcb_save_area *save = &svm->vmcb->save;
 469
 470         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 471                                         INTERCEPT_CR3_MASK |
 472                                         INTERCEPT_CR4_MASK;
 473
 474         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 475                                         INTERCEPT_CR3_MASK |
 476                                         INTERCEPT_CR4_MASK |
 477                                         INTERCEPT_CR8_MASK;
 478
 479         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 480                                         INTERCEPT_DR1_MASK |
 481                                         INTERCEPT_DR2_MASK |
 482                                         INTERCEPT_DR3_MASK;
 483
 484         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 485                                         INTERCEPT_DR1_MASK |
 486                                         INTERCEPT_DR2_MASK |
 487                                         INTERCEPT_DR3_MASK |
 488                                         INTERCEPT_DR5_MASK |
 489                                         INTERCEPT_DR7_MASK;
 490
 491         control->intercept_exceptions = (1 << PF_VECTOR) |
 492                                         (1 << UD_VECTOR) |
 493                                         (1 << MC_VECTOR);
 494
 495
 496         control->intercept =    (1ULL << INTERCEPT_INTR) |
 497                                 (1ULL << INTERCEPT_NMI) |
 498                                 (1ULL << INTERCEPT_SMI) |
 499                                 (1ULL << INTERCEPT_CPUID) |
 500                                 (1ULL << INTERCEPT_INVD) |
 501                                 (1ULL << INTERCEPT_HLT) |
 502                                 (1ULL << INTERCEPT_INVLPG) |
 503                                 (1ULL << INTERCEPT_INVLPGA) |
 504                                 (1ULL << INTERCEPT_IOIO_PROT) |
 505                                 (1ULL << INTERCEPT_MSR_PROT) |
 506                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 507                                 (1ULL << INTERCEPT_SHUTDOWN) |
 508                                 (1ULL << INTERCEPT_VMRUN) |
 509                                 (1ULL << INTERCEPT_VMMCALL) |
 510                                 (1ULL << INTERCEPT_VMLOAD) |
 511                                 (1ULL << INTERCEPT_VMSAVE) |
 512                                 (1ULL << INTERCEPT_STGI) |
 513                                 (1ULL << INTERCEPT_CLGI) |
 514                                 (1ULL << INTERCEPT_SKINIT) |
 515                                 (1ULL << INTERCEPT_WBINVD) |
 516                                 (1ULL << INTERCEPT_MONITOR) |
 517                                 (1ULL << INTERCEPT_MWAIT);
 518
 519         control->iopm_base_pa = iopm_base;
 520         control->msrpm_base_pa = __pa(svm->msrpm);
 521         control->tsc_offset = 0;
 522         control->int_ctl = V_INTR_MASKING_MASK;
 523
 524         init_seg(&save->es);
 525         init_seg(&save->ss);
 526         init_seg(&save->ds);
 527         init_seg(&save->fs);
 528         init_seg(&save->gs);
 529
 530         save->cs.selector = 0xf000;
 531         /* Executable/Readable Code Segment */
 532         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 533                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 534         save->cs.limit = 0xffff;
 535         /*
 536          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 537          * be consistent with it.
 538          *
 539          * Replace when we have real mode working for vmx.
 540          */
 541         save->cs.base = 0xf0000;
 542
 543         save->gdtr.limit = 0xffff;
 544         save->idtr.limit = 0xffff;
 545
 546         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 547         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 548
 549         save->efer = EFER_SVME;
 550         save->dr6 = 0xffff0ff0;
 551         save->dr7 = 0x400;
 552         save->rflags = 2;
 553         save->rip = 0x0000fff0;
 554         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 555
 556         /*
 557          * cr0 val on cpu init should be 0x60000010, we enable cpu
 558          * cache by default. the orderly way is to enable cache in bios.
 559          */
 560         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 561         save->cr4 = X86_CR4_PAE;
 562         /* rdx = ?? */
 563
 564         if (npt_enabled) {
 565                 /* Setup VMCB for Nested Paging */
 566                 control->nested_ctl = 1;
 567                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 568                                         (1ULL << INTERCEPT_INVLPG));
 569                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 570                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 571                                                 INTERCEPT_CR3_MASK);
 572                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 573                                                  INTERCEPT_CR3_MASK);
 574                 save->g_pat = 0x0007040600070406ULL;
 575                 /* enable caching because the QEMU Bios doesn't enable it */
 576                 save->cr0 = X86_CR0_ET;
 577                 save->cr3 = 0;
 578                 save->cr4 = 0;
 579         }
 580         force_new_asid(&svm->vcpu);
 581
 582         svm->nested_vmcb = 0;
 583         svm->vcpu.arch.hflags = HF_GIF_MASK;
 584 }
 585
 586 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 587 {
 588         struct vcpu_svm *svm = to_svm(vcpu);
 589
 590         init_vmcb(svm);
 591
 592         if (vcpu->vcpu_id != 0) {
 593                 kvm_rip_write(vcpu, 0);
 594                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 595                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 596         }
 597         vcpu->arch.regs_avail = ~0;
 598         vcpu->arch.regs_dirty = ~0;
 599
 600         return 0;
 601 }
 602
 603 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 604 {
 605         struct vcpu_svm *svm;
 606         struct page *page;
 607         struct page *msrpm_pages;
 608         struct page *hsave_page;
 609         struct page *nested_msrpm_pages;
 610         int err;
 611
 612         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 613         if (!svm) {
 614                 err = -ENOMEM;
 615                 goto out;
 616         }
 617
 618         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 619         if (err)
 620                 goto free_svm;
 621
 622         page = alloc_page(GFP_KERNEL);
 623         if (!page) {
 624                 err = -ENOMEM;
 625                 goto uninit;
 626         }
 627
 628         err = -ENOMEM;
 629         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 630         if (!msrpm_pages)
 631                 goto uninit;
 632
 633         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 634         if (!nested_msrpm_pages)
 635                 goto uninit;
 636
 637         svm->msrpm = page_address(msrpm_pages);
 638         svm_vcpu_init_msrpm(svm->msrpm);
 639
 640         hsave_page = alloc_page(GFP_KERNEL);
 641         if (!hsave_page)
 642                 goto uninit;
 643         svm->hsave = page_address(hsave_page);
 644
 645         svm->nested_msrpm = page_address(nested_msrpm_pages);
 646
 647         svm->vmcb = page_address(page);
 648         clear_page(svm->vmcb);
 649         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 650         svm->asid_generation = 0;
 651         init_vmcb(svm);
 652
 653         fx_init(&svm->vcpu);
 654         svm->vcpu.fpu_active = 1;
 655         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 656         if (svm->vcpu.vcpu_id == 0)
 657                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 658
 659         return &svm->vcpu;
 660
 661 uninit:
 662         kvm_vcpu_uninit(&svm->vcpu);
 663 free_svm:
 664         kmem_cache_free(kvm_vcpu_cache, svm);
 665 out:
 666         return ERR_PTR(err);
 667 }
 668
 669 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 670 {
 671         struct vcpu_svm *svm = to_svm(vcpu);
 672
 673         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 674         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 675         __free_page(virt_to_page(svm->hsave));
 676         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 677         kvm_vcpu_uninit(vcpu);
 678         kmem_cache_free(kvm_vcpu_cache, svm);
 679 }
 680
 681 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 682 {
 683         struct vcpu_svm *svm = to_svm(vcpu);
 684         int i;
 685
 686         if (unlikely(cpu != vcpu->cpu)) {
 687                 u64 tsc_this, delta;
 688
 689                 /*
 690                  * Make sure that the guest sees a monotonically
 691                  * increasing TSC.
 692                  */
 693                 rdtscll(tsc_this);
 694                 delta = vcpu->arch.host_tsc - tsc_this;
 695                 svm->vmcb->control.tsc_offset += delta;
 696                 vcpu->cpu = cpu;
 697                 kvm_migrate_timers(vcpu);
 698         }
 699
 700         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 701                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 702 }
 703
 704 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 705 {
 706         struct vcpu_svm *svm = to_svm(vcpu);
 707         int i;
 708
 709         ++vcpu->stat.host_state_reload;
 710         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 711                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 712
 713         rdtscll(vcpu->arch.host_tsc);
 714 }
 715
 716 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 717 {
 718         return to_svm(vcpu)->vmcb->save.rflags;
 719 }
 720
 721 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 722 {
 723         to_svm(vcpu)->vmcb->save.rflags = rflags;
 724 }
 725
 726 static void svm_set_vintr(struct vcpu_svm *svm)
 727 {
 728         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 729 }
 730
 731 static void svm_clear_vintr(struct vcpu_svm *svm)
 732 {
 733         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 734 }
 735
 736 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 737 {
 738         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 739
 740         switch (seg) {
 741         case VCPU_SREG_CS: return &save->cs;
 742         case VCPU_SREG_DS: return &save->ds;
 743         case VCPU_SREG_ES: return &save->es;
 744         case VCPU_SREG_FS: return &save->fs;
 745         case VCPU_SREG_GS: return &save->gs;
 746         case VCPU_SREG_SS: return &save->ss;
 747         case VCPU_SREG_TR: return &save->tr;
 748         case VCPU_SREG_LDTR: return &save->ldtr;
 749         }
 750         BUG();
 751         return NULL;
 752 }
 753
 754 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 755 {
 756         struct vmcb_seg *s = svm_seg(vcpu, seg);
 757
 758         return s->base;
 759 }
 760
 761 static void svm_get_segment(struct kvm_vcpu *vcpu,
 762                             struct kvm_segment *var, int seg)
 763 {
 764         struct vmcb_seg *s = svm_seg(vcpu, seg);
 765
 766         var->base = s->base;
 767         var->limit = s->limit;
 768         var->selector = s->selector;
 769         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 770         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 771         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 772         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 773         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 774         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 775         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 776         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 777
 778         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 779          * for cross vendor migration purposes by "not present"
 780          */
 781         var->unusable = !var->present || (var->type == 0);
 782
 783         switch (seg) {
 784         case VCPU_SREG_CS:
 785                 /*
 786                  * SVM always stores 0 for the 'G' bit in the CS selector in
 787                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 788                  * Intel's VMENTRY has a check on the 'G' bit.
 789                  */
 790                 var->g = s->limit > 0xfffff;
 791                 break;
 792         case VCPU_SREG_TR:
 793                 /*
 794                  * Work around a bug where the busy flag in the tr selector
 795                  * isn't exposed
 796                  */
 797                 var->type |= 0x2;
 798                 break;
 799         case VCPU_SREG_DS:
 800         case VCPU_SREG_ES:
 801         case VCPU_SREG_FS:
 802         case VCPU_SREG_GS:
 803                 /*
 804                  * The accessed bit must always be set in the segment
 805                  * descriptor cache, although it can be cleared in the
 806                  * descriptor, the cached bit always remains at 1. Since
 807                  * Intel has a check on this, set it here to support
 808                  * cross-vendor migration.
 809                  */
 810                 if (!var->unusable)
 811                         var->type |= 0x1;
 812                 break;
 813         }
 814 }
 815
 816 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 817 {
 818         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 819
 820         return save->cpl;
 821 }
 822
 823 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 824 {
 825         struct vcpu_svm *svm = to_svm(vcpu);
 826
 827         dt->limit = svm->vmcb->save.idtr.limit;
 828         dt->base = svm->vmcb->save.idtr.base;
 829 }
 830
 831 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 832 {
 833         struct vcpu_svm *svm = to_svm(vcpu);
 834
 835         svm->vmcb->save.idtr.limit = dt->limit;
 836         svm->vmcb->save.idtr.base = dt->base ;
 837 }
 838
 839 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 840 {
 841         struct vcpu_svm *svm = to_svm(vcpu);
 842
 843         dt->limit = svm->vmcb->save.gdtr.limit;
 844         dt->base = svm->vmcb->save.gdtr.base;
 845 }
 846
 847 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 848 {
 849         struct vcpu_svm *svm = to_svm(vcpu);
 850
 851         svm->vmcb->save.gdtr.limit = dt->limit;
 852         svm->vmcb->save.gdtr.base = dt->base ;
 853 }
 854
 855 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 856 {
 857 }
 858
 859 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 860 {
 861         struct vcpu_svm *svm = to_svm(vcpu);
 862
 863 #ifdef CONFIG_X86_64
 864         if (vcpu->arch.shadow_efer & EFER_LME) {
 865                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 866                         vcpu->arch.shadow_efer |= EFER_LMA;
 867                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 868                 }
 869
 870                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 871                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 872                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 873                 }
 874         }
 875 #endif
 876         if (npt_enabled)
 877                 goto set;
 878
 879         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 880                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 881                 vcpu->fpu_active = 1;
 882         }
 883
 884         vcpu->arch.cr0 = cr0;
 885         cr0 |= X86_CR0_PG | X86_CR0_WP;
 886         if (!vcpu->fpu_active) {
 887                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 888                 cr0 |= X86_CR0_TS;
 889         }
 890 set:
 891         /*
 892          * re-enable caching here because the QEMU bios
 893          * does not do it - this results in some delay at
 894          * reboot
 895          */
 896         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 897         svm->vmcb->save.cr0 = cr0;
 898 }
 899
 900 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 901 {
 902         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 903         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 904
 905         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 906                 force_new_asid(vcpu);
 907
 908         vcpu->arch.cr4 = cr4;
 909         if (!npt_enabled)
 910                 cr4 |= X86_CR4_PAE;
 911         cr4 |= host_cr4_mce;
 912         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 913 }
 914
 915 static void svm_set_segment(struct kvm_vcpu *vcpu,
 916                             struct kvm_segment *var, int seg)
 917 {
 918         struct vcpu_svm *svm = to_svm(vcpu);
 919         struct vmcb_seg *s = svm_seg(vcpu, seg);
 920
 921         s->base = var->base;
 922         s->limit = var->limit;
 923         s->selector = var->selector;
 924         if (var->unusable)
 925                 s->attrib = 0;
 926         else {
 927                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 928                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 929                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 930                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 931                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 932                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 933                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 934                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 935         }
 936         if (seg == VCPU_SREG_CS)
 937                 svm->vmcb->save.cpl
 938                         = (svm->vmcb->save.cs.attrib
 939                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 940
 941 }
 942
 943 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 944 {
 945         int old_debug = vcpu->guest_debug;
 946         struct vcpu_svm *svm = to_svm(vcpu);
 947
 948         vcpu->guest_debug = dbg->control;
 949
 950         svm->vmcb->control.intercept_exceptions &=
 951                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 952         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 953                 if (vcpu->guest_debug &
 954                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 955                         svm->vmcb->control.intercept_exceptions |=
 956                                 1 << DB_VECTOR;
 957                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 958                         svm->vmcb->control.intercept_exceptions |=
 959                                 1 << BP_VECTOR;
 960         } else
 961                 vcpu->guest_debug = 0;
 962
 963         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 964                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
 965         else
 966                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
 967
 968         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
 969                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
 970         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
 971                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 972
 973         return 0;
 974 }
 975
 976 static int svm_get_irq(struct kvm_vcpu *vcpu)
 977 {
 978         if (!vcpu->arch.interrupt.pending)
 979                 return -1;
 980         return vcpu->arch.interrupt.nr;
 981 }
 982
 983 static void load_host_msrs(struct kvm_vcpu *vcpu)
 984 {
 985 #ifdef CONFIG_X86_64
 986         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 987 #endif
 988 }
 989
 990 static void save_host_msrs(struct kvm_vcpu *vcpu)
 991 {
 992 #ifdef CONFIG_X86_64
 993         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 994 #endif
 995 }
 996
 997 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 998 {
 999         if (svm_data->next_asid > svm_data->max_asid) {
1000                 ++svm_data->asid_generation;
1001                 svm_data->next_asid = 1;
1002                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1003         }
1004
1005         svm->vcpu.cpu = svm_data->cpu;
1006         svm->asid_generation = svm_data->asid_generation;
1007         svm->vmcb->control.asid = svm_data->next_asid++;
1008 }
1009
1010 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1011 {
1012         struct vcpu_svm *svm = to_svm(vcpu);
1013         unsigned long val;
1014
1015         switch (dr) {
1016         case 0 ... 3:
1017                 val = vcpu->arch.db[dr];
1018                 break;
1019         case 6:
1020                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1021                         val = vcpu->arch.dr6;
1022                 else
1023                         val = svm->vmcb->save.dr6;
1024                 break;
1025         case 7:
1026                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027                         val = vcpu->arch.dr7;
1028                 else
1029                         val = svm->vmcb->save.dr7;
1030                 break;
1031         default:
1032                 val = 0;
1033         }
1034
1035         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1036         return val;
1037 }
1038
1039 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1040                        int *exception)
1041 {
1042         struct vcpu_svm *svm = to_svm(vcpu);
1043
1044         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1045
1046         *exception = 0;
1047
1048         switch (dr) {
1049         case 0 ... 3:
1050                 vcpu->arch.db[dr] = value;
1051                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1052                         vcpu->arch.eff_db[dr] = value;
1053                 return;
1054         case 4 ... 5:
1055                 if (vcpu->arch.cr4 & X86_CR4_DE)
1056                         *exception = UD_VECTOR;
1057                 return;
1058         case 6:
1059                 if (value & 0xffffffff00000000ULL) {
1060                         *exception = GP_VECTOR;
1061                         return;
1062                 }
1063                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1064                 return;
1065         case 7:
1066                 if (value & 0xffffffff00000000ULL) {
1067                         *exception = GP_VECTOR;
1068                         return;
1069                 }
1070                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1071                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1072                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1073                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1074                 }
1075                 return;
1076         default:
1077                 /* FIXME: Possible case? */
1078                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1079                        __func__, dr);
1080                 *exception = UD_VECTOR;
1081                 return;
1082         }
1083 }
1084
1085 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1086 {
1087         u64 fault_address;
1088         u32 error_code;
1089
1090         fault_address  = svm->vmcb->control.exit_info_2;
1091         error_code = svm->vmcb->control.exit_info_1;
1092
1093         if (!npt_enabled)
1094                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1095                             (u32)fault_address, (u32)(fault_address >> 32),
1096                             handler);
1097         else
1098                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1099                             (u32)fault_address, (u32)(fault_address >> 32),
1100                             handler);
1101         /*
1102          * FIXME: Tis shouldn't be necessary here, but there is a flush
1103          * missing in the MMU code. Until we find this bug, flush the
1104          * complete TLB here on an NPF
1105          */
1106         if (npt_enabled)
1107                 svm_flush_tlb(&svm->vcpu);
1108         else {
1109                 if (svm->vcpu.arch.interrupt.pending ||
1110                                 svm->vcpu.arch.exception.pending)
1111                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1112         }
1113         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1114 }
1115
1116 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1117 {
1118         if (!(svm->vcpu.guest_debug &
1119               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1120                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1121                 return 1;
1122         }
1123         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1124         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1125         kvm_run->debug.arch.exception = DB_VECTOR;
1126         return 0;
1127 }
1128
1129 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1130 {
1131         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1132         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1133         kvm_run->debug.arch.exception = BP_VECTOR;
1134         return 0;
1135 }
1136
1137 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1138 {
1139         int er;
1140
1141         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1142         if (er != EMULATE_DONE)
1143                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1144         return 1;
1145 }
1146
1147 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1148 {
1149         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1150         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1151                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1152         svm->vcpu.fpu_active = 1;
1153
1154         return 1;
1155 }
1156
1157 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1158 {
1159         /*
1160          * On an #MC intercept the MCE handler is not called automatically in
1161          * the host. So do it by hand here.
1162          */
1163         asm volatile (
1164                 "int $0x12\n");
1165         /* not sure if we ever come back to this point */
1166
1167         return 1;
1168 }
1169
1170 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1171 {
1172         /*
1173          * VMCB is undefined after a SHUTDOWN intercept
1174          * so reinitialize it.
1175          */
1176         clear_page(svm->vmcb);
1177         init_vmcb(svm);
1178
1179         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1180         return 0;
1181 }
1182
1183 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1184 {
1185         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1186         int size, in, string;
1187         unsigned port;
1188
1189         ++svm->vcpu.stat.io_exits;
1190
1191         svm->next_rip = svm->vmcb->control.exit_info_2;
1192
1193         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1194
1195         if (string) {
1196                 if (emulate_instruction(&svm->vcpu,
1197                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1198                         return 0;
1199                 return 1;
1200         }
1201
1202         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1203         port = io_info >> 16;
1204         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1205
1206         skip_emulated_instruction(&svm->vcpu);
1207         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1208 }
1209
1210 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1211 {
1212         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1213         return 1;
1214 }
1215
1216 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1217 {
1218         ++svm->vcpu.stat.irq_exits;
1219         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1220         return 1;
1221 }
1222
1223 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1224 {
1225         return 1;
1226 }
1227
1228 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1229 {
1230         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1231         skip_emulated_instruction(&svm->vcpu);
1232         return kvm_emulate_halt(&svm->vcpu);
1233 }
1234
1235 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1236 {
1237         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1238         skip_emulated_instruction(&svm->vcpu);
1239         kvm_emulate_hypercall(&svm->vcpu);
1240         return 1;
1241 }
1242
1243 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1244 {
1245         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1246             || !is_paging(&svm->vcpu)) {
1247                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1248                 return 1;
1249         }
1250
1251         if (svm->vmcb->save.cpl) {
1252                 kvm_inject_gp(&svm->vcpu, 0);
1253                 return 1;
1254         }
1255
1256        return 0;
1257 }
1258
1259 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1260                                       bool has_error_code, u32 error_code)
1261 {
1262         if (is_nested(svm)) {
1263                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1264                 svm->vmcb->control.exit_code_hi = 0;
1265                 svm->vmcb->control.exit_info_1 = error_code;
1266                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1267                 if (nested_svm_exit_handled(svm, false)) {
1268                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1269
1270                         nested_svm_vmexit(svm);
1271                         return 1;
1272                 }
1273         }
1274
1275         return 0;
1276 }
1277
1278 static inline int nested_svm_intr(struct vcpu_svm *svm)
1279 {
1280         if (is_nested(svm)) {
1281                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1282                         return 0;
1283
1284                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1285                         return 0;
1286
1287                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1288
1289                 if (nested_svm_exit_handled(svm, false)) {
1290                         nsvm_printk("VMexit -> INTR\n");
1291                         nested_svm_vmexit(svm);
1292                         return 1;
1293                 }
1294         }
1295
1296         return 0;
1297 }
1298
1299 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1300 {
1301         struct page *page;
1302
1303         down_read(&current->mm->mmap_sem);
1304         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1305         up_read(&current->mm->mmap_sem);
1306
1307         if (is_error_page(page)) {
1308                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1309                        __func__, gpa);
1310                 kvm_release_page_clean(page);
1311                 kvm_inject_gp(&svm->vcpu, 0);
1312                 return NULL;
1313         }
1314         return page;
1315 }
1316
1317 static int nested_svm_do(struct vcpu_svm *svm,
1318                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1319                          int (*handler)(struct vcpu_svm *svm,
1320                                         void *arg1,
1321                                         void *arg2,
1322                                         void *opaque))
1323 {
1324         struct page *arg1_page;
1325         struct page *arg2_page = NULL;
1326         void *arg1;
1327         void *arg2 = NULL;
1328         int retval;
1329
1330         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1331         if(arg1_page == NULL)
1332                 return 1;
1333
1334         if (arg2_gpa) {
1335                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1336                 if(arg2_page == NULL) {
1337                         kvm_release_page_clean(arg1_page);
1338                         return 1;
1339                 }
1340         }
1341
1342         arg1 = kmap_atomic(arg1_page, KM_USER0);
1343         if (arg2_gpa)
1344                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1345
1346         retval = handler(svm, arg1, arg2, opaque);
1347
1348         kunmap_atomic(arg1, KM_USER0);
1349         if (arg2_gpa)
1350                 kunmap_atomic(arg2, KM_USER1);
1351
1352         kvm_release_page_dirty(arg1_page);
1353         if (arg2_gpa)
1354                 kvm_release_page_dirty(arg2_page);
1355
1356         return retval;
1357 }
1358
1359 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1360                                         void *arg1,
1361                                         void *arg2,
1362                                         void *opaque)
1363 {
1364         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1365         bool kvm_overrides = *(bool *)opaque;
1366         u32 exit_code = svm->vmcb->control.exit_code;
1367
1368         if (kvm_overrides) {
1369                 switch (exit_code) {
1370                 case SVM_EXIT_INTR:
1371                 case SVM_EXIT_NMI:
1372                         return 0;
1373                 /* For now we are always handling NPFs when using them */
1374                 case SVM_EXIT_NPF:
1375                         if (npt_enabled)
1376                                 return 0;
1377                         break;
1378                 /* When we're shadowing, trap PFs */
1379                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1380                         if (!npt_enabled)
1381                                 return 0;
1382                         break;
1383                 default:
1384                         break;
1385                 }
1386         }
1387
1388         switch (exit_code) {
1389         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1390                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1391                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1392                         return 1;
1393                 break;
1394         }
1395         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1396                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1397                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1398                         return 1;
1399                 break;
1400         }
1401         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1402                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1403                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1404                         return 1;
1405                 break;
1406         }
1407         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1408                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1409                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1410                         return 1;
1411                 break;
1412         }
1413         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1414                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1415                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1416                         return 1;
1417                 break;
1418         }
1419         default: {
1420                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1421                 nsvm_printk("exit code: 0x%x\n", exit_code);
1422                 if (nested_vmcb->control.intercept & exit_bits)
1423                         return 1;
1424         }
1425         }
1426
1427         return 0;
1428 }
1429
1430 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1431                                        void *arg1, void *arg2,
1432                                        void *opaque)
1433 {
1434         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1435         u8 *msrpm = (u8 *)arg2;
1436         u32 t0, t1;
1437         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1438         u32 param = svm->vmcb->control.exit_info_1 & 1;
1439
1440         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1441                 return 0;
1442
1443         switch(msr) {
1444         case 0 ... 0x1fff:
1445                 t0 = (msr * 2) % 8;
1446                 t1 = msr / 8;
1447                 break;
1448         case 0xc0000000 ... 0xc0001fff:
1449                 t0 = (8192 + msr - 0xc0000000) * 2;
1450                 t1 = (t0 / 8);
1451                 t0 %= 8;
1452                 break;
1453         case 0xc0010000 ... 0xc0011fff:
1454                 t0 = (16384 + msr - 0xc0010000) * 2;
1455                 t1 = (t0 / 8);
1456                 t0 %= 8;
1457                 break;
1458         default:
1459                 return 1;
1460                 break;
1461         }
1462         if (msrpm[t1] & ((1 << param) << t0))
1463                 return 1;
1464
1465         return 0;
1466 }
1467
1468 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1469 {
1470         bool k = kvm_override;
1471
1472         switch (svm->vmcb->control.exit_code) {
1473         case SVM_EXIT_MSR:
1474                 return nested_svm_do(svm, svm->nested_vmcb,
1475                                      svm->nested_vmcb_msrpm, NULL,
1476                                      nested_svm_exit_handled_msr);
1477         default: break;
1478         }
1479
1480         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1481                              nested_svm_exit_handled_real);
1482 }
1483
1484 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1485                                   void *arg2, void *opaque)
1486 {
1487         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1488         struct vmcb *hsave = svm->hsave;
1489         u64 nested_save[] = { nested_vmcb->save.cr0,
1490                               nested_vmcb->save.cr3,
1491                               nested_vmcb->save.cr4,
1492                               nested_vmcb->save.efer,
1493                               nested_vmcb->control.intercept_cr_read,
1494                               nested_vmcb->control.intercept_cr_write,
1495                               nested_vmcb->control.intercept_dr_read,
1496                               nested_vmcb->control.intercept_dr_write,
1497                               nested_vmcb->control.intercept_exceptions,
1498                               nested_vmcb->control.intercept,
1499                               nested_vmcb->control.msrpm_base_pa,
1500                               nested_vmcb->control.iopm_base_pa,
1501                               nested_vmcb->control.tsc_offset };
1502
1503         /* Give the current vmcb to the guest */
1504         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1505         nested_vmcb->save.cr0 = nested_save[0];
1506         if (!npt_enabled)
1507                 nested_vmcb->save.cr3 = nested_save[1];
1508         nested_vmcb->save.cr4 = nested_save[2];
1509         nested_vmcb->save.efer = nested_save[3];
1510         nested_vmcb->control.intercept_cr_read = nested_save[4];
1511         nested_vmcb->control.intercept_cr_write = nested_save[5];
1512         nested_vmcb->control.intercept_dr_read = nested_save[6];
1513         nested_vmcb->control.intercept_dr_write = nested_save[7];
1514         nested_vmcb->control.intercept_exceptions = nested_save[8];
1515         nested_vmcb->control.intercept = nested_save[9];
1516         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1517         nested_vmcb->control.iopm_base_pa = nested_save[11];
1518         nested_vmcb->control.tsc_offset = nested_save[12];
1519
1520         /* We always set V_INTR_MASKING and remember the old value in hflags */
1521         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1522                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1523
1524         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1525             (nested_vmcb->control.int_vector)) {
1526                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1527                                 nested_vmcb->control.int_vector);
1528         }
1529
1530         /* Restore the original control entries */
1531         svm->vmcb->control = hsave->control;
1532
1533         /* Kill any pending exceptions */
1534         if (svm->vcpu.arch.exception.pending == true)
1535                 nsvm_printk("WARNING: Pending Exception\n");
1536         svm->vcpu.arch.exception.pending = false;
1537
1538         /* Restore selected save entries */
1539         svm->vmcb->save.es = hsave->save.es;
1540         svm->vmcb->save.cs = hsave->save.cs;
1541         svm->vmcb->save.ss = hsave->save.ss;
1542         svm->vmcb->save.ds = hsave->save.ds;
1543         svm->vmcb->save.gdtr = hsave->save.gdtr;
1544         svm->vmcb->save.idtr = hsave->save.idtr;
1545         svm->vmcb->save.rflags = hsave->save.rflags;
1546         svm_set_efer(&svm->vcpu, hsave->save.efer);
1547         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1548         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1549         if (npt_enabled) {
1550                 svm->vmcb->save.cr3 = hsave->save.cr3;
1551                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1552         } else {
1553                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1554         }
1555         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1556         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1557         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1558         svm->vmcb->save.dr7 = 0;
1559         svm->vmcb->save.cpl = 0;
1560         svm->vmcb->control.exit_int_info = 0;
1561
1562         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1563         /* Exit nested SVM mode */
1564         svm->nested_vmcb = 0;
1565
1566         return 0;
1567 }
1568
1569 static int nested_svm_vmexit(struct vcpu_svm *svm)
1570 {
1571         nsvm_printk("VMexit\n");
1572         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1573                           NULL, nested_svm_vmexit_real))
1574                 return 1;
1575
1576         kvm_mmu_reset_context(&svm->vcpu);
1577         kvm_mmu_load(&svm->vcpu);
1578
1579         return 0;
1580 }
1581
1582 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1583                                   void *arg2, void *opaque)
1584 {
1585         int i;
1586         u32 *nested_msrpm = (u32*)arg1;
1587         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1588                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1589         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1590
1591         return 0;
1592 }
1593
1594 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1595                             void *arg2, void *opaque)
1596 {
1597         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1598         struct vmcb *hsave = svm->hsave;
1599
1600         /* nested_vmcb is our indicator if nested SVM is activated */
1601         svm->nested_vmcb = svm->vmcb->save.rax;
1602
1603         /* Clear internal status */
1604         svm->vcpu.arch.exception.pending = false;
1605
1606         /* Save the old vmcb, so we don't need to pick what we save, but
1607            can restore everything when a VMEXIT occurs */
1608         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1609         /* We need to remember the original CR3 in the SPT case */
1610         if (!npt_enabled)
1611                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1612         hsave->save.cr4 = svm->vcpu.arch.cr4;
1613         hsave->save.rip = svm->next_rip;
1614
1615         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1616                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1617         else
1618                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1619
1620         /* Load the nested guest state */
1621         svm->vmcb->save.es = nested_vmcb->save.es;
1622         svm->vmcb->save.cs = nested_vmcb->save.cs;
1623         svm->vmcb->save.ss = nested_vmcb->save.ss;
1624         svm->vmcb->save.ds = nested_vmcb->save.ds;
1625         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1626         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1627         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1628         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1629         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1630         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1631         if (npt_enabled) {
1632                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1633                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1634         } else {
1635                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1636                 kvm_mmu_reset_context(&svm->vcpu);
1637         }
1638         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1639         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1640         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1641         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1642         /* In case we don't even reach vcpu_run, the fields are not updated */
1643         svm->vmcb->save.rax = nested_vmcb->save.rax;
1644         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1645         svm->vmcb->save.rip = nested_vmcb->save.rip;
1646         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1647         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1648         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1649
1650         /* We don't want a nested guest to be more powerful than the guest,
1651            so all intercepts are ORed */
1652         svm->vmcb->control.intercept_cr_read |=
1653                 nested_vmcb->control.intercept_cr_read;
1654         svm->vmcb->control.intercept_cr_write |=
1655                 nested_vmcb->control.intercept_cr_write;
1656         svm->vmcb->control.intercept_dr_read |=
1657                 nested_vmcb->control.intercept_dr_read;
1658         svm->vmcb->control.intercept_dr_write |=
1659                 nested_vmcb->control.intercept_dr_write;
1660         svm->vmcb->control.intercept_exceptions |=
1661                 nested_vmcb->control.intercept_exceptions;
1662
1663         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1664
1665         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1666
1667         force_new_asid(&svm->vcpu);
1668         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1669         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1670         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1671         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1672                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1673                                 nested_vmcb->control.int_ctl);
1674         }
1675         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1676                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1677         else
1678                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1679
1680         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1681                         nested_vmcb->control.exit_int_info,
1682                         nested_vmcb->control.int_state);
1683
1684         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1685         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1686         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1687         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1688                 nsvm_printk("Injecting Event: 0x%x\n",
1689                                 nested_vmcb->control.event_inj);
1690         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1691         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1692
1693         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1694
1695         return 0;
1696 }
1697
1698 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1699 {
1700         to_vmcb->save.fs = from_vmcb->save.fs;
1701         to_vmcb->save.gs = from_vmcb->save.gs;
1702         to_vmcb->save.tr = from_vmcb->save.tr;
1703         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1704         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1705         to_vmcb->save.star = from_vmcb->save.star;
1706         to_vmcb->save.lstar = from_vmcb->save.lstar;
1707         to_vmcb->save.cstar = from_vmcb->save.cstar;
1708         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1709         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1710         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1711         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1712
1713         return 1;
1714 }
1715
1716 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1717                              void *arg2, void *opaque)
1718 {
1719         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1720 }
1721
1722 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1723                              void *arg2, void *opaque)
1724 {
1725         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1726 }
1727
1728 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1729 {
1730         if (nested_svm_check_permissions(svm))
1731                 return 1;
1732
1733         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1734         skip_emulated_instruction(&svm->vcpu);
1735
1736         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1737
1738         return 1;
1739 }
1740
1741 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1742 {
1743         if (nested_svm_check_permissions(svm))
1744                 return 1;
1745
1746         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1747         skip_emulated_instruction(&svm->vcpu);
1748
1749         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1750
1751         return 1;
1752 }
1753
1754 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1755 {
1756         nsvm_printk("VMrun\n");
1757         if (nested_svm_check_permissions(svm))
1758                 return 1;
1759
1760         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1761         skip_emulated_instruction(&svm->vcpu);
1762
1763         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1764                           NULL, nested_svm_vmrun))
1765                 return 1;
1766
1767         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1768                       NULL, nested_svm_vmrun_msrpm))
1769                 return 1;
1770
1771         return 1;
1772 }
1773
1774 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1775 {
1776         if (nested_svm_check_permissions(svm))
1777                 return 1;
1778
1779         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1780         skip_emulated_instruction(&svm->vcpu);
1781
1782         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1783
1784         return 1;
1785 }
1786
1787 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1788 {
1789         if (nested_svm_check_permissions(svm))
1790                 return 1;
1791
1792         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1793         skip_emulated_instruction(&svm->vcpu);
1794
1795         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1796
1797         /* After a CLGI no interrupts should come */
1798         svm_clear_vintr(svm);
1799         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1800
1801         return 1;
1802 }
1803
1804 static int invalid_op_interception(struct vcpu_svm *svm,
1805                                    struct kvm_run *kvm_run)
1806 {
1807         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1808         return 1;
1809 }
1810
1811 static int task_switch_interception(struct vcpu_svm *svm,
1812                                     struct kvm_run *kvm_run)
1813 {
1814         u16 tss_selector;
1815         int reason;
1816         int int_type = svm->vmcb->control.exit_int_info &
1817                 SVM_EXITINTINFO_TYPE_MASK;
1818         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1819
1820         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1821
1822         if (svm->vmcb->control.exit_info_2 &
1823             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1824                 reason = TASK_SWITCH_IRET;
1825         else if (svm->vmcb->control.exit_info_2 &
1826                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1827                 reason = TASK_SWITCH_JMP;
1828         else if (svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID)
1829                 reason = TASK_SWITCH_GATE;
1830         else
1831                 reason = TASK_SWITCH_CALL;
1832
1833
1834         if (reason != TASK_SWITCH_GATE ||
1835             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1836             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1837              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
1838                 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0,
1839                                         EMULTYPE_SKIP) != EMULATE_DONE)
1840                         return 0;
1841         }
1842
1843         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1844 }
1845
1846 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1847 {
1848         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1849         kvm_emulate_cpuid(&svm->vcpu);
1850         return 1;
1851 }
1852
1853 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1854 {
1855         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1856                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1857         return 1;
1858 }
1859
1860 static int emulate_on_interception(struct vcpu_svm *svm,
1861                                    struct kvm_run *kvm_run)
1862 {
1863         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1864                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1865         return 1;
1866 }
1867
1868 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1869 {
1870         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1871         if (irqchip_in_kernel(svm->vcpu.kvm))
1872                 return 1;
1873         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1874         return 0;
1875 }
1876
1877 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1878 {
1879         struct vcpu_svm *svm = to_svm(vcpu);
1880
1881         switch (ecx) {
1882         case MSR_IA32_TIME_STAMP_COUNTER: {
1883                 u64 tsc;
1884
1885                 rdtscll(tsc);
1886                 *data = svm->vmcb->control.tsc_offset + tsc;
1887                 break;
1888         }
1889         case MSR_K6_STAR:
1890                 *data = svm->vmcb->save.star;
1891                 break;
1892 #ifdef CONFIG_X86_64
1893         case MSR_LSTAR:
1894                 *data = svm->vmcb->save.lstar;
1895                 break;
1896         case MSR_CSTAR:
1897                 *data = svm->vmcb->save.cstar;
1898                 break;
1899         case MSR_KERNEL_GS_BASE:
1900                 *data = svm->vmcb->save.kernel_gs_base;
1901                 break;
1902         case MSR_SYSCALL_MASK:
1903                 *data = svm->vmcb->save.sfmask;
1904                 break;
1905 #endif
1906         case MSR_IA32_SYSENTER_CS:
1907                 *data = svm->vmcb->save.sysenter_cs;
1908                 break;
1909         case MSR_IA32_SYSENTER_EIP:
1910                 *data = svm->vmcb->save.sysenter_eip;
1911                 break;
1912         case MSR_IA32_SYSENTER_ESP:
1913                 *data = svm->vmcb->save.sysenter_esp;
1914                 break;
1915         /* Nobody will change the following 5 values in the VMCB so
1916            we can safely return them on rdmsr. They will always be 0
1917            until LBRV is implemented. */
1918         case MSR_IA32_DEBUGCTLMSR:
1919                 *data = svm->vmcb->save.dbgctl;
1920                 break;
1921         case MSR_IA32_LASTBRANCHFROMIP:
1922                 *data = svm->vmcb->save.br_from;
1923                 break;
1924         case MSR_IA32_LASTBRANCHTOIP:
1925                 *data = svm->vmcb->save.br_to;
1926                 break;
1927         case MSR_IA32_LASTINTFROMIP:
1928                 *data = svm->vmcb->save.last_excp_from;
1929                 break;
1930         case MSR_IA32_LASTINTTOIP:
1931                 *data = svm->vmcb->save.last_excp_to;
1932                 break;
1933         case MSR_VM_HSAVE_PA:
1934                 *data = svm->hsave_msr;
1935                 break;
1936         case MSR_VM_CR:
1937                 *data = 0;
1938                 break;
1939         case MSR_IA32_UCODE_REV:
1940                 *data = 0x01000065;
1941                 break;
1942         default:
1943                 return kvm_get_msr_common(vcpu, ecx, data);
1944         }
1945         return 0;
1946 }
1947
1948 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1949 {
1950         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1951         u64 data;
1952
1953         if (svm_get_msr(&svm->vcpu, ecx, &data))
1954                 kvm_inject_gp(&svm->vcpu, 0);
1955         else {
1956                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1957                             (u32)(data >> 32), handler);
1958
1959                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1960                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1961                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1962                 skip_emulated_instruction(&svm->vcpu);
1963         }
1964         return 1;
1965 }
1966
1967 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1968 {
1969         struct vcpu_svm *svm = to_svm(vcpu);
1970
1971         switch (ecx) {
1972         case MSR_IA32_TIME_STAMP_COUNTER: {
1973                 u64 tsc;
1974
1975                 rdtscll(tsc);
1976                 svm->vmcb->control.tsc_offset = data - tsc;
1977                 break;
1978         }
1979         case MSR_K6_STAR:
1980                 svm->vmcb->save.star = data;
1981                 break;
1982 #ifdef CONFIG_X86_64
1983         case MSR_LSTAR:
1984                 svm->vmcb->save.lstar = data;
1985                 break;
1986         case MSR_CSTAR:
1987                 svm->vmcb->save.cstar = data;
1988                 break;
1989         case MSR_KERNEL_GS_BASE:
1990                 svm->vmcb->save.kernel_gs_base = data;
1991                 break;
1992         case MSR_SYSCALL_MASK:
1993                 svm->vmcb->save.sfmask = data;
1994                 break;
1995 #endif
1996         case MSR_IA32_SYSENTER_CS:
1997                 svm->vmcb->save.sysenter_cs = data;
1998                 break;
1999         case MSR_IA32_SYSENTER_EIP:
2000                 svm->vmcb->save.sysenter_eip = data;
2001                 break;
2002         case MSR_IA32_SYSENTER_ESP:
2003                 svm->vmcb->save.sysenter_esp = data;
2004                 break;
2005         case MSR_IA32_DEBUGCTLMSR:
2006                 if (!svm_has(SVM_FEATURE_LBRV)) {
2007                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2008                                         __func__, data);
2009                         break;
2010                 }
2011                 if (data & DEBUGCTL_RESERVED_BITS)
2012                         return 1;
2013
2014                 svm->vmcb->save.dbgctl = data;
2015                 if (data & (1ULL<<0))
2016                         svm_enable_lbrv(svm);
2017                 else
2018                         svm_disable_lbrv(svm);
2019                 break;
2020         case MSR_K7_EVNTSEL0:
2021         case MSR_K7_EVNTSEL1:
2022         case MSR_K7_EVNTSEL2:
2023         case MSR_K7_EVNTSEL3:
2024         case MSR_K7_PERFCTR0:
2025         case MSR_K7_PERFCTR1:
2026         case MSR_K7_PERFCTR2:
2027         case MSR_K7_PERFCTR3:
2028                 /*
2029                  * Just discard all writes to the performance counters; this
2030                  * should keep both older linux and windows 64-bit guests
2031                  * happy
2032                  */
2033                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2034
2035                 break;
2036         case MSR_VM_HSAVE_PA:
2037                 svm->hsave_msr = data;
2038                 break;
2039         default:
2040                 return kvm_set_msr_common(vcpu, ecx, data);
2041         }
2042         return 0;
2043 }
2044
2045 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2046 {
2047         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2048         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2049                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2050
2051         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2052                     handler);
2053
2054         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2055         if (svm_set_msr(&svm->vcpu, ecx, data))
2056                 kvm_inject_gp(&svm->vcpu, 0);
2057         else
2058                 skip_emulated_instruction(&svm->vcpu);
2059         return 1;
2060 }
2061
2062 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2063 {
2064         if (svm->vmcb->control.exit_info_1)
2065                 return wrmsr_interception(svm, kvm_run);
2066         else
2067                 return rdmsr_interception(svm, kvm_run);
2068 }
2069
2070 static int interrupt_window_interception(struct vcpu_svm *svm,
2071                                    struct kvm_run *kvm_run)
2072 {
2073         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2074
2075         svm_clear_vintr(svm);
2076         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2077         /*
2078          * If the user space waits to inject interrupts, exit as soon as
2079          * possible
2080          */
2081         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2082             kvm_run->request_interrupt_window &&
2083             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2084                 ++svm->vcpu.stat.irq_window_exits;
2085                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2086                 return 0;
2087         }
2088
2089         return 1;
2090 }
2091
2092 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2093                                       struct kvm_run *kvm_run) = {
2094         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2095         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2096         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2097         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2098         /* for now: */
2099         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2100         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2101         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2102         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2103         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2104         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2105         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2106         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2107         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2108         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2109         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2110         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2111         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2112         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2113         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2114         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2115         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2116         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2117         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2118         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2119         [SVM_EXIT_INTR]                         = intr_interception,
2120         [SVM_EXIT_NMI]                          = nmi_interception,
2121         [SVM_EXIT_SMI]                          = nop_on_interception,
2122         [SVM_EXIT_INIT]                         = nop_on_interception,
2123         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2124         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2125         [SVM_EXIT_CPUID]                        = cpuid_interception,
2126         [SVM_EXIT_INVD]                         = emulate_on_interception,
2127         [SVM_EXIT_HLT]                          = halt_interception,
2128         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2129         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2130         [SVM_EXIT_IOIO]                         = io_interception,
2131         [SVM_EXIT_MSR]                          = msr_interception,
2132         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2133         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2134         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2135         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2136         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2137         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2138         [SVM_EXIT_STGI]                         = stgi_interception,
2139         [SVM_EXIT_CLGI]                         = clgi_interception,
2140         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2141         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2142         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2143         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2144         [SVM_EXIT_NPF]                          = pf_interception,
2145 };
2146
2147 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2148 {
2149         struct vcpu_svm *svm = to_svm(vcpu);
2150         u32 exit_code = svm->vmcb->control.exit_code;
2151
2152         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2153                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2154
2155         if (is_nested(svm)) {
2156                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2157                             exit_code, svm->vmcb->control.exit_info_1,
2158                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2159                 if (nested_svm_exit_handled(svm, true)) {
2160                         nested_svm_vmexit(svm);
2161                         nsvm_printk("-> #VMEXIT\n");
2162                         return 1;
2163                 }
2164         }
2165
2166         if (npt_enabled) {
2167                 int mmu_reload = 0;
2168                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2169                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2170                         mmu_reload = 1;
2171                 }
2172                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2173                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2174                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2175                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2176                                 kvm_inject_gp(vcpu, 0);
2177                                 return 1;
2178                         }
2179                 }
2180                 if (mmu_reload) {
2181                         kvm_mmu_reset_context(vcpu);
2182                         kvm_mmu_load(vcpu);
2183                 }
2184         }
2185
2186
2187         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2188                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2189                 kvm_run->fail_entry.hardware_entry_failure_reason
2190                         = svm->vmcb->control.exit_code;
2191                 return 0;
2192         }
2193
2194         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2195             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2196             exit_code != SVM_EXIT_NPF)
2197                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2198                        "exit_code 0x%x\n",
2199                        __func__, svm->vmcb->control.exit_int_info,
2200                        exit_code);
2201
2202         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2203             || !svm_exit_handlers[exit_code]) {
2204                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2205                 kvm_run->hw.hardware_exit_reason = exit_code;
2206                 return 0;
2207         }
2208
2209         return svm_exit_handlers[exit_code](svm, kvm_run);
2210 }
2211
2212 static void reload_tss(struct kvm_vcpu *vcpu)
2213 {
2214         int cpu = raw_smp_processor_id();
2215
2216         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2217         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2218         load_TR_desc();
2219 }
2220
2221 static void pre_svm_run(struct vcpu_svm *svm)
2222 {
2223         int cpu = raw_smp_processor_id();
2224
2225         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2226
2227         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2228         if (svm->vcpu.cpu != cpu ||
2229             svm->asid_generation != svm_data->asid_generation)
2230                 new_asid(svm, svm_data);
2231 }
2232
2233
2234 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2235 {
2236         struct vmcb_control_area *control;
2237
2238         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2239
2240         ++svm->vcpu.stat.irq_injections;
2241         control = &svm->vmcb->control;
2242         control->int_vector = irq;
2243         control->int_ctl &= ~V_INTR_PRIO_MASK;
2244         control->int_ctl |= V_IRQ_MASK |
2245                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2246 }
2247
2248 static void svm_queue_irq(struct vcpu_svm *svm, unsigned nr)
2249 {
2250         svm->vmcb->control.event_inj = nr |
2251                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2252 }
2253
2254 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2255 {
2256         struct vcpu_svm *svm = to_svm(vcpu);
2257
2258         nested_svm_intr(svm);
2259
2260         svm_queue_irq(svm, irq);
2261 }
2262
2263 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2264 {
2265         struct vcpu_svm *svm = to_svm(vcpu);
2266         struct vmcb *vmcb = svm->vmcb;
2267         int max_irr, tpr;
2268
2269         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2270                 return;
2271
2272         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2273
2274         max_irr = kvm_lapic_find_highest_irr(vcpu);
2275         if (max_irr == -1)
2276                 return;
2277
2278         tpr = kvm_lapic_get_cr8(vcpu) << 4;
2279
2280         if (tpr >= (max_irr & 0xf0))
2281                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2282 }
2283
2284 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2285 {
2286         struct vcpu_svm *svm = to_svm(vcpu);
2287         struct vmcb *vmcb = svm->vmcb;
2288         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2289                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2290                 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2291 }
2292
2293 static void enable_irq_window(struct kvm_vcpu *vcpu)
2294 {
2295         svm_set_vintr(to_svm(vcpu));
2296         svm_inject_irq(to_svm(vcpu), 0x0);
2297 }
2298
2299 static void svm_intr_inject(struct kvm_vcpu *vcpu)
2300 {
2301         /* try to reinject previous events if any */
2302         if (vcpu->arch.interrupt.pending) {
2303                 svm_queue_irq(to_svm(vcpu), vcpu->arch.interrupt.nr);
2304                 return;
2305         }
2306
2307         /* try to inject new event if pending */
2308         if (kvm_cpu_has_interrupt(vcpu)) {
2309                 if (vcpu->arch.interrupt_window_open) {
2310                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
2311                         svm_queue_irq(to_svm(vcpu), vcpu->arch.interrupt.nr);
2312                 }
2313         }
2314 }
2315
2316 static void svm_intr_assist(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2317 {
2318         struct vcpu_svm *svm = to_svm(vcpu);
2319         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
2320                 kvm_run->request_interrupt_window;
2321
2322         if (nested_svm_intr(svm))
2323                 goto out;
2324
2325         svm->vcpu.arch.interrupt_window_open = svm_interrupt_allowed(vcpu);
2326
2327         svm_intr_inject(vcpu);
2328
2329         if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
2330                 enable_irq_window(vcpu);
2331
2332 out:
2333         update_cr8_intercept(vcpu);
2334 }
2335
2336 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2337 {
2338         return 0;
2339 }
2340
2341 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2342 {
2343         force_new_asid(vcpu);
2344 }
2345
2346 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2347 {
2348 }
2349
2350 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2351 {
2352         struct vcpu_svm *svm = to_svm(vcpu);
2353
2354         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2355                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2356                 kvm_lapic_set_tpr(vcpu, cr8);
2357         }
2358 }
2359
2360 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2361 {
2362         struct vcpu_svm *svm = to_svm(vcpu);
2363         u64 cr8;
2364
2365         if (!irqchip_in_kernel(vcpu->kvm))
2366                 return;
2367
2368         cr8 = kvm_get_cr8(vcpu);
2369         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2370         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2371 }
2372
2373 static void svm_complete_interrupts(struct vcpu_svm *svm)
2374 {
2375         u8 vector;
2376         int type;
2377         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2378
2379         svm->vcpu.arch.nmi_injected = false;
2380         kvm_clear_exception_queue(&svm->vcpu);
2381         kvm_clear_interrupt_queue(&svm->vcpu);
2382
2383         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2384                 return;
2385
2386         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2387         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2388
2389         switch (type) {
2390         case SVM_EXITINTINFO_TYPE_NMI:
2391                 svm->vcpu.arch.nmi_injected = true;
2392                 break;
2393         case SVM_EXITINTINFO_TYPE_EXEPT:
2394                 /* In case of software exception do not reinject an exception
2395                    vector, but re-execute and instruction instead */
2396                 if (vector == BP_VECTOR || vector == OF_VECTOR)
2397                         break;
2398                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2399                         u32 err = svm->vmcb->control.exit_int_info_err;
2400                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2401
2402                 } else
2403                         kvm_queue_exception(&svm->vcpu, vector);
2404                 break;
2405         case SVM_EXITINTINFO_TYPE_INTR:
2406                 kvm_queue_interrupt(&svm->vcpu, vector);
2407                 break;
2408         default:
2409                 break;
2410         }
2411 }
2412
2413 #ifdef CONFIG_X86_64
2414 #define R "r"
2415 #else
2416 #define R "e"
2417 #endif
2418
2419 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2420 {
2421         struct vcpu_svm *svm = to_svm(vcpu);
2422         u16 fs_selector;
2423         u16 gs_selector;
2424         u16 ldt_selector;
2425
2426         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2427         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2428         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2429
2430         pre_svm_run(svm);
2431
2432         sync_lapic_to_cr8(vcpu);
2433
2434         save_host_msrs(vcpu);
2435         fs_selector = kvm_read_fs();
2436         gs_selector = kvm_read_gs();
2437         ldt_selector = kvm_read_ldt();
2438         svm->host_cr2 = kvm_read_cr2();
2439         if (!is_nested(svm))
2440                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2441         /* required for live migration with NPT */
2442         if (npt_enabled)
2443                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2444
2445         clgi();
2446
2447         local_irq_enable();
2448
2449         asm volatile (
2450                 "push %%"R"bp; \n\t"
2451                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2452                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2453                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2454                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2455                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2456                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2457 #ifdef CONFIG_X86_64
2458                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2459                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2460                 "mov %c[r10](%[svm]), %%r10 \n\t"
2461                 "mov %c[r11](%[svm]), %%r11 \n\t"
2462                 "mov %c[r12](%[svm]), %%r12 \n\t"
2463                 "mov %c[r13](%[svm]), %%r13 \n\t"
2464                 "mov %c[r14](%[svm]), %%r14 \n\t"
2465                 "mov %c[r15](%[svm]), %%r15 \n\t"
2466 #endif
2467
2468                 /* Enter guest mode */
2469                 "push %%"R"ax \n\t"
2470                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2471                 __ex(SVM_VMLOAD) "\n\t"
2472                 __ex(SVM_VMRUN) "\n\t"
2473                 __ex(SVM_VMSAVE) "\n\t"
2474                 "pop %%"R"ax \n\t"
2475
2476                 /* Save guest registers, load host registers */
2477                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2478                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2479                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2480                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2481                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2482                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2483 #ifdef CONFIG_X86_64
2484                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2485                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2486                 "mov %%r10, %c[r10](%[svm]) \n\t"
2487                 "mov %%r11, %c[r11](%[svm]) \n\t"
2488                 "mov %%r12, %c[r12](%[svm]) \n\t"
2489                 "mov %%r13, %c[r13](%[svm]) \n\t"
2490                 "mov %%r14, %c[r14](%[svm]) \n\t"
2491                 "mov %%r15, %c[r15](%[svm]) \n\t"
2492 #endif
2493                 "pop %%"R"bp"
2494                 :
2495                 : [svm]"a"(svm),
2496                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2497                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2498                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2499                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2500                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2501                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2502                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2503 #ifdef CONFIG_X86_64
2504                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2505                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2506                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2507                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2508                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2509                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2510                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2511                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2512 #endif
2513                 : "cc", "memory"
2514                 , R"bx", R"cx", R"dx", R"si", R"di"
2515 #ifdef CONFIG_X86_64
2516                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2517 #endif
2518                 );
2519
2520         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2521         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2522         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2523         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2524
2525         kvm_write_cr2(svm->host_cr2);
2526
2527         kvm_load_fs(fs_selector);
2528         kvm_load_gs(gs_selector);
2529         kvm_load_ldt(ldt_selector);
2530         load_host_msrs(vcpu);
2531
2532         reload_tss(vcpu);
2533
2534         local_irq_disable();
2535
2536         stgi();
2537
2538         sync_cr8_to_lapic(vcpu);
2539
2540         svm->next_rip = 0;
2541
2542         svm_complete_interrupts(svm);
2543 }
2544
2545 #undef R
2546
2547 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2548 {
2549         struct vcpu_svm *svm = to_svm(vcpu);
2550
2551         if (npt_enabled) {
2552                 svm->vmcb->control.nested_cr3 = root;
2553                 force_new_asid(vcpu);
2554                 return;
2555         }
2556
2557         svm->vmcb->save.cr3 = root;
2558         force_new_asid(vcpu);
2559
2560         if (vcpu->fpu_active) {
2561                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2562                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2563                 vcpu->fpu_active = 0;
2564         }
2565 }
2566
2567 static int is_disabled(void)
2568 {
2569         u64 vm_cr;
2570
2571         rdmsrl(MSR_VM_CR, vm_cr);
2572         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2573                 return 1;
2574
2575         return 0;
2576 }
2577
2578 static void
2579 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2580 {
2581         /*
2582          * Patch in the VMMCALL instruction:
2583          */
2584         hypercall[0] = 0x0f;
2585         hypercall[1] = 0x01;
2586         hypercall[2] = 0xd9;
2587 }
2588
2589 static void svm_check_processor_compat(void *rtn)
2590 {
2591         *(int *)rtn = 0;
2592 }
2593
2594 static bool svm_cpu_has_accelerated_tpr(void)
2595 {
2596         return false;
2597 }
2598
2599 static int get_npt_level(void)
2600 {
2601 #ifdef CONFIG_X86_64
2602         return PT64_ROOT_LEVEL;
2603 #else
2604         return PT32E_ROOT_LEVEL;
2605 #endif
2606 }
2607
2608 static int svm_get_mt_mask_shift(void)
2609 {
2610         return 0;
2611 }
2612
2613 static struct kvm_x86_ops svm_x86_ops = {
2614         .cpu_has_kvm_support = has_svm,
2615         .disabled_by_bios = is_disabled,
2616         .hardware_setup = svm_hardware_setup,
2617         .hardware_unsetup = svm_hardware_unsetup,
2618         .check_processor_compatibility = svm_check_processor_compat,
2619         .hardware_enable = svm_hardware_enable,
2620         .hardware_disable = svm_hardware_disable,
2621         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2622
2623         .vcpu_create = svm_create_vcpu,
2624         .vcpu_free = svm_free_vcpu,
2625         .vcpu_reset = svm_vcpu_reset,
2626
2627         .prepare_guest_switch = svm_prepare_guest_switch,
2628         .vcpu_load = svm_vcpu_load,
2629         .vcpu_put = svm_vcpu_put,
2630
2631         .set_guest_debug = svm_guest_debug,
2632         .get_msr = svm_get_msr,
2633         .set_msr = svm_set_msr,
2634         .get_segment_base = svm_get_segment_base,
2635         .get_segment = svm_get_segment,
2636         .set_segment = svm_set_segment,
2637         .get_cpl = svm_get_cpl,
2638         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2639         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2640         .set_cr0 = svm_set_cr0,
2641         .set_cr3 = svm_set_cr3,
2642         .set_cr4 = svm_set_cr4,
2643         .set_efer = svm_set_efer,
2644         .get_idt = svm_get_idt,
2645         .set_idt = svm_set_idt,
2646         .get_gdt = svm_get_gdt,
2647         .set_gdt = svm_set_gdt,
2648         .get_dr = svm_get_dr,
2649         .set_dr = svm_set_dr,
2650         .get_rflags = svm_get_rflags,
2651         .set_rflags = svm_set_rflags,
2652
2653         .tlb_flush = svm_flush_tlb,
2654
2655         .run = svm_vcpu_run,
2656         .handle_exit = handle_exit,
2657         .skip_emulated_instruction = skip_emulated_instruction,
2658         .patch_hypercall = svm_patch_hypercall,
2659         .get_irq = svm_get_irq,
2660         .set_irq = svm_set_irq,
2661         .queue_exception = svm_queue_exception,
2662         .exception_injected = svm_exception_injected,
2663         .inject_pending_irq = svm_intr_assist,
2664         .inject_pending_vectors = svm_intr_assist,
2665         .interrupt_allowed = svm_interrupt_allowed,
2666
2667         .set_tss_addr = svm_set_tss_addr,
2668         .get_tdp_level = get_npt_level,
2669         .get_mt_mask_shift = svm_get_mt_mask_shift,
2670 };
2671
2672 static int __init svm_init(void)
2673 {
2674         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2675                               THIS_MODULE);
2676 }
2677
2678 static void __exit svm_exit(void)
2679 {
2680         kvm_exit();
2681 }
2682
2683 module_init(svm_init)
2684 module_exit(svm_exit)