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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49
  50 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  51 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  52 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  53
  54 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  55
  56 /* Turn on to get debugging output*/
  57 /* #define NESTED_DEBUG */
  58
  59 #ifdef NESTED_DEBUG
  60 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  61 #else
  62 #define nsvm_printk(fmt, args...) do {} while(0)
  63 #endif
  64
  65 static const u32 host_save_user_msrs[] = {
  66 #ifdef CONFIG_X86_64
  67         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  68         MSR_FS_BASE,
  69 #endif
  70         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  71 };
  72
  73 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  74
  75 struct kvm_vcpu;
  76
  77 struct nested_state {
  78         struct vmcb *hsave;
  79         u64 hsave_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87
  88         /* cache for intercepts of the guest */
  89         u16 intercept_cr_read;
  90         u16 intercept_cr_write;
  91         u16 intercept_dr_read;
  92         u16 intercept_dr_write;
  93         u32 intercept_exceptions;
  94         u64 intercept;
  95
  96 };
  97
  98 struct vcpu_svm {
  99         struct kvm_vcpu vcpu;
 100         struct vmcb *vmcb;
 101         unsigned long vmcb_pa;
 102         struct svm_cpu_data *svm_data;
 103         uint64_t asid_generation;
 104         uint64_t sysenter_esp;
 105         uint64_t sysenter_eip;
 106
 107         u64 next_rip;
 108
 109         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 110         u64 host_gs_base;
 111
 112         u32 *msrpm;
 113
 114         struct nested_state nested;
 115 };
 116
 117 /* enable NPT for AMD64 and X86 with PAE */
 118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 119 static bool npt_enabled = true;
 120 #else
 121 static bool npt_enabled = false;
 122 #endif
 123 static int npt = 1;
 124
 125 module_param(npt, int, S_IRUGO);
 126
 127 static int nested = 1;
 128 module_param(nested, int, S_IRUGO);
 129
 130 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 131 static void svm_complete_interrupts(struct vcpu_svm *svm);
 132
 133 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 134 static int nested_svm_vmexit(struct vcpu_svm *svm);
 135 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 136                                       bool has_error_code, u32 error_code);
 137
 138 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 139 {
 140         return container_of(vcpu, struct vcpu_svm, vcpu);
 141 }
 142
 143 static inline bool is_nested(struct vcpu_svm *svm)
 144 {
 145         return svm->nested.vmcb;
 146 }
 147
 148 static inline void enable_gif(struct vcpu_svm *svm)
 149 {
 150         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 151 }
 152
 153 static inline void disable_gif(struct vcpu_svm *svm)
 154 {
 155         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 156 }
 157
 158 static inline bool gif_set(struct vcpu_svm *svm)
 159 {
 160         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 161 }
 162
 163 static unsigned long iopm_base;
 164
 165 struct kvm_ldttss_desc {
 166         u16 limit0;
 167         u16 base0;
 168         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 169         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 170         u32 base3;
 171         u32 zero1;
 172 } __attribute__((packed));
 173
 174 struct svm_cpu_data {
 175         int cpu;
 176
 177         u64 asid_generation;
 178         u32 max_asid;
 179         u32 next_asid;
 180         struct kvm_ldttss_desc *tss_desc;
 181
 182         struct page *save_area;
 183 };
 184
 185 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 186 static uint32_t svm_features;
 187
 188 struct svm_init_data {
 189         int cpu;
 190         int r;
 191 };
 192
 193 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 194
 195 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 196 #define MSRS_RANGE_SIZE 2048
 197 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 198
 199 #define MAX_INST_SIZE 15
 200
 201 static inline u32 svm_has(u32 feat)
 202 {
 203         return svm_features & feat;
 204 }
 205
 206 static inline void clgi(void)
 207 {
 208         asm volatile (__ex(SVM_CLGI));
 209 }
 210
 211 static inline void stgi(void)
 212 {
 213         asm volatile (__ex(SVM_STGI));
 214 }
 215
 216 static inline void invlpga(unsigned long addr, u32 asid)
 217 {
 218         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 219 }
 220
 221 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 222 {
 223         to_svm(vcpu)->asid_generation--;
 224 }
 225
 226 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 227 {
 228         force_new_asid(vcpu);
 229 }
 230
 231 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 232 {
 233         if (!npt_enabled && !(efer & EFER_LMA))
 234                 efer &= ~EFER_LME;
 235
 236         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 237         vcpu->arch.shadow_efer = efer;
 238 }
 239
 240 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 241                                 bool has_error_code, u32 error_code)
 242 {
 243         struct vcpu_svm *svm = to_svm(vcpu);
 244
 245         /* If we are within a nested VM we'd better #VMEXIT and let the
 246            guest handle the exception */
 247         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 248                 return;
 249
 250         svm->vmcb->control.event_inj = nr
 251                 | SVM_EVTINJ_VALID
 252                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 253                 | SVM_EVTINJ_TYPE_EXEPT;
 254         svm->vmcb->control.event_inj_err = error_code;
 255 }
 256
 257 static int is_external_interrupt(u32 info)
 258 {
 259         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 260         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 261 }
 262
 263 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 264 {
 265         struct vcpu_svm *svm = to_svm(vcpu);
 266         u32 ret = 0;
 267
 268         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 269                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 270         return ret & mask;
 271 }
 272
 273 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 274 {
 275         struct vcpu_svm *svm = to_svm(vcpu);
 276
 277         if (mask == 0)
 278                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 279         else
 280                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 281
 282 }
 283
 284 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 285 {
 286         struct vcpu_svm *svm = to_svm(vcpu);
 287
 288         if (!svm->next_rip) {
 289                 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
 290                                 EMULATE_DONE)
 291                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 292                 return;
 293         }
 294         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 295                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 296                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 297
 298         kvm_rip_write(vcpu, svm->next_rip);
 299         svm_set_interrupt_shadow(vcpu, 0);
 300 }
 301
 302 static int has_svm(void)
 303 {
 304         const char *msg;
 305
 306         if (!cpu_has_svm(&msg)) {
 307                 printk(KERN_INFO "has_svm: %s\n", msg);
 308                 return 0;
 309         }
 310
 311         return 1;
 312 }
 313
 314 static void svm_hardware_disable(void *garbage)
 315 {
 316         cpu_svm_disable();
 317 }
 318
 319 static void svm_hardware_enable(void *garbage)
 320 {
 321
 322         struct svm_cpu_data *sd;
 323         uint64_t efer;
 324         struct descriptor_table gdt_descr;
 325         struct desc_struct *gdt;
 326         int me = raw_smp_processor_id();
 327
 328         if (!has_svm()) {
 329                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 330                 return;
 331         }
 332         sd = per_cpu(svm_data, me);
 333
 334         if (!sd) {
 335                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 336                        me);
 337                 return;
 338         }
 339
 340         sd->asid_generation = 1;
 341         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 342         sd->next_asid = sd->max_asid + 1;
 343
 344         kvm_get_gdt(&gdt_descr);
 345         gdt = (struct desc_struct *)gdt_descr.base;
 346         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 347
 348         rdmsrl(MSR_EFER, efer);
 349         wrmsrl(MSR_EFER, efer | EFER_SVME);
 350
 351         wrmsrl(MSR_VM_HSAVE_PA,
 352                page_to_pfn(sd->save_area) << PAGE_SHIFT);
 353 }
 354
 355 static void svm_cpu_uninit(int cpu)
 356 {
 357         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 358
 359         if (!sd)
 360                 return;
 361
 362         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 363         __free_page(sd->save_area);
 364         kfree(sd);
 365 }
 366
 367 static int svm_cpu_init(int cpu)
 368 {
 369         struct svm_cpu_data *sd;
 370         int r;
 371
 372         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 373         if (!sd)
 374                 return -ENOMEM;
 375         sd->cpu = cpu;
 376         sd->save_area = alloc_page(GFP_KERNEL);
 377         r = -ENOMEM;
 378         if (!sd->save_area)
 379                 goto err_1;
 380
 381         per_cpu(svm_data, cpu) = sd;
 382
 383         return 0;
 384
 385 err_1:
 386         kfree(sd);
 387         return r;
 388
 389 }
 390
 391 static void set_msr_interception(u32 *msrpm, unsigned msr,
 392                                  int read, int write)
 393 {
 394         int i;
 395
 396         for (i = 0; i < NUM_MSR_MAPS; i++) {
 397                 if (msr >= msrpm_ranges[i] &&
 398                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 399                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 400                                           msrpm_ranges[i]) * 2;
 401
 402                         u32 *base = msrpm + (msr_offset / 32);
 403                         u32 msr_shift = msr_offset % 32;
 404                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 405                         *base = (*base & ~(0x3 << msr_shift)) |
 406                                 (mask << msr_shift);
 407                         return;
 408                 }
 409         }
 410         BUG();
 411 }
 412
 413 static void svm_vcpu_init_msrpm(u32 *msrpm)
 414 {
 415         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 416
 417 #ifdef CONFIG_X86_64
 418         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 419         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 420         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 421         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 422         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 423         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 424 #endif
 425         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 426         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 427 }
 428
 429 static void svm_enable_lbrv(struct vcpu_svm *svm)
 430 {
 431         u32 *msrpm = svm->msrpm;
 432
 433         svm->vmcb->control.lbr_ctl = 1;
 434         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 435         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 436         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 437         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 438 }
 439
 440 static void svm_disable_lbrv(struct vcpu_svm *svm)
 441 {
 442         u32 *msrpm = svm->msrpm;
 443
 444         svm->vmcb->control.lbr_ctl = 0;
 445         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 446         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 447         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 448         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 449 }
 450
 451 static __init int svm_hardware_setup(void)
 452 {
 453         int cpu;
 454         struct page *iopm_pages;
 455         void *iopm_va;
 456         int r;
 457
 458         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 459
 460         if (!iopm_pages)
 461                 return -ENOMEM;
 462
 463         iopm_va = page_address(iopm_pages);
 464         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 465         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 466
 467         if (boot_cpu_has(X86_FEATURE_NX))
 468                 kvm_enable_efer_bits(EFER_NX);
 469
 470         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 471                 kvm_enable_efer_bits(EFER_FFXSR);
 472
 473         if (nested) {
 474                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 475                 kvm_enable_efer_bits(EFER_SVME);
 476         }
 477
 478         for_each_online_cpu(cpu) {
 479                 r = svm_cpu_init(cpu);
 480                 if (r)
 481                         goto err;
 482         }
 483
 484         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 485
 486         if (!svm_has(SVM_FEATURE_NPT))
 487                 npt_enabled = false;
 488
 489         if (npt_enabled && !npt) {
 490                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 491                 npt_enabled = false;
 492         }
 493
 494         if (npt_enabled) {
 495                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 496                 kvm_enable_tdp();
 497         } else
 498                 kvm_disable_tdp();
 499
 500         return 0;
 501
 502 err:
 503         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 504         iopm_base = 0;
 505         return r;
 506 }
 507
 508 static __exit void svm_hardware_unsetup(void)
 509 {
 510         int cpu;
 511
 512         for_each_online_cpu(cpu)
 513                 svm_cpu_uninit(cpu);
 514
 515         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 516         iopm_base = 0;
 517 }
 518
 519 static void init_seg(struct vmcb_seg *seg)
 520 {
 521         seg->selector = 0;
 522         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 523                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 524         seg->limit = 0xffff;
 525         seg->base = 0;
 526 }
 527
 528 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 529 {
 530         seg->selector = 0;
 531         seg->attrib = SVM_SELECTOR_P_MASK | type;
 532         seg->limit = 0xffff;
 533         seg->base = 0;
 534 }
 535
 536 static void init_vmcb(struct vcpu_svm *svm)
 537 {
 538         struct vmcb_control_area *control = &svm->vmcb->control;
 539         struct vmcb_save_area *save = &svm->vmcb->save;
 540
 541         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 542                                         INTERCEPT_CR3_MASK |
 543                                         INTERCEPT_CR4_MASK;
 544
 545         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 546                                         INTERCEPT_CR3_MASK |
 547                                         INTERCEPT_CR4_MASK |
 548                                         INTERCEPT_CR8_MASK;
 549
 550         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 551                                         INTERCEPT_DR1_MASK |
 552                                         INTERCEPT_DR2_MASK |
 553                                         INTERCEPT_DR3_MASK;
 554
 555         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 556                                         INTERCEPT_DR1_MASK |
 557                                         INTERCEPT_DR2_MASK |
 558                                         INTERCEPT_DR3_MASK |
 559                                         INTERCEPT_DR5_MASK |
 560                                         INTERCEPT_DR7_MASK;
 561
 562         control->intercept_exceptions = (1 << PF_VECTOR) |
 563                                         (1 << UD_VECTOR) |
 564                                         (1 << MC_VECTOR);
 565
 566
 567         control->intercept =    (1ULL << INTERCEPT_INTR) |
 568                                 (1ULL << INTERCEPT_NMI) |
 569                                 (1ULL << INTERCEPT_SMI) |
 570                                 (1ULL << INTERCEPT_CPUID) |
 571                                 (1ULL << INTERCEPT_INVD) |
 572                                 (1ULL << INTERCEPT_HLT) |
 573                                 (1ULL << INTERCEPT_INVLPG) |
 574                                 (1ULL << INTERCEPT_INVLPGA) |
 575                                 (1ULL << INTERCEPT_IOIO_PROT) |
 576                                 (1ULL << INTERCEPT_MSR_PROT) |
 577                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 578                                 (1ULL << INTERCEPT_SHUTDOWN) |
 579                                 (1ULL << INTERCEPT_VMRUN) |
 580                                 (1ULL << INTERCEPT_VMMCALL) |
 581                                 (1ULL << INTERCEPT_VMLOAD) |
 582                                 (1ULL << INTERCEPT_VMSAVE) |
 583                                 (1ULL << INTERCEPT_STGI) |
 584                                 (1ULL << INTERCEPT_CLGI) |
 585                                 (1ULL << INTERCEPT_SKINIT) |
 586                                 (1ULL << INTERCEPT_WBINVD) |
 587                                 (1ULL << INTERCEPT_MONITOR) |
 588                                 (1ULL << INTERCEPT_MWAIT);
 589
 590         control->iopm_base_pa = iopm_base;
 591         control->msrpm_base_pa = __pa(svm->msrpm);
 592         control->tsc_offset = 0;
 593         control->int_ctl = V_INTR_MASKING_MASK;
 594
 595         init_seg(&save->es);
 596         init_seg(&save->ss);
 597         init_seg(&save->ds);
 598         init_seg(&save->fs);
 599         init_seg(&save->gs);
 600
 601         save->cs.selector = 0xf000;
 602         /* Executable/Readable Code Segment */
 603         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 604                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 605         save->cs.limit = 0xffff;
 606         /*
 607          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 608          * be consistent with it.
 609          *
 610          * Replace when we have real mode working for vmx.
 611          */
 612         save->cs.base = 0xf0000;
 613
 614         save->gdtr.limit = 0xffff;
 615         save->idtr.limit = 0xffff;
 616
 617         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 618         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 619
 620         save->efer = EFER_SVME;
 621         save->dr6 = 0xffff0ff0;
 622         save->dr7 = 0x400;
 623         save->rflags = 2;
 624         save->rip = 0x0000fff0;
 625         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 626
 627         /*
 628          * cr0 val on cpu init should be 0x60000010, we enable cpu
 629          * cache by default. the orderly way is to enable cache in bios.
 630          */
 631         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 632         save->cr4 = X86_CR4_PAE;
 633         /* rdx = ?? */
 634
 635         if (npt_enabled) {
 636                 /* Setup VMCB for Nested Paging */
 637                 control->nested_ctl = 1;
 638                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 639                                         (1ULL << INTERCEPT_INVLPG));
 640                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 641                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 642                                                 INTERCEPT_CR3_MASK);
 643                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 644                                                  INTERCEPT_CR3_MASK);
 645                 save->g_pat = 0x0007040600070406ULL;
 646                 /* enable caching because the QEMU Bios doesn't enable it */
 647                 save->cr0 = X86_CR0_ET;
 648                 save->cr3 = 0;
 649                 save->cr4 = 0;
 650         }
 651         force_new_asid(&svm->vcpu);
 652
 653         svm->nested.vmcb = 0;
 654         svm->vcpu.arch.hflags = 0;
 655
 656         enable_gif(svm);
 657 }
 658
 659 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 660 {
 661         struct vcpu_svm *svm = to_svm(vcpu);
 662
 663         init_vmcb(svm);
 664
 665         if (!kvm_vcpu_is_bsp(vcpu)) {
 666                 kvm_rip_write(vcpu, 0);
 667                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 668                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 669         }
 670         vcpu->arch.regs_avail = ~0;
 671         vcpu->arch.regs_dirty = ~0;
 672
 673         return 0;
 674 }
 675
 676 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 677 {
 678         struct vcpu_svm *svm;
 679         struct page *page;
 680         struct page *msrpm_pages;
 681         struct page *hsave_page;
 682         struct page *nested_msrpm_pages;
 683         int err;
 684
 685         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 686         if (!svm) {
 687                 err = -ENOMEM;
 688                 goto out;
 689         }
 690
 691         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 692         if (err)
 693                 goto free_svm;
 694
 695         page = alloc_page(GFP_KERNEL);
 696         if (!page) {
 697                 err = -ENOMEM;
 698                 goto uninit;
 699         }
 700
 701         err = -ENOMEM;
 702         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 703         if (!msrpm_pages)
 704                 goto uninit;
 705
 706         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 707         if (!nested_msrpm_pages)
 708                 goto uninit;
 709
 710         svm->msrpm = page_address(msrpm_pages);
 711         svm_vcpu_init_msrpm(svm->msrpm);
 712
 713         hsave_page = alloc_page(GFP_KERNEL);
 714         if (!hsave_page)
 715                 goto uninit;
 716         svm->nested.hsave = page_address(hsave_page);
 717
 718         svm->nested.msrpm = page_address(nested_msrpm_pages);
 719
 720         svm->vmcb = page_address(page);
 721         clear_page(svm->vmcb);
 722         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 723         svm->asid_generation = 0;
 724         init_vmcb(svm);
 725
 726         fx_init(&svm->vcpu);
 727         svm->vcpu.fpu_active = 1;
 728         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 729         if (kvm_vcpu_is_bsp(&svm->vcpu))
 730                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 731
 732         return &svm->vcpu;
 733
 734 uninit:
 735         kvm_vcpu_uninit(&svm->vcpu);
 736 free_svm:
 737         kmem_cache_free(kvm_vcpu_cache, svm);
 738 out:
 739         return ERR_PTR(err);
 740 }
 741
 742 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 743 {
 744         struct vcpu_svm *svm = to_svm(vcpu);
 745
 746         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 747         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 748         __free_page(virt_to_page(svm->nested.hsave));
 749         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 750         kvm_vcpu_uninit(vcpu);
 751         kmem_cache_free(kvm_vcpu_cache, svm);
 752 }
 753
 754 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 755 {
 756         struct vcpu_svm *svm = to_svm(vcpu);
 757         int i;
 758
 759         if (unlikely(cpu != vcpu->cpu)) {
 760                 u64 tsc_this, delta;
 761
 762                 /*
 763                  * Make sure that the guest sees a monotonically
 764                  * increasing TSC.
 765                  */
 766                 rdtscll(tsc_this);
 767                 delta = vcpu->arch.host_tsc - tsc_this;
 768                 svm->vmcb->control.tsc_offset += delta;
 769                 vcpu->cpu = cpu;
 770                 kvm_migrate_timers(vcpu);
 771                 svm->asid_generation = 0;
 772         }
 773
 774         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 775                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 776 }
 777
 778 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 779 {
 780         struct vcpu_svm *svm = to_svm(vcpu);
 781         int i;
 782
 783         ++vcpu->stat.host_state_reload;
 784         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 785                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 786
 787         rdtscll(vcpu->arch.host_tsc);
 788 }
 789
 790 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 791 {
 792         return to_svm(vcpu)->vmcb->save.rflags;
 793 }
 794
 795 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 796 {
 797         to_svm(vcpu)->vmcb->save.rflags = rflags;
 798 }
 799
 800 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 801 {
 802         switch (reg) {
 803         case VCPU_EXREG_PDPTR:
 804                 BUG_ON(!npt_enabled);
 805                 load_pdptrs(vcpu, vcpu->arch.cr3);
 806                 break;
 807         default:
 808                 BUG();
 809         }
 810 }
 811
 812 static void svm_set_vintr(struct vcpu_svm *svm)
 813 {
 814         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 815 }
 816
 817 static void svm_clear_vintr(struct vcpu_svm *svm)
 818 {
 819         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 820 }
 821
 822 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 823 {
 824         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 825
 826         switch (seg) {
 827         case VCPU_SREG_CS: return &save->cs;
 828         case VCPU_SREG_DS: return &save->ds;
 829         case VCPU_SREG_ES: return &save->es;
 830         case VCPU_SREG_FS: return &save->fs;
 831         case VCPU_SREG_GS: return &save->gs;
 832         case VCPU_SREG_SS: return &save->ss;
 833         case VCPU_SREG_TR: return &save->tr;
 834         case VCPU_SREG_LDTR: return &save->ldtr;
 835         }
 836         BUG();
 837         return NULL;
 838 }
 839
 840 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 841 {
 842         struct vmcb_seg *s = svm_seg(vcpu, seg);
 843
 844         return s->base;
 845 }
 846
 847 static void svm_get_segment(struct kvm_vcpu *vcpu,
 848                             struct kvm_segment *var, int seg)
 849 {
 850         struct vmcb_seg *s = svm_seg(vcpu, seg);
 851
 852         var->base = s->base;
 853         var->limit = s->limit;
 854         var->selector = s->selector;
 855         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 856         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 857         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 858         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 859         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 860         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 861         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 862         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 863
 864         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 865          * for cross vendor migration purposes by "not present"
 866          */
 867         var->unusable = !var->present || (var->type == 0);
 868
 869         switch (seg) {
 870         case VCPU_SREG_CS:
 871                 /*
 872                  * SVM always stores 0 for the 'G' bit in the CS selector in
 873                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 874                  * Intel's VMENTRY has a check on the 'G' bit.
 875                  */
 876                 var->g = s->limit > 0xfffff;
 877                 break;
 878         case VCPU_SREG_TR:
 879                 /*
 880                  * Work around a bug where the busy flag in the tr selector
 881                  * isn't exposed
 882                  */
 883                 var->type |= 0x2;
 884                 break;
 885         case VCPU_SREG_DS:
 886         case VCPU_SREG_ES:
 887         case VCPU_SREG_FS:
 888         case VCPU_SREG_GS:
 889                 /*
 890                  * The accessed bit must always be set in the segment
 891                  * descriptor cache, although it can be cleared in the
 892                  * descriptor, the cached bit always remains at 1. Since
 893                  * Intel has a check on this, set it here to support
 894                  * cross-vendor migration.
 895                  */
 896                 if (!var->unusable)
 897                         var->type |= 0x1;
 898                 break;
 899         case VCPU_SREG_SS:
 900                 /* On AMD CPUs sometimes the DB bit in the segment
 901                  * descriptor is left as 1, although the whole segment has
 902                  * been made unusable. Clear it here to pass an Intel VMX
 903                  * entry check when cross vendor migrating.
 904                  */
 905                 if (var->unusable)
 906                         var->db = 0;
 907                 break;
 908         }
 909 }
 910
 911 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 912 {
 913         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 914
 915         return save->cpl;
 916 }
 917
 918 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 919 {
 920         struct vcpu_svm *svm = to_svm(vcpu);
 921
 922         dt->limit = svm->vmcb->save.idtr.limit;
 923         dt->base = svm->vmcb->save.idtr.base;
 924 }
 925
 926 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 927 {
 928         struct vcpu_svm *svm = to_svm(vcpu);
 929
 930         svm->vmcb->save.idtr.limit = dt->limit;
 931         svm->vmcb->save.idtr.base = dt->base ;
 932 }
 933
 934 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937
 938         dt->limit = svm->vmcb->save.gdtr.limit;
 939         dt->base = svm->vmcb->save.gdtr.base;
 940 }
 941
 942 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 943 {
 944         struct vcpu_svm *svm = to_svm(vcpu);
 945
 946         svm->vmcb->save.gdtr.limit = dt->limit;
 947         svm->vmcb->save.gdtr.base = dt->base ;
 948 }
 949
 950 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 951 {
 952 }
 953
 954 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 955 {
 956         struct vcpu_svm *svm = to_svm(vcpu);
 957
 958 #ifdef CONFIG_X86_64
 959         if (vcpu->arch.shadow_efer & EFER_LME) {
 960                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 961                         vcpu->arch.shadow_efer |= EFER_LMA;
 962                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 963                 }
 964
 965                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 966                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 967                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 968                 }
 969         }
 970 #endif
 971         if (npt_enabled)
 972                 goto set;
 973
 974         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 975                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 976                 vcpu->fpu_active = 1;
 977         }
 978
 979         vcpu->arch.cr0 = cr0;
 980         cr0 |= X86_CR0_PG | X86_CR0_WP;
 981         if (!vcpu->fpu_active) {
 982                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 983                 cr0 |= X86_CR0_TS;
 984         }
 985 set:
 986         /*
 987          * re-enable caching here because the QEMU bios
 988          * does not do it - this results in some delay at
 989          * reboot
 990          */
 991         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 992         svm->vmcb->save.cr0 = cr0;
 993 }
 994
 995 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 996 {
 997         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 998         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 999
1000         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1001                 force_new_asid(vcpu);
1002
1003         vcpu->arch.cr4 = cr4;
1004         if (!npt_enabled)
1005                 cr4 |= X86_CR4_PAE;
1006         cr4 |= host_cr4_mce;
1007         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1008 }
1009
1010 static void svm_set_segment(struct kvm_vcpu *vcpu,
1011                             struct kvm_segment *var, int seg)
1012 {
1013         struct vcpu_svm *svm = to_svm(vcpu);
1014         struct vmcb_seg *s = svm_seg(vcpu, seg);
1015
1016         s->base = var->base;
1017         s->limit = var->limit;
1018         s->selector = var->selector;
1019         if (var->unusable)
1020                 s->attrib = 0;
1021         else {
1022                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1023                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1024                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1025                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1026                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1027                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1028                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1029                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1030         }
1031         if (seg == VCPU_SREG_CS)
1032                 svm->vmcb->save.cpl
1033                         = (svm->vmcb->save.cs.attrib
1034                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1035
1036 }
1037
1038 static void update_db_intercept(struct kvm_vcpu *vcpu)
1039 {
1040         struct vcpu_svm *svm = to_svm(vcpu);
1041
1042         svm->vmcb->control.intercept_exceptions &=
1043                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1044
1045         if (vcpu->arch.singlestep)
1046                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1047
1048         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1049                 if (vcpu->guest_debug &
1050                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1051                         svm->vmcb->control.intercept_exceptions |=
1052                                 1 << DB_VECTOR;
1053                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1054                         svm->vmcb->control.intercept_exceptions |=
1055                                 1 << BP_VECTOR;
1056         } else
1057                 vcpu->guest_debug = 0;
1058 }
1059
1060 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1061 {
1062         int old_debug = vcpu->guest_debug;
1063         struct vcpu_svm *svm = to_svm(vcpu);
1064
1065         vcpu->guest_debug = dbg->control;
1066
1067         update_db_intercept(vcpu);
1068
1069         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1070                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1071         else
1072                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1073
1074         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1075                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1076         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1077                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1078
1079         return 0;
1080 }
1081
1082 static void load_host_msrs(struct kvm_vcpu *vcpu)
1083 {
1084 #ifdef CONFIG_X86_64
1085         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1086 #endif
1087 }
1088
1089 static void save_host_msrs(struct kvm_vcpu *vcpu)
1090 {
1091 #ifdef CONFIG_X86_64
1092         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1093 #endif
1094 }
1095
1096 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1097 {
1098         if (sd->next_asid > sd->max_asid) {
1099                 ++sd->asid_generation;
1100                 sd->next_asid = 1;
1101                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1102         }
1103
1104         svm->asid_generation = sd->asid_generation;
1105         svm->vmcb->control.asid = sd->next_asid++;
1106 }
1107
1108 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1109 {
1110         struct vcpu_svm *svm = to_svm(vcpu);
1111         unsigned long val;
1112
1113         switch (dr) {
1114         case 0 ... 3:
1115                 val = vcpu->arch.db[dr];
1116                 break;
1117         case 6:
1118                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1119                         val = vcpu->arch.dr6;
1120                 else
1121                         val = svm->vmcb->save.dr6;
1122                 break;
1123         case 7:
1124                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1125                         val = vcpu->arch.dr7;
1126                 else
1127                         val = svm->vmcb->save.dr7;
1128                 break;
1129         default:
1130                 val = 0;
1131         }
1132
1133         return val;
1134 }
1135
1136 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1137                        int *exception)
1138 {
1139         struct vcpu_svm *svm = to_svm(vcpu);
1140
1141         *exception = 0;
1142
1143         switch (dr) {
1144         case 0 ... 3:
1145                 vcpu->arch.db[dr] = value;
1146                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1147                         vcpu->arch.eff_db[dr] = value;
1148                 return;
1149         case 4 ... 5:
1150                 if (vcpu->arch.cr4 & X86_CR4_DE)
1151                         *exception = UD_VECTOR;
1152                 return;
1153         case 6:
1154                 if (value & 0xffffffff00000000ULL) {
1155                         *exception = GP_VECTOR;
1156                         return;
1157                 }
1158                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1159                 return;
1160         case 7:
1161                 if (value & 0xffffffff00000000ULL) {
1162                         *exception = GP_VECTOR;
1163                         return;
1164                 }
1165                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1166                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1167                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1168                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1169                 }
1170                 return;
1171         default:
1172                 /* FIXME: Possible case? */
1173                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1174                        __func__, dr);
1175                 *exception = UD_VECTOR;
1176                 return;
1177         }
1178 }
1179
1180 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1181 {
1182         u64 fault_address;
1183         u32 error_code;
1184
1185         fault_address  = svm->vmcb->control.exit_info_2;
1186         error_code = svm->vmcb->control.exit_info_1;
1187
1188         trace_kvm_page_fault(fault_address, error_code);
1189         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1190                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1191         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1192 }
1193
1194 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1195 {
1196         if (!(svm->vcpu.guest_debug &
1197               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1198                 !svm->vcpu.arch.singlestep) {
1199                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1200                 return 1;
1201         }
1202
1203         if (svm->vcpu.arch.singlestep) {
1204                 svm->vcpu.arch.singlestep = false;
1205                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1206                         svm->vmcb->save.rflags &=
1207                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1208                 update_db_intercept(&svm->vcpu);
1209         }
1210
1211         if (svm->vcpu.guest_debug &
1212             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1213                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1214                 kvm_run->debug.arch.pc =
1215                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1216                 kvm_run->debug.arch.exception = DB_VECTOR;
1217                 return 0;
1218         }
1219
1220         return 1;
1221 }
1222
1223 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1224 {
1225         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1226         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1227         kvm_run->debug.arch.exception = BP_VECTOR;
1228         return 0;
1229 }
1230
1231 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1232 {
1233         int er;
1234
1235         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1236         if (er != EMULATE_DONE)
1237                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1238         return 1;
1239 }
1240
1241 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1242 {
1243         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1244         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1245                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1246         svm->vcpu.fpu_active = 1;
1247
1248         return 1;
1249 }
1250
1251 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1252 {
1253         /*
1254          * On an #MC intercept the MCE handler is not called automatically in
1255          * the host. So do it by hand here.
1256          */
1257         asm volatile (
1258                 "int $0x12\n");
1259         /* not sure if we ever come back to this point */
1260
1261         return 1;
1262 }
1263
1264 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1265 {
1266         /*
1267          * VMCB is undefined after a SHUTDOWN intercept
1268          * so reinitialize it.
1269          */
1270         clear_page(svm->vmcb);
1271         init_vmcb(svm);
1272
1273         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1274         return 0;
1275 }
1276
1277 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1278 {
1279         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1280         int size, in, string;
1281         unsigned port;
1282
1283         ++svm->vcpu.stat.io_exits;
1284
1285         svm->next_rip = svm->vmcb->control.exit_info_2;
1286
1287         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1288
1289         if (string) {
1290                 if (emulate_instruction(&svm->vcpu,
1291                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1292                         return 0;
1293                 return 1;
1294         }
1295
1296         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1297         port = io_info >> 16;
1298         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1299
1300         skip_emulated_instruction(&svm->vcpu);
1301         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1302 }
1303
1304 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1305 {
1306         return 1;
1307 }
1308
1309 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1310 {
1311         ++svm->vcpu.stat.irq_exits;
1312         return 1;
1313 }
1314
1315 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1316 {
1317         return 1;
1318 }
1319
1320 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1321 {
1322         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1323         skip_emulated_instruction(&svm->vcpu);
1324         return kvm_emulate_halt(&svm->vcpu);
1325 }
1326
1327 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1328 {
1329         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1330         skip_emulated_instruction(&svm->vcpu);
1331         kvm_emulate_hypercall(&svm->vcpu);
1332         return 1;
1333 }
1334
1335 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1336 {
1337         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1338             || !is_paging(&svm->vcpu)) {
1339                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1340                 return 1;
1341         }
1342
1343         if (svm->vmcb->save.cpl) {
1344                 kvm_inject_gp(&svm->vcpu, 0);
1345                 return 1;
1346         }
1347
1348        return 0;
1349 }
1350
1351 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1352                                       bool has_error_code, u32 error_code)
1353 {
1354         if (!is_nested(svm))
1355                 return 0;
1356
1357         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1358         svm->vmcb->control.exit_code_hi = 0;
1359         svm->vmcb->control.exit_info_1 = error_code;
1360         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1361
1362         return nested_svm_exit_handled(svm);
1363 }
1364
1365 static inline int nested_svm_intr(struct vcpu_svm *svm)
1366 {
1367         if (!is_nested(svm))
1368                 return 0;
1369
1370         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1371                 return 0;
1372
1373         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1374                 return 0;
1375
1376         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1377
1378         if (nested_svm_exit_handled(svm)) {
1379                 nsvm_printk("VMexit -> INTR\n");
1380                 return 1;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1387 {
1388         struct page *page;
1389
1390         down_read(&current->mm->mmap_sem);
1391         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1392         up_read(&current->mm->mmap_sem);
1393
1394         if (is_error_page(page))
1395                 goto error;
1396
1397         return kmap_atomic(page, idx);
1398
1399 error:
1400         kvm_release_page_clean(page);
1401         kvm_inject_gp(&svm->vcpu, 0);
1402
1403         return NULL;
1404 }
1405
1406 static void nested_svm_unmap(void *addr, enum km_type idx)
1407 {
1408         struct page *page;
1409
1410         if (!addr)
1411                 return;
1412
1413         page = kmap_atomic_to_page(addr);
1414
1415         kunmap_atomic(addr, idx);
1416         kvm_release_page_dirty(page);
1417 }
1418
1419 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1420 {
1421         u32 param = svm->vmcb->control.exit_info_1 & 1;
1422         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1423         bool ret = false;
1424         u32 t0, t1;
1425         u8 *msrpm;
1426
1427         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1428                 return false;
1429
1430         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1431
1432         if (!msrpm)
1433                 goto out;
1434
1435         switch (msr) {
1436         case 0 ... 0x1fff:
1437                 t0 = (msr * 2) % 8;
1438                 t1 = msr / 8;
1439                 break;
1440         case 0xc0000000 ... 0xc0001fff:
1441                 t0 = (8192 + msr - 0xc0000000) * 2;
1442                 t1 = (t0 / 8);
1443                 t0 %= 8;
1444                 break;
1445         case 0xc0010000 ... 0xc0011fff:
1446                 t0 = (16384 + msr - 0xc0010000) * 2;
1447                 t1 = (t0 / 8);
1448                 t0 %= 8;
1449                 break;
1450         default:
1451                 ret = true;
1452                 goto out;
1453         }
1454
1455         ret = msrpm[t1] & ((1 << param) << t0);
1456
1457 out:
1458         nested_svm_unmap(msrpm, KM_USER0);
1459
1460         return ret;
1461 }
1462
1463 static int nested_svm_exit_special(struct vcpu_svm *svm)
1464 {
1465         u32 exit_code = svm->vmcb->control.exit_code;
1466
1467         switch (exit_code) {
1468         case SVM_EXIT_INTR:
1469         case SVM_EXIT_NMI:
1470                 return NESTED_EXIT_HOST;
1471                 /* For now we are always handling NPFs when using them */
1472         case SVM_EXIT_NPF:
1473                 if (npt_enabled)
1474                         return NESTED_EXIT_HOST;
1475                 break;
1476         /* When we're shadowing, trap PFs */
1477         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1478                 if (!npt_enabled)
1479                         return NESTED_EXIT_HOST;
1480                 break;
1481         default:
1482                 break;
1483         }
1484
1485         return NESTED_EXIT_CONTINUE;
1486 }
1487
1488 /*
1489  * If this function returns true, this #vmexit was already handled
1490  */
1491 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1492 {
1493         u32 exit_code = svm->vmcb->control.exit_code;
1494         int vmexit = NESTED_EXIT_HOST;
1495
1496         switch (exit_code) {
1497         case SVM_EXIT_MSR:
1498                 vmexit = nested_svm_exit_handled_msr(svm);
1499                 break;
1500         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1501                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1502                 if (svm->nested.intercept_cr_read & cr_bits)
1503                         vmexit = NESTED_EXIT_DONE;
1504                 break;
1505         }
1506         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1507                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1508                 if (svm->nested.intercept_cr_write & cr_bits)
1509                         vmexit = NESTED_EXIT_DONE;
1510                 break;
1511         }
1512         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1513                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1514                 if (svm->nested.intercept_dr_read & dr_bits)
1515                         vmexit = NESTED_EXIT_DONE;
1516                 break;
1517         }
1518         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1519                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1520                 if (svm->nested.intercept_dr_write & dr_bits)
1521                         vmexit = NESTED_EXIT_DONE;
1522                 break;
1523         }
1524         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1525                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1526                 if (svm->nested.intercept_exceptions & excp_bits)
1527                         vmexit = NESTED_EXIT_DONE;
1528                 break;
1529         }
1530         default: {
1531                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1532                 nsvm_printk("exit code: 0x%x\n", exit_code);
1533                 if (svm->nested.intercept & exit_bits)
1534                         vmexit = NESTED_EXIT_DONE;
1535         }
1536         }
1537
1538         if (vmexit == NESTED_EXIT_DONE) {
1539                 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1540                 nested_svm_vmexit(svm);
1541         }
1542
1543         return vmexit;
1544 }
1545
1546 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1547 {
1548         struct vmcb_control_area *dst  = &dst_vmcb->control;
1549         struct vmcb_control_area *from = &from_vmcb->control;
1550
1551         dst->intercept_cr_read    = from->intercept_cr_read;
1552         dst->intercept_cr_write   = from->intercept_cr_write;
1553         dst->intercept_dr_read    = from->intercept_dr_read;
1554         dst->intercept_dr_write   = from->intercept_dr_write;
1555         dst->intercept_exceptions = from->intercept_exceptions;
1556         dst->intercept            = from->intercept;
1557         dst->iopm_base_pa         = from->iopm_base_pa;
1558         dst->msrpm_base_pa        = from->msrpm_base_pa;
1559         dst->tsc_offset           = from->tsc_offset;
1560         dst->asid                 = from->asid;
1561         dst->tlb_ctl              = from->tlb_ctl;
1562         dst->int_ctl              = from->int_ctl;
1563         dst->int_vector           = from->int_vector;
1564         dst->int_state            = from->int_state;
1565         dst->exit_code            = from->exit_code;
1566         dst->exit_code_hi         = from->exit_code_hi;
1567         dst->exit_info_1          = from->exit_info_1;
1568         dst->exit_info_2          = from->exit_info_2;
1569         dst->exit_int_info        = from->exit_int_info;
1570         dst->exit_int_info_err    = from->exit_int_info_err;
1571         dst->nested_ctl           = from->nested_ctl;
1572         dst->event_inj            = from->event_inj;
1573         dst->event_inj_err        = from->event_inj_err;
1574         dst->nested_cr3           = from->nested_cr3;
1575         dst->lbr_ctl              = from->lbr_ctl;
1576 }
1577
1578 static int nested_svm_vmexit(struct vcpu_svm *svm)
1579 {
1580         struct vmcb *nested_vmcb;
1581         struct vmcb *hsave = svm->nested.hsave;
1582         struct vmcb *vmcb = svm->vmcb;
1583
1584         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1585         if (!nested_vmcb)
1586                 return 1;
1587
1588         /* Give the current vmcb to the guest */
1589         disable_gif(svm);
1590
1591         nested_vmcb->save.es     = vmcb->save.es;
1592         nested_vmcb->save.cs     = vmcb->save.cs;
1593         nested_vmcb->save.ss     = vmcb->save.ss;
1594         nested_vmcb->save.ds     = vmcb->save.ds;
1595         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1596         nested_vmcb->save.idtr   = vmcb->save.idtr;
1597         if (npt_enabled)
1598                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1599         nested_vmcb->save.cr2    = vmcb->save.cr2;
1600         nested_vmcb->save.rflags = vmcb->save.rflags;
1601         nested_vmcb->save.rip    = vmcb->save.rip;
1602         nested_vmcb->save.rsp    = vmcb->save.rsp;
1603         nested_vmcb->save.rax    = vmcb->save.rax;
1604         nested_vmcb->save.dr7    = vmcb->save.dr7;
1605         nested_vmcb->save.dr6    = vmcb->save.dr6;
1606         nested_vmcb->save.cpl    = vmcb->save.cpl;
1607
1608         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1609         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1610         nested_vmcb->control.int_state         = vmcb->control.int_state;
1611         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1612         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1613         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1614         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1615         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1616         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1617         nested_vmcb->control.tlb_ctl           = 0;
1618         nested_vmcb->control.event_inj         = 0;
1619         nested_vmcb->control.event_inj_err     = 0;
1620
1621         /* We always set V_INTR_MASKING and remember the old value in hflags */
1622         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1623                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1624
1625         /* Restore the original control entries */
1626         copy_vmcb_control_area(vmcb, hsave);
1627
1628         /* Kill any pending exceptions */
1629         if (svm->vcpu.arch.exception.pending == true)
1630                 nsvm_printk("WARNING: Pending Exception\n");
1631
1632         kvm_clear_exception_queue(&svm->vcpu);
1633         kvm_clear_interrupt_queue(&svm->vcpu);
1634
1635         /* Restore selected save entries */
1636         svm->vmcb->save.es = hsave->save.es;
1637         svm->vmcb->save.cs = hsave->save.cs;
1638         svm->vmcb->save.ss = hsave->save.ss;
1639         svm->vmcb->save.ds = hsave->save.ds;
1640         svm->vmcb->save.gdtr = hsave->save.gdtr;
1641         svm->vmcb->save.idtr = hsave->save.idtr;
1642         svm->vmcb->save.rflags = hsave->save.rflags;
1643         svm_set_efer(&svm->vcpu, hsave->save.efer);
1644         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1645         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1646         if (npt_enabled) {
1647                 svm->vmcb->save.cr3 = hsave->save.cr3;
1648                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1649         } else {
1650                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1651         }
1652         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1653         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1654         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1655         svm->vmcb->save.dr7 = 0;
1656         svm->vmcb->save.cpl = 0;
1657         svm->vmcb->control.exit_int_info = 0;
1658
1659         /* Exit nested SVM mode */
1660         svm->nested.vmcb = 0;
1661
1662         nested_svm_unmap(nested_vmcb, KM_USER0);
1663
1664         kvm_mmu_reset_context(&svm->vcpu);
1665         kvm_mmu_load(&svm->vcpu);
1666
1667         return 0;
1668 }
1669
1670 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1671 {
1672         u32 *nested_msrpm;
1673         int i;
1674
1675         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1676         if (!nested_msrpm)
1677                 return false;
1678
1679         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1680                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1681
1682         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1683
1684         nested_svm_unmap(nested_msrpm, KM_USER0);
1685
1686         return true;
1687 }
1688
1689 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1690 {
1691         struct vmcb *nested_vmcb;
1692         struct vmcb *hsave = svm->nested.hsave;
1693         struct vmcb *vmcb = svm->vmcb;
1694
1695         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1696         if (!nested_vmcb)
1697                 return false;
1698
1699         /* nested_vmcb is our indicator if nested SVM is activated */
1700         svm->nested.vmcb = svm->vmcb->save.rax;
1701
1702         /* Clear internal status */
1703         kvm_clear_exception_queue(&svm->vcpu);
1704         kvm_clear_interrupt_queue(&svm->vcpu);
1705
1706         /* Save the old vmcb, so we don't need to pick what we save, but
1707            can restore everything when a VMEXIT occurs */
1708         hsave->save.es     = vmcb->save.es;
1709         hsave->save.cs     = vmcb->save.cs;
1710         hsave->save.ss     = vmcb->save.ss;
1711         hsave->save.ds     = vmcb->save.ds;
1712         hsave->save.gdtr   = vmcb->save.gdtr;
1713         hsave->save.idtr   = vmcb->save.idtr;
1714         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1715         hsave->save.cr0    = svm->vcpu.arch.cr0;
1716         hsave->save.cr4    = svm->vcpu.arch.cr4;
1717         hsave->save.rflags = vmcb->save.rflags;
1718         hsave->save.rip    = svm->next_rip;
1719         hsave->save.rsp    = vmcb->save.rsp;
1720         hsave->save.rax    = vmcb->save.rax;
1721         if (npt_enabled)
1722                 hsave->save.cr3    = vmcb->save.cr3;
1723         else
1724                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1725
1726         copy_vmcb_control_area(hsave, vmcb);
1727
1728         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1729                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1730         else
1731                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1732
1733         /* Load the nested guest state */
1734         svm->vmcb->save.es = nested_vmcb->save.es;
1735         svm->vmcb->save.cs = nested_vmcb->save.cs;
1736         svm->vmcb->save.ss = nested_vmcb->save.ss;
1737         svm->vmcb->save.ds = nested_vmcb->save.ds;
1738         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1739         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1740         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1741         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1742         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1743         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1744         if (npt_enabled) {
1745                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1746                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1747         } else {
1748                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1749                 kvm_mmu_reset_context(&svm->vcpu);
1750         }
1751         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1752         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1753         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1754         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1755         /* In case we don't even reach vcpu_run, the fields are not updated */
1756         svm->vmcb->save.rax = nested_vmcb->save.rax;
1757         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1758         svm->vmcb->save.rip = nested_vmcb->save.rip;
1759         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1760         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1761         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1762
1763         /* We don't want a nested guest to be more powerful than the guest,
1764            so all intercepts are ORed */
1765         svm->vmcb->control.intercept_cr_read |=
1766                 nested_vmcb->control.intercept_cr_read;
1767         svm->vmcb->control.intercept_cr_write |=
1768                 nested_vmcb->control.intercept_cr_write;
1769         svm->vmcb->control.intercept_dr_read |=
1770                 nested_vmcb->control.intercept_dr_read;
1771         svm->vmcb->control.intercept_dr_write |=
1772                 nested_vmcb->control.intercept_dr_write;
1773         svm->vmcb->control.intercept_exceptions |=
1774                 nested_vmcb->control.intercept_exceptions;
1775
1776         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1777
1778         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1779
1780         /* cache intercepts */
1781         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1782         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1783         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1784         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1785         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1786         svm->nested.intercept            = nested_vmcb->control.intercept;
1787
1788         force_new_asid(&svm->vcpu);
1789         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1790         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1791         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1792         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1793                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1794                                 nested_vmcb->control.int_ctl);
1795         }
1796         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1797                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1798         else
1799                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1800
1801         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1802                         nested_vmcb->control.exit_int_info,
1803                         nested_vmcb->control.int_state);
1804
1805         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1806         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1807         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1808         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1809                 nsvm_printk("Injecting Event: 0x%x\n",
1810                                 nested_vmcb->control.event_inj);
1811         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1812         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1813
1814         nested_svm_unmap(nested_vmcb, KM_USER0);
1815
1816         enable_gif(svm);
1817
1818         return true;
1819 }
1820
1821 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1822 {
1823         to_vmcb->save.fs = from_vmcb->save.fs;
1824         to_vmcb->save.gs = from_vmcb->save.gs;
1825         to_vmcb->save.tr = from_vmcb->save.tr;
1826         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1827         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1828         to_vmcb->save.star = from_vmcb->save.star;
1829         to_vmcb->save.lstar = from_vmcb->save.lstar;
1830         to_vmcb->save.cstar = from_vmcb->save.cstar;
1831         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1832         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1833         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1834         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1835 }
1836
1837 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1838 {
1839         struct vmcb *nested_vmcb;
1840
1841         if (nested_svm_check_permissions(svm))
1842                 return 1;
1843
1844         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1845         skip_emulated_instruction(&svm->vcpu);
1846
1847         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1848         if (!nested_vmcb)
1849                 return 1;
1850
1851         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1852         nested_svm_unmap(nested_vmcb, KM_USER0);
1853
1854         return 1;
1855 }
1856
1857 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1858 {
1859         struct vmcb *nested_vmcb;
1860
1861         if (nested_svm_check_permissions(svm))
1862                 return 1;
1863
1864         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1865         skip_emulated_instruction(&svm->vcpu);
1866
1867         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1868         if (!nested_vmcb)
1869                 return 1;
1870
1871         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1872         nested_svm_unmap(nested_vmcb, KM_USER0);
1873
1874         return 1;
1875 }
1876
1877 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1878 {
1879         nsvm_printk("VMrun\n");
1880
1881         if (nested_svm_check_permissions(svm))
1882                 return 1;
1883
1884         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1885         skip_emulated_instruction(&svm->vcpu);
1886
1887         if (!nested_svm_vmrun(svm))
1888                 return 1;
1889
1890         if (!nested_svm_vmrun_msrpm(svm))
1891                 goto failed;
1892
1893         return 1;
1894
1895 failed:
1896
1897         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1898         svm->vmcb->control.exit_code_hi = 0;
1899         svm->vmcb->control.exit_info_1  = 0;
1900         svm->vmcb->control.exit_info_2  = 0;
1901
1902         nested_svm_vmexit(svm);
1903
1904         return 1;
1905 }
1906
1907 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1908 {
1909         if (nested_svm_check_permissions(svm))
1910                 return 1;
1911
1912         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1913         skip_emulated_instruction(&svm->vcpu);
1914
1915         enable_gif(svm);
1916
1917         return 1;
1918 }
1919
1920 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1921 {
1922         if (nested_svm_check_permissions(svm))
1923                 return 1;
1924
1925         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1926         skip_emulated_instruction(&svm->vcpu);
1927
1928         disable_gif(svm);
1929
1930         /* After a CLGI no interrupts should come */
1931         svm_clear_vintr(svm);
1932         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1933
1934         return 1;
1935 }
1936
1937 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1938 {
1939         struct kvm_vcpu *vcpu = &svm->vcpu;
1940         nsvm_printk("INVLPGA\n");
1941
1942         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1943         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1944
1945         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946         skip_emulated_instruction(&svm->vcpu);
1947         return 1;
1948 }
1949
1950 static int invalid_op_interception(struct vcpu_svm *svm,
1951                                    struct kvm_run *kvm_run)
1952 {
1953         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1954         return 1;
1955 }
1956
1957 static int task_switch_interception(struct vcpu_svm *svm,
1958                                     struct kvm_run *kvm_run)
1959 {
1960         u16 tss_selector;
1961         int reason;
1962         int int_type = svm->vmcb->control.exit_int_info &
1963                 SVM_EXITINTINFO_TYPE_MASK;
1964         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1965         uint32_t type =
1966                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1967         uint32_t idt_v =
1968                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1969
1970         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1971
1972         if (svm->vmcb->control.exit_info_2 &
1973             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1974                 reason = TASK_SWITCH_IRET;
1975         else if (svm->vmcb->control.exit_info_2 &
1976                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1977                 reason = TASK_SWITCH_JMP;
1978         else if (idt_v)
1979                 reason = TASK_SWITCH_GATE;
1980         else
1981                 reason = TASK_SWITCH_CALL;
1982
1983         if (reason == TASK_SWITCH_GATE) {
1984                 switch (type) {
1985                 case SVM_EXITINTINFO_TYPE_NMI:
1986                         svm->vcpu.arch.nmi_injected = false;
1987                         break;
1988                 case SVM_EXITINTINFO_TYPE_EXEPT:
1989                         kvm_clear_exception_queue(&svm->vcpu);
1990                         break;
1991                 case SVM_EXITINTINFO_TYPE_INTR:
1992                         kvm_clear_interrupt_queue(&svm->vcpu);
1993                         break;
1994                 default:
1995                         break;
1996                 }
1997         }
1998
1999         if (reason != TASK_SWITCH_GATE ||
2000             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2001             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2002              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2003                 skip_emulated_instruction(&svm->vcpu);
2004
2005         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2006 }
2007
2008 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2009 {
2010         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2011         kvm_emulate_cpuid(&svm->vcpu);
2012         return 1;
2013 }
2014
2015 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2016 {
2017         ++svm->vcpu.stat.nmi_window_exits;
2018         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2019         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2020         return 1;
2021 }
2022
2023 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2024 {
2025         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2026                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2027         return 1;
2028 }
2029
2030 static int emulate_on_interception(struct vcpu_svm *svm,
2031                                    struct kvm_run *kvm_run)
2032 {
2033         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
2034                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2035         return 1;
2036 }
2037
2038 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2039 {
2040         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2041         /* instruction emulation calls kvm_set_cr8() */
2042         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
2043         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2044                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2045                 return 1;
2046         }
2047         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2048                 return 1;
2049         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2050         return 0;
2051 }
2052
2053 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2054 {
2055         struct vcpu_svm *svm = to_svm(vcpu);
2056
2057         switch (ecx) {
2058         case MSR_IA32_TSC: {
2059                 u64 tsc;
2060
2061                 rdtscll(tsc);
2062                 *data = svm->vmcb->control.tsc_offset + tsc;
2063                 break;
2064         }
2065         case MSR_K6_STAR:
2066                 *data = svm->vmcb->save.star;
2067                 break;
2068 #ifdef CONFIG_X86_64
2069         case MSR_LSTAR:
2070                 *data = svm->vmcb->save.lstar;
2071                 break;
2072         case MSR_CSTAR:
2073                 *data = svm->vmcb->save.cstar;
2074                 break;
2075         case MSR_KERNEL_GS_BASE:
2076                 *data = svm->vmcb->save.kernel_gs_base;
2077                 break;
2078         case MSR_SYSCALL_MASK:
2079                 *data = svm->vmcb->save.sfmask;
2080                 break;
2081 #endif
2082         case MSR_IA32_SYSENTER_CS:
2083                 *data = svm->vmcb->save.sysenter_cs;
2084                 break;
2085         case MSR_IA32_SYSENTER_EIP:
2086                 *data = svm->sysenter_eip;
2087                 break;
2088         case MSR_IA32_SYSENTER_ESP:
2089                 *data = svm->sysenter_esp;
2090                 break;
2091         /* Nobody will change the following 5 values in the VMCB so
2092            we can safely return them on rdmsr. They will always be 0
2093            until LBRV is implemented. */
2094         case MSR_IA32_DEBUGCTLMSR:
2095                 *data = svm->vmcb->save.dbgctl;
2096                 break;
2097         case MSR_IA32_LASTBRANCHFROMIP:
2098                 *data = svm->vmcb->save.br_from;
2099                 break;
2100         case MSR_IA32_LASTBRANCHTOIP:
2101                 *data = svm->vmcb->save.br_to;
2102                 break;
2103         case MSR_IA32_LASTINTFROMIP:
2104                 *data = svm->vmcb->save.last_excp_from;
2105                 break;
2106         case MSR_IA32_LASTINTTOIP:
2107                 *data = svm->vmcb->save.last_excp_to;
2108                 break;
2109         case MSR_VM_HSAVE_PA:
2110                 *data = svm->nested.hsave_msr;
2111                 break;
2112         case MSR_VM_CR:
2113                 *data = 0;
2114                 break;
2115         case MSR_IA32_UCODE_REV:
2116                 *data = 0x01000065;
2117                 break;
2118         default:
2119                 return kvm_get_msr_common(vcpu, ecx, data);
2120         }
2121         return 0;
2122 }
2123
2124 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2125 {
2126         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2127         u64 data;
2128
2129         if (svm_get_msr(&svm->vcpu, ecx, &data))
2130                 kvm_inject_gp(&svm->vcpu, 0);
2131         else {
2132                 trace_kvm_msr_read(ecx, data);
2133
2134                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2135                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2136                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2137                 skip_emulated_instruction(&svm->vcpu);
2138         }
2139         return 1;
2140 }
2141
2142 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2143 {
2144         struct vcpu_svm *svm = to_svm(vcpu);
2145
2146         switch (ecx) {
2147         case MSR_IA32_TSC: {
2148                 u64 tsc;
2149
2150                 rdtscll(tsc);
2151                 svm->vmcb->control.tsc_offset = data - tsc;
2152                 break;
2153         }
2154         case MSR_K6_STAR:
2155                 svm->vmcb->save.star = data;
2156                 break;
2157 #ifdef CONFIG_X86_64
2158         case MSR_LSTAR:
2159                 svm->vmcb->save.lstar = data;
2160                 break;
2161         case MSR_CSTAR:
2162                 svm->vmcb->save.cstar = data;
2163                 break;
2164         case MSR_KERNEL_GS_BASE:
2165                 svm->vmcb->save.kernel_gs_base = data;
2166                 break;
2167         case MSR_SYSCALL_MASK:
2168                 svm->vmcb->save.sfmask = data;
2169                 break;
2170 #endif
2171         case MSR_IA32_SYSENTER_CS:
2172                 svm->vmcb->save.sysenter_cs = data;
2173                 break;
2174         case MSR_IA32_SYSENTER_EIP:
2175                 svm->sysenter_eip = data;
2176                 svm->vmcb->save.sysenter_eip = data;
2177                 break;
2178         case MSR_IA32_SYSENTER_ESP:
2179                 svm->sysenter_esp = data;
2180                 svm->vmcb->save.sysenter_esp = data;
2181                 break;
2182         case MSR_IA32_DEBUGCTLMSR:
2183                 if (!svm_has(SVM_FEATURE_LBRV)) {
2184                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2185                                         __func__, data);
2186                         break;
2187                 }
2188                 if (data & DEBUGCTL_RESERVED_BITS)
2189                         return 1;
2190
2191                 svm->vmcb->save.dbgctl = data;
2192                 if (data & (1ULL<<0))
2193                         svm_enable_lbrv(svm);
2194                 else
2195                         svm_disable_lbrv(svm);
2196                 break;
2197         case MSR_VM_HSAVE_PA:
2198                 svm->nested.hsave_msr = data;
2199                 break;
2200         case MSR_VM_CR:
2201         case MSR_VM_IGNNE:
2202                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2203                 break;
2204         default:
2205                 return kvm_set_msr_common(vcpu, ecx, data);
2206         }
2207         return 0;
2208 }
2209
2210 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2211 {
2212         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2213         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2214                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2215
2216         trace_kvm_msr_write(ecx, data);
2217
2218         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2219         if (svm_set_msr(&svm->vcpu, ecx, data))
2220                 kvm_inject_gp(&svm->vcpu, 0);
2221         else
2222                 skip_emulated_instruction(&svm->vcpu);
2223         return 1;
2224 }
2225
2226 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2227 {
2228         if (svm->vmcb->control.exit_info_1)
2229                 return wrmsr_interception(svm, kvm_run);
2230         else
2231                 return rdmsr_interception(svm, kvm_run);
2232 }
2233
2234 static int interrupt_window_interception(struct vcpu_svm *svm,
2235                                    struct kvm_run *kvm_run)
2236 {
2237         svm_clear_vintr(svm);
2238         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2239         /*
2240          * If the user space waits to inject interrupts, exit as soon as
2241          * possible
2242          */
2243         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2244             kvm_run->request_interrupt_window &&
2245             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2246                 ++svm->vcpu.stat.irq_window_exits;
2247                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2248                 return 0;
2249         }
2250
2251         return 1;
2252 }
2253
2254 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2255                                       struct kvm_run *kvm_run) = {
2256         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2257         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2258         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2259         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2260         /* for now: */
2261         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2262         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2263         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2264         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2265         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2266         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2267         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2268         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2269         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2270         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2271         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2272         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2273         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2274         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2275         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2276         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2277         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2278         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2279         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2280         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2281         [SVM_EXIT_INTR]                         = intr_interception,
2282         [SVM_EXIT_NMI]                          = nmi_interception,
2283         [SVM_EXIT_SMI]                          = nop_on_interception,
2284         [SVM_EXIT_INIT]                         = nop_on_interception,
2285         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2286         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2287         [SVM_EXIT_CPUID]                        = cpuid_interception,
2288         [SVM_EXIT_IRET]                         = iret_interception,
2289         [SVM_EXIT_INVD]                         = emulate_on_interception,
2290         [SVM_EXIT_HLT]                          = halt_interception,
2291         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2292         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2293         [SVM_EXIT_IOIO]                         = io_interception,
2294         [SVM_EXIT_MSR]                          = msr_interception,
2295         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2296         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2297         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2298         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2299         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2300         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2301         [SVM_EXIT_STGI]                         = stgi_interception,
2302         [SVM_EXIT_CLGI]                         = clgi_interception,
2303         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2304         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2305         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2306         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2307         [SVM_EXIT_NPF]                          = pf_interception,
2308 };
2309
2310 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2311 {
2312         struct vcpu_svm *svm = to_svm(vcpu);
2313         u32 exit_code = svm->vmcb->control.exit_code;
2314
2315         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2316
2317         if (is_nested(svm)) {
2318                 int vmexit;
2319
2320                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2321                             exit_code, svm->vmcb->control.exit_info_1,
2322                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2323
2324                 vmexit = nested_svm_exit_special(svm);
2325
2326                 if (vmexit == NESTED_EXIT_CONTINUE)
2327                         vmexit = nested_svm_exit_handled(svm);
2328
2329                 if (vmexit == NESTED_EXIT_DONE)
2330                         return 1;
2331         }
2332
2333         svm_complete_interrupts(svm);
2334
2335         if (npt_enabled) {
2336                 int mmu_reload = 0;
2337                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2338                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2339                         mmu_reload = 1;
2340                 }
2341                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2342                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2343                 if (mmu_reload) {
2344                         kvm_mmu_reset_context(vcpu);
2345                         kvm_mmu_load(vcpu);
2346                 }
2347         }
2348
2349
2350         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2351                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2352                 kvm_run->fail_entry.hardware_entry_failure_reason
2353                         = svm->vmcb->control.exit_code;
2354                 return 0;
2355         }
2356
2357         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2358             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2359             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2360                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2361                        "exit_code 0x%x\n",
2362                        __func__, svm->vmcb->control.exit_int_info,
2363                        exit_code);
2364
2365         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2366             || !svm_exit_handlers[exit_code]) {
2367                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2368                 kvm_run->hw.hardware_exit_reason = exit_code;
2369                 return 0;
2370         }
2371
2372         return svm_exit_handlers[exit_code](svm, kvm_run);
2373 }
2374
2375 static void reload_tss(struct kvm_vcpu *vcpu)
2376 {
2377         int cpu = raw_smp_processor_id();
2378
2379         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2380         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2381         load_TR_desc();
2382 }
2383
2384 static void pre_svm_run(struct vcpu_svm *svm)
2385 {
2386         int cpu = raw_smp_processor_id();
2387
2388         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2389
2390         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2391         /* FIXME: handle wraparound of asid_generation */
2392         if (svm->asid_generation != sd->asid_generation)
2393                 new_asid(svm, sd);
2394 }
2395
2396 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2397 {
2398         struct vcpu_svm *svm = to_svm(vcpu);
2399
2400         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2401         vcpu->arch.hflags |= HF_NMI_MASK;
2402         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2403         ++vcpu->stat.nmi_injections;
2404 }
2405
2406 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2407 {
2408         struct vmcb_control_area *control;
2409
2410         trace_kvm_inj_virq(irq);
2411
2412         ++svm->vcpu.stat.irq_injections;
2413         control = &svm->vmcb->control;
2414         control->int_vector = irq;
2415         control->int_ctl &= ~V_INTR_PRIO_MASK;
2416         control->int_ctl |= V_IRQ_MASK |
2417                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2418 }
2419
2420 static void svm_set_irq(struct kvm_vcpu *vcpu)
2421 {
2422         struct vcpu_svm *svm = to_svm(vcpu);
2423
2424         BUG_ON(!(gif_set(svm)));
2425
2426         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2427                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2428 }
2429
2430 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2431 {
2432         struct vcpu_svm *svm = to_svm(vcpu);
2433
2434         if (irr == -1)
2435                 return;
2436
2437         if (tpr >= irr)
2438                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2439 }
2440
2441 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2442 {
2443         struct vcpu_svm *svm = to_svm(vcpu);
2444         struct vmcb *vmcb = svm->vmcb;
2445         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2446                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2447 }
2448
2449 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2450 {
2451         struct vcpu_svm *svm = to_svm(vcpu);
2452         struct vmcb *vmcb = svm->vmcb;
2453         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2454                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2455                 gif_set(svm) &&
2456                 !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
2457 }
2458
2459 static void enable_irq_window(struct kvm_vcpu *vcpu)
2460 {
2461         struct vcpu_svm *svm = to_svm(vcpu);
2462         nsvm_printk("Trying to open IRQ window\n");
2463
2464         nested_svm_intr(svm);
2465
2466         /* In case GIF=0 we can't rely on the CPU to tell us when
2467          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2468          * The next time we get that intercept, this function will be
2469          * called again though and we'll get the vintr intercept. */
2470         if (gif_set(svm)) {
2471                 svm_set_vintr(svm);
2472                 svm_inject_irq(svm, 0x0);
2473         }
2474 }
2475
2476 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2477 {
2478         struct vcpu_svm *svm = to_svm(vcpu);
2479
2480         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2481             == HF_NMI_MASK)
2482                 return; /* IRET will cause a vm exit */
2483
2484         /* Something prevents NMI from been injected. Single step over
2485            possible problem (IRET or exception injection or interrupt
2486            shadow) */
2487         vcpu->arch.singlestep = true;
2488         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2489         update_db_intercept(vcpu);
2490 }
2491
2492 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2493 {
2494         return 0;
2495 }
2496
2497 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2498 {
2499         force_new_asid(vcpu);
2500 }
2501
2502 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2503 {
2504 }
2505
2506 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2507 {
2508         struct vcpu_svm *svm = to_svm(vcpu);
2509
2510         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2511                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2512                 kvm_set_cr8(vcpu, cr8);
2513         }
2514 }
2515
2516 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2517 {
2518         struct vcpu_svm *svm = to_svm(vcpu);
2519         u64 cr8;
2520
2521         cr8 = kvm_get_cr8(vcpu);
2522         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2523         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2524 }
2525
2526 static void svm_complete_interrupts(struct vcpu_svm *svm)
2527 {
2528         u8 vector;
2529         int type;
2530         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2531
2532         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2533                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2534
2535         svm->vcpu.arch.nmi_injected = false;
2536         kvm_clear_exception_queue(&svm->vcpu);
2537         kvm_clear_interrupt_queue(&svm->vcpu);
2538
2539         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2540                 return;
2541
2542         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2543         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2544
2545         switch (type) {
2546         case SVM_EXITINTINFO_TYPE_NMI:
2547                 svm->vcpu.arch.nmi_injected = true;
2548                 break;
2549         case SVM_EXITINTINFO_TYPE_EXEPT:
2550                 /* In case of software exception do not reinject an exception
2551                    vector, but re-execute and instruction instead */
2552                 if (is_nested(svm))
2553                         break;
2554                 if (kvm_exception_is_soft(vector))
2555                         break;
2556                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2557                         u32 err = svm->vmcb->control.exit_int_info_err;
2558                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2559
2560                 } else
2561                         kvm_queue_exception(&svm->vcpu, vector);
2562                 break;
2563         case SVM_EXITINTINFO_TYPE_INTR:
2564                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2565                 break;
2566         default:
2567                 break;
2568         }
2569 }
2570
2571 #ifdef CONFIG_X86_64
2572 #define R "r"
2573 #else
2574 #define R "e"
2575 #endif
2576
2577 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2578 {
2579         struct vcpu_svm *svm = to_svm(vcpu);
2580         u16 fs_selector;
2581         u16 gs_selector;
2582         u16 ldt_selector;
2583
2584         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2585         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2586         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2587
2588         pre_svm_run(svm);
2589
2590         sync_lapic_to_cr8(vcpu);
2591
2592         save_host_msrs(vcpu);
2593         fs_selector = kvm_read_fs();
2594         gs_selector = kvm_read_gs();
2595         ldt_selector = kvm_read_ldt();
2596         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2597         /* required for live migration with NPT */
2598         if (npt_enabled)
2599                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2600
2601         clgi();
2602
2603         local_irq_enable();
2604
2605         asm volatile (
2606                 "push %%"R"bp; \n\t"
2607                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2608                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2609                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2610                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2611                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2612                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2613 #ifdef CONFIG_X86_64
2614                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2615                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2616                 "mov %c[r10](%[svm]), %%r10 \n\t"
2617                 "mov %c[r11](%[svm]), %%r11 \n\t"
2618                 "mov %c[r12](%[svm]), %%r12 \n\t"
2619                 "mov %c[r13](%[svm]), %%r13 \n\t"
2620                 "mov %c[r14](%[svm]), %%r14 \n\t"
2621                 "mov %c[r15](%[svm]), %%r15 \n\t"
2622 #endif
2623
2624                 /* Enter guest mode */
2625                 "push %%"R"ax \n\t"
2626                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2627                 __ex(SVM_VMLOAD) "\n\t"
2628                 __ex(SVM_VMRUN) "\n\t"
2629                 __ex(SVM_VMSAVE) "\n\t"
2630                 "pop %%"R"ax \n\t"
2631
2632                 /* Save guest registers, load host registers */
2633                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2634                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2635                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2636                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2637                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2638                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2639 #ifdef CONFIG_X86_64
2640                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2641                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2642                 "mov %%r10, %c[r10](%[svm]) \n\t"
2643                 "mov %%r11, %c[r11](%[svm]) \n\t"
2644                 "mov %%r12, %c[r12](%[svm]) \n\t"
2645                 "mov %%r13, %c[r13](%[svm]) \n\t"
2646                 "mov %%r14, %c[r14](%[svm]) \n\t"
2647                 "mov %%r15, %c[r15](%[svm]) \n\t"
2648 #endif
2649                 "pop %%"R"bp"
2650                 :
2651                 : [svm]"a"(svm),
2652                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2653                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2654                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2655                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2656                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2657                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2658                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2659 #ifdef CONFIG_X86_64
2660                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2661                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2662                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2663                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2664                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2665                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2666                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2667                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2668 #endif
2669                 : "cc", "memory"
2670                 , R"bx", R"cx", R"dx", R"si", R"di"
2671 #ifdef CONFIG_X86_64
2672                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2673 #endif
2674                 );
2675
2676         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2677         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2678         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2679         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2680
2681         kvm_load_fs(fs_selector);
2682         kvm_load_gs(gs_selector);
2683         kvm_load_ldt(ldt_selector);
2684         load_host_msrs(vcpu);
2685
2686         reload_tss(vcpu);
2687
2688         local_irq_disable();
2689
2690         stgi();
2691
2692         sync_cr8_to_lapic(vcpu);
2693
2694         svm->next_rip = 0;
2695
2696         if (npt_enabled) {
2697                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2698                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2699         }
2700 }
2701
2702 #undef R
2703
2704 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2705 {
2706         struct vcpu_svm *svm = to_svm(vcpu);
2707
2708         if (npt_enabled) {
2709                 svm->vmcb->control.nested_cr3 = root;
2710                 force_new_asid(vcpu);
2711                 return;
2712         }
2713
2714         svm->vmcb->save.cr3 = root;
2715         force_new_asid(vcpu);
2716
2717         if (vcpu->fpu_active) {
2718                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2719                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2720                 vcpu->fpu_active = 0;
2721         }
2722 }
2723
2724 static int is_disabled(void)
2725 {
2726         u64 vm_cr;
2727
2728         rdmsrl(MSR_VM_CR, vm_cr);
2729         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2730                 return 1;
2731
2732         return 0;
2733 }
2734
2735 static void
2736 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2737 {
2738         /*
2739          * Patch in the VMMCALL instruction:
2740          */
2741         hypercall[0] = 0x0f;
2742         hypercall[1] = 0x01;
2743         hypercall[2] = 0xd9;
2744 }
2745
2746 static void svm_check_processor_compat(void *rtn)
2747 {
2748         *(int *)rtn = 0;
2749 }
2750
2751 static bool svm_cpu_has_accelerated_tpr(void)
2752 {
2753         return false;
2754 }
2755
2756 static int get_npt_level(void)
2757 {
2758 #ifdef CONFIG_X86_64
2759         return PT64_ROOT_LEVEL;
2760 #else
2761         return PT32E_ROOT_LEVEL;
2762 #endif
2763 }
2764
2765 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2766 {
2767         return 0;
2768 }
2769
2770 static const struct trace_print_flags svm_exit_reasons_str[] = {
2771         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2772         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2773         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2774         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2775         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2776         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2777         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2778         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2779         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2780         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2781         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2782         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2783         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2784         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2785         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2786         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2787         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2788         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2789         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2790         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2791         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2792         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2793         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2794         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2795         { SVM_EXIT_INTR,                        "interrupt" },
2796         { SVM_EXIT_NMI,                         "nmi" },
2797         { SVM_EXIT_SMI,                         "smi" },
2798         { SVM_EXIT_INIT,                        "init" },
2799         { SVM_EXIT_VINTR,                       "vintr" },
2800         { SVM_EXIT_CPUID,                       "cpuid" },
2801         { SVM_EXIT_INVD,                        "invd" },
2802         { SVM_EXIT_HLT,                         "hlt" },
2803         { SVM_EXIT_INVLPG,                      "invlpg" },
2804         { SVM_EXIT_INVLPGA,                     "invlpga" },
2805         { SVM_EXIT_IOIO,                        "io" },
2806         { SVM_EXIT_MSR,                         "msr" },
2807         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2808         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2809         { SVM_EXIT_VMRUN,                       "vmrun" },
2810         { SVM_EXIT_VMMCALL,                     "hypercall" },
2811         { SVM_EXIT_VMLOAD,                      "vmload" },
2812         { SVM_EXIT_VMSAVE,                      "vmsave" },
2813         { SVM_EXIT_STGI,                        "stgi" },
2814         { SVM_EXIT_CLGI,                        "clgi" },
2815         { SVM_EXIT_SKINIT,                      "skinit" },
2816         { SVM_EXIT_WBINVD,                      "wbinvd" },
2817         { SVM_EXIT_MONITOR,                     "monitor" },
2818         { SVM_EXIT_MWAIT,                       "mwait" },
2819         { SVM_EXIT_NPF,                         "npf" },
2820         { -1, NULL }
2821 };
2822
2823 static bool svm_gb_page_enable(void)
2824 {
2825         return true;
2826 }
2827
2828 static struct kvm_x86_ops svm_x86_ops = {
2829         .cpu_has_kvm_support = has_svm,
2830         .disabled_by_bios = is_disabled,
2831         .hardware_setup = svm_hardware_setup,
2832         .hardware_unsetup = svm_hardware_unsetup,
2833         .check_processor_compatibility = svm_check_processor_compat,
2834         .hardware_enable = svm_hardware_enable,
2835         .hardware_disable = svm_hardware_disable,
2836         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2837
2838         .vcpu_create = svm_create_vcpu,
2839         .vcpu_free = svm_free_vcpu,
2840         .vcpu_reset = svm_vcpu_reset,
2841
2842         .prepare_guest_switch = svm_prepare_guest_switch,
2843         .vcpu_load = svm_vcpu_load,
2844         .vcpu_put = svm_vcpu_put,
2845
2846         .set_guest_debug = svm_guest_debug,
2847         .get_msr = svm_get_msr,
2848         .set_msr = svm_set_msr,
2849         .get_segment_base = svm_get_segment_base,
2850         .get_segment = svm_get_segment,
2851         .set_segment = svm_set_segment,
2852         .get_cpl = svm_get_cpl,
2853         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2854         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2855         .set_cr0 = svm_set_cr0,
2856         .set_cr3 = svm_set_cr3,
2857         .set_cr4 = svm_set_cr4,
2858         .set_efer = svm_set_efer,
2859         .get_idt = svm_get_idt,
2860         .set_idt = svm_set_idt,
2861         .get_gdt = svm_get_gdt,
2862         .set_gdt = svm_set_gdt,
2863         .get_dr = svm_get_dr,
2864         .set_dr = svm_set_dr,
2865         .cache_reg = svm_cache_reg,
2866         .get_rflags = svm_get_rflags,
2867         .set_rflags = svm_set_rflags,
2868
2869         .tlb_flush = svm_flush_tlb,
2870
2871         .run = svm_vcpu_run,
2872         .handle_exit = handle_exit,
2873         .skip_emulated_instruction = skip_emulated_instruction,
2874         .set_interrupt_shadow = svm_set_interrupt_shadow,
2875         .get_interrupt_shadow = svm_get_interrupt_shadow,
2876         .patch_hypercall = svm_patch_hypercall,
2877         .set_irq = svm_set_irq,
2878         .set_nmi = svm_inject_nmi,
2879         .queue_exception = svm_queue_exception,
2880         .interrupt_allowed = svm_interrupt_allowed,
2881         .nmi_allowed = svm_nmi_allowed,
2882         .enable_nmi_window = enable_nmi_window,
2883         .enable_irq_window = enable_irq_window,
2884         .update_cr8_intercept = update_cr8_intercept,
2885
2886         .set_tss_addr = svm_set_tss_addr,
2887         .get_tdp_level = get_npt_level,
2888         .get_mt_mask = svm_get_mt_mask,
2889
2890         .exit_reasons_str = svm_exit_reasons_str,
2891         .gb_page_enable = svm_gb_page_enable,
2892 };
2893
2894 static int __init svm_init(void)
2895 {
2896         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2897                               THIS_MODULE);
2898 }
2899
2900 static void __exit svm_exit(void)
2901 {
2902         kvm_exit();
2903 }
2904
2905 module_init(svm_init)
2906 module_exit(svm_exit)