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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 #define IOPM_ALLOC_ORDER 2
  40 #define MSRPM_ALLOC_ORDER 1
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* Turn on to get debugging output*/
  52 /* #define NESTED_DEBUG */
  53
  54 #ifdef NESTED_DEBUG
  55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  56 #else
  57 #define nsvm_printk(fmt, args...) do {} while(0)
  58 #endif
  59
  60 /* enable NPT for AMD64 and X86 with PAE */
  61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  62 static bool npt_enabled = true;
  63 #else
  64 static bool npt_enabled = false;
  65 #endif
  66 static int npt = 1;
  67
  68 module_param(npt, int, S_IRUGO);
  69
  70 static int nested = 0;
  71 module_param(nested, int, S_IRUGO);
  72
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline void clgi(void)
 136 {
 137         asm volatile (__ex(SVM_CLGI));
 138 }
 139
 140 static inline void stgi(void)
 141 {
 142         asm volatile (__ex(SVM_STGI));
 143 }
 144
 145 static inline void invlpga(unsigned long addr, u32 asid)
 146 {
 147         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 148 }
 149
 150 static inline unsigned long kvm_read_cr2(void)
 151 {
 152         unsigned long cr2;
 153
 154         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 155         return cr2;
 156 }
 157
 158 static inline void kvm_write_cr2(unsigned long val)
 159 {
 160         asm volatile ("mov %0, %%cr2" :: "r" (val));
 161 }
 162
 163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 164 {
 165         to_svm(vcpu)->asid_generation--;
 166 }
 167
 168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 169 {
 170         force_new_asid(vcpu);
 171 }
 172
 173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 174 {
 175         if (!npt_enabled && !(efer & EFER_LMA))
 176                 efer &= ~EFER_LME;
 177
 178         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 179         vcpu->arch.shadow_efer = efer;
 180 }
 181
 182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 183                                 bool has_error_code, u32 error_code)
 184 {
 185         struct vcpu_svm *svm = to_svm(vcpu);
 186
 187         /* If we are within a nested VM we'd better #VMEXIT and let the
 188            guest handle the exception */
 189         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 190                 return;
 191
 192         svm->vmcb->control.event_inj = nr
 193                 | SVM_EVTINJ_VALID
 194                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 195                 | SVM_EVTINJ_TYPE_EXEPT;
 196         svm->vmcb->control.event_inj_err = error_code;
 197 }
 198
 199 static int is_external_interrupt(u32 info)
 200 {
 201         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 202         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 203 }
 204
 205 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 206 {
 207         struct vcpu_svm *svm = to_svm(vcpu);
 208
 209         if (!svm->next_rip) {
 210                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 211                 return;
 212         }
 213         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 214                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 215                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 216
 217         kvm_rip_write(vcpu, svm->next_rip);
 218         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 219
 220         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 221 }
 222
 223 static int has_svm(void)
 224 {
 225         const char *msg;
 226
 227         if (!cpu_has_svm(&msg)) {
 228                 printk(KERN_INFO "has_svm: %s\n", msg);
 229                 return 0;
 230         }
 231
 232         return 1;
 233 }
 234
 235 static void svm_hardware_disable(void *garbage)
 236 {
 237         cpu_svm_disable();
 238 }
 239
 240 static void svm_hardware_enable(void *garbage)
 241 {
 242
 243         struct svm_cpu_data *svm_data;
 244         uint64_t efer;
 245         struct desc_ptr gdt_descr;
 246         struct desc_struct *gdt;
 247         int me = raw_smp_processor_id();
 248
 249         if (!has_svm()) {
 250                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 251                 return;
 252         }
 253         svm_data = per_cpu(svm_data, me);
 254
 255         if (!svm_data) {
 256                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 257                        me);
 258                 return;
 259         }
 260
 261         svm_data->asid_generation = 1;
 262         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 263         svm_data->next_asid = svm_data->max_asid + 1;
 264
 265         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 266         gdt = (struct desc_struct *)gdt_descr.address;
 267         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 268
 269         rdmsrl(MSR_EFER, efer);
 270         wrmsrl(MSR_EFER, efer | EFER_SVME);
 271
 272         wrmsrl(MSR_VM_HSAVE_PA,
 273                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 274 }
 275
 276 static void svm_cpu_uninit(int cpu)
 277 {
 278         struct svm_cpu_data *svm_data
 279                 = per_cpu(svm_data, raw_smp_processor_id());
 280
 281         if (!svm_data)
 282                 return;
 283
 284         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 285         __free_page(svm_data->save_area);
 286         kfree(svm_data);
 287 }
 288
 289 static int svm_cpu_init(int cpu)
 290 {
 291         struct svm_cpu_data *svm_data;
 292         int r;
 293
 294         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 295         if (!svm_data)
 296                 return -ENOMEM;
 297         svm_data->cpu = cpu;
 298         svm_data->save_area = alloc_page(GFP_KERNEL);
 299         r = -ENOMEM;
 300         if (!svm_data->save_area)
 301                 goto err_1;
 302
 303         per_cpu(svm_data, cpu) = svm_data;
 304
 305         return 0;
 306
 307 err_1:
 308         kfree(svm_data);
 309         return r;
 310
 311 }
 312
 313 static void set_msr_interception(u32 *msrpm, unsigned msr,
 314                                  int read, int write)
 315 {
 316         int i;
 317
 318         for (i = 0; i < NUM_MSR_MAPS; i++) {
 319                 if (msr >= msrpm_ranges[i] &&
 320                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 321                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 322                                           msrpm_ranges[i]) * 2;
 323
 324                         u32 *base = msrpm + (msr_offset / 32);
 325                         u32 msr_shift = msr_offset % 32;
 326                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 327                         *base = (*base & ~(0x3 << msr_shift)) |
 328                                 (mask << msr_shift);
 329                         return;
 330                 }
 331         }
 332         BUG();
 333 }
 334
 335 static void svm_vcpu_init_msrpm(u32 *msrpm)
 336 {
 337         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 338
 339 #ifdef CONFIG_X86_64
 340         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 341         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 342         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 343         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 344         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 345         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 346 #endif
 347         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 348         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 349         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 350         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 351 }
 352
 353 static void svm_enable_lbrv(struct vcpu_svm *svm)
 354 {
 355         u32 *msrpm = svm->msrpm;
 356
 357         svm->vmcb->control.lbr_ctl = 1;
 358         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 359         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 360         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 361         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 362 }
 363
 364 static void svm_disable_lbrv(struct vcpu_svm *svm)
 365 {
 366         u32 *msrpm = svm->msrpm;
 367
 368         svm->vmcb->control.lbr_ctl = 0;
 369         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 370         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 371         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 372         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 373 }
 374
 375 static __init int svm_hardware_setup(void)
 376 {
 377         int cpu;
 378         struct page *iopm_pages;
 379         void *iopm_va;
 380         int r;
 381
 382         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 383
 384         if (!iopm_pages)
 385                 return -ENOMEM;
 386
 387         iopm_va = page_address(iopm_pages);
 388         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 389         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 390
 391         if (boot_cpu_has(X86_FEATURE_NX))
 392                 kvm_enable_efer_bits(EFER_NX);
 393
 394         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 395                 kvm_enable_efer_bits(EFER_FFXSR);
 396
 397         if (nested) {
 398                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 399                 kvm_enable_efer_bits(EFER_SVME);
 400         }
 401
 402         for_each_online_cpu(cpu) {
 403                 r = svm_cpu_init(cpu);
 404                 if (r)
 405                         goto err;
 406         }
 407
 408         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 409
 410         if (!svm_has(SVM_FEATURE_NPT))
 411                 npt_enabled = false;
 412
 413         if (npt_enabled && !npt) {
 414                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 415                 npt_enabled = false;
 416         }
 417
 418         if (npt_enabled) {
 419                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 420                 kvm_enable_tdp();
 421         } else
 422                 kvm_disable_tdp();
 423
 424         return 0;
 425
 426 err:
 427         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 428         iopm_base = 0;
 429         return r;
 430 }
 431
 432 static __exit void svm_hardware_unsetup(void)
 433 {
 434         int cpu;
 435
 436         for_each_online_cpu(cpu)
 437                 svm_cpu_uninit(cpu);
 438
 439         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 440         iopm_base = 0;
 441 }
 442
 443 static void init_seg(struct vmcb_seg *seg)
 444 {
 445         seg->selector = 0;
 446         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 447                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 448         seg->limit = 0xffff;
 449         seg->base = 0;
 450 }
 451
 452 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 453 {
 454         seg->selector = 0;
 455         seg->attrib = SVM_SELECTOR_P_MASK | type;
 456         seg->limit = 0xffff;
 457         seg->base = 0;
 458 }
 459
 460 static void init_vmcb(struct vcpu_svm *svm)
 461 {
 462         struct vmcb_control_area *control = &svm->vmcb->control;
 463         struct vmcb_save_area *save = &svm->vmcb->save;
 464
 465         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 466                                         INTERCEPT_CR3_MASK |
 467                                         INTERCEPT_CR4_MASK;
 468
 469         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 470                                         INTERCEPT_CR3_MASK |
 471                                         INTERCEPT_CR4_MASK |
 472                                         INTERCEPT_CR8_MASK;
 473
 474         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 475                                         INTERCEPT_DR1_MASK |
 476                                         INTERCEPT_DR2_MASK |
 477                                         INTERCEPT_DR3_MASK;
 478
 479         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 480                                         INTERCEPT_DR1_MASK |
 481                                         INTERCEPT_DR2_MASK |
 482                                         INTERCEPT_DR3_MASK |
 483                                         INTERCEPT_DR5_MASK |
 484                                         INTERCEPT_DR7_MASK;
 485
 486         control->intercept_exceptions = (1 << PF_VECTOR) |
 487                                         (1 << UD_VECTOR) |
 488                                         (1 << MC_VECTOR);
 489
 490
 491         control->intercept =    (1ULL << INTERCEPT_INTR) |
 492                                 (1ULL << INTERCEPT_NMI) |
 493                                 (1ULL << INTERCEPT_SMI) |
 494                                 (1ULL << INTERCEPT_CPUID) |
 495                                 (1ULL << INTERCEPT_INVD) |
 496                                 (1ULL << INTERCEPT_HLT) |
 497                                 (1ULL << INTERCEPT_INVLPG) |
 498                                 (1ULL << INTERCEPT_INVLPGA) |
 499                                 (1ULL << INTERCEPT_IOIO_PROT) |
 500                                 (1ULL << INTERCEPT_MSR_PROT) |
 501                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 502                                 (1ULL << INTERCEPT_SHUTDOWN) |
 503                                 (1ULL << INTERCEPT_VMRUN) |
 504                                 (1ULL << INTERCEPT_VMMCALL) |
 505                                 (1ULL << INTERCEPT_VMLOAD) |
 506                                 (1ULL << INTERCEPT_VMSAVE) |
 507                                 (1ULL << INTERCEPT_STGI) |
 508                                 (1ULL << INTERCEPT_CLGI) |
 509                                 (1ULL << INTERCEPT_SKINIT) |
 510                                 (1ULL << INTERCEPT_WBINVD) |
 511                                 (1ULL << INTERCEPT_MONITOR) |
 512                                 (1ULL << INTERCEPT_MWAIT);
 513
 514         control->iopm_base_pa = iopm_base;
 515         control->msrpm_base_pa = __pa(svm->msrpm);
 516         control->tsc_offset = 0;
 517         control->int_ctl = V_INTR_MASKING_MASK;
 518
 519         init_seg(&save->es);
 520         init_seg(&save->ss);
 521         init_seg(&save->ds);
 522         init_seg(&save->fs);
 523         init_seg(&save->gs);
 524
 525         save->cs.selector = 0xf000;
 526         /* Executable/Readable Code Segment */
 527         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 528                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 529         save->cs.limit = 0xffff;
 530         /*
 531          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 532          * be consistent with it.
 533          *
 534          * Replace when we have real mode working for vmx.
 535          */
 536         save->cs.base = 0xf0000;
 537
 538         save->gdtr.limit = 0xffff;
 539         save->idtr.limit = 0xffff;
 540
 541         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 542         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 543
 544         save->efer = EFER_SVME;
 545         save->dr6 = 0xffff0ff0;
 546         save->dr7 = 0x400;
 547         save->rflags = 2;
 548         save->rip = 0x0000fff0;
 549         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 550
 551         /*
 552          * cr0 val on cpu init should be 0x60000010, we enable cpu
 553          * cache by default. the orderly way is to enable cache in bios.
 554          */
 555         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 556         save->cr4 = X86_CR4_PAE;
 557         /* rdx = ?? */
 558
 559         if (npt_enabled) {
 560                 /* Setup VMCB for Nested Paging */
 561                 control->nested_ctl = 1;
 562                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 563                                         (1ULL << INTERCEPT_INVLPG));
 564                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 565                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 566                                                 INTERCEPT_CR3_MASK);
 567                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 568                                                  INTERCEPT_CR3_MASK);
 569                 save->g_pat = 0x0007040600070406ULL;
 570                 /* enable caching because the QEMU Bios doesn't enable it */
 571                 save->cr0 = X86_CR0_ET;
 572                 save->cr3 = 0;
 573                 save->cr4 = 0;
 574         }
 575         force_new_asid(&svm->vcpu);
 576
 577         svm->nested_vmcb = 0;
 578         svm->vcpu.arch.hflags = HF_GIF_MASK;
 579 }
 580
 581 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 582 {
 583         struct vcpu_svm *svm = to_svm(vcpu);
 584
 585         init_vmcb(svm);
 586
 587         if (vcpu->vcpu_id != 0) {
 588                 kvm_rip_write(vcpu, 0);
 589                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 590                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 591         }
 592         vcpu->arch.regs_avail = ~0;
 593         vcpu->arch.regs_dirty = ~0;
 594
 595         return 0;
 596 }
 597
 598 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 599 {
 600         struct vcpu_svm *svm;
 601         struct page *page;
 602         struct page *msrpm_pages;
 603         struct page *hsave_page;
 604         struct page *nested_msrpm_pages;
 605         int err;
 606
 607         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 608         if (!svm) {
 609                 err = -ENOMEM;
 610                 goto out;
 611         }
 612
 613         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 614         if (err)
 615                 goto free_svm;
 616
 617         page = alloc_page(GFP_KERNEL);
 618         if (!page) {
 619                 err = -ENOMEM;
 620                 goto uninit;
 621         }
 622
 623         err = -ENOMEM;
 624         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 625         if (!msrpm_pages)
 626                 goto uninit;
 627
 628         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 629         if (!nested_msrpm_pages)
 630                 goto uninit;
 631
 632         svm->msrpm = page_address(msrpm_pages);
 633         svm_vcpu_init_msrpm(svm->msrpm);
 634
 635         hsave_page = alloc_page(GFP_KERNEL);
 636         if (!hsave_page)
 637                 goto uninit;
 638         svm->hsave = page_address(hsave_page);
 639
 640         svm->nested_msrpm = page_address(nested_msrpm_pages);
 641
 642         svm->vmcb = page_address(page);
 643         clear_page(svm->vmcb);
 644         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 645         svm->asid_generation = 0;
 646         init_vmcb(svm);
 647
 648         fx_init(&svm->vcpu);
 649         svm->vcpu.fpu_active = 1;
 650         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 651         if (svm->vcpu.vcpu_id == 0)
 652                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 653
 654         return &svm->vcpu;
 655
 656 uninit:
 657         kvm_vcpu_uninit(&svm->vcpu);
 658 free_svm:
 659         kmem_cache_free(kvm_vcpu_cache, svm);
 660 out:
 661         return ERR_PTR(err);
 662 }
 663
 664 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 665 {
 666         struct vcpu_svm *svm = to_svm(vcpu);
 667
 668         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 669         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 670         __free_page(virt_to_page(svm->hsave));
 671         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 672         kvm_vcpu_uninit(vcpu);
 673         kmem_cache_free(kvm_vcpu_cache, svm);
 674 }
 675
 676 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 677 {
 678         struct vcpu_svm *svm = to_svm(vcpu);
 679         int i;
 680
 681         if (unlikely(cpu != vcpu->cpu)) {
 682                 u64 tsc_this, delta;
 683
 684                 /*
 685                  * Make sure that the guest sees a monotonically
 686                  * increasing TSC.
 687                  */
 688                 rdtscll(tsc_this);
 689                 delta = vcpu->arch.host_tsc - tsc_this;
 690                 svm->vmcb->control.tsc_offset += delta;
 691                 vcpu->cpu = cpu;
 692                 kvm_migrate_timers(vcpu);
 693         }
 694
 695         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 696                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 697 }
 698
 699 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 700 {
 701         struct vcpu_svm *svm = to_svm(vcpu);
 702         int i;
 703
 704         ++vcpu->stat.host_state_reload;
 705         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 706                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 707
 708         rdtscll(vcpu->arch.host_tsc);
 709 }
 710
 711 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 712 {
 713         return to_svm(vcpu)->vmcb->save.rflags;
 714 }
 715
 716 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 717 {
 718         to_svm(vcpu)->vmcb->save.rflags = rflags;
 719 }
 720
 721 static void svm_set_vintr(struct vcpu_svm *svm)
 722 {
 723         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 724 }
 725
 726 static void svm_clear_vintr(struct vcpu_svm *svm)
 727 {
 728         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 729 }
 730
 731 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 732 {
 733         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 734
 735         switch (seg) {
 736         case VCPU_SREG_CS: return &save->cs;
 737         case VCPU_SREG_DS: return &save->ds;
 738         case VCPU_SREG_ES: return &save->es;
 739         case VCPU_SREG_FS: return &save->fs;
 740         case VCPU_SREG_GS: return &save->gs;
 741         case VCPU_SREG_SS: return &save->ss;
 742         case VCPU_SREG_TR: return &save->tr;
 743         case VCPU_SREG_LDTR: return &save->ldtr;
 744         }
 745         BUG();
 746         return NULL;
 747 }
 748
 749 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 750 {
 751         struct vmcb_seg *s = svm_seg(vcpu, seg);
 752
 753         return s->base;
 754 }
 755
 756 static void svm_get_segment(struct kvm_vcpu *vcpu,
 757                             struct kvm_segment *var, int seg)
 758 {
 759         struct vmcb_seg *s = svm_seg(vcpu, seg);
 760
 761         var->base = s->base;
 762         var->limit = s->limit;
 763         var->selector = s->selector;
 764         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 765         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 766         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 767         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 768         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 769         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 770         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 771         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 772
 773         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 774          * for cross vendor migration purposes by "not present"
 775          */
 776         var->unusable = !var->present || (var->type == 0);
 777
 778         switch (seg) {
 779         case VCPU_SREG_CS:
 780                 /*
 781                  * SVM always stores 0 for the 'G' bit in the CS selector in
 782                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 783                  * Intel's VMENTRY has a check on the 'G' bit.
 784                  */
 785                 var->g = s->limit > 0xfffff;
 786                 break;
 787         case VCPU_SREG_TR:
 788                 /*
 789                  * Work around a bug where the busy flag in the tr selector
 790                  * isn't exposed
 791                  */
 792                 var->type |= 0x2;
 793                 break;
 794         case VCPU_SREG_DS:
 795         case VCPU_SREG_ES:
 796         case VCPU_SREG_FS:
 797         case VCPU_SREG_GS:
 798                 /*
 799                  * The accessed bit must always be set in the segment
 800                  * descriptor cache, although it can be cleared in the
 801                  * descriptor, the cached bit always remains at 1. Since
 802                  * Intel has a check on this, set it here to support
 803                  * cross-vendor migration.
 804                  */
 805                 if (!var->unusable)
 806                         var->type |= 0x1;
 807                 break;
 808         }
 809 }
 810
 811 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 812 {
 813         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 814
 815         return save->cpl;
 816 }
 817
 818 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 819 {
 820         struct vcpu_svm *svm = to_svm(vcpu);
 821
 822         dt->limit = svm->vmcb->save.idtr.limit;
 823         dt->base = svm->vmcb->save.idtr.base;
 824 }
 825
 826 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 827 {
 828         struct vcpu_svm *svm = to_svm(vcpu);
 829
 830         svm->vmcb->save.idtr.limit = dt->limit;
 831         svm->vmcb->save.idtr.base = dt->base ;
 832 }
 833
 834 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 835 {
 836         struct vcpu_svm *svm = to_svm(vcpu);
 837
 838         dt->limit = svm->vmcb->save.gdtr.limit;
 839         dt->base = svm->vmcb->save.gdtr.base;
 840 }
 841
 842 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 843 {
 844         struct vcpu_svm *svm = to_svm(vcpu);
 845
 846         svm->vmcb->save.gdtr.limit = dt->limit;
 847         svm->vmcb->save.gdtr.base = dt->base ;
 848 }
 849
 850 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 851 {
 852 }
 853
 854 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 855 {
 856         struct vcpu_svm *svm = to_svm(vcpu);
 857
 858 #ifdef CONFIG_X86_64
 859         if (vcpu->arch.shadow_efer & EFER_LME) {
 860                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 861                         vcpu->arch.shadow_efer |= EFER_LMA;
 862                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 863                 }
 864
 865                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 866                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 867                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 868                 }
 869         }
 870 #endif
 871         if (npt_enabled)
 872                 goto set;
 873
 874         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 875                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 876                 vcpu->fpu_active = 1;
 877         }
 878
 879         vcpu->arch.cr0 = cr0;
 880         cr0 |= X86_CR0_PG | X86_CR0_WP;
 881         if (!vcpu->fpu_active) {
 882                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 883                 cr0 |= X86_CR0_TS;
 884         }
 885 set:
 886         /*
 887          * re-enable caching here because the QEMU bios
 888          * does not do it - this results in some delay at
 889          * reboot
 890          */
 891         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 892         svm->vmcb->save.cr0 = cr0;
 893 }
 894
 895 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 896 {
 897         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 898         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 899
 900         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 901                 force_new_asid(vcpu);
 902
 903         vcpu->arch.cr4 = cr4;
 904         if (!npt_enabled)
 905                 cr4 |= X86_CR4_PAE;
 906         cr4 |= host_cr4_mce;
 907         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 908 }
 909
 910 static void svm_set_segment(struct kvm_vcpu *vcpu,
 911                             struct kvm_segment *var, int seg)
 912 {
 913         struct vcpu_svm *svm = to_svm(vcpu);
 914         struct vmcb_seg *s = svm_seg(vcpu, seg);
 915
 916         s->base = var->base;
 917         s->limit = var->limit;
 918         s->selector = var->selector;
 919         if (var->unusable)
 920                 s->attrib = 0;
 921         else {
 922                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 923                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 924                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 925                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 926                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 927                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 928                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 929                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 930         }
 931         if (seg == VCPU_SREG_CS)
 932                 svm->vmcb->save.cpl
 933                         = (svm->vmcb->save.cs.attrib
 934                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 935
 936 }
 937
 938 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 939 {
 940         int old_debug = vcpu->guest_debug;
 941         struct vcpu_svm *svm = to_svm(vcpu);
 942
 943         vcpu->guest_debug = dbg->control;
 944
 945         svm->vmcb->control.intercept_exceptions &=
 946                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 947         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 948                 if (vcpu->guest_debug &
 949                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 950                         svm->vmcb->control.intercept_exceptions |=
 951                                 1 << DB_VECTOR;
 952                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 953                         svm->vmcb->control.intercept_exceptions |=
 954                                 1 << BP_VECTOR;
 955         } else
 956                 vcpu->guest_debug = 0;
 957
 958         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 959                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
 960         else
 961                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
 962
 963         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
 964                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
 965         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
 966                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 967
 968         return 0;
 969 }
 970
 971 static int svm_get_irq(struct kvm_vcpu *vcpu)
 972 {
 973         if (!vcpu->arch.interrupt.pending)
 974                 return -1;
 975         return vcpu->arch.interrupt.nr;
 976 }
 977
 978 static void load_host_msrs(struct kvm_vcpu *vcpu)
 979 {
 980 #ifdef CONFIG_X86_64
 981         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 982 #endif
 983 }
 984
 985 static void save_host_msrs(struct kvm_vcpu *vcpu)
 986 {
 987 #ifdef CONFIG_X86_64
 988         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 989 #endif
 990 }
 991
 992 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 993 {
 994         if (svm_data->next_asid > svm_data->max_asid) {
 995                 ++svm_data->asid_generation;
 996                 svm_data->next_asid = 1;
 997                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 998         }
 999
1000         svm->vcpu.cpu = svm_data->cpu;
1001         svm->asid_generation = svm_data->asid_generation;
1002         svm->vmcb->control.asid = svm_data->next_asid++;
1003 }
1004
1005 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1006 {
1007         struct vcpu_svm *svm = to_svm(vcpu);
1008         unsigned long val;
1009
1010         switch (dr) {
1011         case 0 ... 3:
1012                 val = vcpu->arch.db[dr];
1013                 break;
1014         case 6:
1015                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1016                         val = vcpu->arch.dr6;
1017                 else
1018                         val = svm->vmcb->save.dr6;
1019                 break;
1020         case 7:
1021                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022                         val = vcpu->arch.dr7;
1023                 else
1024                         val = svm->vmcb->save.dr7;
1025                 break;
1026         default:
1027                 val = 0;
1028         }
1029
1030         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1031         return val;
1032 }
1033
1034 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1035                        int *exception)
1036 {
1037         struct vcpu_svm *svm = to_svm(vcpu);
1038
1039         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1040
1041         *exception = 0;
1042
1043         switch (dr) {
1044         case 0 ... 3:
1045                 vcpu->arch.db[dr] = value;
1046                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1047                         vcpu->arch.eff_db[dr] = value;
1048                 return;
1049         case 4 ... 5:
1050                 if (vcpu->arch.cr4 & X86_CR4_DE)
1051                         *exception = UD_VECTOR;
1052                 return;
1053         case 6:
1054                 if (value & 0xffffffff00000000ULL) {
1055                         *exception = GP_VECTOR;
1056                         return;
1057                 }
1058                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1059                 return;
1060         case 7:
1061                 if (value & 0xffffffff00000000ULL) {
1062                         *exception = GP_VECTOR;
1063                         return;
1064                 }
1065                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1066                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1067                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1068                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1069                 }
1070                 return;
1071         default:
1072                 /* FIXME: Possible case? */
1073                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1074                        __func__, dr);
1075                 *exception = UD_VECTOR;
1076                 return;
1077         }
1078 }
1079
1080 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1081 {
1082         u64 fault_address;
1083         u32 error_code;
1084
1085         fault_address  = svm->vmcb->control.exit_info_2;
1086         error_code = svm->vmcb->control.exit_info_1;
1087
1088         if (!npt_enabled)
1089                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1090                             (u32)fault_address, (u32)(fault_address >> 32),
1091                             handler);
1092         else
1093                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1094                             (u32)fault_address, (u32)(fault_address >> 32),
1095                             handler);
1096         /*
1097          * FIXME: Tis shouldn't be necessary here, but there is a flush
1098          * missing in the MMU code. Until we find this bug, flush the
1099          * complete TLB here on an NPF
1100          */
1101         if (npt_enabled)
1102                 svm_flush_tlb(&svm->vcpu);
1103         else {
1104                 if (svm->vcpu.arch.interrupt.pending ||
1105                                 svm->vcpu.arch.exception.pending)
1106                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1107         }
1108         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1109 }
1110
1111 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1112 {
1113         if (!(svm->vcpu.guest_debug &
1114               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1115                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1116                 return 1;
1117         }
1118         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1119         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1120         kvm_run->debug.arch.exception = DB_VECTOR;
1121         return 0;
1122 }
1123
1124 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1125 {
1126         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1127         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1128         kvm_run->debug.arch.exception = BP_VECTOR;
1129         return 0;
1130 }
1131
1132 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1133 {
1134         int er;
1135
1136         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1137         if (er != EMULATE_DONE)
1138                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1139         return 1;
1140 }
1141
1142 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1143 {
1144         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1145         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1146                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1147         svm->vcpu.fpu_active = 1;
1148
1149         return 1;
1150 }
1151
1152 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1153 {
1154         /*
1155          * On an #MC intercept the MCE handler is not called automatically in
1156          * the host. So do it by hand here.
1157          */
1158         asm volatile (
1159                 "int $0x12\n");
1160         /* not sure if we ever come back to this point */
1161
1162         return 1;
1163 }
1164
1165 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166 {
1167         /*
1168          * VMCB is undefined after a SHUTDOWN intercept
1169          * so reinitialize it.
1170          */
1171         clear_page(svm->vmcb);
1172         init_vmcb(svm);
1173
1174         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1175         return 0;
1176 }
1177
1178 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1179 {
1180         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1181         int size, in, string;
1182         unsigned port;
1183
1184         ++svm->vcpu.stat.io_exits;
1185
1186         svm->next_rip = svm->vmcb->control.exit_info_2;
1187
1188         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1189
1190         if (string) {
1191                 if (emulate_instruction(&svm->vcpu,
1192                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1193                         return 0;
1194                 return 1;
1195         }
1196
1197         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1198         port = io_info >> 16;
1199         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1200
1201         skip_emulated_instruction(&svm->vcpu);
1202         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1203 }
1204
1205 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1206 {
1207         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1208         return 1;
1209 }
1210
1211 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1212 {
1213         ++svm->vcpu.stat.irq_exits;
1214         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1215         return 1;
1216 }
1217
1218 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1219 {
1220         return 1;
1221 }
1222
1223 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1224 {
1225         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1226         skip_emulated_instruction(&svm->vcpu);
1227         return kvm_emulate_halt(&svm->vcpu);
1228 }
1229
1230 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1231 {
1232         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1233         skip_emulated_instruction(&svm->vcpu);
1234         kvm_emulate_hypercall(&svm->vcpu);
1235         return 1;
1236 }
1237
1238 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1239 {
1240         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1241             || !is_paging(&svm->vcpu)) {
1242                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1243                 return 1;
1244         }
1245
1246         if (svm->vmcb->save.cpl) {
1247                 kvm_inject_gp(&svm->vcpu, 0);
1248                 return 1;
1249         }
1250
1251        return 0;
1252 }
1253
1254 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1255                                       bool has_error_code, u32 error_code)
1256 {
1257         if (is_nested(svm)) {
1258                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1259                 svm->vmcb->control.exit_code_hi = 0;
1260                 svm->vmcb->control.exit_info_1 = error_code;
1261                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1262                 if (nested_svm_exit_handled(svm, false)) {
1263                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1264
1265                         nested_svm_vmexit(svm);
1266                         return 1;
1267                 }
1268         }
1269
1270         return 0;
1271 }
1272
1273 static inline int nested_svm_intr(struct vcpu_svm *svm)
1274 {
1275         if (is_nested(svm)) {
1276                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1277                         return 0;
1278
1279                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1280                         return 0;
1281
1282                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1283
1284                 if (nested_svm_exit_handled(svm, false)) {
1285                         nsvm_printk("VMexit -> INTR\n");
1286                         nested_svm_vmexit(svm);
1287                         return 1;
1288                 }
1289         }
1290
1291         return 0;
1292 }
1293
1294 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1295 {
1296         struct page *page;
1297
1298         down_read(&current->mm->mmap_sem);
1299         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1300         up_read(&current->mm->mmap_sem);
1301
1302         if (is_error_page(page)) {
1303                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1304                        __func__, gpa);
1305                 kvm_release_page_clean(page);
1306                 kvm_inject_gp(&svm->vcpu, 0);
1307                 return NULL;
1308         }
1309         return page;
1310 }
1311
1312 static int nested_svm_do(struct vcpu_svm *svm,
1313                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1314                          int (*handler)(struct vcpu_svm *svm,
1315                                         void *arg1,
1316                                         void *arg2,
1317                                         void *opaque))
1318 {
1319         struct page *arg1_page;
1320         struct page *arg2_page = NULL;
1321         void *arg1;
1322         void *arg2 = NULL;
1323         int retval;
1324
1325         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1326         if(arg1_page == NULL)
1327                 return 1;
1328
1329         if (arg2_gpa) {
1330                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1331                 if(arg2_page == NULL) {
1332                         kvm_release_page_clean(arg1_page);
1333                         return 1;
1334                 }
1335         }
1336
1337         arg1 = kmap_atomic(arg1_page, KM_USER0);
1338         if (arg2_gpa)
1339                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1340
1341         retval = handler(svm, arg1, arg2, opaque);
1342
1343         kunmap_atomic(arg1, KM_USER0);
1344         if (arg2_gpa)
1345                 kunmap_atomic(arg2, KM_USER1);
1346
1347         kvm_release_page_dirty(arg1_page);
1348         if (arg2_gpa)
1349                 kvm_release_page_dirty(arg2_page);
1350
1351         return retval;
1352 }
1353
1354 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1355                                         void *arg1,
1356                                         void *arg2,
1357                                         void *opaque)
1358 {
1359         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1360         bool kvm_overrides = *(bool *)opaque;
1361         u32 exit_code = svm->vmcb->control.exit_code;
1362
1363         if (kvm_overrides) {
1364                 switch (exit_code) {
1365                 case SVM_EXIT_INTR:
1366                 case SVM_EXIT_NMI:
1367                         return 0;
1368                 /* For now we are always handling NPFs when using them */
1369                 case SVM_EXIT_NPF:
1370                         if (npt_enabled)
1371                                 return 0;
1372                         break;
1373                 /* When we're shadowing, trap PFs */
1374                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1375                         if (!npt_enabled)
1376                                 return 0;
1377                         break;
1378                 default:
1379                         break;
1380                 }
1381         }
1382
1383         switch (exit_code) {
1384         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1385                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1386                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1387                         return 1;
1388                 break;
1389         }
1390         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1391                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1392                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1393                         return 1;
1394                 break;
1395         }
1396         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1397                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1398                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1399                         return 1;
1400                 break;
1401         }
1402         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1403                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1404                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1405                         return 1;
1406                 break;
1407         }
1408         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1409                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1410                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1411                         return 1;
1412                 break;
1413         }
1414         default: {
1415                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1416                 nsvm_printk("exit code: 0x%x\n", exit_code);
1417                 if (nested_vmcb->control.intercept & exit_bits)
1418                         return 1;
1419         }
1420         }
1421
1422         return 0;
1423 }
1424
1425 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1426                                        void *arg1, void *arg2,
1427                                        void *opaque)
1428 {
1429         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1430         u8 *msrpm = (u8 *)arg2;
1431         u32 t0, t1;
1432         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1433         u32 param = svm->vmcb->control.exit_info_1 & 1;
1434
1435         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1436                 return 0;
1437
1438         switch(msr) {
1439         case 0 ... 0x1fff:
1440                 t0 = (msr * 2) % 8;
1441                 t1 = msr / 8;
1442                 break;
1443         case 0xc0000000 ... 0xc0001fff:
1444                 t0 = (8192 + msr - 0xc0000000) * 2;
1445                 t1 = (t0 / 8);
1446                 t0 %= 8;
1447                 break;
1448         case 0xc0010000 ... 0xc0011fff:
1449                 t0 = (16384 + msr - 0xc0010000) * 2;
1450                 t1 = (t0 / 8);
1451                 t0 %= 8;
1452                 break;
1453         default:
1454                 return 1;
1455                 break;
1456         }
1457         if (msrpm[t1] & ((1 << param) << t0))
1458                 return 1;
1459
1460         return 0;
1461 }
1462
1463 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1464 {
1465         bool k = kvm_override;
1466
1467         switch (svm->vmcb->control.exit_code) {
1468         case SVM_EXIT_MSR:
1469                 return nested_svm_do(svm, svm->nested_vmcb,
1470                                      svm->nested_vmcb_msrpm, NULL,
1471                                      nested_svm_exit_handled_msr);
1472         default: break;
1473         }
1474
1475         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1476                              nested_svm_exit_handled_real);
1477 }
1478
1479 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1480                                   void *arg2, void *opaque)
1481 {
1482         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1483         struct vmcb *hsave = svm->hsave;
1484         u64 nested_save[] = { nested_vmcb->save.cr0,
1485                               nested_vmcb->save.cr3,
1486                               nested_vmcb->save.cr4,
1487                               nested_vmcb->save.efer,
1488                               nested_vmcb->control.intercept_cr_read,
1489                               nested_vmcb->control.intercept_cr_write,
1490                               nested_vmcb->control.intercept_dr_read,
1491                               nested_vmcb->control.intercept_dr_write,
1492                               nested_vmcb->control.intercept_exceptions,
1493                               nested_vmcb->control.intercept,
1494                               nested_vmcb->control.msrpm_base_pa,
1495                               nested_vmcb->control.iopm_base_pa,
1496                               nested_vmcb->control.tsc_offset };
1497
1498         /* Give the current vmcb to the guest */
1499         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1500         nested_vmcb->save.cr0 = nested_save[0];
1501         if (!npt_enabled)
1502                 nested_vmcb->save.cr3 = nested_save[1];
1503         nested_vmcb->save.cr4 = nested_save[2];
1504         nested_vmcb->save.efer = nested_save[3];
1505         nested_vmcb->control.intercept_cr_read = nested_save[4];
1506         nested_vmcb->control.intercept_cr_write = nested_save[5];
1507         nested_vmcb->control.intercept_dr_read = nested_save[6];
1508         nested_vmcb->control.intercept_dr_write = nested_save[7];
1509         nested_vmcb->control.intercept_exceptions = nested_save[8];
1510         nested_vmcb->control.intercept = nested_save[9];
1511         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1512         nested_vmcb->control.iopm_base_pa = nested_save[11];
1513         nested_vmcb->control.tsc_offset = nested_save[12];
1514
1515         /* We always set V_INTR_MASKING and remember the old value in hflags */
1516         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1517                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1518
1519         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1520             (nested_vmcb->control.int_vector)) {
1521                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1522                                 nested_vmcb->control.int_vector);
1523         }
1524
1525         /* Restore the original control entries */
1526         svm->vmcb->control = hsave->control;
1527
1528         /* Kill any pending exceptions */
1529         if (svm->vcpu.arch.exception.pending == true)
1530                 nsvm_printk("WARNING: Pending Exception\n");
1531         svm->vcpu.arch.exception.pending = false;
1532
1533         /* Restore selected save entries */
1534         svm->vmcb->save.es = hsave->save.es;
1535         svm->vmcb->save.cs = hsave->save.cs;
1536         svm->vmcb->save.ss = hsave->save.ss;
1537         svm->vmcb->save.ds = hsave->save.ds;
1538         svm->vmcb->save.gdtr = hsave->save.gdtr;
1539         svm->vmcb->save.idtr = hsave->save.idtr;
1540         svm->vmcb->save.rflags = hsave->save.rflags;
1541         svm_set_efer(&svm->vcpu, hsave->save.efer);
1542         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1543         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1544         if (npt_enabled) {
1545                 svm->vmcb->save.cr3 = hsave->save.cr3;
1546                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1547         } else {
1548                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1549         }
1550         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1551         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1552         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1553         svm->vmcb->save.dr7 = 0;
1554         svm->vmcb->save.cpl = 0;
1555         svm->vmcb->control.exit_int_info = 0;
1556
1557         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1558         /* Exit nested SVM mode */
1559         svm->nested_vmcb = 0;
1560
1561         return 0;
1562 }
1563
1564 static int nested_svm_vmexit(struct vcpu_svm *svm)
1565 {
1566         nsvm_printk("VMexit\n");
1567         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1568                           NULL, nested_svm_vmexit_real))
1569                 return 1;
1570
1571         kvm_mmu_reset_context(&svm->vcpu);
1572         kvm_mmu_load(&svm->vcpu);
1573
1574         return 0;
1575 }
1576
1577 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1578                                   void *arg2, void *opaque)
1579 {
1580         int i;
1581         u32 *nested_msrpm = (u32*)arg1;
1582         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1583                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1584         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1585
1586         return 0;
1587 }
1588
1589 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1590                             void *arg2, void *opaque)
1591 {
1592         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1593         struct vmcb *hsave = svm->hsave;
1594
1595         /* nested_vmcb is our indicator if nested SVM is activated */
1596         svm->nested_vmcb = svm->vmcb->save.rax;
1597
1598         /* Clear internal status */
1599         svm->vcpu.arch.exception.pending = false;
1600
1601         /* Save the old vmcb, so we don't need to pick what we save, but
1602            can restore everything when a VMEXIT occurs */
1603         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1604         /* We need to remember the original CR3 in the SPT case */
1605         if (!npt_enabled)
1606                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1607         hsave->save.cr4 = svm->vcpu.arch.cr4;
1608         hsave->save.rip = svm->next_rip;
1609
1610         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1611                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1612         else
1613                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1614
1615         /* Load the nested guest state */
1616         svm->vmcb->save.es = nested_vmcb->save.es;
1617         svm->vmcb->save.cs = nested_vmcb->save.cs;
1618         svm->vmcb->save.ss = nested_vmcb->save.ss;
1619         svm->vmcb->save.ds = nested_vmcb->save.ds;
1620         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1621         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1622         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1623         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1624         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1625         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1626         if (npt_enabled) {
1627                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1628                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1629         } else {
1630                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1631                 kvm_mmu_reset_context(&svm->vcpu);
1632         }
1633         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1634         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1635         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1636         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1637         /* In case we don't even reach vcpu_run, the fields are not updated */
1638         svm->vmcb->save.rax = nested_vmcb->save.rax;
1639         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1640         svm->vmcb->save.rip = nested_vmcb->save.rip;
1641         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1642         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1643         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1644
1645         /* We don't want a nested guest to be more powerful than the guest,
1646            so all intercepts are ORed */
1647         svm->vmcb->control.intercept_cr_read |=
1648                 nested_vmcb->control.intercept_cr_read;
1649         svm->vmcb->control.intercept_cr_write |=
1650                 nested_vmcb->control.intercept_cr_write;
1651         svm->vmcb->control.intercept_dr_read |=
1652                 nested_vmcb->control.intercept_dr_read;
1653         svm->vmcb->control.intercept_dr_write |=
1654                 nested_vmcb->control.intercept_dr_write;
1655         svm->vmcb->control.intercept_exceptions |=
1656                 nested_vmcb->control.intercept_exceptions;
1657
1658         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1659
1660         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1661
1662         force_new_asid(&svm->vcpu);
1663         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1664         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1665         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1666         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1667                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1668                                 nested_vmcb->control.int_ctl);
1669         }
1670         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1671                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1672         else
1673                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1674
1675         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1676                         nested_vmcb->control.exit_int_info,
1677                         nested_vmcb->control.int_state);
1678
1679         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1680         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1681         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1682         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1683                 nsvm_printk("Injecting Event: 0x%x\n",
1684                                 nested_vmcb->control.event_inj);
1685         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1686         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1687
1688         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1689
1690         return 0;
1691 }
1692
1693 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1694 {
1695         to_vmcb->save.fs = from_vmcb->save.fs;
1696         to_vmcb->save.gs = from_vmcb->save.gs;
1697         to_vmcb->save.tr = from_vmcb->save.tr;
1698         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1699         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1700         to_vmcb->save.star = from_vmcb->save.star;
1701         to_vmcb->save.lstar = from_vmcb->save.lstar;
1702         to_vmcb->save.cstar = from_vmcb->save.cstar;
1703         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1704         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1705         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1706         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1707
1708         return 1;
1709 }
1710
1711 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1712                              void *arg2, void *opaque)
1713 {
1714         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1715 }
1716
1717 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1718                              void *arg2, void *opaque)
1719 {
1720         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1721 }
1722
1723 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1724 {
1725         if (nested_svm_check_permissions(svm))
1726                 return 1;
1727
1728         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1729         skip_emulated_instruction(&svm->vcpu);
1730
1731         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1732
1733         return 1;
1734 }
1735
1736 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1737 {
1738         if (nested_svm_check_permissions(svm))
1739                 return 1;
1740
1741         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1742         skip_emulated_instruction(&svm->vcpu);
1743
1744         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1745
1746         return 1;
1747 }
1748
1749 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1750 {
1751         nsvm_printk("VMrun\n");
1752         if (nested_svm_check_permissions(svm))
1753                 return 1;
1754
1755         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1756         skip_emulated_instruction(&svm->vcpu);
1757
1758         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1759                           NULL, nested_svm_vmrun))
1760                 return 1;
1761
1762         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1763                       NULL, nested_svm_vmrun_msrpm))
1764                 return 1;
1765
1766         return 1;
1767 }
1768
1769 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1770 {
1771         if (nested_svm_check_permissions(svm))
1772                 return 1;
1773
1774         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1775         skip_emulated_instruction(&svm->vcpu);
1776
1777         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1778
1779         return 1;
1780 }
1781
1782 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1783 {
1784         if (nested_svm_check_permissions(svm))
1785                 return 1;
1786
1787         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1788         skip_emulated_instruction(&svm->vcpu);
1789
1790         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1791
1792         /* After a CLGI no interrupts should come */
1793         svm_clear_vintr(svm);
1794         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1795
1796         return 1;
1797 }
1798
1799 static int invalid_op_interception(struct vcpu_svm *svm,
1800                                    struct kvm_run *kvm_run)
1801 {
1802         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1803         return 1;
1804 }
1805
1806 static int task_switch_interception(struct vcpu_svm *svm,
1807                                     struct kvm_run *kvm_run)
1808 {
1809         u16 tss_selector;
1810         int reason;
1811         int int_type = svm->vmcb->control.exit_int_info &
1812                 SVM_EXITINTINFO_TYPE_MASK;
1813         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1814
1815         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1816
1817         if (svm->vmcb->control.exit_info_2 &
1818             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1819                 reason = TASK_SWITCH_IRET;
1820         else if (svm->vmcb->control.exit_info_2 &
1821                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1822                 reason = TASK_SWITCH_JMP;
1823         else if (svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID)
1824                 reason = TASK_SWITCH_GATE;
1825         else
1826                 reason = TASK_SWITCH_CALL;
1827
1828
1829         if (reason != TASK_SWITCH_GATE ||
1830             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1831             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1832              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
1833                 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0,
1834                                         EMULTYPE_SKIP) != EMULATE_DONE)
1835                         return 0;
1836         }
1837
1838         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1839 }
1840
1841 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1842 {
1843         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1844         kvm_emulate_cpuid(&svm->vcpu);
1845         return 1;
1846 }
1847
1848 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1849 {
1850         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1851                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1852         return 1;
1853 }
1854
1855 static int emulate_on_interception(struct vcpu_svm *svm,
1856                                    struct kvm_run *kvm_run)
1857 {
1858         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1859                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1860         return 1;
1861 }
1862
1863 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1864 {
1865         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1866         if (irqchip_in_kernel(svm->vcpu.kvm))
1867                 return 1;
1868         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1869         return 0;
1870 }
1871
1872 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1873 {
1874         struct vcpu_svm *svm = to_svm(vcpu);
1875
1876         switch (ecx) {
1877         case MSR_IA32_TIME_STAMP_COUNTER: {
1878                 u64 tsc;
1879
1880                 rdtscll(tsc);
1881                 *data = svm->vmcb->control.tsc_offset + tsc;
1882                 break;
1883         }
1884         case MSR_K6_STAR:
1885                 *data = svm->vmcb->save.star;
1886                 break;
1887 #ifdef CONFIG_X86_64
1888         case MSR_LSTAR:
1889                 *data = svm->vmcb->save.lstar;
1890                 break;
1891         case MSR_CSTAR:
1892                 *data = svm->vmcb->save.cstar;
1893                 break;
1894         case MSR_KERNEL_GS_BASE:
1895                 *data = svm->vmcb->save.kernel_gs_base;
1896                 break;
1897         case MSR_SYSCALL_MASK:
1898                 *data = svm->vmcb->save.sfmask;
1899                 break;
1900 #endif
1901         case MSR_IA32_SYSENTER_CS:
1902                 *data = svm->vmcb->save.sysenter_cs;
1903                 break;
1904         case MSR_IA32_SYSENTER_EIP:
1905                 *data = svm->vmcb->save.sysenter_eip;
1906                 break;
1907         case MSR_IA32_SYSENTER_ESP:
1908                 *data = svm->vmcb->save.sysenter_esp;
1909                 break;
1910         /* Nobody will change the following 5 values in the VMCB so
1911            we can safely return them on rdmsr. They will always be 0
1912            until LBRV is implemented. */
1913         case MSR_IA32_DEBUGCTLMSR:
1914                 *data = svm->vmcb->save.dbgctl;
1915                 break;
1916         case MSR_IA32_LASTBRANCHFROMIP:
1917                 *data = svm->vmcb->save.br_from;
1918                 break;
1919         case MSR_IA32_LASTBRANCHTOIP:
1920                 *data = svm->vmcb->save.br_to;
1921                 break;
1922         case MSR_IA32_LASTINTFROMIP:
1923                 *data = svm->vmcb->save.last_excp_from;
1924                 break;
1925         case MSR_IA32_LASTINTTOIP:
1926                 *data = svm->vmcb->save.last_excp_to;
1927                 break;
1928         case MSR_VM_HSAVE_PA:
1929                 *data = svm->hsave_msr;
1930                 break;
1931         case MSR_VM_CR:
1932                 *data = 0;
1933                 break;
1934         case MSR_IA32_UCODE_REV:
1935                 *data = 0x01000065;
1936                 break;
1937         default:
1938                 return kvm_get_msr_common(vcpu, ecx, data);
1939         }
1940         return 0;
1941 }
1942
1943 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1944 {
1945         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1946         u64 data;
1947
1948         if (svm_get_msr(&svm->vcpu, ecx, &data))
1949                 kvm_inject_gp(&svm->vcpu, 0);
1950         else {
1951                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1952                             (u32)(data >> 32), handler);
1953
1954                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1955                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1956                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1957                 skip_emulated_instruction(&svm->vcpu);
1958         }
1959         return 1;
1960 }
1961
1962 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1963 {
1964         struct vcpu_svm *svm = to_svm(vcpu);
1965
1966         switch (ecx) {
1967         case MSR_IA32_TIME_STAMP_COUNTER: {
1968                 u64 tsc;
1969
1970                 rdtscll(tsc);
1971                 svm->vmcb->control.tsc_offset = data - tsc;
1972                 break;
1973         }
1974         case MSR_K6_STAR:
1975                 svm->vmcb->save.star = data;
1976                 break;
1977 #ifdef CONFIG_X86_64
1978         case MSR_LSTAR:
1979                 svm->vmcb->save.lstar = data;
1980                 break;
1981         case MSR_CSTAR:
1982                 svm->vmcb->save.cstar = data;
1983                 break;
1984         case MSR_KERNEL_GS_BASE:
1985                 svm->vmcb->save.kernel_gs_base = data;
1986                 break;
1987         case MSR_SYSCALL_MASK:
1988                 svm->vmcb->save.sfmask = data;
1989                 break;
1990 #endif
1991         case MSR_IA32_SYSENTER_CS:
1992                 svm->vmcb->save.sysenter_cs = data;
1993                 break;
1994         case MSR_IA32_SYSENTER_EIP:
1995                 svm->vmcb->save.sysenter_eip = data;
1996                 break;
1997         case MSR_IA32_SYSENTER_ESP:
1998                 svm->vmcb->save.sysenter_esp = data;
1999                 break;
2000         case MSR_IA32_DEBUGCTLMSR:
2001                 if (!svm_has(SVM_FEATURE_LBRV)) {
2002                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2003                                         __func__, data);
2004                         break;
2005                 }
2006                 if (data & DEBUGCTL_RESERVED_BITS)
2007                         return 1;
2008
2009                 svm->vmcb->save.dbgctl = data;
2010                 if (data & (1ULL<<0))
2011                         svm_enable_lbrv(svm);
2012                 else
2013                         svm_disable_lbrv(svm);
2014                 break;
2015         case MSR_K7_EVNTSEL0:
2016         case MSR_K7_EVNTSEL1:
2017         case MSR_K7_EVNTSEL2:
2018         case MSR_K7_EVNTSEL3:
2019         case MSR_K7_PERFCTR0:
2020         case MSR_K7_PERFCTR1:
2021         case MSR_K7_PERFCTR2:
2022         case MSR_K7_PERFCTR3:
2023                 /*
2024                  * Just discard all writes to the performance counters; this
2025                  * should keep both older linux and windows 64-bit guests
2026                  * happy
2027                  */
2028                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2029
2030                 break;
2031         case MSR_VM_HSAVE_PA:
2032                 svm->hsave_msr = data;
2033                 break;
2034         default:
2035                 return kvm_set_msr_common(vcpu, ecx, data);
2036         }
2037         return 0;
2038 }
2039
2040 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2041 {
2042         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2043         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2044                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2045
2046         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2047                     handler);
2048
2049         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2050         if (svm_set_msr(&svm->vcpu, ecx, data))
2051                 kvm_inject_gp(&svm->vcpu, 0);
2052         else
2053                 skip_emulated_instruction(&svm->vcpu);
2054         return 1;
2055 }
2056
2057 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2058 {
2059         if (svm->vmcb->control.exit_info_1)
2060                 return wrmsr_interception(svm, kvm_run);
2061         else
2062                 return rdmsr_interception(svm, kvm_run);
2063 }
2064
2065 static int interrupt_window_interception(struct vcpu_svm *svm,
2066                                    struct kvm_run *kvm_run)
2067 {
2068         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2069
2070         svm_clear_vintr(svm);
2071         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2072         /*
2073          * If the user space waits to inject interrupts, exit as soon as
2074          * possible
2075          */
2076         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2077             kvm_run->request_interrupt_window &&
2078             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2079                 ++svm->vcpu.stat.irq_window_exits;
2080                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2081                 return 0;
2082         }
2083
2084         return 1;
2085 }
2086
2087 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2088                                       struct kvm_run *kvm_run) = {
2089         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2090         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2091         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2092         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2093         /* for now: */
2094         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2095         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2096         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2097         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2098         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2099         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2100         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2101         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2102         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2103         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2104         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2105         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2106         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2107         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2108         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2109         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2110         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2111         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2112         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2113         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2114         [SVM_EXIT_INTR]                         = intr_interception,
2115         [SVM_EXIT_NMI]                          = nmi_interception,
2116         [SVM_EXIT_SMI]                          = nop_on_interception,
2117         [SVM_EXIT_INIT]                         = nop_on_interception,
2118         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2119         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2120         [SVM_EXIT_CPUID]                        = cpuid_interception,
2121         [SVM_EXIT_INVD]                         = emulate_on_interception,
2122         [SVM_EXIT_HLT]                          = halt_interception,
2123         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2124         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2125         [SVM_EXIT_IOIO]                         = io_interception,
2126         [SVM_EXIT_MSR]                          = msr_interception,
2127         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2128         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2129         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2130         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2131         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2132         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2133         [SVM_EXIT_STGI]                         = stgi_interception,
2134         [SVM_EXIT_CLGI]                         = clgi_interception,
2135         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2136         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2137         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2138         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2139         [SVM_EXIT_NPF]                          = pf_interception,
2140 };
2141
2142 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2143 {
2144         struct vcpu_svm *svm = to_svm(vcpu);
2145         u32 exit_code = svm->vmcb->control.exit_code;
2146
2147         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2148                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2149
2150         if (is_nested(svm)) {
2151                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2152                             exit_code, svm->vmcb->control.exit_info_1,
2153                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2154                 if (nested_svm_exit_handled(svm, true)) {
2155                         nested_svm_vmexit(svm);
2156                         nsvm_printk("-> #VMEXIT\n");
2157                         return 1;
2158                 }
2159         }
2160
2161         if (npt_enabled) {
2162                 int mmu_reload = 0;
2163                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2164                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2165                         mmu_reload = 1;
2166                 }
2167                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2168                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2169                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2170                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2171                                 kvm_inject_gp(vcpu, 0);
2172                                 return 1;
2173                         }
2174                 }
2175                 if (mmu_reload) {
2176                         kvm_mmu_reset_context(vcpu);
2177                         kvm_mmu_load(vcpu);
2178                 }
2179         }
2180
2181
2182         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2183                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2184                 kvm_run->fail_entry.hardware_entry_failure_reason
2185                         = svm->vmcb->control.exit_code;
2186                 return 0;
2187         }
2188
2189         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2190             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2191             exit_code != SVM_EXIT_NPF)
2192                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2193                        "exit_code 0x%x\n",
2194                        __func__, svm->vmcb->control.exit_int_info,
2195                        exit_code);
2196
2197         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2198             || !svm_exit_handlers[exit_code]) {
2199                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2200                 kvm_run->hw.hardware_exit_reason = exit_code;
2201                 return 0;
2202         }
2203
2204         return svm_exit_handlers[exit_code](svm, kvm_run);
2205 }
2206
2207 static void reload_tss(struct kvm_vcpu *vcpu)
2208 {
2209         int cpu = raw_smp_processor_id();
2210
2211         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2212         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2213         load_TR_desc();
2214 }
2215
2216 static void pre_svm_run(struct vcpu_svm *svm)
2217 {
2218         int cpu = raw_smp_processor_id();
2219
2220         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2221
2222         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2223         if (svm->vcpu.cpu != cpu ||
2224             svm->asid_generation != svm_data->asid_generation)
2225                 new_asid(svm, svm_data);
2226 }
2227
2228
2229 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2230 {
2231         struct vmcb_control_area *control;
2232
2233         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2234
2235         ++svm->vcpu.stat.irq_injections;
2236         control = &svm->vmcb->control;
2237         control->int_vector = irq;
2238         control->int_ctl &= ~V_INTR_PRIO_MASK;
2239         control->int_ctl |= V_IRQ_MASK |
2240                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2241 }
2242
2243 static void svm_queue_irq(struct vcpu_svm *svm, unsigned nr)
2244 {
2245         svm->vmcb->control.event_inj = nr |
2246                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2247 }
2248
2249 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2250 {
2251         struct vcpu_svm *svm = to_svm(vcpu);
2252
2253         nested_svm_intr(svm);
2254
2255         svm_queue_irq(svm, irq);
2256 }
2257
2258 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2259 {
2260         struct vcpu_svm *svm = to_svm(vcpu);
2261         struct vmcb *vmcb = svm->vmcb;
2262         int max_irr, tpr;
2263
2264         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2265                 return;
2266
2267         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2268
2269         max_irr = kvm_lapic_find_highest_irr(vcpu);
2270         if (max_irr == -1)
2271                 return;
2272
2273         tpr = kvm_lapic_get_cr8(vcpu) << 4;
2274
2275         if (tpr >= (max_irr & 0xf0))
2276                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2277 }
2278
2279 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2280 {
2281         struct vcpu_svm *svm = to_svm(vcpu);
2282         struct vmcb *vmcb = svm->vmcb;
2283         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2284                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2285                 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2286 }
2287
2288 static void enable_irq_window(struct kvm_vcpu *vcpu)
2289 {
2290         svm_set_vintr(to_svm(vcpu));
2291         svm_inject_irq(to_svm(vcpu), 0x0);
2292 }
2293
2294 static void svm_intr_inject(struct kvm_vcpu *vcpu)
2295 {
2296         /* try to reinject previous events if any */
2297         if (vcpu->arch.interrupt.pending) {
2298                 svm_queue_irq(to_svm(vcpu), vcpu->arch.interrupt.nr);
2299                 return;
2300         }
2301
2302         /* try to inject new event if pending */
2303         if (kvm_cpu_has_interrupt(vcpu)) {
2304                 if (vcpu->arch.interrupt_window_open) {
2305                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
2306                         svm_queue_irq(to_svm(vcpu), vcpu->arch.interrupt.nr);
2307                 }
2308         }
2309 }
2310
2311 static void svm_intr_assist(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2312 {
2313         struct vcpu_svm *svm = to_svm(vcpu);
2314         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
2315                 kvm_run->request_interrupt_window;
2316
2317         if (nested_svm_intr(svm))
2318                 goto out;
2319
2320         svm->vcpu.arch.interrupt_window_open = svm_interrupt_allowed(vcpu);
2321
2322         svm_intr_inject(vcpu);
2323
2324         if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
2325                 enable_irq_window(vcpu);
2326
2327 out:
2328         update_cr8_intercept(vcpu);
2329 }
2330
2331 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2332 {
2333         return 0;
2334 }
2335
2336 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2337 {
2338         force_new_asid(vcpu);
2339 }
2340
2341 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2342 {
2343 }
2344
2345 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2346 {
2347         struct vcpu_svm *svm = to_svm(vcpu);
2348
2349         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2350                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2351                 kvm_set_cr8(vcpu, cr8);
2352         }
2353 }
2354
2355 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2356 {
2357         struct vcpu_svm *svm = to_svm(vcpu);
2358         u64 cr8;
2359
2360         cr8 = kvm_get_cr8(vcpu);
2361         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2362         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2363 }
2364
2365 static void svm_complete_interrupts(struct vcpu_svm *svm)
2366 {
2367         u8 vector;
2368         int type;
2369         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2370
2371         svm->vcpu.arch.nmi_injected = false;
2372         kvm_clear_exception_queue(&svm->vcpu);
2373         kvm_clear_interrupt_queue(&svm->vcpu);
2374
2375         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2376                 return;
2377
2378         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2379         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2380
2381         switch (type) {
2382         case SVM_EXITINTINFO_TYPE_NMI:
2383                 svm->vcpu.arch.nmi_injected = true;
2384                 break;
2385         case SVM_EXITINTINFO_TYPE_EXEPT:
2386                 /* In case of software exception do not reinject an exception
2387                    vector, but re-execute and instruction instead */
2388                 if (vector == BP_VECTOR || vector == OF_VECTOR)
2389                         break;
2390                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2391                         u32 err = svm->vmcb->control.exit_int_info_err;
2392                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2393
2394                 } else
2395                         kvm_queue_exception(&svm->vcpu, vector);
2396                 break;
2397         case SVM_EXITINTINFO_TYPE_INTR:
2398                 kvm_queue_interrupt(&svm->vcpu, vector);
2399                 break;
2400         default:
2401                 break;
2402         }
2403 }
2404
2405 #ifdef CONFIG_X86_64
2406 #define R "r"
2407 #else
2408 #define R "e"
2409 #endif
2410
2411 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2412 {
2413         struct vcpu_svm *svm = to_svm(vcpu);
2414         u16 fs_selector;
2415         u16 gs_selector;
2416         u16 ldt_selector;
2417
2418         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2419         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2420         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2421
2422         pre_svm_run(svm);
2423
2424         sync_lapic_to_cr8(vcpu);
2425
2426         save_host_msrs(vcpu);
2427         fs_selector = kvm_read_fs();
2428         gs_selector = kvm_read_gs();
2429         ldt_selector = kvm_read_ldt();
2430         svm->host_cr2 = kvm_read_cr2();
2431         if (!is_nested(svm))
2432                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2433         /* required for live migration with NPT */
2434         if (npt_enabled)
2435                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2436
2437         clgi();
2438
2439         local_irq_enable();
2440
2441         asm volatile (
2442                 "push %%"R"bp; \n\t"
2443                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2444                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2445                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2446                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2447                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2448                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2449 #ifdef CONFIG_X86_64
2450                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2451                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2452                 "mov %c[r10](%[svm]), %%r10 \n\t"
2453                 "mov %c[r11](%[svm]), %%r11 \n\t"
2454                 "mov %c[r12](%[svm]), %%r12 \n\t"
2455                 "mov %c[r13](%[svm]), %%r13 \n\t"
2456                 "mov %c[r14](%[svm]), %%r14 \n\t"
2457                 "mov %c[r15](%[svm]), %%r15 \n\t"
2458 #endif
2459
2460                 /* Enter guest mode */
2461                 "push %%"R"ax \n\t"
2462                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2463                 __ex(SVM_VMLOAD) "\n\t"
2464                 __ex(SVM_VMRUN) "\n\t"
2465                 __ex(SVM_VMSAVE) "\n\t"
2466                 "pop %%"R"ax \n\t"
2467
2468                 /* Save guest registers, load host registers */
2469                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2470                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2471                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2472                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2473                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2474                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2475 #ifdef CONFIG_X86_64
2476                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2477                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2478                 "mov %%r10, %c[r10](%[svm]) \n\t"
2479                 "mov %%r11, %c[r11](%[svm]) \n\t"
2480                 "mov %%r12, %c[r12](%[svm]) \n\t"
2481                 "mov %%r13, %c[r13](%[svm]) \n\t"
2482                 "mov %%r14, %c[r14](%[svm]) \n\t"
2483                 "mov %%r15, %c[r15](%[svm]) \n\t"
2484 #endif
2485                 "pop %%"R"bp"
2486                 :
2487                 : [svm]"a"(svm),
2488                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2489                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2490                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2491                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2492                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2493                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2494                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2495 #ifdef CONFIG_X86_64
2496                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2497                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2498                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2499                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2500                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2501                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2502                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2503                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2504 #endif
2505                 : "cc", "memory"
2506                 , R"bx", R"cx", R"dx", R"si", R"di"
2507 #ifdef CONFIG_X86_64
2508                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2509 #endif
2510                 );
2511
2512         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2513         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2514         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2515         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2516
2517         kvm_write_cr2(svm->host_cr2);
2518
2519         kvm_load_fs(fs_selector);
2520         kvm_load_gs(gs_selector);
2521         kvm_load_ldt(ldt_selector);
2522         load_host_msrs(vcpu);
2523
2524         reload_tss(vcpu);
2525
2526         local_irq_disable();
2527
2528         stgi();
2529
2530         sync_cr8_to_lapic(vcpu);
2531
2532         svm->next_rip = 0;
2533
2534         svm_complete_interrupts(svm);
2535 }
2536
2537 #undef R
2538
2539 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2540 {
2541         struct vcpu_svm *svm = to_svm(vcpu);
2542
2543         if (npt_enabled) {
2544                 svm->vmcb->control.nested_cr3 = root;
2545                 force_new_asid(vcpu);
2546                 return;
2547         }
2548
2549         svm->vmcb->save.cr3 = root;
2550         force_new_asid(vcpu);
2551
2552         if (vcpu->fpu_active) {
2553                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2554                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2555                 vcpu->fpu_active = 0;
2556         }
2557 }
2558
2559 static int is_disabled(void)
2560 {
2561         u64 vm_cr;
2562
2563         rdmsrl(MSR_VM_CR, vm_cr);
2564         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2565                 return 1;
2566
2567         return 0;
2568 }
2569
2570 static void
2571 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2572 {
2573         /*
2574          * Patch in the VMMCALL instruction:
2575          */
2576         hypercall[0] = 0x0f;
2577         hypercall[1] = 0x01;
2578         hypercall[2] = 0xd9;
2579 }
2580
2581 static void svm_check_processor_compat(void *rtn)
2582 {
2583         *(int *)rtn = 0;
2584 }
2585
2586 static bool svm_cpu_has_accelerated_tpr(void)
2587 {
2588         return false;
2589 }
2590
2591 static int get_npt_level(void)
2592 {
2593 #ifdef CONFIG_X86_64
2594         return PT64_ROOT_LEVEL;
2595 #else
2596         return PT32E_ROOT_LEVEL;
2597 #endif
2598 }
2599
2600 static int svm_get_mt_mask_shift(void)
2601 {
2602         return 0;
2603 }
2604
2605 static struct kvm_x86_ops svm_x86_ops = {
2606         .cpu_has_kvm_support = has_svm,
2607         .disabled_by_bios = is_disabled,
2608         .hardware_setup = svm_hardware_setup,
2609         .hardware_unsetup = svm_hardware_unsetup,
2610         .check_processor_compatibility = svm_check_processor_compat,
2611         .hardware_enable = svm_hardware_enable,
2612         .hardware_disable = svm_hardware_disable,
2613         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2614
2615         .vcpu_create = svm_create_vcpu,
2616         .vcpu_free = svm_free_vcpu,
2617         .vcpu_reset = svm_vcpu_reset,
2618
2619         .prepare_guest_switch = svm_prepare_guest_switch,
2620         .vcpu_load = svm_vcpu_load,
2621         .vcpu_put = svm_vcpu_put,
2622
2623         .set_guest_debug = svm_guest_debug,
2624         .get_msr = svm_get_msr,
2625         .set_msr = svm_set_msr,
2626         .get_segment_base = svm_get_segment_base,
2627         .get_segment = svm_get_segment,
2628         .set_segment = svm_set_segment,
2629         .get_cpl = svm_get_cpl,
2630         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2631         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2632         .set_cr0 = svm_set_cr0,
2633         .set_cr3 = svm_set_cr3,
2634         .set_cr4 = svm_set_cr4,
2635         .set_efer = svm_set_efer,
2636         .get_idt = svm_get_idt,
2637         .set_idt = svm_set_idt,
2638         .get_gdt = svm_get_gdt,
2639         .set_gdt = svm_set_gdt,
2640         .get_dr = svm_get_dr,
2641         .set_dr = svm_set_dr,
2642         .get_rflags = svm_get_rflags,
2643         .set_rflags = svm_set_rflags,
2644
2645         .tlb_flush = svm_flush_tlb,
2646
2647         .run = svm_vcpu_run,
2648         .handle_exit = handle_exit,
2649         .skip_emulated_instruction = skip_emulated_instruction,
2650         .patch_hypercall = svm_patch_hypercall,
2651         .get_irq = svm_get_irq,
2652         .set_irq = svm_set_irq,
2653         .queue_exception = svm_queue_exception,
2654         .inject_pending_irq = svm_intr_assist,
2655         .interrupt_allowed = svm_interrupt_allowed,
2656
2657         .set_tss_addr = svm_set_tss_addr,
2658         .get_tdp_level = get_npt_level,
2659         .get_mt_mask_shift = svm_get_mt_mask_shift,
2660 };
2661
2662 static int __init svm_init(void)
2663 {
2664         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2665                               THIS_MODULE);
2666 }
2667
2668 static void __exit svm_exit(void)
2669 {
2670         kvm_exit();
2671 }
2672
2673 module_init(svm_init)
2674 module_exit(svm_exit)