SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  * Authors:
  25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  26  *   Port from Qemu.
  27  */
  28 #include <linux/mm.h>
  29 #include <linux/bitops.h>
  30 #include "irq.h"
  31
  32 #include <linux/kvm_host.h>
  33 #include "trace.h"
  34
  35 static void pic_lock(struct kvm_pic *s)
  36         __acquires(&s->lock)
  37 {
  38         spin_lock(&s->lock);
  39 }
  40
  41 static void pic_unlock(struct kvm_pic *s)
  42         __releases(&s->lock)
  43 {
  44         struct kvm *kvm = s->kvm;
  45         unsigned acks = s->pending_acks;
  46         bool wakeup = s->wakeup_needed;
  47         struct kvm_vcpu *vcpu;
  48
  49         s->pending_acks = 0;
  50         s->wakeup_needed = false;
  51
  52         spin_unlock(&s->lock);
  53
  54         while (acks) {
  55                 kvm_notify_acked_irq(kvm, SELECT_PIC(__ffs(acks)),
  56                                      __ffs(acks));
  57                 acks &= acks - 1;
  58         }
  59
  60         if (wakeup) {
  61                 vcpu = s->kvm->bsp_vcpu;
  62                 if (vcpu)
  63                         kvm_vcpu_kick(vcpu);
  64         }
  65 }
  66
  67 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  68 {
  69         s->isr &= ~(1 << irq);
  70         s->isr_ack |= (1 << irq);
  71 }
  72
  73 void kvm_pic_clear_isr_ack(struct kvm *kvm)
  74 {
  75         struct kvm_pic *s = pic_irqchip(kvm);
  76         pic_lock(s);
  77         s->pics[0].isr_ack = 0xff;
  78         s->pics[1].isr_ack = 0xff;
  79         pic_unlock(s);
  80 }
  81
  82 /*
  83  * set irq level. If an edge is detected, then the IRR is set to 1
  84  */
  85 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  86 {
  87         int mask, ret = 1;
  88         mask = 1 << irq;
  89         if (s->elcr & mask)     /* level triggered */
  90                 if (level) {
  91                         ret = !(s->irr & mask);
  92                         s->irr |= mask;
  93                         s->last_irr |= mask;
  94                 } else {
  95                         s->irr &= ~mask;
  96                         s->last_irr &= ~mask;
  97                 }
  98         else    /* edge triggered */
  99                 if (level) {
 100                         if ((s->last_irr & mask) == 0) {
 101                                 ret = !(s->irr & mask);
 102                                 s->irr |= mask;
 103                         }
 104                         s->last_irr |= mask;
 105                 } else
 106                         s->last_irr &= ~mask;
 107
 108         return (s->imr & mask) ? -1 : ret;
 109 }
 110
 111 /*
 112  * return the highest priority found in mask (highest = smallest
 113  * number). Return 8 if no irq
 114  */
 115 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 116 {
 117         int priority;
 118         if (mask == 0)
 119                 return 8;
 120         priority = 0;
 121         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 122                 priority++;
 123         return priority;
 124 }
 125
 126 /*
 127  * return the pic wanted interrupt. return -1 if none
 128  */
 129 static int pic_get_irq(struct kvm_kpic_state *s)
 130 {
 131         int mask, cur_priority, priority;
 132
 133         mask = s->irr & ~s->imr;
 134         priority = get_priority(s, mask);
 135         if (priority == 8)
 136                 return -1;
 137         /*
 138          * compute current priority. If special fully nested mode on the
 139          * master, the IRQ coming from the slave is not taken into account
 140          * for the priority computation.
 141          */
 142         mask = s->isr;
 143         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 144                 mask &= ~(1 << 2);
 145         cur_priority = get_priority(s, mask);
 146         if (priority < cur_priority)
 147                 /*
 148                  * higher priority found: an irq should be generated
 149                  */
 150                 return (priority + s->priority_add) & 7;
 151         else
 152                 return -1;
 153 }
 154
 155 /*
 156  * raise irq to CPU if necessary. must be called every time the active
 157  * irq may change
 158  */
 159 static void pic_update_irq(struct kvm_pic *s)
 160 {
 161         int irq2, irq;
 162
 163         irq2 = pic_get_irq(&s->pics[1]);
 164         if (irq2 >= 0) {
 165                 /*
 166                  * if irq request by slave pic, signal master PIC
 167                  */
 168                 pic_set_irq1(&s->pics[0], 2, 1);
 169                 pic_set_irq1(&s->pics[0], 2, 0);
 170         }
 171         irq = pic_get_irq(&s->pics[0]);
 172         if (irq >= 0)
 173                 s->irq_request(s->irq_request_opaque, 1);
 174         else
 175                 s->irq_request(s->irq_request_opaque, 0);
 176 }
 177
 178 void kvm_pic_update_irq(struct kvm_pic *s)
 179 {
 180         pic_lock(s);
 181         pic_update_irq(s);
 182         pic_unlock(s);
 183 }
 184
 185 int kvm_pic_set_irq(void *opaque, int irq, int level)
 186 {
 187         struct kvm_pic *s = opaque;
 188         int ret = -1;
 189
 190         pic_lock(s);
 191         if (irq >= 0 && irq < PIC_NUM_PINS) {
 192                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 193                 pic_update_irq(s);
 194                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 195                                       s->pics[irq >> 3].imr, ret == 0);
 196         }
 197         pic_unlock(s);
 198
 199         return ret;
 200 }
 201
 202 /*
 203  * acknowledge interrupt 'irq'
 204  */
 205 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 206 {
 207         s->isr |= 1 << irq;
 208         if (s->auto_eoi) {
 209                 if (s->rotate_on_auto_eoi)
 210                         s->priority_add = (irq + 1) & 7;
 211                 pic_clear_isr(s, irq);
 212         }
 213         /*
 214          * We don't clear a level sensitive interrupt here
 215          */
 216         if (!(s->elcr & (1 << irq)))
 217                 s->irr &= ~(1 << irq);
 218 }
 219
 220 int kvm_pic_read_irq(struct kvm *kvm)
 221 {
 222         int irq, irq2, intno;
 223         struct kvm_pic *s = pic_irqchip(kvm);
 224
 225         pic_lock(s);
 226         irq = pic_get_irq(&s->pics[0]);
 227         if (irq >= 0) {
 228                 pic_intack(&s->pics[0], irq);
 229                 if (irq == 2) {
 230                         irq2 = pic_get_irq(&s->pics[1]);
 231                         if (irq2 >= 0)
 232                                 pic_intack(&s->pics[1], irq2);
 233                         else
 234                                 /*
 235                                  * spurious IRQ on slave controller
 236                                  */
 237                                 irq2 = 7;
 238                         intno = s->pics[1].irq_base + irq2;
 239                         irq = irq2 + 8;
 240                 } else
 241                         intno = s->pics[0].irq_base + irq;
 242         } else {
 243                 /*
 244                  * spurious IRQ on host controller
 245                  */
 246                 irq = 7;
 247                 intno = s->pics[0].irq_base + irq;
 248         }
 249         pic_update_irq(s);
 250         pic_unlock(s);
 251         kvm_notify_acked_irq(kvm, SELECT_PIC(irq), irq);
 252
 253         return intno;
 254 }
 255
 256 void kvm_pic_reset(struct kvm_kpic_state *s)
 257 {
 258         int irq, irqbase, n;
 259         struct kvm *kvm = s->pics_state->irq_request_opaque;
 260         struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu;
 261
 262         if (s == &s->pics_state->pics[0])
 263                 irqbase = 0;
 264         else
 265                 irqbase = 8;
 266
 267         for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
 268                 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
 269                         if (s->irr & (1 << irq) || s->isr & (1 << irq)) {
 270                                 n = irq + irqbase;
 271                                 s->pics_state->pending_acks |= 1 << n;
 272                         }
 273         }
 274         s->last_irr = 0;
 275         s->irr = 0;
 276         s->imr = 0;
 277         s->isr = 0;
 278         s->isr_ack = 0xff;
 279         s->priority_add = 0;
 280         s->irq_base = 0;
 281         s->read_reg_select = 0;
 282         s->poll = 0;
 283         s->special_mask = 0;
 284         s->init_state = 0;
 285         s->auto_eoi = 0;
 286         s->rotate_on_auto_eoi = 0;
 287         s->special_fully_nested_mode = 0;
 288         s->init4 = 0;
 289 }
 290
 291 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 292 {
 293         struct kvm_kpic_state *s = opaque;
 294         int priority, cmd, irq;
 295
 296         addr &= 1;
 297         if (addr == 0) {
 298                 if (val & 0x10) {
 299                         kvm_pic_reset(s);       /* init */
 300                         /*
 301                          * deassert a pending interrupt
 302                          */
 303                         s->pics_state->irq_request(s->pics_state->
 304                                                    irq_request_opaque, 0);
 305                         s->init_state = 1;
 306                         s->init4 = val & 1;
 307                         if (val & 0x02)
 308                                 printk(KERN_ERR "single mode not supported");
 309                         if (val & 0x08)
 310                                 printk(KERN_ERR
 311                                        "level sensitive irq not supported");
 312                 } else if (val & 0x08) {
 313                         if (val & 0x04)
 314                                 s->poll = 1;
 315                         if (val & 0x02)
 316                                 s->read_reg_select = val & 1;
 317                         if (val & 0x40)
 318                                 s->special_mask = (val >> 5) & 1;
 319                 } else {
 320                         cmd = val >> 5;
 321                         switch (cmd) {
 322                         case 0:
 323                         case 4:
 324                                 s->rotate_on_auto_eoi = cmd >> 2;
 325                                 break;
 326                         case 1: /* end of interrupt */
 327                         case 5:
 328                                 priority = get_priority(s, s->isr);
 329                                 if (priority != 8) {
 330                                         irq = (priority + s->priority_add) & 7;
 331                                         pic_clear_isr(s, irq);
 332                                         if (cmd == 5)
 333                                                 s->priority_add = (irq + 1) & 7;
 334                                         pic_update_irq(s->pics_state);
 335                                 }
 336                                 break;
 337                         case 3:
 338                                 irq = val & 7;
 339                                 pic_clear_isr(s, irq);
 340                                 pic_update_irq(s->pics_state);
 341                                 break;
 342                         case 6:
 343                                 s->priority_add = (val + 1) & 7;
 344                                 pic_update_irq(s->pics_state);
 345                                 break;
 346                         case 7:
 347                                 irq = val & 7;
 348                                 s->priority_add = (irq + 1) & 7;
 349                                 pic_clear_isr(s, irq);
 350                                 pic_update_irq(s->pics_state);
 351                                 break;
 352                         default:
 353                                 break;  /* no operation */
 354                         }
 355                 }
 356         } else
 357                 switch (s->init_state) {
 358                 case 0:         /* normal mode */
 359                         s->imr = val;
 360                         pic_update_irq(s->pics_state);
 361                         break;
 362                 case 1:
 363                         s->irq_base = val & 0xf8;
 364                         s->init_state = 2;
 365                         break;
 366                 case 2:
 367                         if (s->init4)
 368                                 s->init_state = 3;
 369                         else
 370                                 s->init_state = 0;
 371                         break;
 372                 case 3:
 373                         s->special_fully_nested_mode = (val >> 4) & 1;
 374                         s->auto_eoi = (val >> 1) & 1;
 375                         s->init_state = 0;
 376                         break;
 377                 }
 378 }
 379
 380 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 381 {
 382         int ret;
 383
 384         ret = pic_get_irq(s);
 385         if (ret >= 0) {
 386                 if (addr1 >> 7) {
 387                         s->pics_state->pics[0].isr &= ~(1 << 2);
 388                         s->pics_state->pics[0].irr &= ~(1 << 2);
 389                 }
 390                 s->irr &= ~(1 << ret);
 391                 pic_clear_isr(s, ret);
 392                 if (addr1 >> 7 || ret != 2)
 393                         pic_update_irq(s->pics_state);
 394         } else {
 395                 ret = 0x07;
 396                 pic_update_irq(s->pics_state);
 397         }
 398
 399         return ret;
 400 }
 401
 402 static u32 pic_ioport_read(void *opaque, u32 addr1)
 403 {
 404         struct kvm_kpic_state *s = opaque;
 405         unsigned int addr;
 406         int ret;
 407
 408         addr = addr1;
 409         addr &= 1;
 410         if (s->poll) {
 411                 ret = pic_poll_read(s, addr1);
 412                 s->poll = 0;
 413         } else
 414                 if (addr == 0)
 415                         if (s->read_reg_select)
 416                                 ret = s->isr;
 417                         else
 418                                 ret = s->irr;
 419                 else
 420                         ret = s->imr;
 421         return ret;
 422 }
 423
 424 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 425 {
 426         struct kvm_kpic_state *s = opaque;
 427         s->elcr = val & s->elcr_mask;
 428 }
 429
 430 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 431 {
 432         struct kvm_kpic_state *s = opaque;
 433         return s->elcr;
 434 }
 435
 436 static int picdev_in_range(gpa_t addr)
 437 {
 438         switch (addr) {
 439         case 0x20:
 440         case 0x21:
 441         case 0xa0:
 442         case 0xa1:
 443         case 0x4d0:
 444         case 0x4d1:
 445                 return 1;
 446         default:
 447                 return 0;
 448         }
 449 }
 450
 451 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
 452 {
 453         return container_of(dev, struct kvm_pic, dev);
 454 }
 455
 456 static int picdev_write(struct kvm_io_device *this,
 457                          gpa_t addr, int len, const void *val)
 458 {
 459         struct kvm_pic *s = to_pic(this);
 460         unsigned char data = *(unsigned char *)val;
 461         if (!picdev_in_range(addr))
 462                 return -EOPNOTSUPP;
 463
 464         if (len != 1) {
 465                 if (printk_ratelimit())
 466                         printk(KERN_ERR "PIC: non byte write\n");
 467                 return 0;
 468         }
 469         pic_lock(s);
 470         switch (addr) {
 471         case 0x20:
 472         case 0x21:
 473         case 0xa0:
 474         case 0xa1:
 475                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 476                 break;
 477         case 0x4d0:
 478         case 0x4d1:
 479                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 480                 break;
 481         }
 482         pic_unlock(s);
 483         return 0;
 484 }
 485
 486 static int picdev_read(struct kvm_io_device *this,
 487                        gpa_t addr, int len, void *val)
 488 {
 489         struct kvm_pic *s = to_pic(this);
 490         unsigned char data = 0;
 491         if (!picdev_in_range(addr))
 492                 return -EOPNOTSUPP;
 493
 494         if (len != 1) {
 495                 if (printk_ratelimit())
 496                         printk(KERN_ERR "PIC: non byte read\n");
 497                 return 0;
 498         }
 499         pic_lock(s);
 500         switch (addr) {
 501         case 0x20:
 502         case 0x21:
 503         case 0xa0:
 504         case 0xa1:
 505                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 506                 break;
 507         case 0x4d0:
 508         case 0x4d1:
 509                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 510                 break;
 511         }
 512         *(unsigned char *)val = data;
 513         pic_unlock(s);
 514         return 0;
 515 }
 516
 517 /*
 518  * callback when PIC0 irq status changed
 519  */
 520 static void pic_irq_request(void *opaque, int level)
 521 {
 522         struct kvm *kvm = opaque;
 523         struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
 524         struct kvm_pic *s = pic_irqchip(kvm);
 525         int irq = pic_get_irq(&s->pics[0]);
 526
 527         s->output = level;
 528         if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
 529                 s->pics[0].isr_ack &= ~(1 << irq);
 530                 s->wakeup_needed = true;
 531         }
 532 }
 533
 534 static const struct kvm_io_device_ops picdev_ops = {
 535         .read     = picdev_read,
 536         .write    = picdev_write,
 537 };
 538
 539 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 540 {
 541         struct kvm_pic *s;
 542         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 543         if (!s)
 544                 return NULL;
 545         spin_lock_init(&s->lock);
 546         s->kvm = kvm;
 547         s->pics[0].elcr_mask = 0xf8;
 548         s->pics[1].elcr_mask = 0xde;
 549         s->irq_request = pic_irq_request;
 550         s->irq_request_opaque = kvm;
 551         s->pics[0].pics_state = s;
 552         s->pics[1].pics_state = s;
 553
 554         /*
 555          * Initialize PIO device
 556          */
 557         kvm_iodevice_init(&s->dev, &picdev_ops);
 558         kvm_io_bus_register_dev(kvm, &kvm->pio_bus, &s->dev);
 559         return s;
 560 }