1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/module.h>
5 #include <linux/timer.h>
6 #include <linux/acpi_pmtmr.h>
7 #include <linux/cpufreq.h>
9 #include <linux/delay.h>
10 #include <linux/clocksource.h>
11 #include <linux/percpu.h>
14 #include <asm/timer.h>
15 #include <asm/vgtod.h>
17 #include <asm/delay.h>
19 unsigned int cpu_khz; /* TSC clocks / usec, not used here */
20 EXPORT_SYMBOL(cpu_khz);
22 EXPORT_SYMBOL(tsc_khz);
25 * TSC can be unstable due to cpufreq or due to unsynced TSCs
27 static int tsc_unstable;
29 /* native_sched_clock() is called before tsc_init(), so
30 we must start with the TSC soft disabled to prevent
31 erroneous rdtsc usage on !cpu_has_tsc processors */
32 static int tsc_disabled = -1;
35 * Scheduler clock - returns current time in nanosec units.
37 u64 native_sched_clock(void)
42 * Fall back to jiffies if there's no TSC available:
43 * ( But note that we still use it if the TSC is marked
44 * unstable. We do this because unlike Time Of Day,
45 * the scheduler clock tolerates small errors and it's
46 * very important for it to be as fast as the platform
49 if (unlikely(tsc_disabled)) {
50 /* No locking but a rare wrong value is not a big deal: */
51 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
54 /* read the Time Stamp Counter: */
57 /* return the value in ns */
58 return cycles_2_ns(this_offset);
61 /* We need to define a real function for sched_clock, to override the
62 weak default version */
63 #ifdef CONFIG_PARAVIRT
64 unsigned long long sched_clock(void)
66 return paravirt_sched_clock();
70 sched_clock(void) __attribute__((alias("native_sched_clock")));
73 int check_tsc_unstable(void)
77 EXPORT_SYMBOL_GPL(check_tsc_unstable);
80 int __init notsc_setup(char *str)
82 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
83 "cannot disable TSC completely.\n");
89 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
92 int __init notsc_setup(char *str)
94 setup_clear_cpu_cap(X86_FEATURE_TSC);
99 __setup("notsc", notsc_setup);
101 #define MAX_RETRIES 5
102 #define SMI_TRESHOLD 50000
105 * Read TSC and the reference counters. Take care of SMI disturbance
107 static u64 tsc_read_refs(u64 *p, int hpet)
112 for (i = 0; i < MAX_RETRIES; i++) {
115 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
117 *p = acpi_pm_read_early();
119 if ((t2 - t1) < SMI_TRESHOLD)
126 * Calculate the TSC frequency from HPET reference
128 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
133 hpet2 += 0x100000000ULL;
135 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
136 do_div(tmp, 1000000);
137 do_div(deltatsc, tmp);
139 return (unsigned long) deltatsc;
143 * Calculate the TSC frequency from PMTimer reference
145 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
153 pm2 += (u64)ACPI_PM_OVRRUN;
155 tmp = pm2 * 1000000000LL;
156 do_div(tmp, PMTMR_TICKS_PER_SEC);
157 do_div(deltatsc, tmp);
159 return (unsigned long) deltatsc;
163 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
164 #define CAL_PIT_LOOPS 1000
167 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
168 #define CAL2_PIT_LOOPS 5000
172 * Try to calibrate the TSC against the Programmable
173 * Interrupt Timer and return the frequency of the TSC
176 * Return ULONG_MAX on failure to calibrate.
178 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
180 u64 tsc, t1, t2, delta;
181 unsigned long tscmin, tscmax;
184 /* Set the Gate high, disable speaker */
185 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
188 * Setup CTC channel 2* for mode 0, (interrupt on terminal
189 * count mode), binary count. Set the latch register to 50ms
190 * (LSB then MSB) to begin countdown.
193 outb(latch & 0xff, 0x42);
194 outb(latch >> 8, 0x42);
196 tsc = t1 = t2 = get_cycles();
201 while ((inb(0x61) & 0x20) == 0) {
205 if ((unsigned long) delta < tscmin)
206 tscmin = (unsigned int) delta;
207 if ((unsigned long) delta > tscmax)
208 tscmax = (unsigned int) delta;
215 * If we were not able to read the PIT more than loopmin
216 * times, then we have been hit by a massive SMI
218 * If the maximum is 10 times larger than the minimum,
219 * then we got hit by an SMI as well.
221 if (pitcnt < loopmin || tscmax > 10 * tscmin)
224 /* Calculate the PIT value */
231 * This reads the current MSB of the PIT counter, and
232 * checks if we are running on sufficiently fast and
233 * non-virtualized hardware.
235 * Our expectations are:
237 * - the PIT is running at roughly 1.19MHz
239 * - each IO is going to take about 1us on real hardware,
240 * but we allow it to be much faster (by a factor of 10) or
241 * _slightly_ slower (ie we allow up to a 2us read+counter
242 * update - anything else implies a unacceptably slow CPU
243 * or PIT for the fast calibration to work.
245 * - with 256 PIT ticks to read the value, we have 214us to
246 * see the same MSB (and overhead like doing a single TSC
247 * read per MSB value etc).
249 * - We're doing 2 reads per loop (LSB, MSB), and we expect
250 * them each to take about a microsecond on real hardware.
251 * So we expect a count value of around 100. But we'll be
252 * generous, and accept anything over 50.
254 * - if the PIT is stuck, and we see *many* more reads, we
255 * return early (and the next caller of pit_expect_msb()
256 * then consider it a failure when they don't see the
257 * next expected value).
259 * These expectations mean that we know that we have seen the
260 * transition from one expected value to another with a fairly
261 * high accuracy, and we didn't miss any events. We can thus
262 * use the TSC value at the transitions to calculate a pretty
263 * good value for the TSC frequencty.
265 static inline int pit_expect_msb(unsigned char val)
269 for (count = 0; count < 50000; count++) {
272 if (inb(0x42) != val)
279 * How many MSB values do we want to see? We aim for a
280 * 15ms calibration, which assuming a 2us counter read
281 * error should give us roughly 150 ppm precision for
284 #define QUICK_PIT_MS 15
285 #define QUICK_PIT_ITERATIONS (QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
287 static unsigned long quick_pit_calibrate(void)
289 /* Set the Gate high, disable speaker */
290 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
293 * Counter 2, mode 0 (one-shot), binary count
295 * NOTE! Mode 2 decrements by two (and then the
296 * output is flipped each time, giving the same
297 * final output frequency as a decrement-by-one),
298 * so mode 0 is much better when looking at the
303 /* Start at 0xffff */
307 if (pit_expect_msb(0xff)) {
310 unsigned char expect = 0xfe;
313 for (i = 0; i < QUICK_PIT_ITERATIONS; i++, expect--) {
314 if (!pit_expect_msb(expect))
320 * Ok, if we get here, then we've seen the
321 * MSB of the PIT decrement QUICK_PIT_ITERATIONS
322 * times, and each MSB had many hits, so we never
323 * had any sudden jumps.
325 * As a result, we can depend on there not being
326 * any odd delays anywhere, and the TSC reads are
329 * kHz = ticks / time-in-seconds / 1000;
330 * kHz = (t2 - t1) / (QPI * 256 / PIT_TICK_RATE) / 1000
331 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (QPI * 256 * 1000)
333 delta = (t2 - t1)*PIT_TICK_RATE;
334 do_div(delta, QUICK_PIT_ITERATIONS*256*1000);
335 printk("Fast TSC calibration using PIT\n");
343 * native_calibrate_tsc - calibrate the tsc on boot
345 unsigned long native_calibrate_tsc(void)
347 u64 tsc1, tsc2, delta, ref1, ref2;
348 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
349 unsigned long flags, latch, ms, fast_calibrate;
350 int hpet = is_hpet_enabled(), i, loopmin;
352 local_irq_save(flags);
353 fast_calibrate = quick_pit_calibrate();
354 local_irq_restore(flags);
356 return fast_calibrate;
359 * Run 5 calibration loops to get the lowest frequency value
360 * (the best estimate). We use two different calibration modes
363 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
364 * load a timeout of 50ms. We read the time right after we
365 * started the timer and wait until the PIT count down reaches
366 * zero. In each wait loop iteration we read the TSC and check
367 * the delta to the previous read. We keep track of the min
368 * and max values of that delta. The delta is mostly defined
369 * by the IO time of the PIT access, so we can detect when a
370 * SMI/SMM disturbance happend between the two reads. If the
371 * maximum time is significantly larger than the minimum time,
372 * then we discard the result and have another try.
374 * 2) Reference counter. If available we use the HPET or the
375 * PMTIMER as a reference to check the sanity of that value.
376 * We use separate TSC readouts and check inside of the
377 * reference read for a SMI/SMM disturbance. We dicard
378 * disturbed values here as well. We do that around the PIT
379 * calibration delay loop as we have to wait for a certain
380 * amount of time anyway.
383 /* Preset PIT loop values */
386 loopmin = CAL_PIT_LOOPS;
388 for (i = 0; i < 3; i++) {
389 unsigned long tsc_pit_khz;
392 * Read the start value and the reference count of
393 * hpet/pmtimer when available. Then do the PIT
394 * calibration, which will take at least 50ms, and
395 * read the end value.
397 local_irq_save(flags);
398 tsc1 = tsc_read_refs(&ref1, hpet);
399 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
400 tsc2 = tsc_read_refs(&ref2, hpet);
401 local_irq_restore(flags);
403 /* Pick the lowest PIT TSC calibration so far */
404 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
406 /* hpet or pmtimer available ? */
407 if (!hpet && !ref1 && !ref2)
410 /* Check, whether the sampling was disturbed by an SMI */
411 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
414 tsc2 = (tsc2 - tsc1) * 1000000LL;
416 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
418 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
420 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
422 /* Check the reference deviation */
423 delta = ((u64) tsc_pit_min) * 100;
424 do_div(delta, tsc_ref_min);
427 * If both calibration results are inside a 10% window
428 * then we can be sure, that the calibration
429 * succeeded. We break out of the loop right away. We
430 * use the reference value, as it is more precise.
432 if (delta >= 90 && delta <= 110) {
434 "TSC: PIT calibration matches %s. %d loops\n",
435 hpet ? "HPET" : "PMTIMER", i + 1);
440 * Check whether PIT failed more than once. This
441 * happens in virtualized environments. We need to
442 * give the virtual PC a slightly longer timeframe for
443 * the HPET/PMTIMER to make the result precise.
445 if (i == 1 && tsc_pit_min == ULONG_MAX) {
448 loopmin = CAL2_PIT_LOOPS;
453 * Now check the results.
455 if (tsc_pit_min == ULONG_MAX) {
456 /* PIT gave no useful value */
457 printk(KERN_WARNING "TSC: PIT calibration failed due to "
458 "SMI disturbance.\n");
460 /* We don't have an alternative source, disable TSC */
461 if (!hpet && !ref1 && !ref2) {
462 printk("TSC: No reference (HPET/PMTIMER) available\n");
466 /* The alternative source failed as well, disable TSC */
467 if (tsc_ref_min == ULONG_MAX) {
468 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
473 /* Use the alternative source */
474 printk(KERN_INFO "TSC: using %s reference calibration\n",
475 hpet ? "HPET" : "PMTIMER");
480 /* We don't have an alternative source, use the PIT calibration value */
481 if (!hpet && !ref1 && !ref2) {
482 printk(KERN_INFO "TSC: Using PIT calibration value\n");
486 /* The alternative source failed, use the PIT calibration value */
487 if (tsc_ref_min == ULONG_MAX) {
488 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
489 "Using PIT calibration\n");
494 * The calibration values differ too much. In doubt, we use
495 * the PIT value as we know that there are PMTIMERs around
496 * running at double speed. At least we let the user know:
498 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
499 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
500 printk(KERN_INFO "TSC: Using PIT calibration value\n");
505 /* Only called from the Powernow K7 cpu freq driver */
506 int recalibrate_cpu_khz(void)
509 unsigned long cpu_khz_old = cpu_khz;
512 tsc_khz = calibrate_tsc();
514 cpu_data(0).loops_per_jiffy =
515 cpufreq_scale(cpu_data(0).loops_per_jiffy,
516 cpu_khz_old, cpu_khz);
525 EXPORT_SYMBOL(recalibrate_cpu_khz);
527 #endif /* CONFIG_X86_32 */
529 /* Accelerators for sched_clock()
530 * convert from cycles(64bits) => nanoseconds (64bits)
532 * ns = cycles / (freq / ns_per_sec)
533 * ns = cycles * (ns_per_sec / freq)
534 * ns = cycles * (10^9 / (cpu_khz * 10^3))
535 * ns = cycles * (10^6 / cpu_khz)
537 * Then we use scaling math (suggested by george@mvista.com) to get:
538 * ns = cycles * (10^6 * SC / cpu_khz) / SC
539 * ns = cycles * cyc2ns_scale / SC
541 * And since SC is a constant power of two, we can convert the div
544 * We can use khz divisor instead of mhz to keep a better precision, since
545 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
546 * (mathieu.desnoyers@polymtl.ca)
548 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
551 DEFINE_PER_CPU(unsigned long, cyc2ns);
553 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
555 unsigned long long tsc_now, ns_now;
556 unsigned long flags, *scale;
558 local_irq_save(flags);
559 sched_clock_idle_sleep_event();
561 scale = &per_cpu(cyc2ns, cpu);
564 ns_now = __cycles_2_ns(tsc_now);
567 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
569 sched_clock_idle_wakeup_event(0);
570 local_irq_restore(flags);
573 #ifdef CONFIG_CPU_FREQ
575 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
578 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
579 * not that important because current Opteron setups do not support
580 * scaling on SMP anyroads.
582 * Should fix up last_tsc too. Currently gettimeofday in the
583 * first tick after the change will be slightly wrong.
586 static unsigned int ref_freq;
587 static unsigned long loops_per_jiffy_ref;
588 static unsigned long tsc_khz_ref;
590 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
593 struct cpufreq_freqs *freq = data;
594 unsigned long *lpj, dummy;
596 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
600 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
602 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
604 lpj = &boot_cpu_data.loops_per_jiffy;
608 ref_freq = freq->old;
609 loops_per_jiffy_ref = *lpj;
610 tsc_khz_ref = tsc_khz;
612 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
613 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
614 (val == CPUFREQ_RESUMECHANGE)) {
615 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
617 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
618 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
619 mark_tsc_unstable("cpufreq changes");
622 set_cyc2ns_scale(tsc_khz, freq->cpu);
627 static struct notifier_block time_cpufreq_notifier_block = {
628 .notifier_call = time_cpufreq_notifier
631 static int __init cpufreq_tsc(void)
635 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
637 cpufreq_register_notifier(&time_cpufreq_notifier_block,
638 CPUFREQ_TRANSITION_NOTIFIER);
642 core_initcall(cpufreq_tsc);
644 #endif /* CONFIG_CPU_FREQ */
646 /* clocksource code */
648 static struct clocksource clocksource_tsc;
651 * We compare the TSC to the cycle_last value in the clocksource
652 * structure to avoid a nasty time-warp. This can be observed in a
653 * very small window right after one CPU updated cycle_last under
654 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
655 * is smaller than the cycle_last reference value due to a TSC which
656 * is slighty behind. This delta is nowhere else observable, but in
657 * that case it results in a forward time jump in the range of hours
658 * due to the unsigned delta calculation of the time keeping core
659 * code, which is necessary to support wrapping clocksources like pm
662 static cycle_t read_tsc(void)
664 cycle_t ret = (cycle_t)get_cycles();
666 return ret >= clocksource_tsc.cycle_last ?
667 ret : clocksource_tsc.cycle_last;
671 static cycle_t __vsyscall_fn vread_tsc(void)
673 cycle_t ret = (cycle_t)vget_cycles();
675 return ret >= __vsyscall_gtod_data.clock.cycle_last ?
676 ret : __vsyscall_gtod_data.clock.cycle_last;
680 static struct clocksource clocksource_tsc = {
684 .mask = CLOCKSOURCE_MASK(64),
686 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
687 CLOCK_SOURCE_MUST_VERIFY,
693 void mark_tsc_unstable(char *reason)
697 printk("Marking TSC unstable due to %s\n", reason);
698 /* Change only the rating, when not registered */
699 if (clocksource_tsc.mult)
700 clocksource_change_rating(&clocksource_tsc, 0);
702 clocksource_tsc.rating = 0;
706 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
708 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
710 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
716 /* List of systems that have known TSC problems */
717 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
719 .callback = dmi_mark_tsc_unstable,
720 .ident = "IBM Thinkpad 380XD",
722 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
723 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
730 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
732 #ifdef CONFIG_MGEODE_LX
733 /* RTSC counts during suspend */
734 #define RTSC_SUSP 0x100
736 static void __init check_geode_tsc_reliable(void)
738 unsigned long res_low, res_high;
740 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
741 if (res_low & RTSC_SUSP)
742 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
745 static inline void check_geode_tsc_reliable(void) { }
749 * Make an educated guess if the TSC is trustworthy and synchronized
752 __cpuinit int unsynchronized_tsc(void)
754 if (!cpu_has_tsc || tsc_unstable)
758 if (apic_is_clustered_box())
762 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
765 * Intel systems are normally all synchronized.
766 * Exceptions must mark TSC as unstable:
768 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
769 /* assume multi socket systems are not synchronized: */
770 if (num_possible_cpus() > 1)
777 static void __init init_tsc_clocksource(void)
779 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
780 clocksource_tsc.shift);
781 /* lower the rating if we already know its unstable: */
782 if (check_tsc_unstable()) {
783 clocksource_tsc.rating = 0;
784 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
786 clocksource_register(&clocksource_tsc);
789 void __init tsc_init(void)
797 tsc_khz = calibrate_tsc();
801 mark_tsc_unstable("could not calculate TSC khz");
806 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
807 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
808 cpu_khz = calibrate_cpu();
811 lpj = ((u64)tsc_khz * 1000);
815 printk("Detected %lu.%03lu MHz processor.\n",
816 (unsigned long)cpu_khz / 1000,
817 (unsigned long)cpu_khz % 1000);
820 * Secondary CPUs do not run through tsc_init(), so set up
821 * all the scale factors for all CPUs, assuming the same
822 * speed as the bootup CPU. (cpufreq notifiers will fix this
823 * up if their speed diverges)
825 for_each_possible_cpu(cpu)
826 set_cyc2ns_scale(cpu_khz, cpu);
828 if (tsc_disabled > 0)
831 /* now allow native_sched_clock() to use rdtsc */
835 /* Check and install the TSC clocksource */
836 dmi_check_system(bad_tsc_dmi_table);
838 if (unsynchronized_tsc())
839 mark_tsc_unstable("TSCs unsynchronized");
841 check_geode_tsc_reliable();
842 init_tsc_clocksource();