2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
56 #include <asm/trampoline.h>
59 #include <asm/pgtable.h>
60 #include <asm/tlbflush.h>
63 #include <asm/genapic.h>
64 #include <asm/setup.h>
65 #include <asm/uv/uv.h>
66 #include <linux/mc146818rtc.h>
68 #include <mach_apic.h>
69 #include <mach_wakecpu.h>
70 #include <smpboot_hooks.h>
73 u8 apicid_2_node[MAX_APICID];
74 static int low_mappings;
77 /* State of each CPU */
78 DEFINE_PER_CPU(int, cpu_state) = { 0 };
80 /* Store all idle threads, this can be reused instead of creating
81 * a new thread. Also avoids complicated thread destroy functionality
84 #ifdef CONFIG_HOTPLUG_CPU
86 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
87 * removed after init for !CONFIG_HOTPLUG_CPU.
89 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
90 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
91 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
93 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
94 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
95 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
98 /* Number of siblings per CPU package */
99 int smp_num_siblings = 1;
100 EXPORT_SYMBOL(smp_num_siblings);
102 /* Last level cache ID of each logical CPU */
103 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
105 /* representing HT siblings of each logical CPU */
106 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
107 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
109 /* representing HT and core siblings of each logical CPU */
110 DEFINE_PER_CPU(cpumask_t, cpu_core_map);
111 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
113 /* Per CPU bogomips and other parameters */
114 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
115 EXPORT_PER_CPU_SYMBOL(cpu_info);
117 static atomic_t init_deasserted;
120 /* Set if we find a B stepping CPU */
121 static int __cpuinitdata smp_b_stepping;
123 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
125 /* which logical CPUs are on which nodes */
126 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
127 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
128 EXPORT_SYMBOL(node_to_cpumask_map);
129 /* which node each logical CPU is on */
130 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
131 EXPORT_SYMBOL(cpu_to_node_map);
133 /* set up a mapping between cpu and node. */
134 static void map_cpu_to_node(int cpu, int node)
136 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
137 cpumask_set_cpu(cpu, &node_to_cpumask_map[node]);
138 cpu_to_node_map[cpu] = node;
141 /* undo a mapping between cpu and node. */
142 static void unmap_cpu_to_node(int cpu)
146 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
147 for (node = 0; node < MAX_NUMNODES; node++)
148 cpumask_clear_cpu(cpu, &node_to_cpumask_map[node]);
149 cpu_to_node_map[cpu] = 0;
151 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
152 #define map_cpu_to_node(cpu, node) ({})
153 #define unmap_cpu_to_node(cpu) ({})
157 static int boot_cpu_logical_apicid;
159 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
160 { [0 ... NR_CPUS-1] = BAD_APICID };
162 static void map_cpu_to_logical_apicid(void)
164 int cpu = smp_processor_id();
165 int apicid = logical_smp_processor_id();
166 int node = apic->apicid_to_node(apicid);
168 if (!node_online(node))
169 node = first_online_node;
171 cpu_2_logical_apicid[cpu] = apicid;
172 map_cpu_to_node(cpu, node);
175 void numa_remove_cpu(int cpu)
177 cpu_2_logical_apicid[cpu] = BAD_APICID;
178 unmap_cpu_to_node(cpu);
181 #define map_cpu_to_logical_apicid() do {} while (0)
185 * Report back to the Boot Processor.
188 static void __cpuinit smp_callin(void)
191 unsigned long timeout;
194 * If waken up by an INIT in an 82489DX configuration
195 * we may get here before an INIT-deassert IPI reaches
196 * our local APIC. We have to wait for the IPI or we'll
197 * lock up on an APIC access.
199 if (apic->wait_for_init_deassert)
200 apic->wait_for_init_deassert(&init_deasserted);
203 * (This works even if the APIC is not enabled.)
205 phys_id = read_apic_id();
206 cpuid = smp_processor_id();
207 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
208 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
211 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
214 * STARTUP IPIs are fragile beasts as they might sometimes
215 * trigger some glue motherboard logic. Complete APIC bus
216 * silence for 1 second, this overestimates the time the
217 * boot CPU is spending to send the up to 2 STARTUP IPIs
218 * by a factor of two. This should be enough.
222 * Waiting 2s total for startup (udelay is not yet working)
224 timeout = jiffies + 2*HZ;
225 while (time_before(jiffies, timeout)) {
227 * Has the boot CPU finished it's STARTUP sequence?
229 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
234 if (!time_before(jiffies, timeout)) {
235 panic("%s: CPU%d started up but did not get a callout!\n",
240 * the boot CPU has finished the init stage and is spinning
241 * on callin_map until we finish. We are free to set up this
242 * CPU, first the APIC. (this is probably redundant on most
246 pr_debug("CALLIN, before setup_local_APIC().\n");
247 smp_callin_clear_local_apic();
249 end_local_APIC_setup();
250 map_cpu_to_logical_apicid();
252 notify_cpu_starting(cpuid);
256 * Need to enable IRQs because it can take longer and then
257 * the NMI watchdog might kill us.
262 pr_debug("Stack at about %p\n", &cpuid);
265 * Save our processor parameters
267 smp_store_cpu_info(cpuid);
270 * Allow the master to continue.
272 cpumask_set_cpu(cpuid, cpu_callin_mask);
275 static int __cpuinitdata unsafe_smp;
278 * Activate a secondary processor.
280 notrace static void __cpuinit start_secondary(void *unused)
283 * Don't put *anything* before cpu_init(), SMP booting is too
284 * fragile that we want to limit the things done here to the
285 * most necessary things.
292 /* otherwise gcc will move up smp_processor_id before the cpu_init */
295 * Check TSC synchronization with the BP:
297 check_tsc_sync_target();
299 if (nmi_watchdog == NMI_IO_APIC) {
300 disable_8259A_irq(0);
301 enable_NMI_through_LVT0();
311 /* This must be done before setting cpu_online_map */
312 set_cpu_sibling_map(raw_smp_processor_id());
316 * We need to hold call_lock, so there is no inconsistency
317 * between the time smp_call_function() determines number of
318 * IPI recipients, and the time when the determination is made
319 * for which cpus receive the IPI. Holding this
320 * lock helps us to not include this cpu in a currently in progress
321 * smp_call_function().
323 * We need to hold vector_lock so there the set of online cpus
324 * does not change while we are assigning vectors to cpus. Holding
325 * this lock ensures we don't half assign or remove an irq from a cpu.
329 __setup_vector_irq(smp_processor_id());
330 set_cpu_online(smp_processor_id(), true);
331 unlock_vector_lock();
333 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
335 /* enable local interrupts */
338 setup_secondary_clock();
344 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
347 * Mask B, Pentium, but not Pentium MMX
349 if (c->x86_vendor == X86_VENDOR_INTEL &&
351 c->x86_mask >= 1 && c->x86_mask <= 4 &&
354 * Remember we have B step Pentia with bugs
359 * Certain Athlons might work (for various values of 'work') in SMP
360 * but they are not certified as MP capable.
362 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
364 if (num_possible_cpus() == 1)
367 /* Athlon 660/661 is valid. */
368 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
372 /* Duron 670 is valid */
373 if ((c->x86_model == 7) && (c->x86_mask == 0))
377 * Athlon 662, Duron 671, and Athlon >model 7 have capability
378 * bit. It's worth noting that the A5 stepping (662) of some
379 * Athlon XP's have the MP bit set.
380 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
383 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
384 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
389 /* If we get here, not a certified SMP capable AMD system. */
397 static void __cpuinit smp_checks(void)
400 printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
401 "with B stepping processors.\n");
404 * Don't taint if we are running SMP kernel on a single non-MP
407 if (unsafe_smp && num_online_cpus() > 1) {
408 printk(KERN_INFO "WARNING: This combination of AMD"
409 "processors is not suitable for SMP.\n");
410 add_taint(TAINT_UNSAFE_SMP);
415 * The bootstrap kernel entry code has set these up. Save them for
419 void __cpuinit smp_store_cpu_info(int id)
421 struct cpuinfo_x86 *c = &cpu_data(id);
426 identify_secondary_cpu(c);
431 void __cpuinit set_cpu_sibling_map(int cpu)
434 struct cpuinfo_x86 *c = &cpu_data(cpu);
436 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
438 if (smp_num_siblings > 1) {
439 for_each_cpu(i, cpu_sibling_setup_mask) {
440 struct cpuinfo_x86 *o = &cpu_data(i);
442 if (c->phys_proc_id == o->phys_proc_id &&
443 c->cpu_core_id == o->cpu_core_id) {
444 cpumask_set_cpu(i, cpu_sibling_mask(cpu));
445 cpumask_set_cpu(cpu, cpu_sibling_mask(i));
446 cpumask_set_cpu(i, cpu_core_mask(cpu));
447 cpumask_set_cpu(cpu, cpu_core_mask(i));
448 cpumask_set_cpu(i, &c->llc_shared_map);
449 cpumask_set_cpu(cpu, &o->llc_shared_map);
453 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
456 cpumask_set_cpu(cpu, &c->llc_shared_map);
458 if (current_cpu_data.x86_max_cores == 1) {
459 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
464 for_each_cpu(i, cpu_sibling_setup_mask) {
465 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
466 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
467 cpumask_set_cpu(i, &c->llc_shared_map);
468 cpumask_set_cpu(cpu, &cpu_data(i).llc_shared_map);
470 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
471 cpumask_set_cpu(i, cpu_core_mask(cpu));
472 cpumask_set_cpu(cpu, cpu_core_mask(i));
474 * Does this new cpu bringup a new core?
476 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
478 * for each core in package, increment
479 * the booted_cores for this new cpu
481 if (cpumask_first(cpu_sibling_mask(i)) == i)
484 * increment the core count for all
485 * the other cpus in this package
488 cpu_data(i).booted_cores++;
489 } else if (i != cpu && !c->booted_cores)
490 c->booted_cores = cpu_data(i).booted_cores;
495 /* maps the cpu to the sched domain representing multi-core */
496 const struct cpumask *cpu_coregroup_mask(int cpu)
498 struct cpuinfo_x86 *c = &cpu_data(cpu);
500 * For perf, we return last level cache shared map.
501 * And for power savings, we return cpu_core_map
503 if (sched_mc_power_savings || sched_smt_power_savings)
504 return cpu_core_mask(cpu);
506 return &c->llc_shared_map;
509 cpumask_t cpu_coregroup_map(int cpu)
511 return *cpu_coregroup_mask(cpu);
514 static void impress_friends(void)
517 unsigned long bogosum = 0;
519 * Allow the user to impress friends.
521 pr_debug("Before bogomips.\n");
522 for_each_possible_cpu(cpu)
523 if (cpumask_test_cpu(cpu, cpu_callout_mask))
524 bogosum += cpu_data(cpu).loops_per_jiffy;
526 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
529 (bogosum/(5000/HZ))%100);
531 pr_debug("Before bogocount - setting activated=1.\n");
534 void __inquire_remote_apic(int apicid)
536 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
537 char *names[] = { "ID", "VERSION", "SPIV" };
541 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
543 for (i = 0; i < ARRAY_SIZE(regs); i++) {
544 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
549 status = safe_apic_wait_icr_idle();
552 "a previous APIC delivery may have failed\n");
554 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
559 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
560 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
563 case APIC_ICR_RR_VALID:
564 status = apic_read(APIC_RRR);
565 printk(KERN_CONT "%08x\n", status);
568 printk(KERN_CONT "failed\n");
574 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
575 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
576 * won't ... remember to clear down the APIC, etc later.
579 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
581 unsigned long send_status, accept_status = 0;
585 /* Boot on the stack */
586 /* Kick the second */
587 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
589 pr_debug("Waiting for send to finish...\n");
590 send_status = safe_apic_wait_icr_idle();
593 * Give the other CPU some time to accept the IPI.
596 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
597 maxlvt = lapic_get_maxlvt();
598 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
599 apic_write(APIC_ESR, 0);
600 accept_status = (apic_read(APIC_ESR) & 0xEF);
602 pr_debug("NMI sent.\n");
605 printk(KERN_ERR "APIC never delivered???\n");
607 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
609 return (send_status | accept_status);
613 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
615 unsigned long send_status, accept_status = 0;
616 int maxlvt, num_starts, j;
618 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) {
619 send_status = uv_wakeup_secondary(phys_apicid, start_eip);
620 atomic_set(&init_deasserted, 1);
624 maxlvt = lapic_get_maxlvt();
627 * Be paranoid about clearing APIC errors.
629 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
630 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
631 apic_write(APIC_ESR, 0);
635 pr_debug("Asserting INIT.\n");
638 * Turn INIT on target chip
643 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
646 pr_debug("Waiting for send to finish...\n");
647 send_status = safe_apic_wait_icr_idle();
651 pr_debug("Deasserting INIT.\n");
655 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
657 pr_debug("Waiting for send to finish...\n");
658 send_status = safe_apic_wait_icr_idle();
661 atomic_set(&init_deasserted, 1);
664 * Should we send STARTUP IPIs ?
666 * Determine this based on the APIC version.
667 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
669 if (APIC_INTEGRATED(apic_version[phys_apicid]))
675 * Paravirt / VMI wants a startup IPI hook here to set up the
676 * target processor state.
678 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
679 (unsigned long)stack_start.sp);
682 * Run STARTUP IPI loop.
684 pr_debug("#startup loops: %d.\n", num_starts);
686 for (j = 1; j <= num_starts; j++) {
687 pr_debug("Sending STARTUP #%d.\n", j);
688 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
689 apic_write(APIC_ESR, 0);
691 pr_debug("After apic_write.\n");
698 /* Boot on the stack */
699 /* Kick the second */
700 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
704 * Give the other CPU some time to accept the IPI.
708 pr_debug("Startup point 1.\n");
710 pr_debug("Waiting for send to finish...\n");
711 send_status = safe_apic_wait_icr_idle();
714 * Give the other CPU some time to accept the IPI.
717 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
718 apic_write(APIC_ESR, 0);
719 accept_status = (apic_read(APIC_ESR) & 0xEF);
720 if (send_status || accept_status)
723 pr_debug("After Startup.\n");
726 printk(KERN_ERR "APIC never delivered???\n");
728 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
730 return (send_status | accept_status);
734 struct work_struct work;
735 struct task_struct *idle;
736 struct completion done;
740 static void __cpuinit do_fork_idle(struct work_struct *work)
742 struct create_idle *c_idle =
743 container_of(work, struct create_idle, work);
745 c_idle->idle = fork_idle(c_idle->cpu);
746 complete(&c_idle->done);
749 static int __cpuinit do_boot_cpu(int apicid, int cpu)
751 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
752 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
753 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
756 unsigned long boot_error = 0;
758 unsigned long start_ip;
759 unsigned short nmi_high = 0, nmi_low = 0;
760 struct create_idle c_idle = {
762 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
764 INIT_WORK(&c_idle.work, do_fork_idle);
766 alternatives_smp_switch(1);
768 c_idle.idle = get_idle_for_cpu(cpu);
771 * We can't use kernel_thread since we must avoid to
772 * reschedule the child.
775 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
776 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
777 init_idle(c_idle.idle, cpu);
781 if (!keventd_up() || current_is_keventd())
782 c_idle.work.func(&c_idle.work);
784 schedule_work(&c_idle.work);
785 wait_for_completion(&c_idle.done);
788 if (IS_ERR(c_idle.idle)) {
789 printk("failed fork for CPU %d\n", cpu);
790 return PTR_ERR(c_idle.idle);
793 set_idle_for_cpu(cpu, c_idle.idle);
795 per_cpu(current_task, cpu) = c_idle.idle;
797 /* Stack for startup_32 can be just as for start_secondary onwards */
800 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
801 initial_gs = per_cpu_offset(cpu);
802 per_cpu(kernel_stack, cpu) =
803 (unsigned long)task_stack_page(c_idle.idle) -
804 KERNEL_STACK_OFFSET + THREAD_SIZE;
806 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
807 initial_code = (unsigned long)start_secondary;
808 stack_start.sp = (void *) c_idle.idle->thread.sp;
810 /* start_ip had better be page-aligned! */
811 start_ip = setup_trampoline();
813 /* So we see what's up */
814 printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n",
815 cpu, apicid, start_ip);
818 * This grunge runs the startup process for
819 * the targeted processor.
822 atomic_set(&init_deasserted, 0);
824 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
826 pr_debug("Setting warm reset code and vector.\n");
828 store_NMI_vector(&nmi_high, &nmi_low);
830 smpboot_setup_warm_reset_vector(start_ip);
832 * Be paranoid about clearing APIC errors.
834 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
835 apic_write(APIC_ESR, 0);
841 * Starting actual IPI sequence...
843 boot_error = wakeup_secondary_cpu(apicid, start_ip);
847 * allow APs to start initializing.
849 pr_debug("Before Callout %d.\n", cpu);
850 cpumask_set_cpu(cpu, cpu_callout_mask);
851 pr_debug("After Callout %d.\n", cpu);
854 * Wait 5s total for a response
856 for (timeout = 0; timeout < 50000; timeout++) {
857 if (cpumask_test_cpu(cpu, cpu_callin_mask))
858 break; /* It has booted */
862 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
863 /* number CPUs logically, starting from 1 (BSP is 0) */
865 printk(KERN_INFO "CPU%d: ", cpu);
866 print_cpu_info(&cpu_data(cpu));
867 pr_debug("CPU has booted.\n");
870 if (*((volatile unsigned char *)trampoline_base)
872 /* trampoline started but...? */
873 printk(KERN_ERR "Stuck ??\n");
875 /* trampoline code not run */
876 printk(KERN_ERR "Not responding.\n");
877 if (get_uv_system_type() != UV_NON_UNIQUE_APIC)
878 inquire_remote_apic(apicid);
883 /* Try to put things back the way they were before ... */
884 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
886 /* was set by do_boot_cpu() */
887 cpumask_clear_cpu(cpu, cpu_callout_mask);
889 /* was set by cpu_init() */
890 cpumask_clear_cpu(cpu, cpu_initialized_mask);
892 set_cpu_present(cpu, false);
893 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
896 /* mark "stuck" area as not stuck */
897 *((volatile unsigned long *)trampoline_base) = 0;
900 * Cleanup possible dangling ends...
902 smpboot_restore_warm_reset_vector();
908 int default_cpu_present_to_apicid(int mps_cpu)
910 return __default_cpu_present_to_apicid(mps_cpu);
913 int default_check_phys_apicid_present(int boot_cpu_physical_apicid)
915 return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
919 int __cpuinit native_cpu_up(unsigned int cpu)
921 int apicid = apic->cpu_present_to_apicid(cpu);
925 WARN_ON(irqs_disabled());
927 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
929 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
930 !physid_isset(apicid, phys_cpu_present_map)) {
931 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
936 * Already booted CPU?
938 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
939 pr_debug("do_boot_cpu %d Already started\n", cpu);
944 * Save current MTRR state in case it was changed since early boot
945 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
949 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
952 /* init low mem mapping */
953 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY,
954 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
958 err = do_boot_cpu(apicid, cpu);
963 err = do_boot_cpu(apicid, cpu);
966 pr_debug("do_boot_cpu failed %d\n", err);
971 * Check TSC synchronization with the AP (keep irqs disabled
974 local_irq_save(flags);
975 check_tsc_sync_source(cpu);
976 local_irq_restore(flags);
978 while (!cpu_online(cpu)) {
980 touch_nmi_watchdog();
987 * Fall back to non SMP mode after errors.
989 * RED-PEN audit/test this more. I bet there is more state messed up here.
991 static __init void disable_smp(void)
993 /* use the read/write pointers to the present and possible maps */
994 cpumask_copy(&cpu_present_map, cpumask_of(0));
995 cpumask_copy(&cpu_possible_map, cpumask_of(0));
996 smpboot_clear_io_apic_irqs();
998 if (smp_found_config)
999 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1001 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1002 map_cpu_to_logical_apicid();
1003 cpumask_set_cpu(0, cpu_sibling_mask(0));
1004 cpumask_set_cpu(0, cpu_core_mask(0));
1008 * Various sanity checks.
1010 static int __init smp_sanity_check(unsigned max_cpus)
1014 #if defined(CONFIG_X86_PC) && defined(CONFIG_X86_32)
1015 if (def_to_bigsmp && nr_cpu_ids > 8) {
1020 "More than 8 CPUs detected - skipping them.\n"
1021 "Use CONFIG_X86_GENERICARCH and CONFIG_X86_BIGSMP.\n");
1024 for_each_present_cpu(cpu) {
1026 set_cpu_present(cpu, false);
1031 for_each_possible_cpu(cpu) {
1033 set_cpu_possible(cpu, false);
1041 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1043 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1044 hard_smp_processor_id());
1046 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1050 * If we couldn't find an SMP configuration at boot time,
1051 * get out of here now!
1053 if (!smp_found_config && !acpi_lapic) {
1055 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1057 if (APIC_init_uniprocessor())
1058 printk(KERN_NOTICE "Local APIC not detected."
1059 " Using dummy APIC emulation.\n");
1064 * Should not be necessary because the MP table should list the boot
1065 * CPU too, but we do it for the sake of robustness anyway.
1067 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1069 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1070 boot_cpu_physical_apicid);
1071 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1076 * If we couldn't find a local APIC, then get out of here now!
1078 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1080 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1081 boot_cpu_physical_apicid);
1082 printk(KERN_ERR "... forcing use of dummy APIC emulation."
1083 "(tell your hw vendor)\n");
1084 smpboot_clear_io_apic();
1085 disable_ioapic_setup();
1089 verify_local_APIC();
1092 * If SMP should be disabled, then really disable it!
1095 printk(KERN_INFO "SMP mode deactivated.\n");
1096 smpboot_clear_io_apic();
1098 localise_nmi_watchdog();
1102 end_local_APIC_setup();
1109 static void __init smp_cpu_index_default(void)
1112 struct cpuinfo_x86 *c;
1114 for_each_possible_cpu(i) {
1116 /* mark all to hotplug */
1117 c->cpu_index = nr_cpu_ids;
1122 * Prepare for SMP bootup. The MP table or ACPI has been read
1123 * earlier. Just do some sanity checking here and enable APIC mode.
1125 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1128 smp_cpu_index_default();
1129 current_cpu_data = boot_cpu_data;
1130 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1133 * Setup boot CPU information
1135 smp_store_cpu_info(0); /* Final full version of the data */
1136 #ifdef CONFIG_X86_32
1137 boot_cpu_logical_apicid = logical_smp_processor_id();
1139 current_thread_info()->cpu = 0; /* needed? */
1140 set_cpu_sibling_map(0);
1142 #ifdef CONFIG_X86_64
1144 default_setup_apic_routing();
1147 if (smp_sanity_check(max_cpus) < 0) {
1148 printk(KERN_INFO "SMP disabled\n");
1154 if (read_apic_id() != boot_cpu_physical_apicid) {
1155 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1156 read_apic_id(), boot_cpu_physical_apicid);
1157 /* Or can we switch back to PIC here? */
1164 * Switch from PIC to APIC mode.
1168 #ifdef CONFIG_X86_64
1170 * Enable IO APIC before setting up error vector
1172 if (!skip_ioapic_setup && nr_ioapics)
1175 end_local_APIC_setup();
1177 map_cpu_to_logical_apicid();
1179 if (apic->setup_portio_remap)
1180 apic->setup_portio_remap();
1182 smpboot_setup_io_apic();
1184 * Set up local APIC timer on boot CPU.
1187 printk(KERN_INFO "CPU%d: ", 0);
1188 print_cpu_info(&cpu_data(0));
1197 * Early setup to make printk work.
1199 void __init native_smp_prepare_boot_cpu(void)
1201 int me = smp_processor_id();
1202 switch_to_new_gdt();
1203 /* already set me in cpu_online_mask in boot_cpu_init() */
1204 cpumask_set_cpu(me, cpu_callout_mask);
1205 per_cpu(cpu_state, me) = CPU_ONLINE;
1208 void __init native_smp_cpus_done(unsigned int max_cpus)
1210 pr_debug("Boot done.\n");
1214 #ifdef CONFIG_X86_IO_APIC
1215 setup_ioapic_dest();
1217 check_nmi_watchdog();
1220 static int __initdata setup_possible_cpus = -1;
1221 static int __init _setup_possible_cpus(char *str)
1223 get_option(&str, &setup_possible_cpus);
1226 early_param("possible_cpus", _setup_possible_cpus);
1230 * cpu_possible_map should be static, it cannot change as cpu's
1231 * are onlined, or offlined. The reason is per-cpu data-structures
1232 * are allocated by some modules at init time, and dont expect to
1233 * do this dynamically on cpu arrival/departure.
1234 * cpu_present_map on the other hand can change dynamically.
1235 * In case when cpu_hotplug is not compiled, then we resort to current
1236 * behaviour, which is cpu_possible == cpu_present.
1239 * Three ways to find out the number of additional hotplug CPUs:
1240 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1241 * - The user can overwrite it with possible_cpus=NUM
1242 * - Otherwise don't reserve additional CPUs.
1243 * We do this because additional CPUs waste a lot of memory.
1246 __init void prefill_possible_map(void)
1250 /* no processor from mptable or madt */
1251 if (!num_processors)
1254 if (setup_possible_cpus == -1)
1255 possible = num_processors + disabled_cpus;
1257 possible = setup_possible_cpus;
1259 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1261 if (possible > CONFIG_NR_CPUS) {
1263 "%d Processors exceeds NR_CPUS limit of %d\n",
1264 possible, CONFIG_NR_CPUS);
1265 possible = CONFIG_NR_CPUS;
1268 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1269 possible, max_t(int, possible - num_processors, 0));
1271 for (i = 0; i < possible; i++)
1272 set_cpu_possible(i, true);
1274 nr_cpu_ids = possible;
1277 #ifdef CONFIG_HOTPLUG_CPU
1279 static void remove_siblinginfo(int cpu)
1282 struct cpuinfo_x86 *c = &cpu_data(cpu);
1284 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1285 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1287 * last thread sibling in this cpu core going down
1289 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1290 cpu_data(sibling).booted_cores--;
1293 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1294 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1295 cpumask_clear(cpu_sibling_mask(cpu));
1296 cpumask_clear(cpu_core_mask(cpu));
1297 c->phys_proc_id = 0;
1299 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1302 static void __ref remove_cpu_from_maps(int cpu)
1304 set_cpu_online(cpu, false);
1305 cpumask_clear_cpu(cpu, cpu_callout_mask);
1306 cpumask_clear_cpu(cpu, cpu_callin_mask);
1307 /* was set by cpu_init() */
1308 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1309 numa_remove_cpu(cpu);
1312 void cpu_disable_common(void)
1314 int cpu = smp_processor_id();
1317 * Allow any queued timer interrupts to get serviced
1318 * This is only a temporary solution until we cleanup
1319 * fixup_irqs as we do for IA64.
1324 local_irq_disable();
1325 remove_siblinginfo(cpu);
1327 /* It's now safe to remove this processor from the online map */
1329 remove_cpu_from_maps(cpu);
1330 unlock_vector_lock();
1334 int native_cpu_disable(void)
1336 int cpu = smp_processor_id();
1339 * Perhaps use cpufreq to drop frequency, but that could go
1340 * into generic code.
1342 * We won't take down the boot processor on i386 due to some
1343 * interrupts only being able to be serviced by the BSP.
1344 * Especially so if we're not using an IOAPIC -zwane
1349 if (nmi_watchdog == NMI_LOCAL_APIC)
1350 stop_apic_nmi_watchdog(NULL);
1353 cpu_disable_common();
1357 void native_cpu_die(unsigned int cpu)
1359 /* We don't do anything here: idle task is faking death itself. */
1362 for (i = 0; i < 10; i++) {
1363 /* They ack this in play_dead by setting CPU_DEAD */
1364 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1365 printk(KERN_INFO "CPU %d is now offline\n", cpu);
1366 if (1 == num_online_cpus())
1367 alternatives_smp_switch(0);
1372 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1375 void play_dead_common(void)
1378 reset_lazy_tlbstate();
1379 irq_ctx_exit(raw_smp_processor_id());
1380 c1e_remove_cpu(raw_smp_processor_id());
1384 __get_cpu_var(cpu_state) = CPU_DEAD;
1387 * With physical CPU hotplug, we should halt the cpu
1389 local_irq_disable();
1392 void native_play_dead(void)
1398 #else /* ... !CONFIG_HOTPLUG_CPU */
1399 int native_cpu_disable(void)
1404 void native_cpu_die(unsigned int cpu)
1406 /* We said "no" in __cpu_disable */
1410 void native_play_dead(void)