2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <linux/efi.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/mmzone.h>
37 #include <linux/kexec.h>
38 #include <linux/cpufreq.h>
39 #include <linux/dmi.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ctype.h>
42 #include <linux/uaccess.h>
43 #include <linux/init_ohci1394_dma.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
53 #include <video/edid.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/proto.h>
60 #include <asm/setup.h>
61 #include <asm/mach_apic.h>
63 #include <asm/sections.h>
65 #include <asm/cacheflush.h>
68 #include <asm/topology.h>
70 #ifdef CONFIG_PARAVIRT
71 #include <asm/paravirt.h>
80 struct cpuinfo_x86 boot_cpu_data __read_mostly;
81 EXPORT_SYMBOL(boot_cpu_data);
83 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
85 unsigned long mmu_cr4_features;
87 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
90 unsigned long saved_video_mode;
92 int force_mwait __cpuinitdata;
98 char dmi_alloc_data[DMI_MAX_DATA];
103 struct screen_info screen_info;
104 EXPORT_SYMBOL(screen_info);
105 struct sys_desc_table_struct {
106 unsigned short length;
107 unsigned char table[0];
110 struct edid_info edid_info;
111 EXPORT_SYMBOL_GPL(edid_info);
113 extern int root_mountflags;
115 char __initdata command_line[COMMAND_LINE_SIZE];
117 struct resource standard_io_resources[] = {
118 { .name = "dma1", .start = 0x00, .end = 0x1f,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "pic1", .start = 0x20, .end = 0x21,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "timer0", .start = 0x40, .end = 0x43,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "timer1", .start = 0x50, .end = 0x53,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "keyboard", .start = 0x60, .end = 0x6f,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "pic2", .start = 0xa0, .end = 0xa1,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "dma2", .start = 0xc0, .end = 0xdf,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "fpu", .start = 0xf0, .end = 0xff,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
138 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
140 static struct resource data_resource = {
141 .name = "Kernel data",
144 .flags = IORESOURCE_RAM,
146 static struct resource code_resource = {
147 .name = "Kernel code",
150 .flags = IORESOURCE_RAM,
152 static struct resource bss_resource = {
153 .name = "Kernel bss",
156 .flags = IORESOURCE_RAM,
159 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
161 #ifdef CONFIG_PROC_VMCORE
162 /* elfcorehdr= specifies the location of elf core header
163 * stored by the crashed kernel. This option will be passed
164 * by kexec loader to the capture kernel.
166 static int __init setup_elfcorehdr(char *arg)
171 elfcorehdr_addr = memparse(arg, &end);
172 return end > arg ? 0 : -EINVAL;
174 early_param("elfcorehdr", setup_elfcorehdr);
179 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
181 unsigned long bootmap_size, bootmap;
183 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
184 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
187 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
188 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
189 e820_register_active_regions(0, start_pfn, end_pfn);
190 free_bootmem_with_active_regions(0, end_pfn);
191 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
195 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
197 #ifdef CONFIG_EDD_MODULE
201 * copy_edd() - Copy the BIOS EDD information
202 * from boot_params into a safe place.
205 static inline void copy_edd(void)
207 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
208 sizeof(edd.mbr_signature));
209 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
210 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
211 edd.edd_info_nr = boot_params.eddbuf_entries;
214 static inline void copy_edd(void)
220 static void __init reserve_crashkernel(void)
222 unsigned long long total_mem;
223 unsigned long long crash_size, crash_base;
226 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
228 ret = parse_crashkernel(boot_command_line, total_mem,
229 &crash_size, &crash_base);
230 if (ret == 0 && crash_size) {
231 if (crash_base <= 0) {
232 printk(KERN_INFO "crashkernel reservation failed - "
233 "you have to specify a base address\n");
237 if (reserve_bootmem(crash_base, crash_size,
238 BOOTMEM_EXCLUSIVE) < 0) {
239 printk(KERN_INFO "crashkernel reservation failed - "
240 "memory is in use\n");
244 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
245 "for crashkernel (System RAM: %ldMB)\n",
246 (unsigned long)(crash_size >> 20),
247 (unsigned long)(crash_base >> 20),
248 (unsigned long)(total_mem >> 20));
249 crashk_res.start = crash_base;
250 crashk_res.end = crash_base + crash_size - 1;
254 static inline void __init reserve_crashkernel(void)
258 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
259 void __attribute__((weak)) __init memory_setup(void)
261 machine_specific_memory_setup();
265 * setup_arch - architecture-specific boot-time initializations
267 * Note: On x86_64, fixmaps are ready for use even before this is called.
269 void __init setup_arch(char **cmdline_p)
273 printk(KERN_INFO "Command line: %s\n", boot_command_line);
275 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
276 screen_info = boot_params.screen_info;
277 edid_info = boot_params.edid_info;
278 saved_video_mode = boot_params.hdr.vid_mode;
279 bootloader_type = boot_params.hdr.type_of_loader;
281 #ifdef CONFIG_BLK_DEV_RAM
282 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
283 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
284 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
287 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
297 if (!boot_params.hdr.root_flags)
298 root_mountflags &= ~MS_RDONLY;
299 init_mm.start_code = (unsigned long) &_text;
300 init_mm.end_code = (unsigned long) &_etext;
301 init_mm.end_data = (unsigned long) &_edata;
302 init_mm.brk = (unsigned long) &_end;
304 code_resource.start = virt_to_phys(&_text);
305 code_resource.end = virt_to_phys(&_etext)-1;
306 data_resource.start = virt_to_phys(&_etext);
307 data_resource.end = virt_to_phys(&_edata)-1;
308 bss_resource.start = virt_to_phys(&__bss_start);
309 bss_resource.end = virt_to_phys(&__bss_stop)-1;
311 early_identify_cpu(&boot_cpu_data);
313 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
314 *cmdline_p = command_line;
318 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
319 if (init_ohci1394_dma_early)
320 init_ohci1394_dma_on_all_controllers();
323 finish_e820_parsing();
325 early_gart_iommu_check();
327 e820_register_active_regions(0, 0, -1UL);
329 * partially used pages are not usable - thus
330 * we are rounding upwards:
332 end_pfn = e820_end_of_ram();
333 /* update e820 for memory not covered by WB MTRRs */
335 if (mtrr_trim_uncached_memory(end_pfn)) {
336 e820_register_active_regions(0, 0, -1UL);
337 end_pfn = e820_end_of_ram();
340 num_physpages = end_pfn;
344 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
348 #ifdef CONFIG_PARAVIRT
357 /* setup to use the early static init tables during kernel startup */
358 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
359 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
361 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
367 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
368 * Call this early for SRAT node setup.
370 acpi_boot_table_init();
373 /* How many end-of-memory variables you have, grandma! */
374 max_low_pfn = end_pfn;
376 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
378 /* Remove active ranges so rediscovery with NUMA-awareness happens */
379 remove_all_active_ranges();
381 #ifdef CONFIG_ACPI_NUMA
383 * Parse SRAT to discover nodes.
389 numa_initmem_init(0, end_pfn);
391 contig_initmem_init(0, end_pfn);
394 early_res_to_bootmem();
396 #ifdef CONFIG_ACPI_SLEEP
398 * Reserve low memory region for sleep support.
400 acpi_reserve_bootmem();
404 efi_reserve_bootmem();
407 * Find and reserve possible boot-time SMP configuration:
410 #ifdef CONFIG_BLK_DEV_INITRD
411 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
412 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
413 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
414 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
415 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
417 if (ramdisk_end <= end_of_mem) {
418 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
419 initrd_start = ramdisk_image + PAGE_OFFSET;
420 initrd_end = initrd_start+ramdisk_size;
422 /* Assumes everything on node 0 */
423 free_bootmem(ramdisk_image, ramdisk_size);
424 printk(KERN_ERR "initrd extends beyond end of memory "
425 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
426 ramdisk_end, end_of_mem);
431 reserve_crashkernel();
439 * Read APIC and some other early information from ACPI tables.
447 * get boot-time SMP configuration:
449 if (smp_found_config)
451 init_apic_mappings();
452 ioapic_init_mappings();
455 * We trust e820 completely. No explicit ROM probing in memory.
457 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
458 e820_mark_nosave_regions();
460 /* request I/O space for devices used on all i[345]86 PCs */
461 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
462 request_resource(&ioport_resource, &standard_io_resources[i]);
467 #if defined(CONFIG_VGA_CONSOLE)
468 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
469 conswitchp = &vga_con;
470 #elif defined(CONFIG_DUMMY_CONSOLE)
471 conswitchp = &dummy_con;
476 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
480 if (c->extended_cpuid_level < 0x80000004)
483 v = (unsigned int *) c->x86_model_id;
484 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
485 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
486 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
487 c->x86_model_id[48] = 0;
492 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
494 unsigned int n, dummy, eax, ebx, ecx, edx;
496 n = c->extended_cpuid_level;
498 if (n >= 0x80000005) {
499 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
500 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
501 "D cache %dK (%d bytes/line)\n",
502 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
503 c->x86_cache_size = (ecx>>24) + (edx>>24);
504 /* On K8 L1 TLB is inclusive, so don't count it */
508 if (n >= 0x80000006) {
509 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
510 ecx = cpuid_ecx(0x80000006);
511 c->x86_cache_size = ecx >> 16;
512 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
514 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
515 c->x86_cache_size, ecx & 0xFF);
517 if (n >= 0x80000008) {
518 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
519 c->x86_virt_bits = (eax >> 8) & 0xff;
520 c->x86_phys_bits = eax & 0xff;
525 static int __cpuinit nearby_node(int apicid)
529 for (i = apicid - 1; i >= 0; i--) {
530 node = apicid_to_node[i];
531 if (node != NUMA_NO_NODE && node_online(node))
534 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
535 node = apicid_to_node[i];
536 if (node != NUMA_NO_NODE && node_online(node))
539 return first_node(node_online_map); /* Shouldn't happen */
544 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
545 * Assumes number of cores is a power of two.
547 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
552 int cpu = smp_processor_id();
554 unsigned apicid = hard_smp_processor_id();
556 bits = c->x86_coreid_bits;
558 /* Low order bits define the core id (index of core in socket) */
559 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
560 /* Convert the APIC ID into the socket ID */
561 c->phys_proc_id = phys_pkg_id(bits);
564 node = c->phys_proc_id;
565 if (apicid_to_node[apicid] != NUMA_NO_NODE)
566 node = apicid_to_node[apicid];
567 if (!node_online(node)) {
568 /* Two possibilities here:
569 - The CPU is missing memory and no node was created.
570 In that case try picking one from a nearby CPU
571 - The APIC IDs differ from the HyperTransport node IDs
572 which the K8 northbridge parsing fills in.
573 Assume they are all increased by a constant offset,
574 but in the same order as the HT nodeids.
575 If that doesn't result in a usable node fall back to the
576 path for the previous case. */
578 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
580 if (ht_nodeid >= 0 &&
581 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
582 node = apicid_to_node[ht_nodeid];
583 /* Pick a nearby node */
584 if (!node_online(node))
585 node = nearby_node(apicid);
587 numa_set_node(cpu, node);
589 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
594 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
599 /* Multi core CPU? */
600 if (c->extended_cpuid_level < 0x80000008)
603 ecx = cpuid_ecx(0x80000008);
605 c->x86_max_cores = (ecx & 0xff) + 1;
607 /* CPU telling us the core id bits shift? */
608 bits = (ecx >> 12) & 0xF;
610 /* Otherwise recompute */
612 while ((1 << bits) < c->x86_max_cores)
616 c->x86_coreid_bits = bits;
621 #define ENABLE_C1E_MASK 0x18000000
622 #define CPUID_PROCESSOR_SIGNATURE 1
623 #define CPUID_XFAM 0x0ff00000
624 #define CPUID_XFAM_K8 0x00000000
625 #define CPUID_XFAM_10H 0x00100000
626 #define CPUID_XFAM_11H 0x00200000
627 #define CPUID_XMOD 0x000f0000
628 #define CPUID_XMOD_REV_F 0x00040000
630 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
631 static __cpuinit int amd_apic_timer_broken(void)
633 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
635 switch (eax & CPUID_XFAM) {
637 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
641 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
642 if (lo & ENABLE_C1E_MASK)
646 /* err on the side of caution */
652 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
654 early_init_amd_mc(c);
656 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
657 if (c->x86_power & (1<<8))
658 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
661 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
669 * Disable TLB flush filter by setting HWCR.FFDIS on K8
670 * bit 6 of msr C001_0015
672 * Errata 63 for SH-B3 steppings
673 * Errata 122 for all steppings (F+ have it disabled by default)
676 rdmsrl(MSR_K8_HWCR, value);
678 wrmsrl(MSR_K8_HWCR, value);
682 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
683 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
684 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
686 /* On C+ stepping K8 rep microcode works well for copy/memset */
687 level = cpuid_eax(1);
688 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
690 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
691 if (c->x86 == 0x10 || c->x86 == 0x11)
692 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
694 /* Enable workaround for FXSAVE leak */
696 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
698 level = get_model_name(c);
702 /* Should distinguish Models here, but this is only
703 a fallback anyways. */
704 strcpy(c->x86_model_id, "Hammer");
708 display_cacheinfo(c);
710 /* Multi core CPU? */
711 if (c->extended_cpuid_level >= 0x80000008)
714 if (c->extended_cpuid_level >= 0x80000006 &&
715 (cpuid_edx(0x80000006) & 0xf000))
716 num_cache_leaves = 4;
718 num_cache_leaves = 3;
720 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
721 set_cpu_cap(c, X86_FEATURE_K8);
723 /* MFENCE stops RDTSC speculation */
724 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
726 if (amd_apic_timer_broken())
727 disable_apic_timer = 1;
730 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
733 u32 eax, ebx, ecx, edx;
734 int index_msb, core_bits;
736 cpuid(1, &eax, &ebx, &ecx, &edx);
739 if (!cpu_has(c, X86_FEATURE_HT))
741 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
744 smp_num_siblings = (ebx & 0xff0000) >> 16;
746 if (smp_num_siblings == 1) {
747 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
748 } else if (smp_num_siblings > 1) {
750 if (smp_num_siblings > NR_CPUS) {
751 printk(KERN_WARNING "CPU: Unsupported number of "
752 "siblings %d", smp_num_siblings);
753 smp_num_siblings = 1;
757 index_msb = get_count_order(smp_num_siblings);
758 c->phys_proc_id = phys_pkg_id(index_msb);
760 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
762 index_msb = get_count_order(smp_num_siblings);
764 core_bits = get_count_order(c->x86_max_cores);
766 c->cpu_core_id = phys_pkg_id(index_msb) &
767 ((1 << core_bits) - 1);
770 if ((c->x86_max_cores * smp_num_siblings) > 1) {
771 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
773 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
781 * find out the number of processor cores on the die
783 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
787 if (c->cpuid_level < 4)
790 cpuid_count(4, 0, &eax, &t, &t, &t);
793 return ((eax >> 26) + 1);
798 static void __cpuinit srat_detect_node(void)
802 int cpu = smp_processor_id();
803 int apicid = hard_smp_processor_id();
805 /* Don't do the funky fallback heuristics the AMD version employs
807 node = apicid_to_node[apicid];
808 if (node == NUMA_NO_NODE || !node_online(node))
809 node = first_node(node_online_map);
810 numa_set_node(cpu, node);
812 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
816 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
818 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
819 (c->x86 == 0x6 && c->x86_model >= 0x0e))
820 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
823 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
828 init_intel_cacheinfo(c);
829 if (c->cpuid_level > 9) {
830 unsigned eax = cpuid_eax(10);
831 /* Check for version and the number of counters */
832 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
833 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
838 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
840 set_cpu_cap(c, X86_FEATURE_BTS);
842 set_cpu_cap(c, X86_FEATURE_PEBS);
849 n = c->extended_cpuid_level;
850 if (n >= 0x80000008) {
851 unsigned eax = cpuid_eax(0x80000008);
852 c->x86_virt_bits = (eax >> 8) & 0xff;
853 c->x86_phys_bits = eax & 0xff;
854 /* CPUID workaround for Intel 0F34 CPU */
855 if (c->x86_vendor == X86_VENDOR_INTEL &&
856 c->x86 == 0xF && c->x86_model == 0x3 &&
858 c->x86_phys_bits = 36;
862 c->x86_cache_alignment = c->x86_clflush_size * 2;
863 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
864 (c->x86 == 0x6 && c->x86_model >= 0x0e))
865 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
867 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
868 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
869 c->x86_max_cores = intel_num_cpu_cores(c);
874 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
876 char *v = c->x86_vendor_id;
878 if (!strcmp(v, "AuthenticAMD"))
879 c->x86_vendor = X86_VENDOR_AMD;
880 else if (!strcmp(v, "GenuineIntel"))
881 c->x86_vendor = X86_VENDOR_INTEL;
883 c->x86_vendor = X86_VENDOR_UNKNOWN;
886 /* Do some early cpuid on the boot CPU to get some parameter that are
887 needed before check_bugs. Everything advanced is in identify_cpu
889 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
893 c->loops_per_jiffy = loops_per_jiffy;
894 c->x86_cache_size = -1;
895 c->x86_vendor = X86_VENDOR_UNKNOWN;
896 c->x86_model = c->x86_mask = 0; /* So far unknown... */
897 c->x86_vendor_id[0] = '\0'; /* Unset */
898 c->x86_model_id[0] = '\0'; /* Unset */
899 c->x86_clflush_size = 64;
900 c->x86_cache_alignment = c->x86_clflush_size;
901 c->x86_max_cores = 1;
902 c->x86_coreid_bits = 0;
903 c->extended_cpuid_level = 0;
904 memset(&c->x86_capability, 0, sizeof c->x86_capability);
906 /* Get vendor name */
907 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
908 (unsigned int *)&c->x86_vendor_id[0],
909 (unsigned int *)&c->x86_vendor_id[8],
910 (unsigned int *)&c->x86_vendor_id[4]);
914 /* Initialize the standard set of capabilities */
915 /* Note that the vendor-specific code below might override */
917 /* Intel-defined flags: level 0x00000001 */
918 if (c->cpuid_level >= 0x00000001) {
920 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
921 &c->x86_capability[0]);
922 c->x86 = (tfms >> 8) & 0xf;
923 c->x86_model = (tfms >> 4) & 0xf;
924 c->x86_mask = tfms & 0xf;
926 c->x86 += (tfms >> 20) & 0xff;
928 c->x86_model += ((tfms >> 16) & 0xF) << 4;
929 if (c->x86_capability[0] & (1<<19))
930 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
932 /* Have CPUID level 0 only - unheard of */
937 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
939 /* AMD-defined flags: level 0x80000001 */
940 xlvl = cpuid_eax(0x80000000);
941 c->extended_cpuid_level = xlvl;
942 if ((xlvl & 0xffff0000) == 0x80000000) {
943 if (xlvl >= 0x80000001) {
944 c->x86_capability[1] = cpuid_edx(0x80000001);
945 c->x86_capability[6] = cpuid_ecx(0x80000001);
947 if (xlvl >= 0x80000004)
948 get_model_name(c); /* Default name */
951 /* Transmeta-defined flags: level 0x80860001 */
952 xlvl = cpuid_eax(0x80860000);
953 if ((xlvl & 0xffff0000) == 0x80860000) {
954 /* Don't set x86_cpuid_level here for now to not confuse. */
955 if (xlvl >= 0x80860001)
956 c->x86_capability[2] = cpuid_edx(0x80860001);
959 c->extended_cpuid_level = cpuid_eax(0x80000000);
960 if (c->extended_cpuid_level >= 0x80000007)
961 c->x86_power = cpuid_edx(0x80000007);
963 switch (c->x86_vendor) {
967 case X86_VENDOR_INTEL:
975 * This does the hard work of actually picking apart the CPU stuff...
977 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
981 early_identify_cpu(c);
983 init_scattered_cpuid_features(c);
985 c->apicid = phys_pkg_id(0);
988 * Vendor-specific initialization. In this section we
989 * canonicalize the feature flags, meaning if there are
990 * features a certain CPU supports which CPUID doesn't
991 * tell us, CPUID claiming incorrect flags, or other bugs,
992 * we handle them here.
994 * At the end of this section, c->x86_capability better
995 * indicate the features this CPU genuinely supports!
997 switch (c->x86_vendor) {
1002 case X86_VENDOR_INTEL:
1006 case X86_VENDOR_UNKNOWN:
1008 display_cacheinfo(c);
1015 * On SMP, boot_cpu_data holds the common feature set between
1016 * all CPUs; so make sure that we indicate which features are
1017 * common between the CPUs. The first time this routine gets
1018 * executed, c == &boot_cpu_data.
1020 if (c != &boot_cpu_data) {
1021 /* AND the already accumulated flags with these */
1022 for (i = 0; i < NCAPINTS; i++)
1023 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1026 /* Clear all flags overriden by options */
1027 for (i = 0; i < NCAPINTS; i++)
1028 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1030 #ifdef CONFIG_X86_MCE
1033 select_idle_routine(c);
1035 if (c != &boot_cpu_data)
1038 numa_add_cpu(smp_processor_id());
1043 static __init int setup_noclflush(char *arg)
1045 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1048 __setup("noclflush", setup_noclflush);
1050 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1052 if (c->x86_model_id[0])
1053 printk(KERN_CONT "%s", c->x86_model_id);
1055 if (c->x86_mask || c->cpuid_level >= 0)
1056 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1058 printk(KERN_CONT "\n");
1061 static __init int setup_disablecpuid(char *arg)
1064 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1065 setup_clear_cpu_cap(bit);
1070 __setup("clearcpuid=", setup_disablecpuid);