2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <linux/efi.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/iscsi_ibft.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44 #include <linux/init_ohci1394_dma.h>
47 #include <asm/uaccess.h>
48 #include <asm/system.h>
49 #include <asm/vsyscall.h>
54 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/proto.h>
61 #include <asm/setup.h>
63 #include <asm/sections.h>
65 #include <asm/cacheflush.h>
68 #include <asm/topology.h>
69 #include <asm/trampoline.h>
71 #include <mach_apic.h>
72 #ifdef CONFIG_PARAVIRT
73 #include <asm/paravirt.h>
82 struct cpuinfo_x86 boot_cpu_data __read_mostly;
83 EXPORT_SYMBOL(boot_cpu_data);
85 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
87 unsigned long mmu_cr4_features;
89 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
92 unsigned long saved_video_mode;
94 int force_mwait __cpuinitdata;
100 char dmi_alloc_data[DMI_MAX_DATA];
105 struct screen_info screen_info;
106 EXPORT_SYMBOL(screen_info);
107 struct sys_desc_table_struct {
108 unsigned short length;
109 unsigned char table[0];
112 struct edid_info edid_info;
113 EXPORT_SYMBOL_GPL(edid_info);
115 extern int root_mountflags;
117 char __initdata command_line[COMMAND_LINE_SIZE];
119 struct resource standard_io_resources[] = {
120 { .name = "dma1", .start = 0x00, .end = 0x1f,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "pic1", .start = 0x20, .end = 0x21,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "timer0", .start = 0x40, .end = 0x43,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "timer1", .start = 0x50, .end = 0x53,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "keyboard", .start = 0x60, .end = 0x6f,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "pic2", .start = 0xa0, .end = 0xa1,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "dma2", .start = 0xc0, .end = 0xdf,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
136 { .name = "fpu", .start = 0xf0, .end = 0xff,
137 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
140 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
142 static struct resource data_resource = {
143 .name = "Kernel data",
146 .flags = IORESOURCE_RAM,
148 static struct resource code_resource = {
149 .name = "Kernel code",
152 .flags = IORESOURCE_RAM,
154 static struct resource bss_resource = {
155 .name = "Kernel bss",
158 .flags = IORESOURCE_RAM,
161 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
163 #ifdef CONFIG_PROC_VMCORE
164 /* elfcorehdr= specifies the location of elf core header
165 * stored by the crashed kernel. This option will be passed
166 * by kexec loader to the capture kernel.
168 static int __init setup_elfcorehdr(char *arg)
173 elfcorehdr_addr = memparse(arg, &end);
174 return end > arg ? 0 : -EINVAL;
176 early_param("elfcorehdr", setup_elfcorehdr);
181 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
183 unsigned long bootmap_size, bootmap;
185 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
186 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
189 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
190 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
191 e820_register_active_regions(0, start_pfn, end_pfn);
192 free_bootmem_with_active_regions(0, end_pfn);
193 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
197 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
199 #ifdef CONFIG_EDD_MODULE
203 * copy_edd() - Copy the BIOS EDD information
204 * from boot_params into a safe place.
207 static inline void copy_edd(void)
209 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
210 sizeof(edd.mbr_signature));
211 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
212 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
213 edd.edd_info_nr = boot_params.eddbuf_entries;
216 static inline void copy_edd(void)
222 static void __init reserve_crashkernel(void)
224 unsigned long long total_mem;
225 unsigned long long crash_size, crash_base;
228 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
230 ret = parse_crashkernel(boot_command_line, total_mem,
231 &crash_size, &crash_base);
232 if (ret == 0 && crash_size) {
233 if (crash_base <= 0) {
234 printk(KERN_INFO "crashkernel reservation failed - "
235 "you have to specify a base address\n");
239 if (reserve_bootmem(crash_base, crash_size,
240 BOOTMEM_EXCLUSIVE) < 0) {
241 printk(KERN_INFO "crashkernel reservation failed - "
242 "memory is in use\n");
246 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
247 "for crashkernel (System RAM: %ldMB)\n",
248 (unsigned long)(crash_size >> 20),
249 (unsigned long)(crash_base >> 20),
250 (unsigned long)(total_mem >> 20));
251 crashk_res.start = crash_base;
252 crashk_res.end = crash_base + crash_size - 1;
253 insert_resource(&iomem_resource, &crashk_res);
257 static inline void __init reserve_crashkernel(void)
261 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
262 void __attribute__((weak)) __init memory_setup(void)
264 machine_specific_memory_setup();
268 * setup_arch - architecture-specific boot-time initializations
270 * Note: On x86_64, fixmaps are ready for use even before this is called.
272 void __init setup_arch(char **cmdline_p)
276 printk(KERN_INFO "Command line: %s\n", boot_command_line);
278 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
279 screen_info = boot_params.screen_info;
280 edid_info = boot_params.edid_info;
281 saved_video_mode = boot_params.hdr.vid_mode;
282 bootloader_type = boot_params.hdr.type_of_loader;
284 #ifdef CONFIG_BLK_DEV_RAM
285 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
286 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
287 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
290 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
300 if (!boot_params.hdr.root_flags)
301 root_mountflags &= ~MS_RDONLY;
302 init_mm.start_code = (unsigned long) &_text;
303 init_mm.end_code = (unsigned long) &_etext;
304 init_mm.end_data = (unsigned long) &_edata;
305 init_mm.brk = (unsigned long) &_end;
307 code_resource.start = virt_to_phys(&_text);
308 code_resource.end = virt_to_phys(&_etext)-1;
309 data_resource.start = virt_to_phys(&_etext);
310 data_resource.end = virt_to_phys(&_edata)-1;
311 bss_resource.start = virt_to_phys(&__bss_start);
312 bss_resource.end = virt_to_phys(&__bss_stop)-1;
314 early_identify_cpu(&boot_cpu_data);
316 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
317 *cmdline_p = command_line;
321 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
322 if (init_ohci1394_dma_early)
323 init_ohci1394_dma_on_all_controllers();
326 finish_e820_parsing();
328 /* after parse_early_param, so could debug it */
329 insert_resource(&iomem_resource, &code_resource);
330 insert_resource(&iomem_resource, &data_resource);
331 insert_resource(&iomem_resource, &bss_resource);
333 early_gart_iommu_check();
335 e820_register_active_regions(0, 0, -1UL);
337 * partially used pages are not usable - thus
338 * we are rounding upwards:
340 end_pfn = e820_end_of_ram();
341 /* update e820 for memory not covered by WB MTRRs */
343 if (mtrr_trim_uncached_memory(end_pfn)) {
344 e820_register_active_regions(0, 0, -1UL);
345 end_pfn = e820_end_of_ram();
348 num_physpages = end_pfn;
352 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
363 /* setup to use the early static init tables during kernel startup */
364 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
365 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
367 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
373 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
374 * Call this early for SRAT node setup.
376 acpi_boot_table_init();
379 /* How many end-of-memory variables you have, grandma! */
380 max_low_pfn = end_pfn;
382 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
384 /* Remove active ranges so rediscovery with NUMA-awareness happens */
385 remove_all_active_ranges();
387 #ifdef CONFIG_ACPI_NUMA
389 * Parse SRAT to discover nodes.
395 numa_initmem_init(0, end_pfn);
397 contig_initmem_init(0, end_pfn);
400 early_res_to_bootmem();
402 #ifdef CONFIG_ACPI_SLEEP
404 * Reserve low memory region for sleep support.
406 acpi_reserve_bootmem();
410 efi_reserve_bootmem();
413 * Find and reserve possible boot-time SMP configuration:
416 #ifdef CONFIG_BLK_DEV_INITRD
417 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
418 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
419 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
420 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
421 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
423 if (ramdisk_end <= end_of_mem) {
424 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
425 initrd_start = ramdisk_image + PAGE_OFFSET;
426 initrd_end = initrd_start+ramdisk_size;
428 /* Assumes everything on node 0 */
429 free_bootmem(ramdisk_image, ramdisk_size);
430 printk(KERN_ERR "initrd extends beyond end of memory "
431 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
432 ramdisk_end, end_of_mem);
437 reserve_crashkernel();
439 reserve_ibft_region();
448 * Read APIC and some other early information from ACPI tables.
456 * get boot-time SMP configuration:
458 if (smp_found_config)
460 init_apic_mappings();
461 ioapic_init_mappings();
464 * We trust e820 completely. No explicit ROM probing in memory.
466 e820_reserve_resources();
467 e820_mark_nosave_regions();
469 /* request I/O space for devices used on all i[345]86 PCs */
470 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
471 request_resource(&ioport_resource, &standard_io_resources[i]);
476 #if defined(CONFIG_VGA_CONSOLE)
477 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
478 conswitchp = &vga_con;
479 #elif defined(CONFIG_DUMMY_CONSOLE)
480 conswitchp = &dummy_con;
485 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
489 if (c->extended_cpuid_level < 0x80000004)
492 v = (unsigned int *) c->x86_model_id;
493 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
494 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
495 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
496 c->x86_model_id[48] = 0;
501 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
503 unsigned int n, dummy, eax, ebx, ecx, edx;
505 n = c->extended_cpuid_level;
507 if (n >= 0x80000005) {
508 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
509 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
510 "D cache %dK (%d bytes/line)\n",
511 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
512 c->x86_cache_size = (ecx>>24) + (edx>>24);
513 /* On K8 L1 TLB is inclusive, so don't count it */
517 if (n >= 0x80000006) {
518 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
519 ecx = cpuid_ecx(0x80000006);
520 c->x86_cache_size = ecx >> 16;
521 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
523 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
524 c->x86_cache_size, ecx & 0xFF);
526 if (n >= 0x80000008) {
527 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
528 c->x86_virt_bits = (eax >> 8) & 0xff;
529 c->x86_phys_bits = eax & 0xff;
534 static int __cpuinit nearby_node(int apicid)
538 for (i = apicid - 1; i >= 0; i--) {
539 node = apicid_to_node[i];
540 if (node != NUMA_NO_NODE && node_online(node))
543 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
544 node = apicid_to_node[i];
545 if (node != NUMA_NO_NODE && node_online(node))
548 return first_node(node_online_map); /* Shouldn't happen */
553 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
554 * Assumes number of cores is a power of two.
556 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
561 int cpu = smp_processor_id();
563 unsigned apicid = hard_smp_processor_id();
565 bits = c->x86_coreid_bits;
567 /* Low order bits define the core id (index of core in socket) */
568 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
569 /* Convert the initial APIC ID into the socket ID */
570 c->phys_proc_id = c->initial_apicid >> bits;
573 node = c->phys_proc_id;
574 if (apicid_to_node[apicid] != NUMA_NO_NODE)
575 node = apicid_to_node[apicid];
576 if (!node_online(node)) {
577 /* Two possibilities here:
578 - The CPU is missing memory and no node was created.
579 In that case try picking one from a nearby CPU
580 - The APIC IDs differ from the HyperTransport node IDs
581 which the K8 northbridge parsing fills in.
582 Assume they are all increased by a constant offset,
583 but in the same order as the HT nodeids.
584 If that doesn't result in a usable node fall back to the
585 path for the previous case. */
587 int ht_nodeid = c->initial_apicid;
589 if (ht_nodeid >= 0 &&
590 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
591 node = apicid_to_node[ht_nodeid];
592 /* Pick a nearby node */
593 if (!node_online(node))
594 node = nearby_node(apicid);
596 numa_set_node(cpu, node);
598 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
603 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
608 /* Multi core CPU? */
609 if (c->extended_cpuid_level < 0x80000008)
612 ecx = cpuid_ecx(0x80000008);
614 c->x86_max_cores = (ecx & 0xff) + 1;
616 /* CPU telling us the core id bits shift? */
617 bits = (ecx >> 12) & 0xF;
619 /* Otherwise recompute */
621 while ((1 << bits) < c->x86_max_cores)
625 c->x86_coreid_bits = bits;
630 #define ENABLE_C1E_MASK 0x18000000
631 #define CPUID_PROCESSOR_SIGNATURE 1
632 #define CPUID_XFAM 0x0ff00000
633 #define CPUID_XFAM_K8 0x00000000
634 #define CPUID_XFAM_10H 0x00100000
635 #define CPUID_XFAM_11H 0x00200000
636 #define CPUID_XMOD 0x000f0000
637 #define CPUID_XMOD_REV_F 0x00040000
639 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
640 static __cpuinit int amd_apic_timer_broken(void)
642 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
644 switch (eax & CPUID_XFAM) {
646 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
650 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
651 if (lo & ENABLE_C1E_MASK)
655 /* err on the side of caution */
661 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
663 early_init_amd_mc(c);
665 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
666 if (c->x86_power & (1<<8))
667 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
670 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
678 * Disable TLB flush filter by setting HWCR.FFDIS on K8
679 * bit 6 of msr C001_0015
681 * Errata 63 for SH-B3 steppings
682 * Errata 122 for all steppings (F+ have it disabled by default)
685 rdmsrl(MSR_K8_HWCR, value);
687 wrmsrl(MSR_K8_HWCR, value);
691 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
692 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
693 clear_cpu_cap(c, 0*32+31);
695 /* On C+ stepping K8 rep microcode works well for copy/memset */
696 level = cpuid_eax(1);
697 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
699 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
700 if (c->x86 == 0x10 || c->x86 == 0x11)
701 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
703 /* Enable workaround for FXSAVE leak */
705 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
707 level = get_model_name(c);
711 /* Should distinguish Models here, but this is only
712 a fallback anyways. */
713 strcpy(c->x86_model_id, "Hammer");
717 display_cacheinfo(c);
719 /* Multi core CPU? */
720 if (c->extended_cpuid_level >= 0x80000008)
723 if (c->extended_cpuid_level >= 0x80000006 &&
724 (cpuid_edx(0x80000006) & 0xf000))
725 num_cache_leaves = 4;
727 num_cache_leaves = 3;
729 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
730 set_cpu_cap(c, X86_FEATURE_K8);
732 /* MFENCE stops RDTSC speculation */
733 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
735 if (amd_apic_timer_broken())
736 disable_apic_timer = 1;
738 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
739 unsigned long long tseg;
742 * Split up direct mapping around the TSEG SMM area.
743 * Don't do it for gbpages because there seems very little
744 * benefit in doing so.
746 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
747 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
748 set_memory_4k((unsigned long)__va(tseg), 1);
752 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
755 u32 eax, ebx, ecx, edx;
756 int index_msb, core_bits;
758 cpuid(1, &eax, &ebx, &ecx, &edx);
761 if (!cpu_has(c, X86_FEATURE_HT))
763 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
766 smp_num_siblings = (ebx & 0xff0000) >> 16;
768 if (smp_num_siblings == 1) {
769 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
770 } else if (smp_num_siblings > 1) {
772 if (smp_num_siblings > NR_CPUS) {
773 printk(KERN_WARNING "CPU: Unsupported number of "
774 "siblings %d", smp_num_siblings);
775 smp_num_siblings = 1;
779 index_msb = get_count_order(smp_num_siblings);
780 c->phys_proc_id = phys_pkg_id(index_msb);
782 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
784 index_msb = get_count_order(smp_num_siblings);
786 core_bits = get_count_order(c->x86_max_cores);
788 c->cpu_core_id = phys_pkg_id(index_msb) &
789 ((1 << core_bits) - 1);
792 if ((c->x86_max_cores * smp_num_siblings) > 1) {
793 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
795 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
803 * find out the number of processor cores on the die
805 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
809 if (c->cpuid_level < 4)
812 cpuid_count(4, 0, &eax, &t, &t, &t);
815 return ((eax >> 26) + 1);
820 static void __cpuinit srat_detect_node(void)
824 int cpu = smp_processor_id();
825 int apicid = hard_smp_processor_id();
827 /* Don't do the funky fallback heuristics the AMD version employs
829 node = apicid_to_node[apicid];
830 if (node == NUMA_NO_NODE || !node_online(node))
831 node = first_node(node_online_map);
832 numa_set_node(cpu, node);
834 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
838 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
840 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
841 (c->x86 == 0x6 && c->x86_model >= 0x0e))
842 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
845 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
850 init_intel_cacheinfo(c);
851 if (c->cpuid_level > 9) {
852 unsigned eax = cpuid_eax(10);
853 /* Check for version and the number of counters */
854 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
855 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
860 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
862 set_cpu_cap(c, X86_FEATURE_BTS);
864 set_cpu_cap(c, X86_FEATURE_PEBS);
871 n = c->extended_cpuid_level;
872 if (n >= 0x80000008) {
873 unsigned eax = cpuid_eax(0x80000008);
874 c->x86_virt_bits = (eax >> 8) & 0xff;
875 c->x86_phys_bits = eax & 0xff;
876 /* CPUID workaround for Intel 0F34 CPU */
877 if (c->x86_vendor == X86_VENDOR_INTEL &&
878 c->x86 == 0xF && c->x86_model == 0x3 &&
880 c->x86_phys_bits = 36;
884 c->x86_cache_alignment = c->x86_clflush_size * 2;
886 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
887 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
888 c->x86_max_cores = intel_num_cpu_cores(c);
893 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
895 if (c->x86 == 0x6 && c->x86_model >= 0xf)
896 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
899 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
904 n = c->extended_cpuid_level;
905 if (n >= 0x80000008) {
906 unsigned eax = cpuid_eax(0x80000008);
907 c->x86_virt_bits = (eax >> 8) & 0xff;
908 c->x86_phys_bits = eax & 0xff;
911 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
912 c->x86_cache_alignment = c->x86_clflush_size * 2;
913 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
914 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
916 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
919 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
921 char *v = c->x86_vendor_id;
923 if (!strcmp(v, "AuthenticAMD"))
924 c->x86_vendor = X86_VENDOR_AMD;
925 else if (!strcmp(v, "GenuineIntel"))
926 c->x86_vendor = X86_VENDOR_INTEL;
927 else if (!strcmp(v, "CentaurHauls"))
928 c->x86_vendor = X86_VENDOR_CENTAUR;
930 c->x86_vendor = X86_VENDOR_UNKNOWN;
933 /* Do some early cpuid on the boot CPU to get some parameter that are
934 needed before check_bugs. Everything advanced is in identify_cpu
936 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
940 c->loops_per_jiffy = loops_per_jiffy;
941 c->x86_cache_size = -1;
942 c->x86_vendor = X86_VENDOR_UNKNOWN;
943 c->x86_model = c->x86_mask = 0; /* So far unknown... */
944 c->x86_vendor_id[0] = '\0'; /* Unset */
945 c->x86_model_id[0] = '\0'; /* Unset */
946 c->x86_clflush_size = 64;
947 c->x86_cache_alignment = c->x86_clflush_size;
948 c->x86_max_cores = 1;
949 c->x86_coreid_bits = 0;
950 c->extended_cpuid_level = 0;
951 memset(&c->x86_capability, 0, sizeof c->x86_capability);
953 /* Get vendor name */
954 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
955 (unsigned int *)&c->x86_vendor_id[0],
956 (unsigned int *)&c->x86_vendor_id[8],
957 (unsigned int *)&c->x86_vendor_id[4]);
961 /* Initialize the standard set of capabilities */
962 /* Note that the vendor-specific code below might override */
964 /* Intel-defined flags: level 0x00000001 */
965 if (c->cpuid_level >= 0x00000001) {
967 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
968 &c->x86_capability[0]);
969 c->x86 = (tfms >> 8) & 0xf;
970 c->x86_model = (tfms >> 4) & 0xf;
971 c->x86_mask = tfms & 0xf;
973 c->x86 += (tfms >> 20) & 0xff;
975 c->x86_model += ((tfms >> 16) & 0xF) << 4;
976 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
977 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
979 /* Have CPUID level 0 only - unheard of */
983 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
985 c->phys_proc_id = c->initial_apicid;
987 /* AMD-defined flags: level 0x80000001 */
988 xlvl = cpuid_eax(0x80000000);
989 c->extended_cpuid_level = xlvl;
990 if ((xlvl & 0xffff0000) == 0x80000000) {
991 if (xlvl >= 0x80000001) {
992 c->x86_capability[1] = cpuid_edx(0x80000001);
993 c->x86_capability[6] = cpuid_ecx(0x80000001);
995 if (xlvl >= 0x80000004)
996 get_model_name(c); /* Default name */
999 /* Transmeta-defined flags: level 0x80860001 */
1000 xlvl = cpuid_eax(0x80860000);
1001 if ((xlvl & 0xffff0000) == 0x80860000) {
1002 /* Don't set x86_cpuid_level here for now to not confuse. */
1003 if (xlvl >= 0x80860001)
1004 c->x86_capability[2] = cpuid_edx(0x80860001);
1007 c->extended_cpuid_level = cpuid_eax(0x80000000);
1008 if (c->extended_cpuid_level >= 0x80000007)
1009 c->x86_power = cpuid_edx(0x80000007);
1012 clear_cpu_cap(c, X86_FEATURE_PAT);
1014 switch (c->x86_vendor) {
1015 case X86_VENDOR_AMD:
1017 if (c->x86 >= 0xf && c->x86 <= 0x11)
1018 set_cpu_cap(c, X86_FEATURE_PAT);
1020 case X86_VENDOR_INTEL:
1021 early_init_intel(c);
1022 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
1023 set_cpu_cap(c, X86_FEATURE_PAT);
1025 case X86_VENDOR_CENTAUR:
1026 early_init_centaur(c);
1033 * This does the hard work of actually picking apart the CPU stuff...
1035 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1039 early_identify_cpu(c);
1041 init_scattered_cpuid_features(c);
1043 c->apicid = phys_pkg_id(0);
1046 * Vendor-specific initialization. In this section we
1047 * canonicalize the feature flags, meaning if there are
1048 * features a certain CPU supports which CPUID doesn't
1049 * tell us, CPUID claiming incorrect flags, or other bugs,
1050 * we handle them here.
1052 * At the end of this section, c->x86_capability better
1053 * indicate the features this CPU genuinely supports!
1055 switch (c->x86_vendor) {
1056 case X86_VENDOR_AMD:
1060 case X86_VENDOR_INTEL:
1064 case X86_VENDOR_CENTAUR:
1068 case X86_VENDOR_UNKNOWN:
1070 display_cacheinfo(c);
1077 * On SMP, boot_cpu_data holds the common feature set between
1078 * all CPUs; so make sure that we indicate which features are
1079 * common between the CPUs. The first time this routine gets
1080 * executed, c == &boot_cpu_data.
1082 if (c != &boot_cpu_data) {
1083 /* AND the already accumulated flags with these */
1084 for (i = 0; i < NCAPINTS; i++)
1085 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1088 /* Clear all flags overriden by options */
1089 for (i = 0; i < NCAPINTS; i++)
1090 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1092 #ifdef CONFIG_X86_MCE
1095 select_idle_routine(c);
1098 numa_add_cpu(smp_processor_id());
1103 void __cpuinit identify_boot_cpu(void)
1105 identify_cpu(&boot_cpu_data);
1108 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1110 BUG_ON(c == &boot_cpu_data);
1115 static __init int setup_noclflush(char *arg)
1117 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1120 __setup("noclflush", setup_noclflush);
1122 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1124 if (c->x86_model_id[0])
1125 printk(KERN_CONT "%s", c->x86_model_id);
1127 if (c->x86_mask || c->cpuid_level >= 0)
1128 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1130 printk(KERN_CONT "\n");
1133 static __init int setup_disablecpuid(char *arg)
1136 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1137 setup_clear_cpu_cap(bit);
1142 __setup("clearcpuid=", setup_disablecpuid);