SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <trace/power.h>
  12 #include <asm/system.h>
  13 #include <asm/apic.h>
  14 #include <asm/idle.h>
  15 #include <asm/uaccess.h>
  16 #include <asm/i387.h>
  17 #include <asm/ds.h>
  18 #include <asm/debugreg.h>
  19 #include <asm/hw_breakpoint.h>
  20
  21 unsigned long idle_halt;
  22 EXPORT_SYMBOL(idle_halt);
  23 unsigned long idle_nomwait;
  24 EXPORT_SYMBOL(idle_nomwait);
  25
  26 struct kmem_cache *task_xstate_cachep;
  27
  28 DEFINE_TRACE(power_start);
  29 DEFINE_TRACE(power_end);
  30
  31 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  32 {
  33         *dst = *src;
  34         if (src->thread.xstate) {
  35                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  36                                                       GFP_KERNEL);
  37                 if (!dst->thread.xstate)
  38                         return -ENOMEM;
  39                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  40                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  41         }
  42         return 0;
  43 }
  44
  45 void free_thread_xstate(struct task_struct *tsk)
  46 {
  47         if (tsk->thread.xstate) {
  48                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  49                 tsk->thread.xstate = NULL;
  50         }
  51         if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
  52                 flush_thread_hw_breakpoint(tsk);
  53
  54         WARN(tsk->thread.ds_ctx, "leaking DS context\n");
  55 }
  56
  57 void free_thread_info(struct thread_info *ti)
  58 {
  59         free_thread_xstate(ti->task);
  60         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  61 }
  62
  63 void arch_task_cache_init(void)
  64 {
  65         task_xstate_cachep =
  66                 kmem_cache_create("task_xstate", xstate_size,
  67                                   __alignof__(union thread_xstate),
  68                                   SLAB_PANIC, NULL);
  69 }
  70
  71 /*
  72  * Free current thread data structures etc..
  73  */
  74 void exit_thread(void)
  75 {
  76         struct task_struct *me = current;
  77         struct thread_struct *t = &me->thread;
  78         unsigned long *bp = t->io_bitmap_ptr;
  79
  80         if (bp) {
  81                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  82
  83                 t->io_bitmap_ptr = NULL;
  84                 clear_thread_flag(TIF_IO_BITMAP);
  85                 /*
  86                  * Careful, clear this in the TSS too:
  87                  */
  88                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  89                 t->io_bitmap_max = 0;
  90                 put_cpu();
  91                 kfree(bp);
  92         }
  93 }
  94
  95 void flush_thread(void)
  96 {
  97         struct task_struct *tsk = current;
  98
  99 #ifdef CONFIG_X86_64
 100         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
 101                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
 102                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
 103                         clear_tsk_thread_flag(tsk, TIF_IA32);
 104                 } else {
 105                         set_tsk_thread_flag(tsk, TIF_IA32);
 106                         current_thread_info()->status |= TS_COMPAT;
 107                 }
 108         }
 109 #endif
 110
 111         clear_tsk_thread_flag(tsk, TIF_DEBUG);
 112
 113         if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
 114                 flush_thread_hw_breakpoint(tsk);
 115         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 116         /*
 117          * Forget coprocessor state..
 118          */
 119         tsk->fpu_counter = 0;
 120         clear_fpu(tsk);
 121         clear_used_math();
 122 }
 123
 124 static void hard_disable_TSC(void)
 125 {
 126         write_cr4(read_cr4() | X86_CR4_TSD);
 127 }
 128
 129 void disable_TSC(void)
 130 {
 131         preempt_disable();
 132         if (!test_and_set_thread_flag(TIF_NOTSC))
 133                 /*
 134                  * Must flip the CPU state synchronously with
 135                  * TIF_NOTSC in the current running context.
 136                  */
 137                 hard_disable_TSC();
 138         preempt_enable();
 139 }
 140
 141 static void hard_enable_TSC(void)
 142 {
 143         write_cr4(read_cr4() & ~X86_CR4_TSD);
 144 }
 145
 146 static void enable_TSC(void)
 147 {
 148         preempt_disable();
 149         if (test_and_clear_thread_flag(TIF_NOTSC))
 150                 /*
 151                  * Must flip the CPU state synchronously with
 152                  * TIF_NOTSC in the current running context.
 153                  */
 154                 hard_enable_TSC();
 155         preempt_enable();
 156 }
 157
 158 int get_tsc_mode(unsigned long adr)
 159 {
 160         unsigned int val;
 161
 162         if (test_thread_flag(TIF_NOTSC))
 163                 val = PR_TSC_SIGSEGV;
 164         else
 165                 val = PR_TSC_ENABLE;
 166
 167         return put_user(val, (unsigned int __user *)adr);
 168 }
 169
 170 int set_tsc_mode(unsigned int val)
 171 {
 172         if (val == PR_TSC_SIGSEGV)
 173                 disable_TSC();
 174         else if (val == PR_TSC_ENABLE)
 175                 enable_TSC();
 176         else
 177                 return -EINVAL;
 178
 179         return 0;
 180 }
 181
 182 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 183                       struct tss_struct *tss)
 184 {
 185         struct thread_struct *prev, *next;
 186
 187         prev = &prev_p->thread;
 188         next = &next_p->thread;
 189
 190         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 191             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 192                 ds_switch_to(prev_p, next_p);
 193         else if (next->debugctlmsr != prev->debugctlmsr)
 194                 update_debugctlmsr(next->debugctlmsr);
 195
 196         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 197             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 198                 /* prev and next are different */
 199                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 200                         hard_disable_TSC();
 201                 else
 202                         hard_enable_TSC();
 203         }
 204
 205         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 206                 /*
 207                  * Copy the relevant range of the IO bitmap.
 208                  * Normally this is 128 bytes or less:
 209                  */
 210                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 211                        max(prev->io_bitmap_max, next->io_bitmap_max));
 212         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 213                 /*
 214                  * Clear any possible leftover bits:
 215                  */
 216                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 217         }
 218 }
 219
 220 int sys_fork(struct pt_regs *regs)
 221 {
 222         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 223 }
 224
 225 /*
 226  * This is trivial, and on the face of it looks like it
 227  * could equally well be done in user mode.
 228  *
 229  * Not so, for quite unobvious reasons - register pressure.
 230  * In user mode vfork() cannot have a stack frame, and if
 231  * done by calling the "clone()" system call directly, you
 232  * do not have enough call-clobbered registers to hold all
 233  * the information you need.
 234  */
 235 int sys_vfork(struct pt_regs *regs)
 236 {
 237         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 238                        NULL, NULL);
 239 }
 240
 241
 242 /*
 243  * Idle related variables and functions
 244  */
 245 unsigned long boot_option_idle_override = 0;
 246 EXPORT_SYMBOL(boot_option_idle_override);
 247
 248 /*
 249  * Powermanagement idle function, if any..
 250  */
 251 void (*pm_idle)(void);
 252 EXPORT_SYMBOL(pm_idle);
 253
 254 #ifdef CONFIG_X86_32
 255 /*
 256  * This halt magic was a workaround for ancient floppy DMA
 257  * wreckage. It should be safe to remove.
 258  */
 259 static int hlt_counter;
 260 void disable_hlt(void)
 261 {
 262         hlt_counter++;
 263 }
 264 EXPORT_SYMBOL(disable_hlt);
 265
 266 void enable_hlt(void)
 267 {
 268         hlt_counter--;
 269 }
 270 EXPORT_SYMBOL(enable_hlt);
 271
 272 static inline int hlt_use_halt(void)
 273 {
 274         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 275 }
 276 #else
 277 static inline int hlt_use_halt(void)
 278 {
 279         return 1;
 280 }
 281 #endif
 282
 283 /*
 284  * We use this if we don't have any better
 285  * idle routine..
 286  */
 287 void default_idle(void)
 288 {
 289         if (hlt_use_halt()) {
 290                 struct power_trace it;
 291
 292                 trace_power_start(&it, POWER_CSTATE, 1);
 293                 current_thread_info()->status &= ~TS_POLLING;
 294                 /*
 295                  * TS_POLLING-cleared state must be visible before we
 296                  * test NEED_RESCHED:
 297                  */
 298                 smp_mb();
 299
 300                 if (!need_resched())
 301                         safe_halt();    /* enables interrupts racelessly */
 302                 else
 303                         local_irq_enable();
 304                 current_thread_info()->status |= TS_POLLING;
 305                 trace_power_end(&it);
 306         } else {
 307                 local_irq_enable();
 308                 /* loop is done by the caller */
 309                 cpu_relax();
 310         }
 311 }
 312 #ifdef CONFIG_APM_MODULE
 313 EXPORT_SYMBOL(default_idle);
 314 #endif
 315
 316 void stop_this_cpu(void *dummy)
 317 {
 318         local_irq_disable();
 319         /*
 320          * Remove this CPU:
 321          */
 322         set_cpu_online(smp_processor_id(), false);
 323         disable_local_APIC();
 324
 325         for (;;) {
 326                 if (hlt_works(smp_processor_id()))
 327                         halt();
 328         }
 329 }
 330
 331 static void do_nothing(void *unused)
 332 {
 333 }
 334
 335 /*
 336  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 337  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 338  * handler on SMP systems.
 339  *
 340  * Caller must have changed pm_idle to the new value before the call. Old
 341  * pm_idle value will not be used by any CPU after the return of this function.
 342  */
 343 void cpu_idle_wait(void)
 344 {
 345         smp_mb();
 346         /* kick all the CPUs so that they exit out of pm_idle */
 347         smp_call_function(do_nothing, NULL, 1);
 348 }
 349 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 350
 351 /*
 352  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 353  * which can obviate IPI to trigger checking of need_resched.
 354  * We execute MONITOR against need_resched and enter optimized wait state
 355  * through MWAIT. Whenever someone changes need_resched, we would be woken
 356  * up from MWAIT (without an IPI).
 357  *
 358  * New with Core Duo processors, MWAIT can take some hints based on CPU
 359  * capability.
 360  */
 361 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 362 {
 363         struct power_trace it;
 364
 365         trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
 366         if (!need_resched()) {
 367                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 368                         clflush((void *)&current_thread_info()->flags);
 369
 370                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 371                 smp_mb();
 372                 if (!need_resched())
 373                         __mwait(ax, cx);
 374         }
 375         trace_power_end(&it);
 376 }
 377
 378 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 379 static void mwait_idle(void)
 380 {
 381         struct power_trace it;
 382         if (!need_resched()) {
 383                 trace_power_start(&it, POWER_CSTATE, 1);
 384                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 385                         clflush((void *)&current_thread_info()->flags);
 386
 387                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 388                 smp_mb();
 389                 if (!need_resched())
 390                         __sti_mwait(0, 0);
 391                 else
 392                         local_irq_enable();
 393                 trace_power_end(&it);
 394         } else
 395                 local_irq_enable();
 396 }
 397
 398 /*
 399  * On SMP it's slightly faster (but much more power-consuming!)
 400  * to poll the ->work.need_resched flag instead of waiting for the
 401  * cross-CPU IPI to arrive. Use this option with caution.
 402  */
 403 static void poll_idle(void)
 404 {
 405         struct power_trace it;
 406
 407         trace_power_start(&it, POWER_CSTATE, 0);
 408         local_irq_enable();
 409         while (!need_resched())
 410                 cpu_relax();
 411         trace_power_end(&it);
 412 }
 413
 414 /*
 415  * mwait selection logic:
 416  *
 417  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 418  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 419  * then depend on a clock divisor and current Pstate of the core. If
 420  * all cores of a processor are in halt state (C1) the processor can
 421  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 422  * happen.
 423  *
 424  * idle=mwait overrides this decision and forces the usage of mwait.
 425  */
 426 static int __cpuinitdata force_mwait;
 427
 428 #define MWAIT_INFO                      0x05
 429 #define MWAIT_ECX_EXTENDED_INFO         0x01
 430 #define MWAIT_EDX_C1                    0xf0
 431
 432 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 433 {
 434         u32 eax, ebx, ecx, edx;
 435
 436         if (force_mwait)
 437                 return 1;
 438
 439         if (c->cpuid_level < MWAIT_INFO)
 440                 return 0;
 441
 442         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 443         /* Check, whether EDX has extended info about MWAIT */
 444         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 445                 return 1;
 446
 447         /*
 448          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 449          * C1  supports MWAIT
 450          */
 451         return (edx & MWAIT_EDX_C1);
 452 }
 453
 454 /*
 455  * Check for AMD CPUs, which have potentially C1E support
 456  */
 457 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 458 {
 459         if (c->x86_vendor != X86_VENDOR_AMD)
 460                 return 0;
 461
 462         if (c->x86 < 0x0F)
 463                 return 0;
 464
 465         /* Family 0x0f models < rev F do not have C1E */
 466         if (c->x86 == 0x0f && c->x86_model < 0x40)
 467                 return 0;
 468
 469         return 1;
 470 }
 471
 472 static cpumask_var_t c1e_mask;
 473 static int c1e_detected;
 474
 475 void c1e_remove_cpu(int cpu)
 476 {
 477         if (c1e_mask != NULL)
 478                 cpumask_clear_cpu(cpu, c1e_mask);
 479 }
 480
 481 /*
 482  * C1E aware idle routine. We check for C1E active in the interrupt
 483  * pending message MSR. If we detect C1E, then we handle it the same
 484  * way as C3 power states (local apic timer and TSC stop)
 485  */
 486 static void c1e_idle(void)
 487 {
 488         if (need_resched())
 489                 return;
 490
 491         if (!c1e_detected) {
 492                 u32 lo, hi;
 493
 494                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 495                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 496                         c1e_detected = 1;
 497                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 498                                 mark_tsc_unstable("TSC halt in AMD C1E");
 499                         printk(KERN_INFO "System has AMD C1E enabled\n");
 500                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 501                 }
 502         }
 503
 504         if (c1e_detected) {
 505                 int cpu = smp_processor_id();
 506
 507                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 508                         cpumask_set_cpu(cpu, c1e_mask);
 509                         /*
 510                          * Force broadcast so ACPI can not interfere. Needs
 511                          * to run with interrupts enabled as it uses
 512                          * smp_function_call.
 513                          */
 514                         local_irq_enable();
 515                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 516                                            &cpu);
 517                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 518                                cpu);
 519                         local_irq_disable();
 520                 }
 521                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 522
 523                 default_idle();
 524
 525                 /*
 526                  * The switch back from broadcast mode needs to be
 527                  * called with interrupts disabled.
 528                  */
 529                  local_irq_disable();
 530                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 531                  local_irq_enable();
 532         } else
 533                 default_idle();
 534 }
 535
 536 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 537 {
 538 #ifdef CONFIG_SMP
 539         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 540                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 541                         " performance may degrade.\n");
 542         }
 543 #endif
 544         if (pm_idle)
 545                 return;
 546
 547         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 548                 /*
 549                  * One CPU supports mwait => All CPUs supports mwait
 550                  */
 551                 printk(KERN_INFO "using mwait in idle threads.\n");
 552                 pm_idle = mwait_idle;
 553         } else if (check_c1e_idle(c)) {
 554                 printk(KERN_INFO "using C1E aware idle routine\n");
 555                 pm_idle = c1e_idle;
 556         } else
 557                 pm_idle = default_idle;
 558 }
 559
 560 void __init init_c1e_mask(void)
 561 {
 562         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 563         if (pm_idle == c1e_idle) {
 564                 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 565                 cpumask_clear(c1e_mask);
 566         }
 567 }
 568
 569 static int __init idle_setup(char *str)
 570 {
 571         if (!str)
 572                 return -EINVAL;
 573
 574         if (!strcmp(str, "poll")) {
 575                 printk("using polling idle threads.\n");
 576                 pm_idle = poll_idle;
 577         } else if (!strcmp(str, "mwait"))
 578                 force_mwait = 1;
 579         else if (!strcmp(str, "halt")) {
 580                 /*
 581                  * When the boot option of idle=halt is added, halt is
 582                  * forced to be used for CPU idle. In such case CPU C2/C3
 583                  * won't be used again.
 584                  * To continue to load the CPU idle driver, don't touch
 585                  * the boot_option_idle_override.
 586                  */
 587                 pm_idle = default_idle;
 588                 idle_halt = 1;
 589                 return 0;
 590         } else if (!strcmp(str, "nomwait")) {
 591                 /*
 592                  * If the boot option of "idle=nomwait" is added,
 593                  * it means that mwait will be disabled for CPU C2/C3
 594                  * states. In such case it won't touch the variable
 595                  * of boot_option_idle_override.
 596                  */
 597                 idle_nomwait = 1;
 598                 return 0;
 599         } else
 600                 return -1;
 601
 602         boot_option_idle_override = 1;
 603         return 0;
 604 }
 605 early_param("idle", idle_setup);
 606