2 * Dynamic DMA mapping support for AMD Hammer.
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
8 * See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/spinlock.h>
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/topology.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27 #include <linux/kdebug.h>
28 #include <linux/scatterlist.h>
29 #include <linux/iommu-helper.h>
30 #include <linux/sysdev.h>
32 #include <asm/atomic.h>
34 #include <asm/pgtable.h>
35 #include <asm/proto.h>
36 #include <asm/iommu.h>
38 #include <asm/cacheflush.h>
39 #include <asm/swiotlb.h>
42 #include <asm/x86_init.h>
44 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
45 static unsigned long iommu_size; /* size of remapping area bytes */
46 static unsigned long iommu_pages; /* .. and in pages */
48 static u32 *iommu_gatt_base; /* Remapping table */
51 * If this is disabled the IOMMU will use an optimized flushing strategy
52 * of only flushing when an mapping is reused. With it true the GART is
53 * flushed for every mapping. Problem is that doing the lazy flush seems
54 * to trigger bugs with some popular PCI cards, in particular 3ware (but
55 * has been also also seen with Qlogic at least).
57 static int iommu_fullflush = 1;
59 /* Allocation bitmap for the remapping area: */
60 static DEFINE_SPINLOCK(iommu_bitmap_lock);
61 /* Guarded by iommu_bitmap_lock: */
62 static unsigned long *iommu_gart_bitmap;
64 static u32 gart_unmapped_entry;
67 #define GPTE_COHERENT 2
68 #define GPTE_ENCODE(x) \
69 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
70 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
72 #define EMERGENCY_PAGES 32 /* = 128KB */
75 #define AGPEXTERN extern
80 /* backdoor interface to AGP driver */
81 AGPEXTERN int agp_memory_reserved;
82 AGPEXTERN __u32 *agp_gatt_table;
84 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
85 static bool need_flush; /* global flush state. set for each gart wrap */
87 static unsigned long alloc_iommu(struct device *dev, int size,
88 unsigned long align_mask)
90 unsigned long offset, flags;
91 unsigned long boundary_size;
92 unsigned long base_index;
94 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
95 PAGE_SIZE) >> PAGE_SHIFT;
96 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
97 PAGE_SIZE) >> PAGE_SHIFT;
99 spin_lock_irqsave(&iommu_bitmap_lock, flags);
100 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
101 size, base_index, boundary_size, align_mask);
104 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
105 size, base_index, boundary_size,
109 next_bit = offset+size;
110 if (next_bit >= iommu_pages) {
117 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
122 static void free_iommu(unsigned long offset, int size)
126 spin_lock_irqsave(&iommu_bitmap_lock, flags);
127 iommu_area_free(iommu_gart_bitmap, offset, size);
128 if (offset >= next_bit)
129 next_bit = offset + size;
130 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
134 * Use global flush state to avoid races with multiple flushers.
136 static void flush_gart(void)
140 spin_lock_irqsave(&iommu_bitmap_lock, flags);
145 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
148 #ifdef CONFIG_IOMMU_LEAK
149 /* Debugging aid for drivers that don't free their IOMMU tables */
150 static int leak_trace;
151 static int iommu_leak_pages = 20;
153 static void dump_leak(void)
161 show_stack(NULL, NULL);
162 debug_dma_dump_mappings(NULL);
166 static void iommu_full(struct device *dev, size_t size, int dir)
169 * Ran out of IOMMU space for this operation. This is very bad.
170 * Unfortunately the drivers cannot handle this operation properly.
171 * Return some non mapped prereserved space in the aperture and
172 * let the Northbridge deal with it. This will result in garbage
173 * in the IO operation. When the size exceeds the prereserved space
174 * memory corruption will occur or random memory will be DMAed
175 * out. Hopefully no network devices use single mappings that big.
178 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
180 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
181 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
182 panic("PCI-DMA: Memory would be corrupted\n");
183 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
185 "PCI-DMA: Random memory would be DMAed\n");
187 #ifdef CONFIG_IOMMU_LEAK
193 need_iommu(struct device *dev, unsigned long addr, size_t size)
195 return force_iommu || !dma_capable(dev, addr, size);
199 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
201 return !dma_capable(dev, addr, size);
204 /* Map a single continuous physical area into the IOMMU.
205 * Caller needs to check if the iommu is needed and flush.
207 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
208 size_t size, int dir, unsigned long align_mask)
210 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
211 unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
214 if (iommu_page == -1) {
215 if (!nonforced_iommu(dev, phys_mem, size))
217 if (panic_on_overflow)
218 panic("dma_map_area overflow %lu bytes\n", size);
219 iommu_full(dev, size, dir);
220 return bad_dma_address;
223 for (i = 0; i < npages; i++) {
224 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
225 phys_mem += PAGE_SIZE;
227 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
230 /* Map a single area into the IOMMU */
231 static dma_addr_t gart_map_page(struct device *dev, struct page *page,
232 unsigned long offset, size_t size,
233 enum dma_data_direction dir,
234 struct dma_attrs *attrs)
237 phys_addr_t paddr = page_to_phys(page) + offset;
240 dev = &x86_dma_fallback_dev;
242 if (!need_iommu(dev, paddr, size))
245 bus = dma_map_area(dev, paddr, size, dir, 0);
252 * Free a DMA mapping.
254 static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
255 size_t size, enum dma_data_direction dir,
256 struct dma_attrs *attrs)
258 unsigned long iommu_page;
262 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
263 dma_addr >= iommu_bus_base + iommu_size)
266 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
267 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
268 for (i = 0; i < npages; i++) {
269 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
271 free_iommu(iommu_page, npages);
275 * Wrapper for pci_unmap_single working with scatterlists.
277 static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
278 enum dma_data_direction dir, struct dma_attrs *attrs)
280 struct scatterlist *s;
283 for_each_sg(sg, s, nents, i) {
284 if (!s->dma_length || !s->length)
286 gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL);
290 /* Fallback for dma_map_sg in case of overflow */
291 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
294 struct scatterlist *s;
297 #ifdef CONFIG_IOMMU_DEBUG
298 printk(KERN_DEBUG "dma_map_sg overflow\n");
301 for_each_sg(sg, s, nents, i) {
302 unsigned long addr = sg_phys(s);
304 if (nonforced_iommu(dev, addr, s->length)) {
305 addr = dma_map_area(dev, addr, s->length, dir, 0);
306 if (addr == bad_dma_address) {
308 gart_unmap_sg(dev, sg, i, dir, NULL);
310 sg[0].dma_length = 0;
314 s->dma_address = addr;
315 s->dma_length = s->length;
322 /* Map multiple scatterlist entries continuous into the first. */
323 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
324 int nelems, struct scatterlist *sout,
327 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
328 unsigned long iommu_page = iommu_start;
329 struct scatterlist *s;
332 if (iommu_start == -1)
335 for_each_sg(start, s, nelems, i) {
336 unsigned long pages, addr;
337 unsigned long phys_addr = s->dma_address;
339 BUG_ON(s != start && s->offset);
341 sout->dma_address = iommu_bus_base;
342 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
343 sout->dma_length = s->length;
345 sout->dma_length += s->length;
349 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
351 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
356 BUG_ON(iommu_page - iommu_start != pages);
362 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
363 struct scatterlist *sout, unsigned long pages, int need)
367 sout->dma_address = start->dma_address;
368 sout->dma_length = start->length;
371 return __dma_map_cont(dev, start, nelems, sout, pages);
375 * DMA map all entries in a scatterlist.
376 * Merge chunks that have page aligned sizes into a continuous mapping.
378 static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
379 enum dma_data_direction dir, struct dma_attrs *attrs)
381 struct scatterlist *s, *ps, *start_sg, *sgmap;
382 int need = 0, nextneed, i, out, start;
383 unsigned long pages = 0;
384 unsigned int seg_size;
385 unsigned int max_seg_size;
391 dev = &x86_dma_fallback_dev;
395 start_sg = sgmap = sg;
397 max_seg_size = dma_get_max_seg_size(dev);
398 ps = NULL; /* shut up gcc */
399 for_each_sg(sg, s, nents, i) {
400 dma_addr_t addr = sg_phys(s);
402 s->dma_address = addr;
403 BUG_ON(s->length == 0);
405 nextneed = need_iommu(dev, addr, s->length);
407 /* Handle the previous not yet processed entries */
410 * Can only merge when the last chunk ends on a
411 * page boundary and the new one doesn't have an
414 if (!iommu_merge || !nextneed || !need || s->offset ||
415 (s->length + seg_size > max_seg_size) ||
416 (ps->offset + ps->length) % PAGE_SIZE) {
417 if (dma_map_cont(dev, start_sg, i - start,
418 sgmap, pages, need) < 0)
422 sgmap = sg_next(sgmap);
429 seg_size += s->length;
431 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
434 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
439 sgmap = sg_next(sgmap);
440 sgmap->dma_length = 0;
446 gart_unmap_sg(dev, sg, out, dir, NULL);
448 /* When it was forced or merged try again in a dumb way */
449 if (force_iommu || iommu_merge) {
450 out = dma_map_sg_nonforce(dev, sg, nents, dir);
454 if (panic_on_overflow)
455 panic("dma_map_sg: overflow on %lu pages\n", pages);
457 iommu_full(dev, pages << PAGE_SHIFT, dir);
458 for_each_sg(sg, s, nents, i)
459 s->dma_address = bad_dma_address;
463 /* allocate and map a coherent mapping */
465 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
469 unsigned long align_mask;
472 if (force_iommu && !(flag & GFP_DMA)) {
473 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
474 page = alloc_pages(flag | __GFP_ZERO, get_order(size));
478 align_mask = (1UL << get_order(size)) - 1;
479 paddr = dma_map_area(dev, page_to_phys(page), size,
480 DMA_BIDIRECTIONAL, align_mask);
483 if (paddr != bad_dma_address) {
485 return page_address(page);
487 __free_pages(page, get_order(size));
489 return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
494 /* free a coherent mapping */
496 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
499 gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL);
500 free_pages((unsigned long)vaddr, get_order(size));
505 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
510 iommu_size = aper_size;
515 a = aper + iommu_size;
516 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
518 if (iommu_size < 64*1024*1024) {
520 "PCI-DMA: Warning: Small IOMMU %luMB."
521 " Consider increasing the AGP aperture in BIOS\n",
528 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
530 unsigned aper_size = 0, aper_base_32, aper_order;
533 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
534 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
535 aper_order = (aper_order >> 1) & 7;
537 aper_base = aper_base_32 & 0x7fff;
540 aper_size = (32 * 1024 * 1024) << aper_order;
541 if (aper_base + aper_size > 0x100000000UL || !aper_size)
548 static void enable_gart_translations(void)
552 for (i = 0; i < num_k8_northbridges; i++) {
553 struct pci_dev *dev = k8_northbridges[i];
555 enable_gart_translation(dev, __pa(agp_gatt_table));
560 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
561 * resume in the same way as they are handled in gart_iommu_hole_init().
563 static bool fix_up_north_bridges;
564 static u32 aperture_order;
565 static u32 aperture_alloc;
567 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
569 fix_up_north_bridges = true;
570 aperture_order = aper_order;
571 aperture_alloc = aper_alloc;
574 static int gart_resume(struct sys_device *dev)
576 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
578 if (fix_up_north_bridges) {
581 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
583 for (i = 0; i < num_k8_northbridges; i++) {
584 struct pci_dev *dev = k8_northbridges[i];
587 * Don't enable translations just yet. That is the next
588 * step. Restore the pre-suspend aperture settings.
590 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
591 aperture_order << 1);
592 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
593 aperture_alloc >> 25);
597 enable_gart_translations();
602 static int gart_suspend(struct sys_device *dev, pm_message_t state)
607 static struct sysdev_class gart_sysdev_class = {
609 .suspend = gart_suspend,
610 .resume = gart_resume,
614 static struct sys_device device_gart = {
616 .cls = &gart_sysdev_class,
620 * Private Northbridge GATT initialization in case we cannot use the
621 * AGP driver for some reason.
623 static __init int init_k8_gatt(struct agp_kern_info *info)
625 unsigned aper_size, gatt_size, new_aper_size;
626 unsigned aper_base, new_aper_base;
631 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
632 aper_size = aper_base = info->aper_size = 0;
634 for (i = 0; i < num_k8_northbridges; i++) {
635 dev = k8_northbridges[i];
636 new_aper_base = read_aperture(dev, &new_aper_size);
641 aper_size = new_aper_size;
642 aper_base = new_aper_base;
644 if (aper_size != new_aper_size || aper_base != new_aper_base)
649 info->aper_base = aper_base;
650 info->aper_size = aper_size >> 20;
652 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
653 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
654 get_order(gatt_size));
656 panic("Cannot allocate GATT table");
657 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
658 panic("Could not set GART PTEs to uncacheable pages");
660 agp_gatt_table = gatt;
662 error = sysdev_class_register(&gart_sysdev_class);
664 error = sysdev_register(&device_gart);
666 panic("Could not register gart_sysdev -- "
667 "would corrupt data on next suspend");
671 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
672 aper_base, aper_size>>10);
677 /* Should not happen anymore */
678 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
679 "falling back to iommu=soft.\n");
683 static struct dma_map_ops gart_dma_ops = {
684 .map_sg = gart_map_sg,
685 .unmap_sg = gart_unmap_sg,
686 .map_page = gart_map_page,
687 .unmap_page = gart_unmap_page,
688 .alloc_coherent = gart_alloc_coherent,
689 .free_coherent = gart_free_coherent,
692 static void gart_iommu_shutdown(void)
700 for (i = 0; i < num_k8_northbridges; i++) {
703 dev = k8_northbridges[i];
704 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
708 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
712 int __init gart_iommu_init(void)
714 struct agp_kern_info info;
715 unsigned long iommu_start;
716 unsigned long aper_base, aper_size;
717 unsigned long start_pfn, end_pfn;
718 unsigned long scratch;
721 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0)
724 #ifndef CONFIG_AGP_AMD64
727 /* Makefile puts PCI initialization via subsys_initcall first. */
728 /* Add other K8 AGP bridge drivers here */
730 (agp_amd64_init() < 0) ||
731 (agp_copy_info(agp_bridge, &info) < 0);
735 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
736 !gart_iommu_aperture ||
737 (no_agp && init_k8_gatt(&info) < 0)) {
738 if (max_pfn > MAX_DMA32_PFN) {
739 printk(KERN_WARNING "More than 4GB of memory "
740 "but GART IOMMU not available.\n");
741 printk(KERN_WARNING "falling back to iommu=soft.\n");
746 /* need to map that range */
747 aper_size = info.aper_size << 20;
748 aper_base = info.aper_base;
749 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
750 if (end_pfn > max_low_pfn_mapped) {
751 start_pfn = (aper_base>>PAGE_SHIFT);
752 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
755 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
756 iommu_size = check_iommu_size(info.aper_base, aper_size);
757 iommu_pages = iommu_size >> PAGE_SHIFT;
759 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
760 get_order(iommu_pages/8));
761 if (!iommu_gart_bitmap)
762 panic("Cannot allocate iommu bitmap\n");
764 #ifdef CONFIG_IOMMU_LEAK
768 ret = dma_debug_resize_entries(iommu_pages);
771 "PCI-DMA: Cannot trace all the entries\n");
776 * Out of IOMMU space handling.
777 * Reserve some invalid pages at the beginning of the GART.
779 iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
781 agp_memory_reserved = iommu_size;
783 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
786 iommu_start = aper_size - iommu_size;
787 iommu_bus_base = info.aper_base + iommu_start;
788 bad_dma_address = iommu_bus_base;
789 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
792 * Unmap the IOMMU part of the GART. The alias of the page is
793 * always mapped with cache enabled and there is no full cache
794 * coherency across the GART remapping. The unmapping avoids
795 * automatic prefetches from the CPU allocating cache lines in
796 * there. All CPU accesses are done via the direct mapping to
797 * the backing memory. The GART address is only used by PCI
800 set_memory_np((unsigned long)__va(iommu_bus_base),
801 iommu_size >> PAGE_SHIFT);
803 * Tricky. The GART table remaps the physical memory range,
804 * so the CPU wont notice potential aliases and if the memory
805 * is remapped to UC later on, we might surprise the PCI devices
806 * with a stray writeout of a cacheline. So play it sure and
807 * do an explicit, full-scale wbinvd() _after_ having marked all
808 * the pages as Not-Present:
813 * Now all caches are flushed and we can safely enable
814 * GART hardware. Doing it early leaves the possibility
815 * of stale cache entries that can lead to GART PTE
818 enable_gart_translations();
821 * Try to workaround a bug (thanks to BenH):
822 * Set unmapped entries to a scratch page instead of 0.
823 * Any prefetches that hit unmapped entries won't get an bus abort
824 * then. (P2P bridge may be prefetching on DMA reads).
826 scratch = get_zeroed_page(GFP_KERNEL);
828 panic("Cannot allocate iommu scratch page");
829 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
830 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
831 iommu_gatt_base[i] = gart_unmapped_entry;
834 dma_ops = &gart_dma_ops;
835 x86_platform.iommu_shutdown = gart_iommu_shutdown;
841 void __init gart_parse_options(char *p)
845 #ifdef CONFIG_IOMMU_LEAK
846 if (!strncmp(p, "leak", 4)) {
851 if (isdigit(*p) && get_option(&p, &arg))
852 iommu_leak_pages = arg;
855 if (isdigit(*p) && get_option(&p, &arg))
857 if (!strncmp(p, "fullflush", 9))
859 if (!strncmp(p, "nofullflush", 11))
861 if (!strncmp(p, "noagp", 5))
863 if (!strncmp(p, "noaperture", 10))
865 /* duplicated from pci-dma.c */
866 if (!strncmp(p, "force", 5))
867 gart_iommu_aperture_allowed = 1;
868 if (!strncmp(p, "allowed", 7))
869 gart_iommu_aperture_allowed = 1;
870 if (!strncmp(p, "memaper", 7)) {
871 fallback_aper_force = 1;
875 if (get_option(&p, &arg))
876 fallback_aper_order = arg;