2 * Dynamic DMA mapping support for AMD Hammer.
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
8 * See Documentation/DMA-mapping.txt for the interface specification.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/string.h>
20 #include <linux/spinlock.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/topology.h>
24 #include <linux/interrupt.h>
25 #include <linux/bitops.h>
26 #include <linux/kdebug.h>
27 #include <linux/scatterlist.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/pgtable.h>
34 #include <asm/proto.h>
35 #include <asm/iommu.h>
37 #include <asm/cacheflush.h>
38 #include <asm/swiotlb.h>
42 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
43 static unsigned long iommu_size; /* size of remapping area bytes */
44 static unsigned long iommu_pages; /* .. and in pages */
46 static u32 *iommu_gatt_base; /* Remapping table */
49 * If this is disabled the IOMMU will use an optimized flushing strategy
50 * of only flushing when an mapping is reused. With it true the GART is
51 * flushed for every mapping. Problem is that doing the lazy flush seems
52 * to trigger bugs with some popular PCI cards, in particular 3ware (but
53 * has been also also seen with Qlogic at least).
55 int iommu_fullflush = 1;
57 /* Allocation bitmap for the remapping area: */
58 static DEFINE_SPINLOCK(iommu_bitmap_lock);
59 /* Guarded by iommu_bitmap_lock: */
60 static unsigned long *iommu_gart_bitmap;
62 static u32 gart_unmapped_entry;
65 #define GPTE_COHERENT 2
66 #define GPTE_ENCODE(x) \
67 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
68 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
70 #define EMERGENCY_PAGES 32 /* = 128KB */
73 #define AGPEXTERN extern
78 /* backdoor interface to AGP driver */
79 AGPEXTERN int agp_memory_reserved;
80 AGPEXTERN __u32 *agp_gatt_table;
82 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
83 static int need_flush; /* global flush state. set for each gart wrap */
85 static unsigned long alloc_iommu(struct device *dev, int size,
86 unsigned long align_mask)
88 unsigned long offset, flags;
89 unsigned long boundary_size;
90 unsigned long base_index;
92 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
93 PAGE_SIZE) >> PAGE_SHIFT;
94 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
95 PAGE_SIZE) >> PAGE_SHIFT;
97 spin_lock_irqsave(&iommu_bitmap_lock, flags);
98 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
99 size, base_index, boundary_size, align_mask);
102 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
103 size, base_index, boundary_size,
107 next_bit = offset+size;
108 if (next_bit >= iommu_pages) {
115 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
120 static void free_iommu(unsigned long offset, int size)
124 spin_lock_irqsave(&iommu_bitmap_lock, flags);
125 iommu_area_free(iommu_gart_bitmap, offset, size);
126 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
130 * Use global flush state to avoid races with multiple flushers.
132 static void flush_gart(void)
136 spin_lock_irqsave(&iommu_bitmap_lock, flags);
141 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
144 #ifdef CONFIG_IOMMU_LEAK
146 #define SET_LEAK(x) \
148 if (iommu_leak_tab) \
149 iommu_leak_tab[x] = __builtin_return_address(0);\
152 #define CLEAR_LEAK(x) \
154 if (iommu_leak_tab) \
155 iommu_leak_tab[x] = NULL; \
158 /* Debugging aid for drivers that don't free their IOMMU tables */
159 static void **iommu_leak_tab;
160 static int leak_trace;
161 static int iommu_leak_pages = 20;
163 static void dump_leak(void)
168 if (dump || !iommu_leak_tab)
171 show_stack(NULL, NULL);
173 /* Very crude. dump some from the end of the table too */
174 printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
176 for (i = 0; i < iommu_leak_pages; i += 2) {
177 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
178 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0);
179 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
181 printk(KERN_DEBUG "\n");
185 # define CLEAR_LEAK(x)
188 static void iommu_full(struct device *dev, size_t size, int dir)
191 * Ran out of IOMMU space for this operation. This is very bad.
192 * Unfortunately the drivers cannot handle this operation properly.
193 * Return some non mapped prereserved space in the aperture and
194 * let the Northbridge deal with it. This will result in garbage
195 * in the IO operation. When the size exceeds the prereserved space
196 * memory corruption will occur or random memory will be DMAed
197 * out. Hopefully no network devices use single mappings that big.
200 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
202 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
203 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
204 panic("PCI-DMA: Memory would be corrupted\n");
205 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
207 "PCI-DMA: Random memory would be DMAed\n");
209 #ifdef CONFIG_IOMMU_LEAK
215 need_iommu(struct device *dev, unsigned long addr, size_t size)
217 u64 mask = *dev->dma_mask;
218 int high = addr + size > mask;
228 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
230 u64 mask = *dev->dma_mask;
231 int high = addr + size > mask;
237 /* Map a single continuous physical area into the IOMMU.
238 * Caller needs to check if the iommu is needed and flush.
240 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
241 size_t size, int dir, unsigned long align_mask)
243 unsigned long npages = iommu_num_pages(phys_mem, size);
244 unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
247 if (iommu_page == -1) {
248 if (!nonforced_iommu(dev, phys_mem, size))
250 if (panic_on_overflow)
251 panic("dma_map_area overflow %lu bytes\n", size);
252 iommu_full(dev, size, dir);
253 return bad_dma_address;
256 for (i = 0; i < npages; i++) {
257 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
258 SET_LEAK(iommu_page + i);
259 phys_mem += PAGE_SIZE;
261 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
264 /* Map a single area into the IOMMU */
266 gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
271 dev = &x86_dma_fallback_dev;
273 if (!need_iommu(dev, paddr, size))
276 bus = dma_map_area(dev, paddr, size, dir, 0);
283 * Free a DMA mapping.
285 static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
286 size_t size, int direction)
288 unsigned long iommu_page;
292 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
293 dma_addr >= iommu_bus_base + iommu_size)
296 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
297 npages = iommu_num_pages(dma_addr, size);
298 for (i = 0; i < npages; i++) {
299 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
300 CLEAR_LEAK(iommu_page + i);
302 free_iommu(iommu_page, npages);
306 * Wrapper for pci_unmap_single working with scatterlists.
309 gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
311 struct scatterlist *s;
314 for_each_sg(sg, s, nents, i) {
315 if (!s->dma_length || !s->length)
317 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
321 /* Fallback for dma_map_sg in case of overflow */
322 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
325 struct scatterlist *s;
328 #ifdef CONFIG_IOMMU_DEBUG
329 printk(KERN_DEBUG "dma_map_sg overflow\n");
332 for_each_sg(sg, s, nents, i) {
333 unsigned long addr = sg_phys(s);
335 if (nonforced_iommu(dev, addr, s->length)) {
336 addr = dma_map_area(dev, addr, s->length, dir, 0);
337 if (addr == bad_dma_address) {
339 gart_unmap_sg(dev, sg, i, dir);
341 sg[0].dma_length = 0;
345 s->dma_address = addr;
346 s->dma_length = s->length;
353 /* Map multiple scatterlist entries continuous into the first. */
354 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
355 int nelems, struct scatterlist *sout,
358 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
359 unsigned long iommu_page = iommu_start;
360 struct scatterlist *s;
363 if (iommu_start == -1)
366 for_each_sg(start, s, nelems, i) {
367 unsigned long pages, addr;
368 unsigned long phys_addr = s->dma_address;
370 BUG_ON(s != start && s->offset);
372 sout->dma_address = iommu_bus_base;
373 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
374 sout->dma_length = s->length;
376 sout->dma_length += s->length;
380 pages = iommu_num_pages(s->offset, s->length);
382 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
383 SET_LEAK(iommu_page);
388 BUG_ON(iommu_page - iommu_start != pages);
394 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
395 struct scatterlist *sout, unsigned long pages, int need)
399 sout->dma_address = start->dma_address;
400 sout->dma_length = start->length;
403 return __dma_map_cont(dev, start, nelems, sout, pages);
407 * DMA map all entries in a scatterlist.
408 * Merge chunks that have page aligned sizes into a continuous mapping.
411 gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
413 struct scatterlist *s, *ps, *start_sg, *sgmap;
414 int need = 0, nextneed, i, out, start;
415 unsigned long pages = 0;
416 unsigned int seg_size;
417 unsigned int max_seg_size;
423 dev = &x86_dma_fallback_dev;
427 start_sg = sgmap = sg;
429 max_seg_size = dma_get_max_seg_size(dev);
430 ps = NULL; /* shut up gcc */
431 for_each_sg(sg, s, nents, i) {
432 dma_addr_t addr = sg_phys(s);
434 s->dma_address = addr;
435 BUG_ON(s->length == 0);
437 nextneed = need_iommu(dev, addr, s->length);
439 /* Handle the previous not yet processed entries */
442 * Can only merge when the last chunk ends on a
443 * page boundary and the new one doesn't have an
446 if (!iommu_merge || !nextneed || !need || s->offset ||
447 (s->length + seg_size > max_seg_size) ||
448 (ps->offset + ps->length) % PAGE_SIZE) {
449 if (dma_map_cont(dev, start_sg, i - start,
450 sgmap, pages, need) < 0)
454 sgmap = sg_next(sgmap);
461 seg_size += s->length;
463 pages += iommu_num_pages(s->offset, s->length);
466 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
471 sgmap = sg_next(sgmap);
472 sgmap->dma_length = 0;
478 gart_unmap_sg(dev, sg, out, dir);
480 /* When it was forced or merged try again in a dumb way */
481 if (force_iommu || iommu_merge) {
482 out = dma_map_sg_nonforce(dev, sg, nents, dir);
486 if (panic_on_overflow)
487 panic("dma_map_sg: overflow on %lu pages\n", pages);
489 iommu_full(dev, pages << PAGE_SHIFT, dir);
490 for_each_sg(sg, s, nents, i)
491 s->dma_address = bad_dma_address;
495 /* allocate and map a coherent mapping */
497 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
501 unsigned long align_mask;
503 vaddr = (void *)__get_free_pages(flag | __GFP_ZERO, get_order(size));
507 align_mask = (1UL << get_order(size)) - 1;
510 dev = &x86_dma_fallback_dev;
512 *dma_addr = dma_map_area(dev, __pa(vaddr), size, DMA_BIDIRECTIONAL,
516 if (*dma_addr != bad_dma_address)
519 free_pages((unsigned long)vaddr, get_order(size));
524 /* free a coherent mapping */
526 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
529 gart_unmap_single(dev, dma_addr, size, DMA_BIDIRECTIONAL);
530 free_pages((unsigned long)vaddr, get_order(size));
535 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
540 iommu_size = aper_size;
545 a = aper + iommu_size;
546 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
548 if (iommu_size < 64*1024*1024) {
550 "PCI-DMA: Warning: Small IOMMU %luMB."
551 " Consider increasing the AGP aperture in BIOS\n",
558 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
560 unsigned aper_size = 0, aper_base_32, aper_order;
563 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
564 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
565 aper_order = (aper_order >> 1) & 7;
567 aper_base = aper_base_32 & 0x7fff;
570 aper_size = (32 * 1024 * 1024) << aper_order;
571 if (aper_base + aper_size > 0x100000000UL || !aper_size)
578 static void enable_gart_translations(void)
582 for (i = 0; i < num_k8_northbridges; i++) {
583 struct pci_dev *dev = k8_northbridges[i];
585 enable_gart_translation(dev, __pa(agp_gatt_table));
590 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
591 * resume in the same way as they are handled in gart_iommu_hole_init().
593 static bool fix_up_north_bridges;
594 static u32 aperture_order;
595 static u32 aperture_alloc;
597 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
599 fix_up_north_bridges = true;
600 aperture_order = aper_order;
601 aperture_alloc = aper_alloc;
604 static int gart_resume(struct sys_device *dev)
606 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
608 if (fix_up_north_bridges) {
611 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
613 for (i = 0; i < num_k8_northbridges; i++) {
614 struct pci_dev *dev = k8_northbridges[i];
617 * Don't enable translations just yet. That is the next
618 * step. Restore the pre-suspend aperture settings.
620 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
621 aperture_order << 1);
622 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
623 aperture_alloc >> 25);
627 enable_gart_translations();
632 static int gart_suspend(struct sys_device *dev, pm_message_t state)
637 static struct sysdev_class gart_sysdev_class = {
639 .suspend = gart_suspend,
640 .resume = gart_resume,
644 static struct sys_device device_gart = {
646 .cls = &gart_sysdev_class,
650 * Private Northbridge GATT initialization in case we cannot use the
651 * AGP driver for some reason.
653 static __init int init_k8_gatt(struct agp_kern_info *info)
655 unsigned aper_size, gatt_size, new_aper_size;
656 unsigned aper_base, new_aper_base;
660 unsigned long start_pfn, end_pfn;
662 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
663 aper_size = aper_base = info->aper_size = 0;
665 for (i = 0; i < num_k8_northbridges; i++) {
666 dev = k8_northbridges[i];
667 new_aper_base = read_aperture(dev, &new_aper_size);
672 aper_size = new_aper_size;
673 aper_base = new_aper_base;
675 if (aper_size != new_aper_size || aper_base != new_aper_base)
680 info->aper_base = aper_base;
681 info->aper_size = aper_size >> 20;
683 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
684 gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
686 panic("Cannot allocate GATT table");
687 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
688 panic("Could not set GART PTEs to uncacheable pages");
690 memset(gatt, 0, gatt_size);
691 agp_gatt_table = gatt;
693 enable_gart_translations();
695 error = sysdev_class_register(&gart_sysdev_class);
697 error = sysdev_register(&device_gart);
699 panic("Could not register gart_sysdev -- would corrupt data on next suspend");
703 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
704 aper_base, aper_size>>10);
706 /* need to map that range */
707 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
708 if (end_pfn > max_low_pfn_mapped) {
709 start_pfn = (aper_base>>PAGE_SHIFT);
710 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
715 /* Should not happen anymore */
716 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
717 KERN_WARNING "falling back to iommu=soft.\n");
721 extern int agp_amd64_init(void);
723 static struct dma_mapping_ops gart_dma_ops = {
724 .map_single = gart_map_single,
725 .unmap_single = gart_unmap_single,
726 .sync_single_for_cpu = NULL,
727 .sync_single_for_device = NULL,
728 .sync_single_range_for_cpu = NULL,
729 .sync_single_range_for_device = NULL,
730 .sync_sg_for_cpu = NULL,
731 .sync_sg_for_device = NULL,
732 .map_sg = gart_map_sg,
733 .unmap_sg = gart_unmap_sg,
734 .alloc_coherent = gart_alloc_coherent,
735 .free_coherent = gart_free_coherent,
738 void gart_iommu_shutdown(void)
743 if (no_agp && (dma_ops != &gart_dma_ops))
746 for (i = 0; i < num_k8_northbridges; i++) {
749 dev = k8_northbridges[i];
750 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
754 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
758 void __init gart_iommu_init(void)
760 struct agp_kern_info info;
761 unsigned long iommu_start;
762 unsigned long aper_size;
763 unsigned long scratch;
766 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
767 printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
771 #ifndef CONFIG_AGP_AMD64
774 /* Makefile puts PCI initialization via subsys_initcall first. */
775 /* Add other K8 AGP bridge drivers here */
777 (agp_amd64_init() < 0) ||
778 (agp_copy_info(agp_bridge, &info) < 0);
784 /* Did we detect a different HW IOMMU? */
785 if (iommu_detected && !gart_iommu_aperture)
789 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
790 !gart_iommu_aperture ||
791 (no_agp && init_k8_gatt(&info) < 0)) {
792 if (max_pfn > MAX_DMA32_PFN) {
793 printk(KERN_WARNING "More than 4GB of memory "
794 "but GART IOMMU not available.\n"
795 KERN_WARNING "falling back to iommu=soft.\n");
800 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
801 aper_size = info.aper_size * 1024 * 1024;
802 iommu_size = check_iommu_size(info.aper_base, aper_size);
803 iommu_pages = iommu_size >> PAGE_SHIFT;
805 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
806 get_order(iommu_pages/8));
807 if (!iommu_gart_bitmap)
808 panic("Cannot allocate iommu bitmap\n");
809 memset(iommu_gart_bitmap, 0, iommu_pages/8);
811 #ifdef CONFIG_IOMMU_LEAK
813 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
814 get_order(iommu_pages*sizeof(void *)));
816 memset(iommu_leak_tab, 0, iommu_pages * 8);
819 "PCI-DMA: Cannot allocate leak trace area\n");
824 * Out of IOMMU space handling.
825 * Reserve some invalid pages at the beginning of the GART.
827 set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
829 agp_memory_reserved = iommu_size;
831 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
834 iommu_start = aper_size - iommu_size;
835 iommu_bus_base = info.aper_base + iommu_start;
836 bad_dma_address = iommu_bus_base;
837 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
840 * Unmap the IOMMU part of the GART. The alias of the page is
841 * always mapped with cache enabled and there is no full cache
842 * coherency across the GART remapping. The unmapping avoids
843 * automatic prefetches from the CPU allocating cache lines in
844 * there. All CPU accesses are done via the direct mapping to
845 * the backing memory. The GART address is only used by PCI
848 set_memory_np((unsigned long)__va(iommu_bus_base),
849 iommu_size >> PAGE_SHIFT);
851 * Tricky. The GART table remaps the physical memory range,
852 * so the CPU wont notice potential aliases and if the memory
853 * is remapped to UC later on, we might surprise the PCI devices
854 * with a stray writeout of a cacheline. So play it sure and
855 * do an explicit, full-scale wbinvd() _after_ having marked all
856 * the pages as Not-Present:
861 * Try to workaround a bug (thanks to BenH):
862 * Set unmapped entries to a scratch page instead of 0.
863 * Any prefetches that hit unmapped entries won't get an bus abort
864 * then. (P2P bridge may be prefetching on DMA reads).
866 scratch = get_zeroed_page(GFP_KERNEL);
868 panic("Cannot allocate iommu scratch page");
869 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
870 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
871 iommu_gatt_base[i] = gart_unmapped_entry;
874 dma_ops = &gart_dma_ops;
877 void __init gart_parse_options(char *p)
881 #ifdef CONFIG_IOMMU_LEAK
882 if (!strncmp(p, "leak", 4)) {
886 if (isdigit(*p) && get_option(&p, &arg))
887 iommu_leak_pages = arg;
890 if (isdigit(*p) && get_option(&p, &arg))
892 if (!strncmp(p, "fullflush", 8))
894 if (!strncmp(p, "nofullflush", 11))
896 if (!strncmp(p, "noagp", 5))
898 if (!strncmp(p, "noaperture", 10))
900 /* duplicated from pci-dma.c */
901 if (!strncmp(p, "force", 5))
902 gart_iommu_aperture_allowed = 1;
903 if (!strncmp(p, "allowed", 7))
904 gart_iommu_aperture_allowed = 1;
905 if (!strncmp(p, "memaper", 7)) {
906 fallback_aper_force = 1;
910 if (get_option(&p, &arg))
911 fallback_aper_order = arg;