2 * AMD Family 10h mmconfig enablement
5 #include <linux/types.h>
7 #include <linux/string.h>
9 #include <asm/pci-direct.h>
10 #include <linux/sort.h>
15 struct pci_hostbridge_probe {
22 static u64 __cpuinitdata fam10h_pci_mmconf_base;
23 static int __cpuinitdata fam10h_pci_mmconf_base_status;
25 static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
26 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
27 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
35 static int __cpuinit cmp_range(const void *x1, const void *x2)
37 const struct range *r1 = x1;
38 const struct range *r2 = x2;
41 start1 = r1->start >> 32;
42 start2 = r2->start >> 32;
44 return start1 - start2;
48 /* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */
49 #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
50 #define BASE_VALID(b) ((b != (0xfdULL << 32)) && (b != (0xfeULL << 32)))
51 static void __cpuinit get_fam10h_pci_mmconf_base(void)
61 u64 base = FAM10H_PCI_MMCONF_BASE;
64 struct range range[8];
66 /* only try to get setting from BSP */
68 if (fam10h_pci_mmconf_base_status)
71 if (!early_pci_allowed())
75 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
80 bus = pci_probes[i].bus;
81 slot = pci_probes[i].slot;
82 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
85 device = (id>>16) & 0xffff;
86 if (pci_probes[i].vendor == vendor &&
87 pci_probes[i].device == device) {
97 address = MSR_K8_SYSCFG;
100 /* TOP_MEM2 is not enabled? */
101 if (!(val & (1<<21))) {
105 address = MSR_K8_TOP_MEM2;
106 rdmsrl(address, val);
107 tom2 = val & (0xffffULL<<32);
111 base = tom2 + (1ULL<<32);
114 * need to check if the range is in the high mmio range that is
118 for (i = 0; i < 8; i++) {
122 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
126 start = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
127 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
128 end = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
133 range[hi_mmio_num].start = start;
134 range[hi_mmio_num].end = end;
142 sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
144 if (range[hi_mmio_num - 1].end < base)
146 if (range[0].start > base)
149 /* need to find one window */
150 base = range[0].start - (1ULL << 32);
151 if ((base > tom2) && BASE_VALID(base))
153 base = range[hi_mmio_num - 1].end + (1ULL << 32);
154 if ((base > tom2) && BASE_VALID(base))
156 /* need to find window between ranges */
158 for (i = 0; i < hi_mmio_num - 1; i++) {
159 if (range[i + 1].start > (range[i].end + (1ULL << 32))) {
160 base = range[i].end + (1ULL << 32);
161 if ((base > tom2) && BASE_VALID(base))
167 fam10h_pci_mmconf_base_status = -1;
170 fam10h_pci_mmconf_base = base;
171 fam10h_pci_mmconf_base_status = 1;
174 void __cpuinit fam10h_check_enable_mmcfg(void)
179 address = MSR_FAM10H_MMIO_CONF_BASE;
180 rdmsrl(address, val);
182 /* try to make sure that AP's setting is identical to BSP setting */
183 if (val & FAM10H_MMIO_CONF_ENABLE) {
185 busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
186 FAM10H_MMIO_CONF_BUSRANGE_MASK;
188 /* only trust the one handle 256 buses, if acpi=off */
189 if (!acpi_pci_disabled || busnbits >= 8) {
191 base = val & (0xffffULL << 32);
192 if (fam10h_pci_mmconf_base_status <= 0) {
193 fam10h_pci_mmconf_base = base;
194 fam10h_pci_mmconf_base_status = 1;
196 } else if (fam10h_pci_mmconf_base == base)
202 * if it is not enabled, try to enable it and assume only one segment
205 get_fam10h_pci_mmconf_base();
206 if (fam10h_pci_mmconf_base_status <= 0)
209 printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
210 val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
211 (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
212 val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
213 FAM10H_MMIO_CONF_ENABLE;
214 wrmsrl(address, val);