1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/hpet.h>
8 #include <linux/init.h>
13 #include <asm/fixmap.h>
14 #include <asm/i8253.h>
17 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
35 unsigned long hpet_address;
36 unsigned long hpet_num_timers;
37 static void __iomem *hpet_virt_address;
40 struct clock_event_device evt;
48 static struct hpet_dev *hpet_devs;
50 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
52 unsigned long hpet_readl(unsigned long a)
54 return readl(hpet_virt_address + a);
57 static inline void hpet_writel(unsigned long d, unsigned long a)
59 writel(d, hpet_virt_address + a);
63 #include <asm/pgtable.h>
66 static inline void hpet_set_mapping(void)
68 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
70 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
74 static inline void hpet_clear_mapping(void)
76 iounmap(hpet_virt_address);
77 hpet_virt_address = NULL;
81 * HPET command line enable / disable
83 static int boot_hpet_disable;
86 static int __init hpet_setup(char *str)
89 if (!strncmp("disable", str, 7))
90 boot_hpet_disable = 1;
91 if (!strncmp("force", str, 5))
96 __setup("hpet=", hpet_setup);
98 static int __init disable_hpet(char *str)
100 boot_hpet_disable = 1;
103 __setup("nohpet", disable_hpet);
105 static inline int is_hpet_capable(void)
107 return !boot_hpet_disable && hpet_address;
111 * HPET timer interrupt enable / disable
113 static int hpet_legacy_int_enabled;
116 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
118 int is_hpet_enabled(void)
120 return is_hpet_capable() && hpet_legacy_int_enabled;
122 EXPORT_SYMBOL_GPL(is_hpet_enabled);
125 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
126 * timer 0 and timer 1 in case of RTC emulation.
129 static void hpet_reserve_msi_timers(struct hpet_data *hd)
136 for (i = 0; i < hpet_num_timers; i++) {
137 struct hpet_dev *hdev = &hpet_devs[i];
139 if (!(hdev->flags & HPET_DEV_VALID))
142 hd->hd_irq[hdev->num] = hdev->irq;
143 hpet_reserve_timer(hd, hdev->num);
147 static void hpet_reserve_platform_timers(unsigned long id)
149 struct hpet __iomem *hpet = hpet_virt_address;
150 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
151 unsigned int nrtimers, i;
154 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
156 memset(&hd, 0, sizeof(hd));
157 hd.hd_phys_address = hpet_address;
158 hd.hd_address = hpet;
159 hd.hd_nirqs = nrtimers;
160 hpet_reserve_timer(&hd, 0);
162 #ifdef CONFIG_HPET_EMULATE_RTC
163 hpet_reserve_timer(&hd, 1);
167 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
168 * is wrong for i8259!) not the output IRQ. Many BIOS writers
169 * don't bother configuring *any* comparator interrupts.
171 hd.hd_irq[0] = HPET_LEGACY_8254;
172 hd.hd_irq[1] = HPET_LEGACY_RTC;
174 for (i = 2; i < nrtimers; timer++, i++) {
175 hd.hd_irq[i] = (readl(&timer->hpet_config) &
176 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
179 hpet_reserve_msi_timers(&hd);
185 static void hpet_reserve_platform_timers(unsigned long id) { }
191 static unsigned long hpet_period;
193 static void hpet_legacy_set_mode(enum clock_event_mode mode,
194 struct clock_event_device *evt);
195 static int hpet_legacy_next_event(unsigned long delta,
196 struct clock_event_device *evt);
199 * The hpet clock event device
201 static struct clock_event_device hpet_clockevent = {
203 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
204 .set_mode = hpet_legacy_set_mode,
205 .set_next_event = hpet_legacy_next_event,
211 static void hpet_start_counter(void)
213 unsigned long cfg = hpet_readl(HPET_CFG);
215 cfg &= ~HPET_CFG_ENABLE;
216 hpet_writel(cfg, HPET_CFG);
217 hpet_writel(0, HPET_COUNTER);
218 hpet_writel(0, HPET_COUNTER + 4);
219 cfg |= HPET_CFG_ENABLE;
220 hpet_writel(cfg, HPET_CFG);
223 static void hpet_resume_device(void)
228 static void hpet_restart_counter(void)
230 hpet_resume_device();
231 hpet_start_counter();
234 static void hpet_enable_legacy_int(void)
236 unsigned long cfg = hpet_readl(HPET_CFG);
238 cfg |= HPET_CFG_LEGACY;
239 hpet_writel(cfg, HPET_CFG);
240 hpet_legacy_int_enabled = 1;
243 static void hpet_legacy_clockevent_register(void)
245 /* Start HPET legacy interrupts */
246 hpet_enable_legacy_int();
249 * The mult factor is defined as (include/linux/clockchips.h)
250 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
251 * hpet_period is in units of femtoseconds (per cycle), so
252 * mult/2^shift = cyc/ns = 10^6/hpet_period
253 * mult = (10^6 * 2^shift)/hpet_period
254 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
256 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
257 hpet_period, hpet_clockevent.shift);
258 /* Calculate the min / max delta */
259 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
261 /* 5 usec minimum reprogramming delta. */
262 hpet_clockevent.min_delta_ns = 5000;
265 * Start hpet with the boot cpu mask and make it
266 * global after the IO_APIC has been initialized.
268 hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
269 clockevents_register_device(&hpet_clockevent);
270 global_clock_event = &hpet_clockevent;
271 printk(KERN_DEBUG "hpet clockevent registered\n");
274 static int hpet_setup_msi_irq(unsigned int irq);
276 static void hpet_set_mode(enum clock_event_mode mode,
277 struct clock_event_device *evt, int timer)
279 unsigned long cfg, cmp, now;
283 case CLOCK_EVT_MODE_PERIODIC:
284 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
285 delta >>= evt->shift;
286 now = hpet_readl(HPET_COUNTER);
287 cmp = now + (unsigned long) delta;
288 cfg = hpet_readl(HPET_Tn_CFG(timer));
289 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
290 HPET_TN_SETVAL | HPET_TN_32BIT;
291 hpet_writel(cfg, HPET_Tn_CFG(timer));
293 * The first write after writing TN_SETVAL to the
294 * config register sets the counter value, the second
295 * write sets the period.
297 hpet_writel(cmp, HPET_Tn_CMP(timer));
299 hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
302 case CLOCK_EVT_MODE_ONESHOT:
303 cfg = hpet_readl(HPET_Tn_CFG(timer));
304 cfg &= ~HPET_TN_PERIODIC;
305 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
306 hpet_writel(cfg, HPET_Tn_CFG(timer));
309 case CLOCK_EVT_MODE_UNUSED:
310 case CLOCK_EVT_MODE_SHUTDOWN:
311 cfg = hpet_readl(HPET_Tn_CFG(timer));
312 cfg &= ~HPET_TN_ENABLE;
313 hpet_writel(cfg, HPET_Tn_CFG(timer));
316 case CLOCK_EVT_MODE_RESUME:
318 hpet_enable_legacy_int();
320 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
321 hpet_setup_msi_irq(hdev->irq);
322 disable_irq(hdev->irq);
323 irq_set_affinity(hdev->irq, cpumask_of_cpu(hdev->cpu));
324 enable_irq(hdev->irq);
330 static int hpet_next_event(unsigned long delta,
331 struct clock_event_device *evt, int timer)
335 cnt = hpet_readl(HPET_COUNTER);
337 hpet_writel(cnt, HPET_Tn_CMP(timer));
340 * We need to read back the CMP register to make sure that
341 * what we wrote hit the chip before we compare it to the
344 WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
346 return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
349 static void hpet_legacy_set_mode(enum clock_event_mode mode,
350 struct clock_event_device *evt)
352 hpet_set_mode(mode, evt, 0);
355 static int hpet_legacy_next_event(unsigned long delta,
356 struct clock_event_device *evt)
358 return hpet_next_event(delta, evt, 0);
364 #ifdef CONFIG_PCI_MSI
365 void hpet_msi_unmask(unsigned int irq)
367 struct hpet_dev *hdev = get_irq_data(irq);
371 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
373 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
376 void hpet_msi_mask(unsigned int irq)
379 struct hpet_dev *hdev = get_irq_data(irq);
382 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
384 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
387 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
389 struct hpet_dev *hdev = get_irq_data(irq);
391 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
392 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
395 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
397 struct hpet_dev *hdev = get_irq_data(irq);
399 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
400 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
404 static void hpet_msi_set_mode(enum clock_event_mode mode,
405 struct clock_event_device *evt)
407 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
408 hpet_set_mode(mode, evt, hdev->num);
411 static int hpet_msi_next_event(unsigned long delta,
412 struct clock_event_device *evt)
414 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
415 return hpet_next_event(delta, evt, hdev->num);
418 static int hpet_setup_msi_irq(unsigned int irq)
420 if (arch_setup_hpet_msi(irq)) {
427 static int hpet_assign_irq(struct hpet_dev *dev)
435 set_irq_data(irq, dev);
437 if (hpet_setup_msi_irq(irq))
444 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
446 struct hpet_dev *dev = (struct hpet_dev *)data;
447 struct clock_event_device *hevt = &dev->evt;
449 if (!hevt->event_handler) {
450 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
455 hevt->event_handler(hevt);
459 static int hpet_setup_irq(struct hpet_dev *dev)
462 if (request_irq(dev->irq, hpet_interrupt_handler,
463 IRQF_SHARED|IRQF_NOBALANCING, dev->name, dev))
466 disable_irq(dev->irq);
467 irq_set_affinity(dev->irq, cpumask_of_cpu(dev->cpu));
468 enable_irq(dev->irq);
473 /* This should be called in specific @cpu */
474 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
476 struct clock_event_device *evt = &hdev->evt;
479 WARN_ON(cpu != smp_processor_id());
480 if (!(hdev->flags & HPET_DEV_VALID))
483 if (hpet_setup_msi_irq(hdev->irq))
487 per_cpu(cpu_hpet_dev, cpu) = hdev;
488 evt->name = hdev->name;
489 hpet_setup_irq(hdev);
490 evt->irq = hdev->irq;
493 evt->features = CLOCK_EVT_FEAT_ONESHOT;
494 if (hdev->flags & HPET_DEV_PERI_CAP)
495 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
497 evt->set_mode = hpet_msi_set_mode;
498 evt->set_next_event = hpet_msi_next_event;
502 * The period is a femto seconds value. We need to calculate the
503 * scaled math multiplication factor for nanosecond to hpet tick
506 hpet_freq = 1000000000000000ULL;
507 do_div(hpet_freq, hpet_period);
508 evt->mult = div_sc((unsigned long) hpet_freq,
509 NSEC_PER_SEC, evt->shift);
510 /* Calculate the max delta */
511 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
512 /* 5 usec minimum reprogramming delta. */
513 evt->min_delta_ns = 5000;
515 evt->cpumask = cpumask_of_cpu(hdev->cpu);
516 clockevents_register_device(evt);
520 /* Reserve at least one timer for userspace (/dev/hpet) */
521 #define RESERVE_TIMERS 1
523 #define RESERVE_TIMERS 0
525 void hpet_msi_capability_lookup(unsigned int start_timer)
528 unsigned int num_timers;
529 unsigned int num_timers_used = 0;
532 id = hpet_readl(HPET_ID);
534 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
535 num_timers++; /* Value read out starts from 0 */
537 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
541 hpet_num_timers = num_timers;
543 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
544 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
545 unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
547 /* Only consider HPET timer with MSI support */
548 if (!(cfg & HPET_TN_FSB_CAP))
552 if (cfg & HPET_TN_PERIODIC_CAP)
553 hdev->flags |= HPET_DEV_PERI_CAP;
556 sprintf(hdev->name, "hpet%d", i);
557 if (hpet_assign_irq(hdev))
560 hdev->flags |= HPET_DEV_FSB_CAP;
561 hdev->flags |= HPET_DEV_VALID;
563 if (num_timers_used == num_possible_cpus())
567 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
568 num_timers, num_timers_used);
571 static struct hpet_dev *hpet_get_unused_timer(void)
578 for (i = 0; i < hpet_num_timers; i++) {
579 struct hpet_dev *hdev = &hpet_devs[i];
581 if (!(hdev->flags & HPET_DEV_VALID))
583 if (test_and_set_bit(HPET_DEV_USED_BIT,
584 (unsigned long *)&hdev->flags))
591 struct hpet_work_struct {
592 struct delayed_work work;
593 struct completion complete;
596 static void hpet_work(struct work_struct *w)
598 struct hpet_dev *hdev;
599 int cpu = smp_processor_id();
600 struct hpet_work_struct *hpet_work;
602 hpet_work = container_of(w, struct hpet_work_struct, work.work);
604 hdev = hpet_get_unused_timer();
606 init_one_hpet_msi_clockevent(hdev, cpu);
608 complete(&hpet_work->complete);
611 static int hpet_cpuhp_notify(struct notifier_block *n,
612 unsigned long action, void *hcpu)
614 unsigned long cpu = (unsigned long)hcpu;
615 struct hpet_work_struct work;
616 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
618 switch (action & 0xf) {
620 INIT_DELAYED_WORK(&work.work, hpet_work);
621 init_completion(&work.complete);
622 /* FIXME: add schedule_work_on() */
623 schedule_delayed_work_on(cpu, &work.work, 0);
624 wait_for_completion(&work.complete);
628 free_irq(hdev->irq, hdev);
629 hdev->flags &= ~HPET_DEV_USED;
630 per_cpu(cpu_hpet_dev, cpu) = NULL;
638 void hpet_msi_capability_lookup(unsigned int start_timer)
643 static int hpet_cpuhp_notify(struct notifier_block *n,
644 unsigned long action, void *hcpu)
652 * Clock source related code
654 static cycle_t read_hpet(void)
656 return (cycle_t)hpet_readl(HPET_COUNTER);
660 static cycle_t __vsyscall_fn vread_hpet(void)
662 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
666 static struct clocksource clocksource_hpet = {
672 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
673 .resume = hpet_restart_counter,
679 static int hpet_clocksource_register(void)
684 /* Start the counter */
685 hpet_start_counter();
687 /* Verify whether hpet counter works */
692 * We don't know the TSC frequency yet, but waiting for
693 * 200000 TSC cycles is safe:
700 } while ((now - start) < 200000UL);
702 if (t1 == read_hpet()) {
704 "HPET counter not counting. HPET disabled\n");
709 * The definition of mult is (include/linux/clocksource.h)
710 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
711 * so we first need to convert hpet_period to ns/cyc units:
712 * mult/2^shift = ns/cyc = hpet_period/10^6
713 * mult = (hpet_period * 2^shift)/10^6
714 * mult = (hpet_period << shift)/FSEC_PER_NSEC
716 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
718 clocksource_register(&clocksource_hpet);
724 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
726 int __init hpet_enable(void)
731 if (!is_hpet_capable())
737 * Read the period and check for a sane value:
739 hpet_period = hpet_readl(HPET_PERIOD);
742 * AMD SB700 based systems with spread spectrum enabled use a
743 * SMM based HPET emulation to provide proper frequency
744 * setting. The SMM code is initialized with the first HPET
745 * register access and takes some time to complete. During
746 * this time the config register reads 0xffffffff. We check
747 * for max. 1000 loops whether the config register reads a non
748 * 0xffffffff value to make sure that HPET is up and running
749 * before we go further. A counting loop is safe, as the HPET
750 * access takes thousands of CPU cycles. On non SB700 based
751 * machines this check is only done once and has no side
754 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
757 "HPET config register value = 0xFFFFFFFF. "
763 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
767 * Read the HPET ID register to retrieve the IRQ routing
768 * information and the number of channels
770 id = hpet_readl(HPET_ID);
772 #ifdef CONFIG_HPET_EMULATE_RTC
774 * The legacy routing mode needs at least two channels, tick timer
775 * and the rtc emulation channel.
777 if (!(id & HPET_ID_NUMBER))
781 if (hpet_clocksource_register())
784 if (id & HPET_ID_LEGSUP) {
785 hpet_legacy_clockevent_register();
786 hpet_msi_capability_lookup(2);
789 hpet_msi_capability_lookup(0);
793 hpet_clear_mapping();
794 boot_hpet_disable = 1;
799 * Needs to be late, as the reserve_timer code calls kalloc !
801 * Not a problem on i386 as hpet_enable is called from late_time_init,
802 * but on x86_64 it is necessary !
804 static __init int hpet_late_init(void)
808 if (boot_hpet_disable)
812 if (!force_hpet_address)
815 hpet_address = force_hpet_address;
817 if (!hpet_virt_address)
821 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
823 for_each_online_cpu(cpu) {
824 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
827 /* This notifier should be called after workqueue is ready */
828 hotcpu_notifier(hpet_cpuhp_notify, -20);
832 fs_initcall(hpet_late_init);
834 void hpet_disable(void)
836 if (is_hpet_capable()) {
837 unsigned long cfg = hpet_readl(HPET_CFG);
839 if (hpet_legacy_int_enabled) {
840 cfg &= ~HPET_CFG_LEGACY;
841 hpet_legacy_int_enabled = 0;
843 cfg &= ~HPET_CFG_ENABLE;
844 hpet_writel(cfg, HPET_CFG);
848 #ifdef CONFIG_HPET_EMULATE_RTC
850 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
851 * is enabled, we support RTC interrupt functionality in software.
852 * RTC has 3 kinds of interrupts:
853 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
855 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
856 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
857 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
858 * (1) and (2) above are implemented using polling at a frequency of
859 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
860 * overhead. (DEFAULT_RTC_INT_FREQ)
861 * For (3), we use interrupts at 64Hz or user specified periodic
862 * frequency, whichever is higher.
864 #include <linux/mc146818rtc.h>
865 #include <linux/rtc.h>
868 #define DEFAULT_RTC_INT_FREQ 64
869 #define DEFAULT_RTC_SHIFT 6
870 #define RTC_NUM_INTS 1
872 static unsigned long hpet_rtc_flags;
873 static int hpet_prev_update_sec;
874 static struct rtc_time hpet_alarm_time;
875 static unsigned long hpet_pie_count;
876 static unsigned long hpet_t1_cmp;
877 static unsigned long hpet_default_delta;
878 static unsigned long hpet_pie_delta;
879 static unsigned long hpet_pie_limit;
881 static rtc_irq_handler irq_handler;
884 * Registers a IRQ handler.
886 int hpet_register_irq_handler(rtc_irq_handler handler)
888 if (!is_hpet_enabled())
893 irq_handler = handler;
897 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
900 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
903 void hpet_unregister_irq_handler(rtc_irq_handler handler)
905 if (!is_hpet_enabled())
911 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
914 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
915 * is not supported by all HPET implementations for timer 1.
917 * hpet_rtc_timer_init() is called when the rtc is initialized.
919 int hpet_rtc_timer_init(void)
921 unsigned long cfg, cnt, delta, flags;
923 if (!is_hpet_enabled())
926 if (!hpet_default_delta) {
929 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
930 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
931 hpet_default_delta = (unsigned long) clc;
934 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
935 delta = hpet_default_delta;
937 delta = hpet_pie_delta;
939 local_irq_save(flags);
941 cnt = delta + hpet_readl(HPET_COUNTER);
942 hpet_writel(cnt, HPET_T1_CMP);
945 cfg = hpet_readl(HPET_T1_CFG);
946 cfg &= ~HPET_TN_PERIODIC;
947 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
948 hpet_writel(cfg, HPET_T1_CFG);
950 local_irq_restore(flags);
954 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
957 * The functions below are called from rtc driver.
958 * Return 0 if HPET is not being used.
959 * Otherwise do the necessary changes and return 1.
961 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
963 if (!is_hpet_enabled())
966 hpet_rtc_flags &= ~bit_mask;
969 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
971 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
973 unsigned long oldbits = hpet_rtc_flags;
975 if (!is_hpet_enabled())
978 hpet_rtc_flags |= bit_mask;
980 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
981 hpet_prev_update_sec = -1;
984 hpet_rtc_timer_init();
988 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
990 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
993 if (!is_hpet_enabled())
996 hpet_alarm_time.tm_hour = hrs;
997 hpet_alarm_time.tm_min = min;
998 hpet_alarm_time.tm_sec = sec;
1002 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1004 int hpet_set_periodic_freq(unsigned long freq)
1008 if (!is_hpet_enabled())
1011 if (freq <= DEFAULT_RTC_INT_FREQ)
1012 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1014 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1016 clc >>= hpet_clockevent.shift;
1017 hpet_pie_delta = (unsigned long) clc;
1021 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1023 int hpet_rtc_dropped_irq(void)
1025 return is_hpet_enabled();
1027 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1029 static void hpet_rtc_timer_reinit(void)
1031 unsigned long cfg, delta;
1034 if (unlikely(!hpet_rtc_flags)) {
1035 cfg = hpet_readl(HPET_T1_CFG);
1036 cfg &= ~HPET_TN_ENABLE;
1037 hpet_writel(cfg, HPET_T1_CFG);
1041 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1042 delta = hpet_default_delta;
1044 delta = hpet_pie_delta;
1047 * Increment the comparator value until we are ahead of the
1051 hpet_t1_cmp += delta;
1052 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1054 } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
1057 if (hpet_rtc_flags & RTC_PIE)
1058 hpet_pie_count += lost_ints;
1059 if (printk_ratelimit())
1060 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1065 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1067 struct rtc_time curr_time;
1068 unsigned long rtc_int_flag = 0;
1070 hpet_rtc_timer_reinit();
1071 memset(&curr_time, 0, sizeof(struct rtc_time));
1073 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1074 get_rtc_time(&curr_time);
1076 if (hpet_rtc_flags & RTC_UIE &&
1077 curr_time.tm_sec != hpet_prev_update_sec) {
1078 if (hpet_prev_update_sec >= 0)
1079 rtc_int_flag = RTC_UF;
1080 hpet_prev_update_sec = curr_time.tm_sec;
1083 if (hpet_rtc_flags & RTC_PIE &&
1084 ++hpet_pie_count >= hpet_pie_limit) {
1085 rtc_int_flag |= RTC_PF;
1089 if (hpet_rtc_flags & RTC_AIE &&
1090 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1091 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1092 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1093 rtc_int_flag |= RTC_AF;
1096 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1098 irq_handler(rtc_int_flag, dev_id);
1102 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);