1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/hpet.h>
8 #include <linux/init.h>
13 #include <asm/fixmap.h>
14 #include <asm/i8253.h>
17 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
35 unsigned long hpet_address;
37 static unsigned long hpet_num_timers;
39 static void __iomem *hpet_virt_address;
42 struct clock_event_device evt;
50 inline unsigned int hpet_readl(unsigned int a)
52 return readl(hpet_virt_address + a);
55 static inline void hpet_writel(unsigned int d, unsigned int a)
57 writel(d, hpet_virt_address + a);
61 #include <asm/pgtable.h>
64 static inline void hpet_set_mapping(void)
66 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
68 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
72 static inline void hpet_clear_mapping(void)
74 iounmap(hpet_virt_address);
75 hpet_virt_address = NULL;
79 * HPET command line enable / disable
81 static int boot_hpet_disable;
83 static int hpet_verbose;
85 static int __init hpet_setup(char *str)
88 if (!strncmp("disable", str, 7))
89 boot_hpet_disable = 1;
90 if (!strncmp("force", str, 5))
92 if (!strncmp("verbose", str, 7))
97 __setup("hpet=", hpet_setup);
99 static int __init disable_hpet(char *str)
101 boot_hpet_disable = 1;
104 __setup("nohpet", disable_hpet);
106 static inline int is_hpet_capable(void)
108 return !boot_hpet_disable && hpet_address;
112 * HPET timer interrupt enable / disable
114 static int hpet_legacy_int_enabled;
117 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
119 int is_hpet_enabled(void)
121 return is_hpet_capable() && hpet_legacy_int_enabled;
123 EXPORT_SYMBOL_GPL(is_hpet_enabled);
125 static void _hpet_print_config(const char *function, int line)
128 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
129 l = hpet_readl(HPET_ID);
130 h = hpet_readl(HPET_PERIOD);
131 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
132 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
133 l = hpet_readl(HPET_CFG);
134 h = hpet_readl(HPET_STATUS);
135 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
136 l = hpet_readl(HPET_COUNTER);
137 h = hpet_readl(HPET_COUNTER+4);
138 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
140 for (i = 0; i < timers; i++) {
141 l = hpet_readl(HPET_Tn_CFG(i));
142 h = hpet_readl(HPET_Tn_CFG(i)+4);
143 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
145 l = hpet_readl(HPET_Tn_CMP(i));
146 h = hpet_readl(HPET_Tn_CMP(i)+4);
147 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
149 l = hpet_readl(HPET_Tn_ROUTE(i));
150 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
151 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
156 #define hpet_print_config() \
159 _hpet_print_config(__FUNCTION__, __LINE__); \
163 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
164 * timer 0 and timer 1 in case of RTC emulation.
168 static void hpet_reserve_msi_timers(struct hpet_data *hd);
170 static void hpet_reserve_platform_timers(unsigned int id)
172 struct hpet __iomem *hpet = hpet_virt_address;
173 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
174 unsigned int nrtimers, i;
177 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
179 memset(&hd, 0, sizeof(hd));
180 hd.hd_phys_address = hpet_address;
181 hd.hd_address = hpet;
182 hd.hd_nirqs = nrtimers;
183 hpet_reserve_timer(&hd, 0);
185 #ifdef CONFIG_HPET_EMULATE_RTC
186 hpet_reserve_timer(&hd, 1);
190 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
191 * is wrong for i8259!) not the output IRQ. Many BIOS writers
192 * don't bother configuring *any* comparator interrupts.
194 hd.hd_irq[0] = HPET_LEGACY_8254;
195 hd.hd_irq[1] = HPET_LEGACY_RTC;
197 for (i = 2; i < nrtimers; timer++, i++) {
198 hd.hd_irq[i] = (readl(&timer->hpet_config) &
199 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
202 hpet_reserve_msi_timers(&hd);
208 static void hpet_reserve_platform_timers(unsigned int id) { }
214 static unsigned long hpet_period;
216 static void hpet_legacy_set_mode(enum clock_event_mode mode,
217 struct clock_event_device *evt);
218 static int hpet_legacy_next_event(unsigned long delta,
219 struct clock_event_device *evt);
222 * The hpet clock event device
224 static struct clock_event_device hpet_clockevent = {
226 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
227 .set_mode = hpet_legacy_set_mode,
228 .set_next_event = hpet_legacy_next_event,
234 static void hpet_stop_counter(void)
236 unsigned long cfg = hpet_readl(HPET_CFG);
237 cfg &= ~HPET_CFG_ENABLE;
238 hpet_writel(cfg, HPET_CFG);
241 static void hpet_reset_counter(void)
243 hpet_writel(0, HPET_COUNTER);
244 hpet_writel(0, HPET_COUNTER + 4);
247 static void hpet_start_counter(void)
249 unsigned int cfg = hpet_readl(HPET_CFG);
250 cfg |= HPET_CFG_ENABLE;
251 hpet_writel(cfg, HPET_CFG);
254 static void hpet_restart_counter(void)
257 hpet_reset_counter();
258 hpet_start_counter();
261 static void hpet_resume_device(void)
266 static void hpet_resume_counter(void)
268 hpet_resume_device();
269 hpet_restart_counter();
272 static void hpet_enable_legacy_int(void)
274 unsigned int cfg = hpet_readl(HPET_CFG);
276 cfg |= HPET_CFG_LEGACY;
277 hpet_writel(cfg, HPET_CFG);
278 hpet_legacy_int_enabled = 1;
281 static void hpet_legacy_clockevent_register(void)
283 /* Start HPET legacy interrupts */
284 hpet_enable_legacy_int();
287 * The mult factor is defined as (include/linux/clockchips.h)
288 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
289 * hpet_period is in units of femtoseconds (per cycle), so
290 * mult/2^shift = cyc/ns = 10^6/hpet_period
291 * mult = (10^6 * 2^shift)/hpet_period
292 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
294 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
295 hpet_period, hpet_clockevent.shift);
296 /* Calculate the min / max delta */
297 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
299 /* 5 usec minimum reprogramming delta. */
300 hpet_clockevent.min_delta_ns = 5000;
303 * Start hpet with the boot cpu mask and make it
304 * global after the IO_APIC has been initialized.
306 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
307 clockevents_register_device(&hpet_clockevent);
308 global_clock_event = &hpet_clockevent;
309 printk(KERN_DEBUG "hpet clockevent registered\n");
312 static int hpet_setup_msi_irq(unsigned int irq);
314 static void hpet_set_mode(enum clock_event_mode mode,
315 struct clock_event_device *evt, int timer)
317 unsigned int cfg, cmp, now;
321 case CLOCK_EVT_MODE_PERIODIC:
323 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
324 delta >>= evt->shift;
325 now = hpet_readl(HPET_COUNTER);
326 cmp = now + (unsigned int) delta;
327 cfg = hpet_readl(HPET_Tn_CFG(timer));
328 /* Make sure we use edge triggered interrupts */
329 cfg &= ~HPET_TN_LEVEL;
330 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
331 HPET_TN_SETVAL | HPET_TN_32BIT;
332 hpet_writel(cfg, HPET_Tn_CFG(timer));
333 hpet_writel(cmp, HPET_Tn_CMP(timer));
336 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
337 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
338 * bit is automatically cleared after the first write.
339 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
340 * Publication # 24674)
342 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
343 hpet_start_counter();
347 case CLOCK_EVT_MODE_ONESHOT:
348 cfg = hpet_readl(HPET_Tn_CFG(timer));
349 cfg &= ~HPET_TN_PERIODIC;
350 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
351 hpet_writel(cfg, HPET_Tn_CFG(timer));
354 case CLOCK_EVT_MODE_UNUSED:
355 case CLOCK_EVT_MODE_SHUTDOWN:
356 cfg = hpet_readl(HPET_Tn_CFG(timer));
357 cfg &= ~HPET_TN_ENABLE;
358 hpet_writel(cfg, HPET_Tn_CFG(timer));
361 case CLOCK_EVT_MODE_RESUME:
363 hpet_enable_legacy_int();
365 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
366 hpet_setup_msi_irq(hdev->irq);
367 disable_irq(hdev->irq);
368 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
369 enable_irq(hdev->irq);
376 static int hpet_next_event(unsigned long delta,
377 struct clock_event_device *evt, int timer)
381 cnt = hpet_readl(HPET_COUNTER);
383 hpet_writel(cnt, HPET_Tn_CMP(timer));
386 * We need to read back the CMP register to make sure that
387 * what we wrote hit the chip before we compare it to the
390 WARN_ON_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt);
392 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
395 static void hpet_legacy_set_mode(enum clock_event_mode mode,
396 struct clock_event_device *evt)
398 hpet_set_mode(mode, evt, 0);
401 static int hpet_legacy_next_event(unsigned long delta,
402 struct clock_event_device *evt)
404 return hpet_next_event(delta, evt, 0);
410 #ifdef CONFIG_PCI_MSI
412 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
413 static struct hpet_dev *hpet_devs;
415 void hpet_msi_unmask(unsigned int irq)
417 struct hpet_dev *hdev = get_irq_data(irq);
421 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
423 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
426 void hpet_msi_mask(unsigned int irq)
429 struct hpet_dev *hdev = get_irq_data(irq);
432 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
434 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
437 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
439 struct hpet_dev *hdev = get_irq_data(irq);
441 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
442 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
445 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
447 struct hpet_dev *hdev = get_irq_data(irq);
449 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
450 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
454 static void hpet_msi_set_mode(enum clock_event_mode mode,
455 struct clock_event_device *evt)
457 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
458 hpet_set_mode(mode, evt, hdev->num);
461 static int hpet_msi_next_event(unsigned long delta,
462 struct clock_event_device *evt)
464 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
465 return hpet_next_event(delta, evt, hdev->num);
468 static int hpet_setup_msi_irq(unsigned int irq)
470 if (arch_setup_hpet_msi(irq)) {
477 static int hpet_assign_irq(struct hpet_dev *dev)
485 set_irq_data(irq, dev);
487 if (hpet_setup_msi_irq(irq))
494 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
496 struct hpet_dev *dev = (struct hpet_dev *)data;
497 struct clock_event_device *hevt = &dev->evt;
499 if (!hevt->event_handler) {
500 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
505 hevt->event_handler(hevt);
509 static int hpet_setup_irq(struct hpet_dev *dev)
512 if (request_irq(dev->irq, hpet_interrupt_handler,
513 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
517 disable_irq(dev->irq);
518 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
519 enable_irq(dev->irq);
521 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
522 dev->name, dev->irq);
527 /* This should be called in specific @cpu */
528 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
530 struct clock_event_device *evt = &hdev->evt;
533 WARN_ON(cpu != smp_processor_id());
534 if (!(hdev->flags & HPET_DEV_VALID))
537 if (hpet_setup_msi_irq(hdev->irq))
541 per_cpu(cpu_hpet_dev, cpu) = hdev;
542 evt->name = hdev->name;
543 hpet_setup_irq(hdev);
544 evt->irq = hdev->irq;
547 evt->features = CLOCK_EVT_FEAT_ONESHOT;
548 if (hdev->flags & HPET_DEV_PERI_CAP)
549 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
551 evt->set_mode = hpet_msi_set_mode;
552 evt->set_next_event = hpet_msi_next_event;
556 * The period is a femto seconds value. We need to calculate the
557 * scaled math multiplication factor for nanosecond to hpet tick
560 hpet_freq = 1000000000000000ULL;
561 do_div(hpet_freq, hpet_period);
562 evt->mult = div_sc((unsigned long) hpet_freq,
563 NSEC_PER_SEC, evt->shift);
564 /* Calculate the max delta */
565 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
566 /* 5 usec minimum reprogramming delta. */
567 evt->min_delta_ns = 5000;
569 evt->cpumask = cpumask_of(hdev->cpu);
570 clockevents_register_device(evt);
574 /* Reserve at least one timer for userspace (/dev/hpet) */
575 #define RESERVE_TIMERS 1
577 #define RESERVE_TIMERS 0
580 static void hpet_msi_capability_lookup(unsigned int start_timer)
583 unsigned int num_timers;
584 unsigned int num_timers_used = 0;
587 if (boot_cpu_has(X86_FEATURE_ARAT))
589 id = hpet_readl(HPET_ID);
591 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
592 num_timers++; /* Value read out starts from 0 */
595 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
599 hpet_num_timers = num_timers;
601 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
602 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
603 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
605 /* Only consider HPET timer with MSI support */
606 if (!(cfg & HPET_TN_FSB_CAP))
610 if (cfg & HPET_TN_PERIODIC_CAP)
611 hdev->flags |= HPET_DEV_PERI_CAP;
614 sprintf(hdev->name, "hpet%d", i);
615 if (hpet_assign_irq(hdev))
618 hdev->flags |= HPET_DEV_FSB_CAP;
619 hdev->flags |= HPET_DEV_VALID;
621 if (num_timers_used == num_possible_cpus())
625 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
626 num_timers, num_timers_used);
630 static void hpet_reserve_msi_timers(struct hpet_data *hd)
637 for (i = 0; i < hpet_num_timers; i++) {
638 struct hpet_dev *hdev = &hpet_devs[i];
640 if (!(hdev->flags & HPET_DEV_VALID))
643 hd->hd_irq[hdev->num] = hdev->irq;
644 hpet_reserve_timer(hd, hdev->num);
649 static struct hpet_dev *hpet_get_unused_timer(void)
656 for (i = 0; i < hpet_num_timers; i++) {
657 struct hpet_dev *hdev = &hpet_devs[i];
659 if (!(hdev->flags & HPET_DEV_VALID))
661 if (test_and_set_bit(HPET_DEV_USED_BIT,
662 (unsigned long *)&hdev->flags))
669 struct hpet_work_struct {
670 struct delayed_work work;
671 struct completion complete;
674 static void hpet_work(struct work_struct *w)
676 struct hpet_dev *hdev;
677 int cpu = smp_processor_id();
678 struct hpet_work_struct *hpet_work;
680 hpet_work = container_of(w, struct hpet_work_struct, work.work);
682 hdev = hpet_get_unused_timer();
684 init_one_hpet_msi_clockevent(hdev, cpu);
686 complete(&hpet_work->complete);
689 static int hpet_cpuhp_notify(struct notifier_block *n,
690 unsigned long action, void *hcpu)
692 unsigned long cpu = (unsigned long)hcpu;
693 struct hpet_work_struct work;
694 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
696 switch (action & 0xf) {
698 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
699 init_completion(&work.complete);
700 /* FIXME: add schedule_work_on() */
701 schedule_delayed_work_on(cpu, &work.work, 0);
702 wait_for_completion(&work.complete);
703 destroy_timer_on_stack(&work.work.timer);
707 free_irq(hdev->irq, hdev);
708 hdev->flags &= ~HPET_DEV_USED;
709 per_cpu(cpu_hpet_dev, cpu) = NULL;
717 static int hpet_setup_msi_irq(unsigned int irq)
721 static void hpet_msi_capability_lookup(unsigned int start_timer)
727 static void hpet_reserve_msi_timers(struct hpet_data *hd)
733 static int hpet_cpuhp_notify(struct notifier_block *n,
734 unsigned long action, void *hcpu)
742 * Clock source related code
744 static cycle_t read_hpet(struct clocksource *cs)
746 return (cycle_t)hpet_readl(HPET_COUNTER);
750 static cycle_t __vsyscall_fn vread_hpet(void)
752 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
756 static struct clocksource clocksource_hpet = {
762 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
763 .resume = hpet_resume_counter,
769 static int hpet_clocksource_register(void)
774 /* Start the counter */
775 hpet_restart_counter();
777 /* Verify whether hpet counter works */
778 t1 = hpet_readl(HPET_COUNTER);
782 * We don't know the TSC frequency yet, but waiting for
783 * 200000 TSC cycles is safe:
790 } while ((now - start) < 200000UL);
792 if (t1 == hpet_readl(HPET_COUNTER)) {
794 "HPET counter not counting. HPET disabled\n");
799 * The definition of mult is (include/linux/clocksource.h)
800 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
801 * so we first need to convert hpet_period to ns/cyc units:
802 * mult/2^shift = ns/cyc = hpet_period/10^6
803 * mult = (hpet_period * 2^shift)/10^6
804 * mult = (hpet_period << shift)/FSEC_PER_NSEC
806 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
808 clocksource_register(&clocksource_hpet);
814 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
816 int __init hpet_enable(void)
821 if (!is_hpet_capable())
827 * Read the period and check for a sane value:
829 hpet_period = hpet_readl(HPET_PERIOD);
832 * AMD SB700 based systems with spread spectrum enabled use a
833 * SMM based HPET emulation to provide proper frequency
834 * setting. The SMM code is initialized with the first HPET
835 * register access and takes some time to complete. During
836 * this time the config register reads 0xffffffff. We check
837 * for max. 1000 loops whether the config register reads a non
838 * 0xffffffff value to make sure that HPET is up and running
839 * before we go further. A counting loop is safe, as the HPET
840 * access takes thousands of CPU cycles. On non SB700 based
841 * machines this check is only done once and has no side
844 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
847 "HPET config register value = 0xFFFFFFFF. "
853 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
857 * Read the HPET ID register to retrieve the IRQ routing
858 * information and the number of channels
860 id = hpet_readl(HPET_ID);
863 #ifdef CONFIG_HPET_EMULATE_RTC
865 * The legacy routing mode needs at least two channels, tick timer
866 * and the rtc emulation channel.
868 if (!(id & HPET_ID_NUMBER))
872 if (hpet_clocksource_register())
875 if (id & HPET_ID_LEGSUP) {
876 hpet_legacy_clockevent_register();
882 hpet_clear_mapping();
888 * Needs to be late, as the reserve_timer code calls kalloc !
890 * Not a problem on i386 as hpet_enable is called from late_time_init,
891 * but on x86_64 it is necessary !
893 static __init int hpet_late_init(void)
897 if (boot_hpet_disable)
901 if (!force_hpet_address)
904 hpet_address = force_hpet_address;
908 if (!hpet_virt_address)
911 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
912 hpet_msi_capability_lookup(2);
914 hpet_msi_capability_lookup(0);
916 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
919 if (boot_cpu_has(X86_FEATURE_ARAT))
922 for_each_online_cpu(cpu) {
923 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
926 /* This notifier should be called after workqueue is ready */
927 hotcpu_notifier(hpet_cpuhp_notify, -20);
931 fs_initcall(hpet_late_init);
933 void hpet_disable(void)
935 if (is_hpet_capable()) {
936 unsigned int cfg = hpet_readl(HPET_CFG);
938 if (hpet_legacy_int_enabled) {
939 cfg &= ~HPET_CFG_LEGACY;
940 hpet_legacy_int_enabled = 0;
942 cfg &= ~HPET_CFG_ENABLE;
943 hpet_writel(cfg, HPET_CFG);
947 #ifdef CONFIG_HPET_EMULATE_RTC
949 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
950 * is enabled, we support RTC interrupt functionality in software.
951 * RTC has 3 kinds of interrupts:
952 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
954 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
955 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
956 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
957 * (1) and (2) above are implemented using polling at a frequency of
958 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
959 * overhead. (DEFAULT_RTC_INT_FREQ)
960 * For (3), we use interrupts at 64Hz or user specified periodic
961 * frequency, whichever is higher.
963 #include <linux/mc146818rtc.h>
964 #include <linux/rtc.h>
967 #define DEFAULT_RTC_INT_FREQ 64
968 #define DEFAULT_RTC_SHIFT 6
969 #define RTC_NUM_INTS 1
971 static unsigned long hpet_rtc_flags;
972 static int hpet_prev_update_sec;
973 static struct rtc_time hpet_alarm_time;
974 static unsigned long hpet_pie_count;
975 static u32 hpet_t1_cmp;
976 static u32 hpet_default_delta;
977 static u32 hpet_pie_delta;
978 static unsigned long hpet_pie_limit;
980 static rtc_irq_handler irq_handler;
983 * Check that the hpet counter c1 is ahead of the c2
985 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
987 return (s32)(c2 - c1) < 0;
991 * Registers a IRQ handler.
993 int hpet_register_irq_handler(rtc_irq_handler handler)
995 if (!is_hpet_enabled())
1000 irq_handler = handler;
1004 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1007 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1010 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1012 if (!is_hpet_enabled())
1018 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1021 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1022 * is not supported by all HPET implementations for timer 1.
1024 * hpet_rtc_timer_init() is called when the rtc is initialized.
1026 int hpet_rtc_timer_init(void)
1028 unsigned int cfg, cnt, delta;
1029 unsigned long flags;
1031 if (!is_hpet_enabled())
1034 if (!hpet_default_delta) {
1037 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1038 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1039 hpet_default_delta = clc;
1042 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1043 delta = hpet_default_delta;
1045 delta = hpet_pie_delta;
1047 local_irq_save(flags);
1049 cnt = delta + hpet_readl(HPET_COUNTER);
1050 hpet_writel(cnt, HPET_T1_CMP);
1053 cfg = hpet_readl(HPET_T1_CFG);
1054 cfg &= ~HPET_TN_PERIODIC;
1055 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1056 hpet_writel(cfg, HPET_T1_CFG);
1058 local_irq_restore(flags);
1062 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1065 * The functions below are called from rtc driver.
1066 * Return 0 if HPET is not being used.
1067 * Otherwise do the necessary changes and return 1.
1069 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1071 if (!is_hpet_enabled())
1074 hpet_rtc_flags &= ~bit_mask;
1077 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1079 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1081 unsigned long oldbits = hpet_rtc_flags;
1083 if (!is_hpet_enabled())
1086 hpet_rtc_flags |= bit_mask;
1088 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1089 hpet_prev_update_sec = -1;
1092 hpet_rtc_timer_init();
1096 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1098 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1101 if (!is_hpet_enabled())
1104 hpet_alarm_time.tm_hour = hrs;
1105 hpet_alarm_time.tm_min = min;
1106 hpet_alarm_time.tm_sec = sec;
1110 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1112 int hpet_set_periodic_freq(unsigned long freq)
1116 if (!is_hpet_enabled())
1119 if (freq <= DEFAULT_RTC_INT_FREQ)
1120 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1122 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1124 clc >>= hpet_clockevent.shift;
1125 hpet_pie_delta = clc;
1129 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1131 int hpet_rtc_dropped_irq(void)
1133 return is_hpet_enabled();
1135 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1137 static void hpet_rtc_timer_reinit(void)
1139 unsigned int cfg, delta;
1142 if (unlikely(!hpet_rtc_flags)) {
1143 cfg = hpet_readl(HPET_T1_CFG);
1144 cfg &= ~HPET_TN_ENABLE;
1145 hpet_writel(cfg, HPET_T1_CFG);
1149 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1150 delta = hpet_default_delta;
1152 delta = hpet_pie_delta;
1155 * Increment the comparator value until we are ahead of the
1159 hpet_t1_cmp += delta;
1160 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1162 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1165 if (hpet_rtc_flags & RTC_PIE)
1166 hpet_pie_count += lost_ints;
1167 if (printk_ratelimit())
1168 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1173 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1175 struct rtc_time curr_time;
1176 unsigned long rtc_int_flag = 0;
1178 hpet_rtc_timer_reinit();
1179 memset(&curr_time, 0, sizeof(struct rtc_time));
1181 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1182 get_rtc_time(&curr_time);
1184 if (hpet_rtc_flags & RTC_UIE &&
1185 curr_time.tm_sec != hpet_prev_update_sec) {
1186 if (hpet_prev_update_sec >= 0)
1187 rtc_int_flag = RTC_UF;
1188 hpet_prev_update_sec = curr_time.tm_sec;
1191 if (hpet_rtc_flags & RTC_PIE &&
1192 ++hpet_pie_count >= hpet_pie_limit) {
1193 rtc_int_flag |= RTC_PF;
1197 if (hpet_rtc_flags & RTC_AIE &&
1198 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1199 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1200 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1201 rtc_int_flag |= RTC_AF;
1204 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1206 irq_handler(rtc_int_flag, dev_id);
1210 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);