SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpu.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/string.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/module.h>
  20 #include <linux/hardirq.h>
  21 #include <linux/timer.h>
  22 #include <linux/proc_fs.h>
  23 #include <asm/current.h>
  24 #include <asm/smp.h>
  25 #include <asm/genapic.h>
  26 #include <asm/ipi.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/uv.h>
  29 #include <asm/uv/uv_mmrs.h>
  30 #include <asm/uv/uv_hub.h>
  31 #include <asm/uv/bios.h>
  32
  33 DEFINE_PER_CPU(int, x2apic_extra_bits);
  34
  35 static enum uv_system_type uv_system_type;
  36
  37 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  38 {
  39         if (!strcmp(oem_id, "SGI")) {
  40                 if (!strcmp(oem_table_id, "UVL"))
  41                         uv_system_type = UV_LEGACY_APIC;
  42                 else if (!strcmp(oem_table_id, "UVX"))
  43                         uv_system_type = UV_X2APIC;
  44                 else if (!strcmp(oem_table_id, "UVH")) {
  45                         uv_system_type = UV_NON_UNIQUE_APIC;
  46                         return 1;
  47                 }
  48         }
  49         return 0;
  50 }
  51
  52 enum uv_system_type get_uv_system_type(void)
  53 {
  54         return uv_system_type;
  55 }
  56
  57 int is_uv_system(void)
  58 {
  59         return uv_system_type != UV_NONE;
  60 }
  61 EXPORT_SYMBOL_GPL(is_uv_system);
  62
  63 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  65
  66 struct uv_blade_info *uv_blade_info;
  67 EXPORT_SYMBOL_GPL(uv_blade_info);
  68
  69 short *uv_node_to_blade;
  70 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  71
  72 short *uv_cpu_to_blade;
  73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  74
  75 short uv_possible_blades;
  76 EXPORT_SYMBOL_GPL(uv_possible_blades);
  77
  78 unsigned long sn_rtc_cycles_per_second;
  79 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  80
  81 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  82
  83 static const struct cpumask *uv_target_cpus(void)
  84 {
  85         return cpumask_of(0);
  86 }
  87
  88 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
  89 {
  90         cpumask_clear(retmask);
  91         cpumask_set_cpu(cpu, retmask);
  92 }
  93
  94 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  95 {
  96         unsigned long val;
  97         int pnode;
  98
  99         pnode = uv_apicid_to_pnode(phys_apicid);
 100         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 101             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 102             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 103             APIC_DM_INIT;
 104         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 105         mdelay(10);
 106
 107         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 108             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 109             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 110             APIC_DM_STARTUP;
 111         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 112         return 0;
 113 }
 114
 115 static void uv_send_IPI_one(int cpu, int vector)
 116 {
 117         unsigned long val, apicid;
 118         int pnode;
 119
 120         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 121         pnode = uv_apicid_to_pnode(apicid);
 122
 123         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 124               (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 125               (vector << UVH_IPI_INT_VECTOR_SHFT);
 126
 127         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 128 }
 129
 130 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 131 {
 132         unsigned int cpu;
 133
 134         for_each_cpu(cpu, mask)
 135                 uv_send_IPI_one(cpu, vector);
 136 }
 137
 138 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 139 {
 140         unsigned int this_cpu = smp_processor_id();
 141         unsigned int cpu;
 142
 143         for_each_cpu(cpu, mask) {
 144                 if (cpu != this_cpu)
 145                         uv_send_IPI_one(cpu, vector);
 146         }
 147 }
 148
 149 static void uv_send_IPI_allbutself(int vector)
 150 {
 151         unsigned int this_cpu = smp_processor_id();
 152         unsigned int cpu;
 153
 154         for_each_online_cpu(cpu) {
 155                 if (cpu != this_cpu)
 156                         uv_send_IPI_one(cpu, vector);
 157         }
 158 }
 159
 160 static void uv_send_IPI_all(int vector)
 161 {
 162         uv_send_IPI_mask(cpu_online_mask, vector);
 163 }
 164
 165 static int uv_apic_id_registered(void)
 166 {
 167         return 1;
 168 }
 169
 170 static void uv_init_apic_ldr(void)
 171 {
 172 }
 173
 174 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 175 {
 176         /*
 177          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 178          * May as well be the first.
 179          */
 180         int cpu = cpumask_first(cpumask);
 181
 182         if ((unsigned)cpu < nr_cpu_ids)
 183                 return per_cpu(x86_cpu_to_apicid, cpu);
 184         else
 185                 return BAD_APICID;
 186 }
 187
 188 static unsigned int
 189 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 190                           const struct cpumask *andmask)
 191 {
 192         int cpu;
 193
 194         /*
 195          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 196          * May as well be the first.
 197          */
 198         for_each_cpu_and(cpu, cpumask, andmask) {
 199                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 200                         break;
 201         }
 202         if (cpu < nr_cpu_ids)
 203                 return per_cpu(x86_cpu_to_apicid, cpu);
 204
 205         return BAD_APICID;
 206 }
 207
 208 static unsigned int x2apic_get_apic_id(unsigned long x)
 209 {
 210         unsigned int id;
 211
 212         WARN_ON(preemptible() && num_online_cpus() > 1);
 213         id = x | __get_cpu_var(x2apic_extra_bits);
 214
 215         return id;
 216 }
 217
 218 static unsigned long set_apic_id(unsigned int id)
 219 {
 220         unsigned long x;
 221
 222         /* maskout x2apic_extra_bits ? */
 223         x = id;
 224         return x;
 225 }
 226
 227 static unsigned int uv_read_apic_id(void)
 228 {
 229
 230         return x2apic_get_apic_id(apic_read(APIC_ID));
 231 }
 232
 233 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 234 {
 235         return uv_read_apic_id() >> index_msb;
 236 }
 237
 238 static void uv_send_IPI_self(int vector)
 239 {
 240         apic_write(APIC_SELF_IPI, vector);
 241 }
 242
 243 struct genapic apic_x2apic_uv_x = {
 244
 245         .name                           = "UV large system",
 246         .probe                          = NULL,
 247         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 248         .apic_id_registered             = uv_apic_id_registered,
 249
 250         .irq_delivery_mode              = dest_Fixed,
 251         .irq_dest_mode                  = 1, /* logical */
 252
 253         .target_cpus                    = uv_target_cpus,
 254         .disable_esr                    = 0,
 255         .dest_logical                   = APIC_DEST_LOGICAL,
 256         .check_apicid_used              = NULL,
 257         .check_apicid_present           = NULL,
 258
 259         .vector_allocation_domain       = uv_vector_allocation_domain,
 260         .init_apic_ldr                  = uv_init_apic_ldr,
 261
 262         .ioapic_phys_id_map             = NULL,
 263         .setup_apic_routing             = NULL,
 264         .multi_timer_check              = NULL,
 265         .apicid_to_node                 = NULL,
 266         .cpu_to_logical_apicid          = NULL,
 267         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 268         .apicid_to_cpu_present          = NULL,
 269         .setup_portio_remap             = NULL,
 270         .check_phys_apicid_present      = default_check_phys_apicid_present,
 271         .enable_apic_mode               = NULL,
 272         .phys_pkg_id                    = uv_phys_pkg_id,
 273         .mps_oem_check                  = NULL,
 274
 275         .get_apic_id                    = x2apic_get_apic_id,
 276         .set_apic_id                    = set_apic_id,
 277         .apic_id_mask                   = 0xFFFFFFFFu,
 278
 279         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 280         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 281
 282         .send_IPI_mask                  = uv_send_IPI_mask,
 283         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 284         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 285         .send_IPI_all                   = uv_send_IPI_all,
 286         .send_IPI_self                  = uv_send_IPI_self,
 287
 288         .wakeup_cpu                     = NULL,
 289         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 290         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 291         .wait_for_init_deassert         = NULL,
 292         .smp_callin_clear_local_apic    = NULL,
 293         .store_NMI_vector               = NULL,
 294         .inquire_remote_apic            = NULL,
 295
 296         .read                           = native_apic_msr_read,
 297         .write                          = native_apic_msr_write,
 298         .icr_read                       = native_x2apic_icr_read,
 299         .icr_write                      = native_x2apic_icr_write,
 300         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 301         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 302 };
 303
 304 static __cpuinit void set_x2apic_extra_bits(int pnode)
 305 {
 306         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 307 }
 308
 309 /*
 310  * Called on boot cpu.
 311  */
 312 static __init int boot_pnode_to_blade(int pnode)
 313 {
 314         int blade;
 315
 316         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 317                 if (pnode == uv_blade_info[blade].pnode)
 318                         return blade;
 319         BUG();
 320 }
 321
 322 struct redir_addr {
 323         unsigned long redirect;
 324         unsigned long alias;
 325 };
 326
 327 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 328
 329 static __initdata struct redir_addr redir_addrs[] = {
 330         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 331         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 332         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 333 };
 334
 335 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 336 {
 337         union uvh_si_alias0_overlay_config_u alias;
 338         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 339         int i;
 340
 341         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 342                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 343                 if (alias.s.base == 0) {
 344                         *size = (1UL << alias.s.m_alias);
 345                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 346                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 347                         return;
 348                 }
 349         }
 350         BUG();
 351 }
 352
 353 static __init void map_low_mmrs(void)
 354 {
 355         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 356         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 357 }
 358
 359 enum map_type {map_wb, map_uc};
 360
 361 static __init void map_high(char *id, unsigned long base, int shift,
 362                             int max_pnode, enum map_type map_type)
 363 {
 364         unsigned long bytes, paddr;
 365
 366         paddr = base << shift;
 367         bytes = (1UL << shift) * (max_pnode + 1);
 368         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 369                                                 paddr + bytes);
 370         if (map_type == map_uc)
 371                 init_extra_mapping_uc(paddr, bytes);
 372         else
 373                 init_extra_mapping_wb(paddr, bytes);
 374
 375 }
 376 static __init void map_gru_high(int max_pnode)
 377 {
 378         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 379         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 380
 381         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 382         if (gru.s.enable)
 383                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 384 }
 385
 386 static __init void map_config_high(int max_pnode)
 387 {
 388         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 389         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 390
 391         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 392         if (cfg.s.enable)
 393                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 394 }
 395
 396 static __init void map_mmr_high(int max_pnode)
 397 {
 398         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 399         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 400
 401         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 402         if (mmr.s.enable)
 403                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 404 }
 405
 406 static __init void map_mmioh_high(int max_pnode)
 407 {
 408         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 409         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 410
 411         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 412         if (mmioh.s.enable)
 413                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 414 }
 415
 416 static __init void uv_rtc_init(void)
 417 {
 418         long status;
 419         u64 ticks_per_sec;
 420
 421         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 422                                         &ticks_per_sec);
 423         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 424                 printk(KERN_WARNING
 425                         "unable to determine platform RTC clock frequency, "
 426                         "guessing.\n");
 427                 /* BIOS gives wrong value for clock freq. so guess */
 428                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 429         } else
 430                 sn_rtc_cycles_per_second = ticks_per_sec;
 431 }
 432
 433 /*
 434  * percpu heartbeat timer
 435  */
 436 static void uv_heartbeat(unsigned long ignored)
 437 {
 438         struct timer_list *timer = &uv_hub_info->scir.timer;
 439         unsigned char bits = uv_hub_info->scir.state;
 440
 441         /* flip heartbeat bit */
 442         bits ^= SCIR_CPU_HEARTBEAT;
 443
 444         /* is this cpu idle? */
 445         if (idle_cpu(raw_smp_processor_id()))
 446                 bits &= ~SCIR_CPU_ACTIVITY;
 447         else
 448                 bits |= SCIR_CPU_ACTIVITY;
 449
 450         /* update system controller interface reg */
 451         uv_set_scir_bits(bits);
 452
 453         /* enable next timer period */
 454         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 455 }
 456
 457 static void __cpuinit uv_heartbeat_enable(int cpu)
 458 {
 459         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 460                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 461
 462                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 463                 setup_timer(timer, uv_heartbeat, cpu);
 464                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 465                 add_timer_on(timer, cpu);
 466                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 467         }
 468
 469         /* check boot cpu */
 470         if (!uv_cpu_hub_info(0)->scir.enabled)
 471                 uv_heartbeat_enable(0);
 472 }
 473
 474 #ifdef CONFIG_HOTPLUG_CPU
 475 static void __cpuinit uv_heartbeat_disable(int cpu)
 476 {
 477         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 478                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 479                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 480         }
 481         uv_set_cpu_scir_bits(cpu, 0xff);
 482 }
 483
 484 /*
 485  * cpu hotplug notifier
 486  */
 487 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 488                                        unsigned long action, void *hcpu)
 489 {
 490         long cpu = (long)hcpu;
 491
 492         switch (action) {
 493         case CPU_ONLINE:
 494                 uv_heartbeat_enable(cpu);
 495                 break;
 496         case CPU_DOWN_PREPARE:
 497                 uv_heartbeat_disable(cpu);
 498                 break;
 499         default:
 500                 break;
 501         }
 502         return NOTIFY_OK;
 503 }
 504
 505 static __init void uv_scir_register_cpu_notifier(void)
 506 {
 507         hotcpu_notifier(uv_scir_cpu_notify, 0);
 508 }
 509
 510 #else /* !CONFIG_HOTPLUG_CPU */
 511
 512 static __init void uv_scir_register_cpu_notifier(void)
 513 {
 514 }
 515
 516 static __init int uv_init_heartbeat(void)
 517 {
 518         int cpu;
 519
 520         if (is_uv_system())
 521                 for_each_online_cpu(cpu)
 522                         uv_heartbeat_enable(cpu);
 523         return 0;
 524 }
 525
 526 late_initcall(uv_init_heartbeat);
 527
 528 #endif /* !CONFIG_HOTPLUG_CPU */
 529
 530 /*
 531  * Called on each cpu to initialize the per_cpu UV data area.
 532  *      ZZZ hotplug not supported yet
 533  */
 534 void __cpuinit uv_cpu_init(void)
 535 {
 536         /* CPU 0 initilization will be done via uv_system_init. */
 537         if (!uv_blade_info)
 538                 return;
 539
 540         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 541
 542         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 543                 set_x2apic_extra_bits(uv_hub_info->pnode);
 544 }
 545
 546
 547 void __init uv_system_init(void)
 548 {
 549         union uvh_si_addr_map_config_u m_n_config;
 550         union uvh_node_id_u node_id;
 551         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 552         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 553         int max_pnode = 0;
 554         unsigned long mmr_base, present;
 555
 556         map_low_mmrs();
 557
 558         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 559         m_val = m_n_config.s.m_skt;
 560         n_val = m_n_config.s.n_skt;
 561         mmr_base =
 562             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 563             ~UV_MMR_ENABLE;
 564         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 565
 566         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 567                 uv_possible_blades +=
 568                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 569         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 570
 571         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 572         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 573
 574         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 575
 576         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 577         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 578         memset(uv_node_to_blade, 255, bytes);
 579
 580         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 581         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 582         memset(uv_cpu_to_blade, 255, bytes);
 583
 584         blade = 0;
 585         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 586                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 587                 for (j = 0; j < 64; j++) {
 588                         if (!test_bit(j, &present))
 589                                 continue;
 590                         uv_blade_info[blade].pnode = (i * 64 + j);
 591                         uv_blade_info[blade].nr_possible_cpus = 0;
 592                         uv_blade_info[blade].nr_online_cpus = 0;
 593                         blade++;
 594                 }
 595         }
 596
 597         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 598         gnode_upper = (((unsigned long)node_id.s.node_id) &
 599                        ~((1 << n_val) - 1)) << m_val;
 600
 601         uv_bios_init();
 602         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 603                             &sn_coherency_id, &sn_region_size);
 604         uv_rtc_init();
 605
 606         for_each_present_cpu(cpu) {
 607                 nid = cpu_to_node(cpu);
 608                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 609                 blade = boot_pnode_to_blade(pnode);
 610                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 611                 uv_blade_info[blade].nr_possible_cpus++;
 612
 613                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 614                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 615                 uv_cpu_hub_info(cpu)->m_val = m_val;
 616                 uv_cpu_hub_info(cpu)->n_val = m_val;
 617                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 618                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 619                 uv_cpu_hub_info(cpu)->pnode = pnode;
 620                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 621                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 622                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 623                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 624                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 625                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
 626                 uv_node_to_blade[nid] = blade;
 627                 uv_cpu_to_blade[cpu] = blade;
 628                 max_pnode = max(pnode, max_pnode);
 629
 630                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 631                         "lcpu %d, blade %d\n",
 632                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 633                         lcpu, blade);
 634         }
 635
 636         map_gru_high(max_pnode);
 637         map_mmr_high(max_pnode);
 638         map_config_high(max_pnode);
 639         map_mmioh_high(max_pnode);
 640
 641         uv_cpu_init();
 642         uv_scir_register_cpu_notifier();
 643         proc_mkdir("sgi_uv", NULL);
 644 }