2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/kernel.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/bootmem.h>
20 #include <linux/module.h>
21 #include <linux/hardirq.h>
24 #include <asm/genapic.h>
25 #include <asm/pgtable.h>
26 #include <asm/uv/uv_mmrs.h>
27 #include <asm/uv/uv_hub.h>
29 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
30 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
32 struct uv_blade_info *uv_blade_info;
33 EXPORT_SYMBOL_GPL(uv_blade_info);
35 short *uv_node_to_blade;
36 EXPORT_SYMBOL_GPL(uv_node_to_blade);
38 short *uv_cpu_to_blade;
39 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
41 short uv_possible_blades;
42 EXPORT_SYMBOL_GPL(uv_possible_blades);
44 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
46 static cpumask_t uv_target_cpus(void)
48 return cpumask_of_cpu(0);
51 static cpumask_t uv_vector_allocation_domain(int cpu)
53 cpumask_t domain = CPU_MASK_NONE;
58 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
63 pnode = uv_apicid_to_pnode(phys_apicid);
64 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
65 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
66 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
68 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
71 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
72 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
73 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
75 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
79 static void uv_send_IPI_one(int cpu, int vector)
81 unsigned long val, apicid, lapicid;
84 apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
85 lapicid = apicid & 0x3f; /* ZZZ macro needed */
86 pnode = uv_apicid_to_pnode(apicid);
88 (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
89 UVH_IPI_INT_APIC_ID_SHFT) |
90 (vector << UVH_IPI_INT_VECTOR_SHFT);
91 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
94 static void uv_send_IPI_mask(cpumask_t mask, int vector)
98 for (cpu = 0; cpu < NR_CPUS; ++cpu)
99 if (cpu_isset(cpu, mask))
100 uv_send_IPI_one(cpu, vector);
103 static void uv_send_IPI_allbutself(int vector)
105 cpumask_t mask = cpu_online_map;
107 cpu_clear(smp_processor_id(), mask);
109 if (!cpus_empty(mask))
110 uv_send_IPI_mask(mask, vector);
113 static void uv_send_IPI_all(int vector)
115 uv_send_IPI_mask(cpu_online_map, vector);
118 static int uv_apic_id_registered(void)
123 static inline void uv_init_apic_ldr(void)
127 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
132 * We're using fixed IRQ delivery, can only return one phys APIC ID.
133 * May as well be the first.
135 cpu = first_cpu(cpumask);
136 if ((unsigned)cpu < NR_CPUS)
137 return per_cpu(x86_cpu_to_apicid, cpu);
142 static unsigned int uv_read_apic_id(void)
146 WARN_ON(preemptible() && num_online_cpus() > 1);
147 id = apic_read(APIC_ID) | __get_cpu_var(x2apic_extra_bits);
152 static unsigned int phys_pkg_id(int index_msb)
154 return uv_read_apic_id() >> index_msb;
157 #ifdef ZZZ /* Needs x2apic patch */
158 static void uv_send_IPI_self(int vector)
160 apic_write(APIC_SELF_IPI, vector);
164 struct genapic apic_x2apic_uv_x = {
165 .name = "UV large system",
166 .int_delivery_mode = dest_Fixed,
167 .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
168 .target_cpus = uv_target_cpus,
169 .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
170 .apic_id_registered = uv_apic_id_registered,
171 .init_apic_ldr = uv_init_apic_ldr,
172 .send_IPI_all = uv_send_IPI_all,
173 .send_IPI_allbutself = uv_send_IPI_allbutself,
174 .send_IPI_mask = uv_send_IPI_mask,
175 /* ZZZ.send_IPI_self = uv_send_IPI_self, */
176 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
177 .phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
178 .read_apic_id = uv_read_apic_id,
181 static __cpuinit void set_x2apic_extra_bits(int pnode)
183 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
187 * Called on boot cpu.
189 static __init int boot_pnode_to_blade(int pnode)
193 for (blade = 0; blade < uv_num_possible_blades(); blade++)
194 if (pnode == uv_blade_info[blade].pnode)
200 unsigned long redirect;
204 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
206 static __initdata struct redir_addr redir_addrs[] = {
207 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
208 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
209 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
212 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
214 union uvh_si_alias0_overlay_config_u alias;
215 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
218 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
219 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
220 if (alias.s.base == 0) {
221 *size = (1UL << alias.s.m_alias);
222 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
223 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
230 static __init void map_low_mmrs(void)
232 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
233 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
236 enum map_type {map_wb, map_uc};
238 static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
240 unsigned long bytes, paddr;
242 paddr = base << shift;
243 bytes = (1UL << shift);
244 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
246 if (map_type == map_uc)
247 init_extra_mapping_uc(paddr, bytes);
249 init_extra_mapping_wb(paddr, bytes);
252 static __init void map_gru_high(int max_pnode)
254 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
255 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
257 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
259 map_high("GRU", gru.s.base, shift, map_wb);
262 static __init void map_config_high(int max_pnode)
264 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
265 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
267 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
269 map_high("CONFIG", cfg.s.base, shift, map_uc);
272 static __init void map_mmr_high(int max_pnode)
274 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
275 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
277 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
279 map_high("MMR", mmr.s.base, shift, map_uc);
282 static __init void map_mmioh_high(int max_pnode)
284 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
285 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
287 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
289 map_high("MMIOH", mmioh.s.base, shift, map_uc);
292 static __init void uv_system_init(void)
294 union uvh_si_addr_map_config_u m_n_config;
295 union uvh_node_id_u node_id;
296 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
297 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
299 unsigned long mmr_base, present;
303 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
304 m_val = m_n_config.s.m_skt;
305 n_val = m_n_config.s.n_skt;
307 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
309 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
311 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
312 uv_possible_blades +=
313 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
314 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
316 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
317 uv_blade_info = alloc_bootmem_pages(bytes);
319 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
321 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
322 uv_node_to_blade = alloc_bootmem_pages(bytes);
323 memset(uv_node_to_blade, 255, bytes);
325 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
326 uv_cpu_to_blade = alloc_bootmem_pages(bytes);
327 memset(uv_cpu_to_blade, 255, bytes);
330 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
331 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
332 for (j = 0; j < 64; j++) {
333 if (!test_bit(j, &present))
335 uv_blade_info[blade].pnode = (i * 64 + j);
336 uv_blade_info[blade].nr_possible_cpus = 0;
337 uv_blade_info[blade].nr_online_cpus = 0;
342 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
343 gnode_upper = (((unsigned long)node_id.s.node_id) &
344 ~((1 << n_val) - 1)) << m_val;
346 for_each_present_cpu(cpu) {
347 nid = cpu_to_node(cpu);
348 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
349 blade = boot_pnode_to_blade(pnode);
350 lcpu = uv_blade_info[blade].nr_possible_cpus;
351 uv_blade_info[blade].nr_possible_cpus++;
353 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
354 uv_cpu_hub_info(cpu)->lowmem_remap_top =
355 lowmem_redir_base + lowmem_redir_size;
356 uv_cpu_hub_info(cpu)->m_val = m_val;
357 uv_cpu_hub_info(cpu)->n_val = m_val;
358 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
359 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
360 uv_cpu_hub_info(cpu)->pnode = pnode;
361 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
362 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
363 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
364 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
365 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
366 uv_node_to_blade[nid] = blade;
367 uv_cpu_to_blade[cpu] = blade;
368 max_pnode = max(pnode, max_pnode);
370 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
371 "lcpu %d, blade %d\n",
372 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
376 map_gru_high(max_pnode);
377 map_mmr_high(max_pnode);
378 map_config_high(max_pnode);
379 map_mmioh_high(max_pnode);
383 * Called on each cpu to initialize the per_cpu UV data area.
384 * ZZZ hotplug not supported yet
386 void __cpuinit uv_cpu_init(void)
388 if (!uv_node_to_blade)
391 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
393 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
394 set_x2apic_extra_bits(uv_hub_info->pnode);