1 #include <linux/console.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/string.h>
5 #include <linux/screen_info.h>
6 #include <linux/usb/ch9.h>
7 #include <linux/pci_regs.h>
8 #include <linux/pci_ids.h>
9 #include <linux/errno.h>
11 #include <asm/processor.h>
12 #include <asm/fcntl.h>
13 #include <asm/setup.h>
14 #include <xen/hvc-console.h>
15 #include <asm/pci-direct.h>
16 #include <asm/fixmap.h>
17 #include <linux/usb/ehci_def.h>
19 /* Simple VGA output */
20 #define VGABASE (__ISA_IO_base + 0xb8000)
22 static int max_ypos = 25, max_xpos = 80;
23 static int current_ypos = 25, current_xpos;
25 static void early_vga_write(struct console *con, const char *str, unsigned n)
30 while ((c = *str++) != '\0' && n-- > 0) {
31 if (current_ypos >= max_ypos) {
32 /* scroll 1 line up */
33 for (k = 1, j = 0; k < max_ypos; k++, j++) {
34 for (i = 0; i < max_xpos; i++) {
35 writew(readw(VGABASE+2*(max_xpos*k+i)),
36 VGABASE + 2*(max_xpos*j + i));
39 for (i = 0; i < max_xpos; i++)
40 writew(0x720, VGABASE + 2*(max_xpos*j + i));
41 current_ypos = max_ypos-1;
46 } else if (c != '\r') {
47 writew(((0x7 << 8) | (unsigned short) c),
48 VGABASE + 2*(max_xpos*current_ypos +
50 if (current_xpos >= max_xpos) {
58 static struct console early_vga_console = {
60 .write = early_vga_write,
61 .flags = CON_PRINTBUFFER,
65 /* Serial functions loosely based on a similar package from Klaus P. Gerlicher */
67 static int early_serial_base = 0x3f8; /* ttyS0 */
73 #define TXR 0 /* Transmit register (WRITE) */
74 #define RXR 0 /* Receive register (READ) */
75 #define IER 1 /* Interrupt Enable */
76 #define IIR 2 /* Interrupt ID */
77 #define FCR 2 /* FIFO control */
78 #define LCR 3 /* Line control */
79 #define MCR 4 /* Modem control */
80 #define LSR 5 /* Line Status */
81 #define MSR 6 /* Modem Status */
82 #define DLL 0 /* Divisor Latch Low */
83 #define DLH 1 /* Divisor latch High */
85 static int early_serial_putc(unsigned char ch)
87 unsigned timeout = 0xffff;
89 while ((inb(early_serial_base + LSR) & XMTRDY) == 0 && --timeout)
91 outb(ch, early_serial_base + TXR);
92 return timeout ? 0 : -1;
95 static void early_serial_write(struct console *con, const char *s, unsigned n)
97 while (*s && n-- > 0) {
99 early_serial_putc('\r');
100 early_serial_putc(*s);
105 #define DEFAULT_BAUD 9600
107 static __init void early_serial_init(char *s)
111 unsigned baud = DEFAULT_BAUD;
119 if (!strncmp(s, "0x", 2)) {
120 early_serial_base = simple_strtoul(s, &e, 16);
122 static const int __initconst bases[] = { 0x3f8, 0x2f8 };
124 if (!strncmp(s, "ttyS", 4))
126 port = simple_strtoul(s, &e, 10);
127 if (port > 1 || s == e)
129 early_serial_base = bases[port];
131 s += strcspn(s, ",");
136 outb(0x3, early_serial_base + LCR); /* 8n1 */
137 outb(0, early_serial_base + IER); /* no interrupt */
138 outb(0, early_serial_base + FCR); /* no fifo */
139 outb(0x3, early_serial_base + MCR); /* DTR + RTS */
142 baud = simple_strtoul(s, &e, 0);
143 if (baud == 0 || s == e)
147 divisor = 115200 / baud;
148 c = inb(early_serial_base + LCR);
149 outb(c | DLAB, early_serial_base + LCR);
150 outb(divisor & 0xff, early_serial_base + DLL);
151 outb((divisor >> 8) & 0xff, early_serial_base + DLH);
152 outb(c & ~DLAB, early_serial_base + LCR);
155 static struct console early_serial_console = {
157 .write = early_serial_write,
158 .flags = CON_PRINTBUFFER,
162 #ifdef CONFIG_EARLY_PRINTK_DBGP
164 static struct ehci_caps __iomem *ehci_caps;
165 static struct ehci_regs __iomem *ehci_regs;
166 static struct ehci_dbg_port __iomem *ehci_debug;
167 static unsigned int dbgp_endpoint_out;
175 static struct ehci_dev ehci_dev;
177 #define USB_DEBUG_DEVNUM 127
179 #define DBGP_DATA_TOGGLE 0x8800
181 static inline u32 dbgp_pid_update(u32 x, u32 tok)
183 return ((x ^ DBGP_DATA_TOGGLE) & 0xffff00) | (tok & 0xff);
186 static inline u32 dbgp_len_update(u32 x, u32 len)
188 return (x & ~0x0f) | (len & 0x0f);
192 * USB Packet IDs (PIDs)
196 #define USB_PID_OUT 0xe1
197 #define USB_PID_IN 0x69
198 #define USB_PID_SOF 0xa5
199 #define USB_PID_SETUP 0x2d
201 #define USB_PID_ACK 0xd2
202 #define USB_PID_NAK 0x5a
203 #define USB_PID_STALL 0x1e
204 #define USB_PID_NYET 0x96
206 #define USB_PID_DATA0 0xc3
207 #define USB_PID_DATA1 0x4b
208 #define USB_PID_DATA2 0x87
209 #define USB_PID_MDATA 0x0f
211 #define USB_PID_PREAMBLE 0x3c
212 #define USB_PID_ERR 0x3c
213 #define USB_PID_SPLIT 0x78
214 #define USB_PID_PING 0xb4
215 #define USB_PID_UNDEF_0 0xf0
217 #define USB_PID_DATA_TOGGLE 0x88
218 #define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
220 #define PCI_CAP_ID_EHCI_DEBUG 0xa
222 #define HUB_ROOT_RESET_TIME 50 /* times are in msec */
223 #define HUB_SHORT_RESET_TIME 10
224 #define HUB_LONG_RESET_TIME 200
225 #define HUB_RESET_TIMEOUT 500
227 #define DBGP_MAX_PACKET 8
229 static int dbgp_wait_until_complete(void)
235 ctrl = readl(&ehci_debug->control);
236 /* Stop when the transaction is finished */
237 if (ctrl & DBGP_DONE)
239 } while (--loop > 0);
245 * Now that we have observed the completed transaction,
246 * clear the done bit.
248 writel(ctrl | DBGP_DONE, &ehci_debug->control);
249 return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
252 static void dbgp_mdelay(int ms)
257 for (i = 0; i < 1000; i++)
262 static void dbgp_breath(void)
264 /* Sleep to give the debug port a chance to breathe */
267 static int dbgp_wait_until_done(unsigned ctrl)
274 writel(ctrl | DBGP_GO, &ehci_debug->control);
275 ret = dbgp_wait_until_complete();
276 pids = readl(&ehci_debug->pids);
277 lpid = DBGP_PID_GET(pids);
283 * If the port is getting full or it has dropped data
284 * start pacing ourselves, not necessary but it's friendly.
286 if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
289 /* If I get a NACK reissue the transmission */
290 if (lpid == USB_PID_NAK) {
298 static void dbgp_set_data(const void *buf, int size)
300 const unsigned char *bytes = buf;
305 for (i = 0; i < 4 && i < size; i++)
306 lo |= bytes[i] << (8*i);
307 for (; i < 8 && i < size; i++)
308 hi |= bytes[i] << (8*(i - 4));
309 writel(lo, &ehci_debug->data03);
310 writel(hi, &ehci_debug->data47);
313 static void dbgp_get_data(void *buf, int size)
315 unsigned char *bytes = buf;
319 lo = readl(&ehci_debug->data03);
320 hi = readl(&ehci_debug->data47);
321 for (i = 0; i < 4 && i < size; i++)
322 bytes[i] = (lo >> (8*i)) & 0xff;
323 for (; i < 8 && i < size; i++)
324 bytes[i] = (hi >> (8*(i - 4))) & 0xff;
327 static int dbgp_bulk_write(unsigned devnum, unsigned endpoint,
328 const char *bytes, int size)
330 u32 pids, addr, ctrl;
333 if (size > DBGP_MAX_PACKET)
336 addr = DBGP_EPADDR(devnum, endpoint);
338 pids = readl(&ehci_debug->pids);
339 pids = dbgp_pid_update(pids, USB_PID_OUT);
341 ctrl = readl(&ehci_debug->control);
342 ctrl = dbgp_len_update(ctrl, size);
346 dbgp_set_data(bytes, size);
347 writel(addr, &ehci_debug->address);
348 writel(pids, &ehci_debug->pids);
350 ret = dbgp_wait_until_done(ctrl);
357 static int dbgp_bulk_read(unsigned devnum, unsigned endpoint, void *data,
360 u32 pids, addr, ctrl;
363 if (size > DBGP_MAX_PACKET)
366 addr = DBGP_EPADDR(devnum, endpoint);
368 pids = readl(&ehci_debug->pids);
369 pids = dbgp_pid_update(pids, USB_PID_IN);
371 ctrl = readl(&ehci_debug->control);
372 ctrl = dbgp_len_update(ctrl, size);
376 writel(addr, &ehci_debug->address);
377 writel(pids, &ehci_debug->pids);
378 ret = dbgp_wait_until_done(ctrl);
384 dbgp_get_data(data, size);
388 static int dbgp_control_msg(unsigned devnum, int requesttype, int request,
389 int value, int index, void *data, int size)
391 u32 pids, addr, ctrl;
392 struct usb_ctrlrequest req;
396 read = (requesttype & USB_DIR_IN) != 0;
397 if (size > (read ? DBGP_MAX_PACKET:0))
400 /* Compute the control message */
401 req.bRequestType = requesttype;
402 req.bRequest = request;
403 req.wValue = cpu_to_le16(value);
404 req.wIndex = cpu_to_le16(index);
405 req.wLength = cpu_to_le16(size);
407 pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
408 addr = DBGP_EPADDR(devnum, 0);
410 ctrl = readl(&ehci_debug->control);
411 ctrl = dbgp_len_update(ctrl, sizeof(req));
415 /* Send the setup message */
416 dbgp_set_data(&req, sizeof(req));
417 writel(addr, &ehci_debug->address);
418 writel(pids, &ehci_debug->pids);
419 ret = dbgp_wait_until_done(ctrl);
423 /* Read the result */
424 return dbgp_bulk_read(devnum, 0, data, size);
428 /* Find a PCI capability */
429 static u32 __init find_cap(u32 num, u32 slot, u32 func, int cap)
434 if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
435 PCI_STATUS_CAP_LIST))
438 pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
439 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
443 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
449 pos = read_pci_config_byte(num, slot, func,
450 pos+PCI_CAP_LIST_NEXT);
455 static u32 __init __find_dbgp(u32 bus, u32 slot, u32 func)
459 class = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
460 if ((class >> 8) != PCI_CLASS_SERIAL_USB_EHCI)
463 return find_cap(bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
466 static u32 __init find_dbgp(int ehci_num, u32 *rbus, u32 *rslot, u32 *rfunc)
470 for (bus = 0; bus < 256; bus++) {
471 for (slot = 0; slot < 32; slot++) {
472 for (func = 0; func < 8; func++) {
475 cap = __find_dbgp(bus, slot, func);
491 static int ehci_reset_port(int port)
494 u32 delay_time, delay;
497 /* Reset the usb debug port */
498 portsc = readl(&ehci_regs->port_status[port - 1]);
500 portsc |= PORT_RESET;
501 writel(portsc, &ehci_regs->port_status[port - 1]);
503 delay = HUB_ROOT_RESET_TIME;
504 for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
505 delay_time += delay) {
508 portsc = readl(&ehci_regs->port_status[port - 1]);
509 if (portsc & PORT_RESET) {
510 /* force reset to complete */
512 writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
513 &ehci_regs->port_status[port - 1]);
515 portsc = readl(&ehci_regs->port_status[port-1]);
516 } while ((portsc & PORT_RESET) && (--loop > 0));
519 /* Device went away? */
520 if (!(portsc & PORT_CONNECT))
523 /* bomb out completely if something weird happend */
524 if ((portsc & PORT_CSC))
527 /* If we've finished resetting, then break out of the loop */
528 if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
534 static int ehci_wait_for_port(int port)
539 for (reps = 0; reps < 3; reps++) {
541 status = readl(&ehci_regs->status);
542 if (status & STS_PCD) {
543 ret = ehci_reset_port(port);
552 # define dbgp_printk early_printk
554 static inline void dbgp_printk(const char *fmt, ...) { }
557 typedef void (*set_debug_port_t)(int port);
559 static void default_set_debug_port(int port)
563 static set_debug_port_t set_debug_port = default_set_debug_port;
565 static void nvidia_set_debug_port(int port)
568 dword = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
570 dword &= ~(0x0f<<12);
571 dword |= ((port & 0x0f)<<12);
572 write_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func, 0x74,
574 dbgp_printk("set debug port to %d\n", port);
577 static void __init detect_set_debug_port(void)
581 vendorid = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
584 if ((vendorid & 0xffff) == 0x10de) {
585 dbgp_printk("using nvidia set_debug_port\n");
586 set_debug_port = nvidia_set_debug_port;
590 static int __init ehci_setup(void)
592 struct usb_debug_descriptor dbgp_desc;
593 u32 cmd, ctrl, status, portsc, hcs_params;
594 u32 debug_port, new_debug_port = 0, n_ports;
606 hcs_params = readl(&ehci_caps->hcs_params);
607 debug_port = HCS_DEBUG_PORT(hcs_params);
608 n_ports = HCS_N_PORTS(hcs_params);
610 dbgp_printk("debug_port: %d\n", debug_port);
611 dbgp_printk("n_ports: %d\n", n_ports);
613 for (i = 1; i <= n_ports; i++) {
614 portsc = readl(&ehci_regs->port_status[i-1]);
615 dbgp_printk("portstatus%d: %08x\n", i, portsc);
618 if (port_map_tried && (new_debug_port != debug_port)) {
620 set_debug_port(new_debug_port);
627 /* Reset the EHCI controller */
628 cmd = readl(&ehci_regs->command);
630 writel(cmd, &ehci_regs->command);
632 cmd = readl(&ehci_regs->command);
633 } while ((cmd & CMD_RESET) && (--loop > 0));
636 dbgp_printk("can not reset ehci\n");
639 dbgp_printk("ehci reset done\n");
641 /* Claim ownership, but do not enable yet */
642 ctrl = readl(&ehci_debug->control);
644 ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
645 writel(ctrl, &ehci_debug->control);
647 /* Start the ehci running */
648 cmd = readl(&ehci_regs->command);
649 cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
651 writel(cmd, &ehci_regs->command);
653 /* Ensure everything is routed to the EHCI */
654 writel(FLAG_CF, &ehci_regs->configured_flag);
656 /* Wait until the controller is no longer halted */
659 status = readl(&ehci_regs->status);
660 } while ((status & STS_HALT) && (--loop > 0));
663 dbgp_printk("ehci can be started\n");
666 dbgp_printk("ehci started\n");
668 /* Wait for a device to show up in the debug port */
669 ret = ehci_wait_for_port(debug_port);
671 dbgp_printk("No device found in debug port\n");
672 goto next_debug_port;
674 dbgp_printk("ehci wait for port done\n");
676 /* Enable the debug port */
677 ctrl = readl(&ehci_debug->control);
679 writel(ctrl, &ehci_debug->control);
680 ctrl = readl(&ehci_debug->control);
681 if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
682 dbgp_printk("No device in debug port\n");
683 writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
686 dbgp_printk("debug ported enabled\n");
688 /* Completely transfer the debug device to the debug controller */
689 portsc = readl(&ehci_regs->port_status[debug_port - 1]);
691 writel(portsc, &ehci_regs->port_status[debug_port - 1]);
695 /* Find the debug device and make it device number 127 */
696 for (devnum = 0; devnum <= 127; devnum++) {
697 ret = dbgp_control_msg(devnum,
698 USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
699 USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
700 &dbgp_desc, sizeof(dbgp_desc));
705 dbgp_printk("Could not find attached debug device\n");
709 dbgp_printk("Attached device is not a debug device\n");
712 dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
714 /* Move the device to 127 if it isn't already there */
715 if (devnum != USB_DEBUG_DEVNUM) {
716 ret = dbgp_control_msg(devnum,
717 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
718 USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
720 dbgp_printk("Could not move attached device to %d\n",
724 devnum = USB_DEBUG_DEVNUM;
725 dbgp_printk("debug device renamed to 127\n");
728 /* Enable the debug interface */
729 ret = dbgp_control_msg(USB_DEBUG_DEVNUM,
730 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
731 USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
733 dbgp_printk(" Could not enable the debug device\n");
736 dbgp_printk("debug interface enabled\n");
738 /* Perform a small write to get the even/odd data state in sync
740 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ", 1);
742 dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
745 dbgp_printk("small write doned\n");
749 /* Things didn't work so remove my claim */
750 ctrl = readl(&ehci_debug->control);
751 ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
752 writel(ctrl, &ehci_debug->control);
756 port_map_tried |= (1<<(debug_port - 1));
757 new_debug_port = ((debug_port-1+1)%n_ports) + 1;
758 if (port_map_tried != ((1<<n_ports) - 1)) {
759 set_debug_port(new_debug_port);
763 set_debug_port(new_debug_port);
770 static int __init early_dbgp_init(char *s)
772 u32 debug_port, bar, offset;
773 u32 bus, slot, func, cap;
774 void __iomem *ehci_bar;
781 if (!early_pci_allowed())
786 dbgp_num = simple_strtoul(s, &e, 10);
787 dbgp_printk("dbgp_num: %d\n", dbgp_num);
789 cap = find_dbgp(dbgp_num, &bus, &slot, &func);
793 dbgp_printk("Found EHCI debug port on %02x:%02x.%1x\n", bus, slot,
796 debug_port = read_pci_config(bus, slot, func, cap);
797 bar = (debug_port >> 29) & 0x7;
798 bar = (bar * 4) + 0xc;
799 offset = (debug_port >> 16) & 0xfff;
800 dbgp_printk("bar: %02x offset: %03x\n", bar, offset);
801 if (bar != PCI_BASE_ADDRESS_0) {
802 dbgp_printk("only debug ports on bar 1 handled.\n");
807 bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
808 dbgp_printk("bar_val: %02x offset: %03x\n", bar_val, offset);
809 if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
810 dbgp_printk("only simple 32bit mmio bars supported\n");
815 /* double check if the mem space is enabled */
816 byte = read_pci_config_byte(bus, slot, func, 0x04);
819 write_pci_config_byte(bus, slot, func, 0x04, byte);
820 dbgp_printk("mmio for ehci enabled\n");
824 * FIXME I don't have the bar size so just guess PAGE_SIZE is more
825 * than enough. 1K is the biggest I have seen.
827 set_fixmap_nocache(FIX_DBGP_BASE, bar_val & PAGE_MASK);
828 ehci_bar = (void __iomem *)__fix_to_virt(FIX_DBGP_BASE);
829 ehci_bar += bar_val & ~PAGE_MASK;
830 dbgp_printk("ehci_bar: %p\n", ehci_bar);
832 ehci_caps = ehci_bar;
833 ehci_regs = ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase));
834 ehci_debug = ehci_bar + offset;
836 ehci_dev.slot = slot;
837 ehci_dev.func = func;
839 detect_set_debug_port();
843 dbgp_printk("ehci_setup failed\n");
852 static void early_dbgp_write(struct console *con, const char *str, u32 n)
860 if (chunk > DBGP_MAX_PACKET)
861 chunk = DBGP_MAX_PACKET;
862 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM,
863 dbgp_endpoint_out, str, chunk);
869 static struct console early_dbgp_console = {
871 .write = early_dbgp_write,
872 .flags = CON_PRINTBUFFER,
877 /* Direct interface for emergencies */
878 static struct console *early_console = &early_vga_console;
879 static int __initdata early_console_initialized;
881 asmlinkage void early_printk(const char *fmt, ...)
888 n = vscnprintf(buf, sizeof(buf), fmt, ap);
889 early_console->write(early_console, buf, n);
894 static int __init setup_early_printk(char *buf)
901 if (early_console_initialized)
903 early_console_initialized = 1;
905 keep_early = (strstr(buf, "keep") != NULL);
907 if (!strncmp(buf, "serial", 6)) {
908 early_serial_init(buf + 6);
909 early_console = &early_serial_console;
910 } else if (!strncmp(buf, "ttyS", 4)) {
911 early_serial_init(buf);
912 early_console = &early_serial_console;
913 } else if (!strncmp(buf, "vga", 3)
914 && boot_params.screen_info.orig_video_isVGA == 1) {
915 max_xpos = boot_params.screen_info.orig_video_cols;
916 max_ypos = boot_params.screen_info.orig_video_lines;
917 current_ypos = boot_params.screen_info.orig_y;
918 early_console = &early_vga_console;
919 #ifdef CONFIG_EARLY_PRINTK_DBGP
920 } else if (!strncmp(buf, "dbgp", 4)) {
921 if (early_dbgp_init(buf+4) < 0)
923 early_console = &early_dbgp_console;
925 * usb subsys will reset ehci controller, so don't keep
930 #ifdef CONFIG_HVC_XEN
931 } else if (!strncmp(buf, "xen", 3)) {
932 early_console = &xenboot_console;
937 early_console->flags &= ~CON_BOOT;
939 early_console->flags |= CON_BOOT;
940 register_console(early_console);
944 early_param("earlyprintk", setup_early_printk);