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   1 #ifdef CONFIG_CPU_SUP_INTEL
   2
   3 /*
   4  * Intel PerfMon, used on Core and later.
   5  */
   6 static const u64 intel_perfmon_event_map[] =
   7 {
   8   [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
   9   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
  10   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
  11   [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
  12   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
  13   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
  14   [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
  15 };
  16
  17 static struct event_constraint intel_core_event_constraints[] =
  18 {
  19         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  20         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  21         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  22         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  23         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  24         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  25         EVENT_CONSTRAINT_END
  26 };
  27
  28 static struct event_constraint intel_core2_event_constraints[] =
  29 {
  30         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  31         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  32         /*
  33          * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
  34          * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
  35          * ratio between these counters.
  36          */
  37         /* FIXED_EVENT_CONSTRAINT(0x013c, 2),  CPU_CLK_UNHALTED.REF */
  38         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  39         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  40         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  41         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  42         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  43         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  44         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  45         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  46         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  47         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  48         EVENT_CONSTRAINT_END
  49 };
  50
  51 static struct event_constraint intel_nehalem_event_constraints[] =
  52 {
  53         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  54         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  55         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  56         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  57         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  58         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  59         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  60         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  61         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  62         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  63         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  64         EVENT_CONSTRAINT_END
  65 };
  66
  67 static struct event_constraint intel_westmere_event_constraints[] =
  68 {
  69         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  70         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  71         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  72         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  73         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  74         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  75         EVENT_CONSTRAINT_END
  76 };
  77
  78 static struct event_constraint intel_gen_event_constraints[] =
  79 {
  80         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  81         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  82         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  83         EVENT_CONSTRAINT_END
  84 };
  85
  86 static u64 intel_pmu_event_map(int hw_event)
  87 {
  88         return intel_perfmon_event_map[hw_event];
  89 }
  90
  91 static __initconst u64 westmere_hw_cache_event_ids
  92                                 [PERF_COUNT_HW_CACHE_MAX]
  93                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  94                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  95 {
  96  [ C(L1D) ] = {
  97         [ C(OP_READ) ] = {
  98                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
  99                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 100         },
 101         [ C(OP_WRITE) ] = {
 102                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 103                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 104         },
 105         [ C(OP_PREFETCH) ] = {
 106                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 107                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 108         },
 109  },
 110  [ C(L1I ) ] = {
 111         [ C(OP_READ) ] = {
 112                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 113                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 114         },
 115         [ C(OP_WRITE) ] = {
 116                 [ C(RESULT_ACCESS) ] = -1,
 117                 [ C(RESULT_MISS)   ] = -1,
 118         },
 119         [ C(OP_PREFETCH) ] = {
 120                 [ C(RESULT_ACCESS) ] = 0x0,
 121                 [ C(RESULT_MISS)   ] = 0x0,
 122         },
 123  },
 124  [ C(LL  ) ] = {
 125         [ C(OP_READ) ] = {
 126                 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
 127                 [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
 128         },
 129         [ C(OP_WRITE) ] = {
 130                 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
 131                 [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
 132         },
 133         [ C(OP_PREFETCH) ] = {
 134                 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
 135                 [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
 136         },
 137  },
 138  [ C(DTLB) ] = {
 139         [ C(OP_READ) ] = {
 140                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 141                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 142         },
 143         [ C(OP_WRITE) ] = {
 144                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 145                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 146         },
 147         [ C(OP_PREFETCH) ] = {
 148                 [ C(RESULT_ACCESS) ] = 0x0,
 149                 [ C(RESULT_MISS)   ] = 0x0,
 150         },
 151  },
 152  [ C(ITLB) ] = {
 153         [ C(OP_READ) ] = {
 154                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 155                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 156         },
 157         [ C(OP_WRITE) ] = {
 158                 [ C(RESULT_ACCESS) ] = -1,
 159                 [ C(RESULT_MISS)   ] = -1,
 160         },
 161         [ C(OP_PREFETCH) ] = {
 162                 [ C(RESULT_ACCESS) ] = -1,
 163                 [ C(RESULT_MISS)   ] = -1,
 164         },
 165  },
 166  [ C(BPU ) ] = {
 167         [ C(OP_READ) ] = {
 168                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 169                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 170         },
 171         [ C(OP_WRITE) ] = {
 172                 [ C(RESULT_ACCESS) ] = -1,
 173                 [ C(RESULT_MISS)   ] = -1,
 174         },
 175         [ C(OP_PREFETCH) ] = {
 176                 [ C(RESULT_ACCESS) ] = -1,
 177                 [ C(RESULT_MISS)   ] = -1,
 178         },
 179  },
 180 };
 181
 182 static __initconst u64 nehalem_hw_cache_event_ids
 183                                 [PERF_COUNT_HW_CACHE_MAX]
 184                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 185                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 186 {
 187  [ C(L1D) ] = {
 188         [ C(OP_READ) ] = {
 189                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI            */
 190                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE         */
 191         },
 192         [ C(OP_WRITE) ] = {
 193                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI            */
 194                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE         */
 195         },
 196         [ C(OP_PREFETCH) ] = {
 197                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 198                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 199         },
 200  },
 201  [ C(L1I ) ] = {
 202         [ C(OP_READ) ] = {
 203                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 204                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 205         },
 206         [ C(OP_WRITE) ] = {
 207                 [ C(RESULT_ACCESS) ] = -1,
 208                 [ C(RESULT_MISS)   ] = -1,
 209         },
 210         [ C(OP_PREFETCH) ] = {
 211                 [ C(RESULT_ACCESS) ] = 0x0,
 212                 [ C(RESULT_MISS)   ] = 0x0,
 213         },
 214  },
 215  [ C(LL  ) ] = {
 216         [ C(OP_READ) ] = {
 217                 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
 218                 [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
 219         },
 220         [ C(OP_WRITE) ] = {
 221                 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
 222                 [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
 223         },
 224         [ C(OP_PREFETCH) ] = {
 225                 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
 226                 [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
 227         },
 228  },
 229  [ C(DTLB) ] = {
 230         [ C(OP_READ) ] = {
 231                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 232                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 233         },
 234         [ C(OP_WRITE) ] = {
 235                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 236                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 237         },
 238         [ C(OP_PREFETCH) ] = {
 239                 [ C(RESULT_ACCESS) ] = 0x0,
 240                 [ C(RESULT_MISS)   ] = 0x0,
 241         },
 242  },
 243  [ C(ITLB) ] = {
 244         [ C(OP_READ) ] = {
 245                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 246                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 247         },
 248         [ C(OP_WRITE) ] = {
 249                 [ C(RESULT_ACCESS) ] = -1,
 250                 [ C(RESULT_MISS)   ] = -1,
 251         },
 252         [ C(OP_PREFETCH) ] = {
 253                 [ C(RESULT_ACCESS) ] = -1,
 254                 [ C(RESULT_MISS)   ] = -1,
 255         },
 256  },
 257  [ C(BPU ) ] = {
 258         [ C(OP_READ) ] = {
 259                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 260                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 261         },
 262         [ C(OP_WRITE) ] = {
 263                 [ C(RESULT_ACCESS) ] = -1,
 264                 [ C(RESULT_MISS)   ] = -1,
 265         },
 266         [ C(OP_PREFETCH) ] = {
 267                 [ C(RESULT_ACCESS) ] = -1,
 268                 [ C(RESULT_MISS)   ] = -1,
 269         },
 270  },
 271 };
 272
 273 static __initconst u64 core2_hw_cache_event_ids
 274                                 [PERF_COUNT_HW_CACHE_MAX]
 275                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 276                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 277 {
 278  [ C(L1D) ] = {
 279         [ C(OP_READ) ] = {
 280                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 281                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 282         },
 283         [ C(OP_WRITE) ] = {
 284                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 285                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 286         },
 287         [ C(OP_PREFETCH) ] = {
 288                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 289                 [ C(RESULT_MISS)   ] = 0,
 290         },
 291  },
 292  [ C(L1I ) ] = {
 293         [ C(OP_READ) ] = {
 294                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 295                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 296         },
 297         [ C(OP_WRITE) ] = {
 298                 [ C(RESULT_ACCESS) ] = -1,
 299                 [ C(RESULT_MISS)   ] = -1,
 300         },
 301         [ C(OP_PREFETCH) ] = {
 302                 [ C(RESULT_ACCESS) ] = 0,
 303                 [ C(RESULT_MISS)   ] = 0,
 304         },
 305  },
 306  [ C(LL  ) ] = {
 307         [ C(OP_READ) ] = {
 308                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 309                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 310         },
 311         [ C(OP_WRITE) ] = {
 312                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 313                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 314         },
 315         [ C(OP_PREFETCH) ] = {
 316                 [ C(RESULT_ACCESS) ] = 0,
 317                 [ C(RESULT_MISS)   ] = 0,
 318         },
 319  },
 320  [ C(DTLB) ] = {
 321         [ C(OP_READ) ] = {
 322                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 323                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 324         },
 325         [ C(OP_WRITE) ] = {
 326                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 327                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 328         },
 329         [ C(OP_PREFETCH) ] = {
 330                 [ C(RESULT_ACCESS) ] = 0,
 331                 [ C(RESULT_MISS)   ] = 0,
 332         },
 333  },
 334  [ C(ITLB) ] = {
 335         [ C(OP_READ) ] = {
 336                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 337                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 338         },
 339         [ C(OP_WRITE) ] = {
 340                 [ C(RESULT_ACCESS) ] = -1,
 341                 [ C(RESULT_MISS)   ] = -1,
 342         },
 343         [ C(OP_PREFETCH) ] = {
 344                 [ C(RESULT_ACCESS) ] = -1,
 345                 [ C(RESULT_MISS)   ] = -1,
 346         },
 347  },
 348  [ C(BPU ) ] = {
 349         [ C(OP_READ) ] = {
 350                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 351                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 352         },
 353         [ C(OP_WRITE) ] = {
 354                 [ C(RESULT_ACCESS) ] = -1,
 355                 [ C(RESULT_MISS)   ] = -1,
 356         },
 357         [ C(OP_PREFETCH) ] = {
 358                 [ C(RESULT_ACCESS) ] = -1,
 359                 [ C(RESULT_MISS)   ] = -1,
 360         },
 361  },
 362 };
 363
 364 static __initconst u64 atom_hw_cache_event_ids
 365                                 [PERF_COUNT_HW_CACHE_MAX]
 366                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 367                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 368 {
 369  [ C(L1D) ] = {
 370         [ C(OP_READ) ] = {
 371                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
 372                 [ C(RESULT_MISS)   ] = 0,
 373         },
 374         [ C(OP_WRITE) ] = {
 375                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
 376                 [ C(RESULT_MISS)   ] = 0,
 377         },
 378         [ C(OP_PREFETCH) ] = {
 379                 [ C(RESULT_ACCESS) ] = 0x0,
 380                 [ C(RESULT_MISS)   ] = 0,
 381         },
 382  },
 383  [ C(L1I ) ] = {
 384         [ C(OP_READ) ] = {
 385                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
 386                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
 387         },
 388         [ C(OP_WRITE) ] = {
 389                 [ C(RESULT_ACCESS) ] = -1,
 390                 [ C(RESULT_MISS)   ] = -1,
 391         },
 392         [ C(OP_PREFETCH) ] = {
 393                 [ C(RESULT_ACCESS) ] = 0,
 394                 [ C(RESULT_MISS)   ] = 0,
 395         },
 396  },
 397  [ C(LL  ) ] = {
 398         [ C(OP_READ) ] = {
 399                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 400                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 401         },
 402         [ C(OP_WRITE) ] = {
 403                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 404                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 405         },
 406         [ C(OP_PREFETCH) ] = {
 407                 [ C(RESULT_ACCESS) ] = 0,
 408                 [ C(RESULT_MISS)   ] = 0,
 409         },
 410  },
 411  [ C(DTLB) ] = {
 412         [ C(OP_READ) ] = {
 413                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
 414                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
 415         },
 416         [ C(OP_WRITE) ] = {
 417                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
 418                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
 419         },
 420         [ C(OP_PREFETCH) ] = {
 421                 [ C(RESULT_ACCESS) ] = 0,
 422                 [ C(RESULT_MISS)   ] = 0,
 423         },
 424  },
 425  [ C(ITLB) ] = {
 426         [ C(OP_READ) ] = {
 427                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 428                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
 429         },
 430         [ C(OP_WRITE) ] = {
 431                 [ C(RESULT_ACCESS) ] = -1,
 432                 [ C(RESULT_MISS)   ] = -1,
 433         },
 434         [ C(OP_PREFETCH) ] = {
 435                 [ C(RESULT_ACCESS) ] = -1,
 436                 [ C(RESULT_MISS)   ] = -1,
 437         },
 438  },
 439  [ C(BPU ) ] = {
 440         [ C(OP_READ) ] = {
 441                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 442                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 443         },
 444         [ C(OP_WRITE) ] = {
 445                 [ C(RESULT_ACCESS) ] = -1,
 446                 [ C(RESULT_MISS)   ] = -1,
 447         },
 448         [ C(OP_PREFETCH) ] = {
 449                 [ C(RESULT_ACCESS) ] = -1,
 450                 [ C(RESULT_MISS)   ] = -1,
 451         },
 452  },
 453 };
 454
 455 static void intel_pmu_disable_all(void)
 456 {
 457         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 458
 459         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 460
 461         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
 462                 intel_pmu_disable_bts();
 463
 464         intel_pmu_pebs_disable_all();
 465         intel_pmu_lbr_disable_all();
 466 }
 467
 468 static void intel_pmu_enable_all(int added)
 469 {
 470         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 471
 472         intel_pmu_pebs_enable_all();
 473         intel_pmu_lbr_enable_all();
 474         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
 475
 476         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
 477                 struct perf_event *event =
 478                         cpuc->events[X86_PMC_IDX_FIXED_BTS];
 479
 480                 if (WARN_ON_ONCE(!event))
 481                         return;
 482
 483                 intel_pmu_enable_bts(event->hw.config);
 484         }
 485 }
 486
 487 /*
 488  * Workaround for:
 489  *   Intel Errata AAK100 (model 26)
 490  *   Intel Errata AAP53  (model 30)
 491  *
 492  * These chips need to be 'reset' when adding counters by programming
 493  * the magic three (non counting) events 0x4300D2, 0x4300B1 and 0x4300B5
 494  * either in sequence on the same PMC or on different PMCs.
 495  */
 496 static void intel_pmu_nhm_enable_all(int added)
 497 {
 498         if (added) {
 499                 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 500                 int i;
 501
 502                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + 0, 0x4300D2);
 503                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + 1, 0x4300B1);
 504                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + 2, 0x4300B5);
 505
 506                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x3);
 507                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
 508
 509                 for (i = 0; i < 3; i++) {
 510                         struct perf_event *event = cpuc->events[i];
 511
 512                         if (!event)
 513                                 continue;
 514
 515                         __x86_pmu_enable_event(&event->hw);
 516                 }
 517         }
 518         intel_pmu_enable_all(added);
 519 }
 520
 521 static inline u64 intel_pmu_get_status(void)
 522 {
 523         u64 status;
 524
 525         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 526
 527         return status;
 528 }
 529
 530 static inline void intel_pmu_ack_status(u64 ack)
 531 {
 532         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
 533 }
 534
 535 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
 536 {
 537         int idx = hwc->idx - X86_PMC_IDX_FIXED;
 538         u64 ctrl_val, mask;
 539
 540         mask = 0xfULL << (idx * 4);
 541
 542         rdmsrl(hwc->config_base, ctrl_val);
 543         ctrl_val &= ~mask;
 544         wrmsrl(hwc->config_base, ctrl_val);
 545 }
 546
 547 static void intel_pmu_disable_event(struct perf_event *event)
 548 {
 549         struct hw_perf_event *hwc = &event->hw;
 550
 551         if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
 552                 intel_pmu_disable_bts();
 553                 intel_pmu_drain_bts_buffer();
 554                 return;
 555         }
 556
 557         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 558                 intel_pmu_disable_fixed(hwc);
 559                 return;
 560         }
 561
 562         x86_pmu_disable_event(event);
 563
 564         if (unlikely(event->attr.precise))
 565                 intel_pmu_pebs_disable(event);
 566 }
 567
 568 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
 569 {
 570         int idx = hwc->idx - X86_PMC_IDX_FIXED;
 571         u64 ctrl_val, bits, mask;
 572
 573         /*
 574          * Enable IRQ generation (0x8),
 575          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
 576          * if requested:
 577          */
 578         bits = 0x8ULL;
 579         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
 580                 bits |= 0x2;
 581         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 582                 bits |= 0x1;
 583
 584         /*
 585          * ANY bit is supported in v3 and up
 586          */
 587         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
 588                 bits |= 0x4;
 589
 590         bits <<= (idx * 4);
 591         mask = 0xfULL << (idx * 4);
 592
 593         rdmsrl(hwc->config_base, ctrl_val);
 594         ctrl_val &= ~mask;
 595         ctrl_val |= bits;
 596         wrmsrl(hwc->config_base, ctrl_val);
 597 }
 598
 599 static void intel_pmu_enable_event(struct perf_event *event)
 600 {
 601         struct hw_perf_event *hwc = &event->hw;
 602
 603         if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
 604                 if (!__get_cpu_var(cpu_hw_events).enabled)
 605                         return;
 606
 607                 intel_pmu_enable_bts(hwc->config);
 608                 return;
 609         }
 610
 611         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 612                 intel_pmu_enable_fixed(hwc);
 613                 return;
 614         }
 615
 616         if (unlikely(event->attr.precise))
 617                 intel_pmu_pebs_enable(event);
 618
 619         __x86_pmu_enable_event(hwc);
 620 }
 621
 622 /*
 623  * Save and restart an expired event. Called by NMI contexts,
 624  * so it has to be careful about preempting normal event ops:
 625  */
 626 static int intel_pmu_save_and_restart(struct perf_event *event)
 627 {
 628         x86_perf_event_update(event);
 629         return x86_perf_event_set_period(event);
 630 }
 631
 632 static void intel_pmu_reset(void)
 633 {
 634         struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
 635         unsigned long flags;
 636         int idx;
 637
 638         if (!x86_pmu.num_counters)
 639                 return;
 640
 641         local_irq_save(flags);
 642
 643         printk("clearing PMU state on CPU#%d\n", smp_processor_id());
 644
 645         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 646                 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
 647                 checking_wrmsrl(x86_pmu.perfctr  + idx, 0ull);
 648         }
 649         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
 650                 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
 651
 652         if (ds)
 653                 ds->bts_index = ds->bts_buffer_base;
 654
 655         local_irq_restore(flags);
 656 }
 657
 658 /*
 659  * This handler is triggered by the local APIC, so the APIC IRQ handling
 660  * rules apply:
 661  */
 662 static int intel_pmu_handle_irq(struct pt_regs *regs)
 663 {
 664         struct perf_sample_data data;
 665         struct cpu_hw_events *cpuc;
 666         int bit, loops;
 667         u64 ack, status;
 668
 669         perf_sample_data_init(&data, 0);
 670
 671         cpuc = &__get_cpu_var(cpu_hw_events);
 672
 673         intel_pmu_disable_all();
 674         intel_pmu_drain_bts_buffer();
 675         status = intel_pmu_get_status();
 676         if (!status) {
 677                 intel_pmu_enable_all(0);
 678                 return 0;
 679         }
 680
 681         loops = 0;
 682 again:
 683         if (++loops > 100) {
 684                 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
 685                 perf_event_print_debug();
 686                 intel_pmu_reset();
 687                 goto done;
 688         }
 689
 690         inc_irq_stat(apic_perf_irqs);
 691         ack = status;
 692
 693         intel_pmu_lbr_read();
 694
 695         /*
 696          * PEBS overflow sets bit 62 in the global status register
 697          */
 698         if (__test_and_clear_bit(62, (unsigned long *)&status))
 699                 x86_pmu.drain_pebs(regs);
 700
 701         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
 702                 struct perf_event *event = cpuc->events[bit];
 703
 704                 if (!test_bit(bit, cpuc->active_mask))
 705                         continue;
 706
 707                 if (!intel_pmu_save_and_restart(event))
 708                         continue;
 709
 710                 data.period = event->hw.last_period;
 711
 712                 if (perf_event_overflow(event, 1, &data, regs))
 713                         x86_pmu_stop(event);
 714         }
 715
 716         intel_pmu_ack_status(ack);
 717
 718         /*
 719          * Repeat if there is more work to be done:
 720          */
 721         status = intel_pmu_get_status();
 722         if (status)
 723                 goto again;
 724
 725 done:
 726         intel_pmu_enable_all(0);
 727         return 1;
 728 }
 729
 730 static struct event_constraint *
 731 intel_bts_constraints(struct perf_event *event)
 732 {
 733         struct hw_perf_event *hwc = &event->hw;
 734         unsigned int hw_event, bts_event;
 735
 736         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
 737         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
 738
 739         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
 740                 return &bts_constraint;
 741
 742         return NULL;
 743 }
 744
 745 static struct event_constraint *
 746 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 747 {
 748         struct event_constraint *c;
 749
 750         c = intel_bts_constraints(event);
 751         if (c)
 752                 return c;
 753
 754         c = intel_pebs_constraints(event);
 755         if (c)
 756                 return c;
 757
 758         return x86_get_event_constraints(cpuc, event);
 759 }
 760
 761 static __initconst struct x86_pmu core_pmu = {
 762         .name                   = "core",
 763         .handle_irq             = x86_pmu_handle_irq,
 764         .disable_all            = x86_pmu_disable_all,
 765         .enable_all             = x86_pmu_enable_all,
 766         .enable                 = x86_pmu_enable_event,
 767         .disable                = x86_pmu_disable_event,
 768         .hw_config              = x86_hw_config,
 769         .schedule_events        = x86_schedule_events,
 770         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
 771         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
 772         .event_map              = intel_pmu_event_map,
 773         .raw_event              = x86_pmu_raw_event,
 774         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
 775         .apic                   = 1,
 776         /*
 777          * Intel PMCs cannot be accessed sanely above 32 bit width,
 778          * so we install an artificial 1<<31 period regardless of
 779          * the generic event period:
 780          */
 781         .max_period             = (1ULL << 31) - 1,
 782         .get_event_constraints  = intel_get_event_constraints,
 783         .event_constraints      = intel_core_event_constraints,
 784 };
 785
 786 static void intel_pmu_cpu_starting(int cpu)
 787 {
 788         init_debug_store_on_cpu(cpu);
 789         /*
 790          * Deal with CPUs that don't clear their LBRs on power-up.
 791          */
 792         intel_pmu_lbr_reset();
 793 }
 794
 795 static void intel_pmu_cpu_dying(int cpu)
 796 {
 797         fini_debug_store_on_cpu(cpu);
 798 }
 799
 800 static __initconst struct x86_pmu intel_pmu = {
 801         .name                   = "Intel",
 802         .handle_irq             = intel_pmu_handle_irq,
 803         .disable_all            = intel_pmu_disable_all,
 804         .enable_all             = intel_pmu_enable_all,
 805         .enable                 = intel_pmu_enable_event,
 806         .disable                = intel_pmu_disable_event,
 807         .hw_config              = x86_hw_config,
 808         .schedule_events        = x86_schedule_events,
 809         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
 810         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
 811         .event_map              = intel_pmu_event_map,
 812         .raw_event              = x86_pmu_raw_event,
 813         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
 814         .apic                   = 1,
 815         /*
 816          * Intel PMCs cannot be accessed sanely above 32 bit width,
 817          * so we install an artificial 1<<31 period regardless of
 818          * the generic event period:
 819          */
 820         .max_period             = (1ULL << 31) - 1,
 821         .get_event_constraints  = intel_get_event_constraints,
 822
 823         .cpu_starting           = intel_pmu_cpu_starting,
 824         .cpu_dying              = intel_pmu_cpu_dying,
 825 };
 826
 827 static void intel_clovertown_quirks(void)
 828 {
 829         /*
 830          * PEBS is unreliable due to:
 831          *
 832          *   AJ67  - PEBS may experience CPL leaks
 833          *   AJ68  - PEBS PMI may be delayed by one event
 834          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
 835          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
 836          *
 837          * AJ67 could be worked around by restricting the OS/USR flags.
 838          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
 839          *
 840          * AJ106 could possibly be worked around by not allowing LBR
 841          *       usage from PEBS, including the fixup.
 842          * AJ68  could possibly be worked around by always programming
 843          *       a pebs_event_reset[0] value and coping with the lost events.
 844          *
 845          * But taken together it might just make sense to not enable PEBS on
 846          * these chips.
 847          */
 848         printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
 849         x86_pmu.pebs = 0;
 850         x86_pmu.pebs_constraints = NULL;
 851 }
 852
 853 static __init int intel_pmu_init(void)
 854 {
 855         union cpuid10_edx edx;
 856         union cpuid10_eax eax;
 857         unsigned int unused;
 858         unsigned int ebx;
 859         int version;
 860
 861         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 862                 switch (boot_cpu_data.x86) {
 863                 case 0x6:
 864                         return p6_pmu_init();
 865                 case 0xf:
 866                         return p4_pmu_init();
 867                 }
 868                 return -ENODEV;
 869         }
 870
 871         /*
 872          * Check whether the Architectural PerfMon supports
 873          * Branch Misses Retired hw_event or not.
 874          */
 875         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
 876         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
 877                 return -ENODEV;
 878
 879         version = eax.split.version_id;
 880         if (version < 2)
 881                 x86_pmu = core_pmu;
 882         else
 883                 x86_pmu = intel_pmu;
 884
 885         x86_pmu.version                 = version;
 886         x86_pmu.num_counters            = eax.split.num_counters;
 887         x86_pmu.cntval_bits             = eax.split.bit_width;
 888         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
 889
 890         /*
 891          * Quirk: v2 perfmon does not report fixed-purpose events, so
 892          * assume at least 3 events:
 893          */
 894         if (version > 1)
 895                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
 896
 897         /*
 898          * v2 and above have a perf capabilities MSR
 899          */
 900         if (version > 1) {
 901                 u64 capabilities;
 902
 903                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
 904                 x86_pmu.intel_cap.capabilities = capabilities;
 905         }
 906
 907         intel_ds_init();
 908
 909         /*
 910          * Install the hw-cache-events table:
 911          */
 912         switch (boot_cpu_data.x86_model) {
 913         case 14: /* 65 nm core solo/duo, "Yonah" */
 914                 pr_cont("Core events, ");
 915                 break;
 916
 917         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
 918                 x86_pmu.quirks = intel_clovertown_quirks;
 919         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
 920         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
 921         case 29: /* six-core 45 nm xeon "Dunnington" */
 922                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
 923                        sizeof(hw_cache_event_ids));
 924
 925                 intel_pmu_lbr_init_core();
 926
 927                 x86_pmu.event_constraints = intel_core2_event_constraints;
 928                 pr_cont("Core2 events, ");
 929                 break;
 930
 931         case 26: /* 45 nm nehalem, "Bloomfield" */
 932         case 30: /* 45 nm nehalem, "Lynnfield" */
 933                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
 934                        sizeof(hw_cache_event_ids));
 935
 936                 intel_pmu_lbr_init_nhm();
 937
 938                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
 939                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
 940                 pr_cont("Nehalem events, ");
 941                 break;
 942
 943         case 28: /* Atom */
 944                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
 945                        sizeof(hw_cache_event_ids));
 946
 947                 intel_pmu_lbr_init_atom();
 948
 949                 x86_pmu.event_constraints = intel_gen_event_constraints;
 950                 pr_cont("Atom events, ");
 951                 break;
 952
 953         case 37: /* 32 nm nehalem, "Clarkdale" */
 954         case 44: /* 32 nm nehalem, "Gulftown" */
 955                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
 956                        sizeof(hw_cache_event_ids));
 957
 958                 intel_pmu_lbr_init_nhm();
 959
 960                 x86_pmu.event_constraints = intel_westmere_event_constraints;
 961                 pr_cont("Westmere events, ");
 962                 break;
 963
 964         default:
 965                 /*
 966                  * default constraints for v2 and up
 967                  */
 968                 x86_pmu.event_constraints = intel_gen_event_constraints;
 969                 pr_cont("generic architected perfmon, ");
 970         }
 971         return 0;
 972 }
 973
 974 #else /* CONFIG_CPU_SUP_INTEL */
 975
 976 static int intel_pmu_init(void)
 977 {
 978         return 0;
 979 }
 980
 981 #endif /* CONFIG_CPU_SUP_INTEL */