2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
6 * Copyright(C) 2009 Jaswinder Singh Rajput
8 * For licencing details see kernel-base/COPYING
11 #include <linux/perf_counter.h>
12 #include <linux/capability.h>
13 #include <linux/notifier.h>
14 #include <linux/hardirq.h>
15 #include <linux/kprobes.h>
16 #include <linux/module.h>
17 #include <linux/kdebug.h>
18 #include <linux/sched.h>
22 static bool perf_counters_initialized __read_mostly;
25 * Number of (generic) HW counters:
27 static int nr_counters_generic __read_mostly;
28 static u64 perf_counter_mask __read_mostly;
29 static u64 counter_value_mask __read_mostly;
30 static int counter_value_bits __read_mostly;
32 static int nr_counters_fixed __read_mostly;
34 struct cpu_hw_counters {
35 struct perf_counter *counters[X86_PMC_IDX_MAX];
36 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
37 unsigned long interrupts;
39 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
44 * struct pmc_x86_ops - performance counter x86 ops
47 u64 (*save_disable_all)(void);
48 void (*restore_all)(u64);
49 u64 (*get_status)(u64);
50 void (*ack_status)(u64);
51 void (*enable)(int, u64);
52 void (*disable)(int, u64);
55 u64 (*event_map)(int);
56 u64 (*raw_event)(u64);
60 static struct pmc_x86_ops *pmc_ops __read_mostly;
62 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
66 static __read_mostly int intel_perfmon_version;
69 * Intel PerfMon v3. Used on Core2 and later.
71 static const u64 intel_perfmon_event_map[] =
73 [PERF_COUNT_CPU_CYCLES] = 0x003c,
74 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
75 [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
76 [PERF_COUNT_CACHE_MISSES] = 0x412e,
77 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
78 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
79 [PERF_COUNT_BUS_CYCLES] = 0x013c,
82 static u64 pmc_intel_event_map(int event)
84 return intel_perfmon_event_map[event];
87 static u64 pmc_intel_raw_event(u64 event)
89 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
90 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
91 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
93 #define CORE_EVNTSEL_MASK \
94 (CORE_EVNTSEL_EVENT_MASK | \
95 CORE_EVNTSEL_UNIT_MASK | \
96 CORE_EVNTSEL_COUNTER_MASK)
98 return event & CORE_EVNTSEL_MASK;
102 * AMD Performance Monitor K7 and later.
104 static const u64 amd_perfmon_event_map[] =
106 [PERF_COUNT_CPU_CYCLES] = 0x0076,
107 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
108 [PERF_COUNT_CACHE_REFERENCES] = 0x0080,
109 [PERF_COUNT_CACHE_MISSES] = 0x0081,
110 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
111 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
114 static u64 pmc_amd_event_map(int event)
116 return amd_perfmon_event_map[event];
119 static u64 pmc_amd_raw_event(u64 event)
121 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
122 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
123 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
125 #define K7_EVNTSEL_MASK \
126 (K7_EVNTSEL_EVENT_MASK | \
127 K7_EVNTSEL_UNIT_MASK | \
128 K7_EVNTSEL_COUNTER_MASK)
130 return event & K7_EVNTSEL_MASK;
134 * Propagate counter elapsed time into the generic counter.
135 * Can only be executed on the CPU where the counter is active.
136 * Returns the delta events processed.
139 x86_perf_counter_update(struct perf_counter *counter,
140 struct hw_perf_counter *hwc, int idx)
142 u64 prev_raw_count, new_raw_count, delta;
145 * Careful: an NMI might modify the previous counter value.
147 * Our tactic to handle this is to first atomically read and
148 * exchange a new raw count - then add that new-prev delta
149 * count to the generic counter atomically:
152 prev_raw_count = atomic64_read(&hwc->prev_count);
153 rdmsrl(hwc->counter_base + idx, new_raw_count);
155 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
156 new_raw_count) != prev_raw_count)
160 * Now we have the new raw value and have updated the prev
161 * timestamp already. We can now calculate the elapsed delta
162 * (counter-)time and add that to the generic counter.
164 * Careful, not all hw sign-extends above the physical width
165 * of the count, so we do that by clipping the delta to 32 bits:
167 delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
169 atomic64_add(delta, &counter->count);
170 atomic64_sub(delta, &hwc->period_left);
174 * Setup the hardware configuration for a given hw_event_type
176 static int __hw_perf_counter_init(struct perf_counter *counter)
178 struct perf_counter_hw_event *hw_event = &counter->hw_event;
179 struct hw_perf_counter *hwc = &counter->hw;
181 if (unlikely(!perf_counters_initialized))
186 * (keep 'enabled' bit clear for now)
188 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
191 * Count user and OS events unless requested not to.
193 if (!hw_event->exclude_user)
194 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
195 if (!hw_event->exclude_kernel)
196 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
199 * If privileged enough, allow NMI events:
202 if (capable(CAP_SYS_ADMIN) && hw_event->nmi)
205 hwc->irq_period = hw_event->irq_period;
207 * Intel PMCs cannot be accessed sanely above 32 bit width,
208 * so we install an artificial 1<<31 period regardless of
209 * the generic counter period:
211 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
212 if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF)
213 hwc->irq_period = 0x7FFFFFFF;
215 atomic64_set(&hwc->period_left, hwc->irq_period);
218 * Raw event type provide the config in the event structure
221 hwc->config |= pmc_ops->raw_event(hw_event->type);
223 if (hw_event->type >= pmc_ops->max_events)
228 hwc->config |= pmc_ops->event_map(hw_event->type);
230 counter->wakeup_pending = 0;
235 static u64 pmc_intel_save_disable_all(void)
239 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
240 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
245 static u64 pmc_amd_save_disable_all(void)
247 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
250 enabled = cpuc->enabled;
253 * ensure we write the disable before we start disabling the
254 * counters proper, so that pcm_amd_enable() does the right thing.
258 for (idx = 0; idx < nr_counters_generic; idx++) {
261 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
262 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) {
263 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
264 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
271 u64 hw_perf_save_disable(void)
273 if (unlikely(!perf_counters_initialized))
276 return pmc_ops->save_disable_all();
279 * Exported because of ACPI idle
281 EXPORT_SYMBOL_GPL(hw_perf_save_disable);
283 static void pmc_intel_restore_all(u64 ctrl)
285 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
288 static void pmc_amd_restore_all(u64 ctrl)
290 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
293 cpuc->enabled = ctrl;
298 for (idx = 0; idx < nr_counters_generic; idx++) {
299 if (test_bit(idx, cpuc->active_mask)) {
302 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
303 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
304 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
309 void hw_perf_restore(u64 ctrl)
311 if (unlikely(!perf_counters_initialized))
314 pmc_ops->restore_all(ctrl);
317 * Exported because of ACPI idle
319 EXPORT_SYMBOL_GPL(hw_perf_restore);
321 static u64 pmc_intel_get_status(u64 mask)
325 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
330 static u64 pmc_amd_get_status(u64 mask)
335 for (idx = 0; idx < nr_counters_generic; idx++) {
338 if (!(mask & (1 << idx)))
341 rdmsrl(MSR_K7_PERFCTR0 + idx, val);
342 val <<= (64 - counter_value_bits);
344 status |= (1 << idx);
350 static u64 hw_perf_get_status(u64 mask)
352 if (unlikely(!perf_counters_initialized))
355 return pmc_ops->get_status(mask);
358 static void pmc_intel_ack_status(u64 ack)
360 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
363 static void pmc_amd_ack_status(u64 ack)
367 static void hw_perf_ack_status(u64 ack)
369 if (unlikely(!perf_counters_initialized))
372 pmc_ops->ack_status(ack);
375 static void pmc_intel_enable(int idx, u64 config)
377 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx,
378 config | ARCH_PERFMON_EVENTSEL0_ENABLE);
381 static void pmc_amd_enable(int idx, u64 config)
383 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
385 set_bit(idx, cpuc->active_mask);
387 config |= ARCH_PERFMON_EVENTSEL0_ENABLE;
389 wrmsrl(MSR_K7_EVNTSEL0 + idx, config);
392 static void hw_perf_enable(int idx, u64 config)
394 if (unlikely(!perf_counters_initialized))
397 pmc_ops->enable(idx, config);
400 static void pmc_intel_disable(int idx, u64 config)
402 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config);
405 static void pmc_amd_disable(int idx, u64 config)
407 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
409 clear_bit(idx, cpuc->active_mask);
410 wrmsrl(MSR_K7_EVNTSEL0 + idx, config);
414 static void hw_perf_disable(int idx, u64 config)
416 if (unlikely(!perf_counters_initialized))
419 pmc_ops->disable(idx, config);
423 __pmc_fixed_disable(struct perf_counter *counter,
424 struct hw_perf_counter *hwc, unsigned int __idx)
426 int idx = __idx - X86_PMC_IDX_FIXED;
430 mask = 0xfULL << (idx * 4);
432 rdmsrl(hwc->config_base, ctrl_val);
434 err = checking_wrmsrl(hwc->config_base, ctrl_val);
438 __pmc_generic_disable(struct perf_counter *counter,
439 struct hw_perf_counter *hwc, unsigned int idx)
441 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
442 __pmc_fixed_disable(counter, hwc, idx);
444 hw_perf_disable(idx, hwc->config);
447 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
450 * Set the next IRQ period, based on the hwc->period_left value.
451 * To be called with the counter disabled in hw:
454 __hw_perf_counter_set_period(struct perf_counter *counter,
455 struct hw_perf_counter *hwc, int idx)
457 s64 left = atomic64_read(&hwc->period_left);
458 s64 period = hwc->irq_period;
462 * If we are way outside a reasoable range then just skip forward:
464 if (unlikely(left <= -period)) {
466 atomic64_set(&hwc->period_left, left);
469 if (unlikely(left <= 0)) {
471 atomic64_set(&hwc->period_left, left);
474 per_cpu(prev_left[idx], smp_processor_id()) = left;
477 * The hw counter starts counting from this counter offset,
478 * mark it to be able to extra future deltas:
480 atomic64_set(&hwc->prev_count, (u64)-left);
482 err = checking_wrmsrl(hwc->counter_base + idx,
483 (u64)(-left) & counter_value_mask);
487 __pmc_fixed_enable(struct perf_counter *counter,
488 struct hw_perf_counter *hwc, unsigned int __idx)
490 int idx = __idx - X86_PMC_IDX_FIXED;
491 u64 ctrl_val, bits, mask;
495 * Enable IRQ generation (0x8),
496 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
500 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
502 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
505 mask = 0xfULL << (idx * 4);
507 rdmsrl(hwc->config_base, ctrl_val);
510 err = checking_wrmsrl(hwc->config_base, ctrl_val);
514 __pmc_generic_enable(struct perf_counter *counter,
515 struct hw_perf_counter *hwc, int idx)
517 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
518 __pmc_fixed_enable(counter, hwc, idx);
520 hw_perf_enable(idx, hwc->config);
524 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
528 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
531 if (unlikely(hwc->nmi))
534 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
536 if (unlikely(event == pmc_ops->event_map(PERF_COUNT_INSTRUCTIONS)))
537 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
538 if (unlikely(event == pmc_ops->event_map(PERF_COUNT_CPU_CYCLES)))
539 return X86_PMC_IDX_FIXED_CPU_CYCLES;
540 if (unlikely(event == pmc_ops->event_map(PERF_COUNT_BUS_CYCLES)))
541 return X86_PMC_IDX_FIXED_BUS_CYCLES;
547 * Find a PMC slot for the freshly enabled / scheduled in counter:
549 static int pmc_generic_enable(struct perf_counter *counter)
551 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
552 struct hw_perf_counter *hwc = &counter->hw;
555 idx = fixed_mode_idx(counter, hwc);
558 * Try to get the fixed counter, if that is already taken
559 * then try to get a generic counter:
561 if (test_and_set_bit(idx, cpuc->used))
564 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
566 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
567 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
570 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
574 /* Try to get the previous generic counter again */
575 if (test_and_set_bit(idx, cpuc->used)) {
577 idx = find_first_zero_bit(cpuc->used, nr_counters_generic);
578 if (idx == nr_counters_generic)
581 set_bit(idx, cpuc->used);
584 hwc->config_base = pmc_ops->eventsel;
585 hwc->counter_base = pmc_ops->perfctr;
588 perf_counters_lapic_init(hwc->nmi);
590 __pmc_generic_disable(counter, hwc, idx);
592 cpuc->counters[idx] = counter;
594 * Make it visible before enabling the hw:
598 __hw_perf_counter_set_period(counter, hwc, idx);
599 __pmc_generic_enable(counter, hwc, idx);
604 void perf_counter_print_debug(void)
606 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
607 struct cpu_hw_counters *cpuc;
610 if (!nr_counters_generic)
615 cpu = smp_processor_id();
616 cpuc = &per_cpu(cpu_hw_counters, cpu);
618 if (intel_perfmon_version >= 2) {
619 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
620 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
621 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
622 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
625 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
626 pr_info("CPU#%d: status: %016llx\n", cpu, status);
627 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
628 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
630 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used);
632 for (idx = 0; idx < nr_counters_generic; idx++) {
633 rdmsrl(pmc_ops->eventsel + idx, pmc_ctrl);
634 rdmsrl(pmc_ops->perfctr + idx, pmc_count);
636 prev_left = per_cpu(prev_left[idx], cpu);
638 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
640 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
641 cpu, idx, pmc_count);
642 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
643 cpu, idx, prev_left);
645 for (idx = 0; idx < nr_counters_fixed; idx++) {
646 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
648 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
649 cpu, idx, pmc_count);
654 static void pmc_generic_disable(struct perf_counter *counter)
656 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
657 struct hw_perf_counter *hwc = &counter->hw;
658 unsigned int idx = hwc->idx;
660 __pmc_generic_disable(counter, hwc, idx);
662 clear_bit(idx, cpuc->used);
663 cpuc->counters[idx] = NULL;
665 * Make sure the cleared pointer becomes visible before we
666 * (potentially) free the counter:
671 * Drain the remaining delta count out of a counter
672 * that we are disabling:
674 x86_perf_counter_update(counter, hwc, idx);
677 static void perf_store_irq_data(struct perf_counter *counter, u64 data)
679 struct perf_data *irqdata = counter->irqdata;
681 if (irqdata->len > PERF_DATA_BUFLEN - sizeof(u64)) {
684 u64 *p = (u64 *) &irqdata->data[irqdata->len];
687 irqdata->len += sizeof(u64);
692 * Save and restart an expired counter. Called by NMI contexts,
693 * so it has to be careful about preempting normal counter ops:
695 static void perf_save_and_restart(struct perf_counter *counter)
697 struct hw_perf_counter *hwc = &counter->hw;
700 x86_perf_counter_update(counter, hwc, idx);
701 __hw_perf_counter_set_period(counter, hwc, idx);
703 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
704 __pmc_generic_enable(counter, hwc, idx);
708 perf_handle_group(struct perf_counter *sibling, u64 *status, u64 *overflown)
710 struct perf_counter *counter, *group_leader = sibling->group_leader;
713 * Store sibling timestamps (if any):
715 list_for_each_entry(counter, &group_leader->sibling_list, list_entry) {
717 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
718 perf_store_irq_data(sibling, counter->hw_event.type);
719 perf_store_irq_data(sibling, atomic64_read(&counter->count));
724 * Maximum interrupt frequency of 100KHz per CPU
726 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
729 * This handler is triggered by the local APIC, so the APIC IRQ handling
732 static int __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
734 int bit, cpu = smp_processor_id();
736 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
739 cpuc->throttle_ctrl = hw_perf_save_disable();
741 status = hw_perf_get_status(cpuc->throttle_ctrl);
747 inc_irq_stat(apic_perf_irqs);
749 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
750 struct perf_counter *counter = cpuc->counters[bit];
752 clear_bit(bit, (unsigned long *) &status);
756 perf_save_and_restart(counter);
758 switch (counter->hw_event.record_type) {
759 case PERF_RECORD_SIMPLE:
761 case PERF_RECORD_IRQ:
762 perf_store_irq_data(counter, instruction_pointer(regs));
764 case PERF_RECORD_GROUP:
765 perf_handle_group(counter, &status, &ack);
769 * From NMI context we cannot call into the scheduler to
770 * do a task wakeup - but we mark these generic as
771 * wakeup_pending and initate a wakeup callback:
774 counter->wakeup_pending = 1;
775 set_tsk_thread_flag(current, TIF_PERF_COUNTERS);
777 wake_up(&counter->waitq);
781 hw_perf_ack_status(ack);
784 * Repeat if there is more work to be done:
786 status = hw_perf_get_status(cpuc->throttle_ctrl);
791 * Restore - do not reenable when global enable is off or throttled:
793 if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS)
794 hw_perf_restore(cpuc->throttle_ctrl);
799 void perf_counter_unthrottle(void)
801 struct cpu_hw_counters *cpuc;
803 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
806 if (unlikely(!perf_counters_initialized))
809 cpuc = &__get_cpu_var(cpu_hw_counters);
810 if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
811 if (printk_ratelimit())
812 printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n");
813 hw_perf_restore(cpuc->throttle_ctrl);
815 cpuc->interrupts = 0;
818 void smp_perf_counter_interrupt(struct pt_regs *regs)
821 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
823 __smp_perf_counter_interrupt(regs, 0);
828 * This handler is triggered by NMI contexts:
830 void perf_counter_notify(struct pt_regs *regs)
832 struct cpu_hw_counters *cpuc;
836 local_irq_save(flags);
837 cpu = smp_processor_id();
838 cpuc = &per_cpu(cpu_hw_counters, cpu);
840 for_each_bit(bit, cpuc->used, X86_PMC_IDX_MAX) {
841 struct perf_counter *counter = cpuc->counters[bit];
846 if (counter->wakeup_pending) {
847 counter->wakeup_pending = 0;
848 wake_up(&counter->waitq);
852 local_irq_restore(flags);
855 void perf_counters_lapic_init(int nmi)
859 if (!perf_counters_initialized)
862 * Enable the performance counter vector in the APIC LVT:
864 apic_val = apic_read(APIC_LVTERR);
866 apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
868 apic_write(APIC_LVTPC, APIC_DM_NMI);
870 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
871 apic_write(APIC_LVTERR, apic_val);
875 perf_counter_nmi_handler(struct notifier_block *self,
876 unsigned long cmd, void *__args)
878 struct die_args *args = __args;
879 struct pt_regs *regs;
893 apic_write(APIC_LVTPC, APIC_DM_NMI);
894 ret = __smp_perf_counter_interrupt(regs, 1);
896 return ret ? NOTIFY_STOP : NOTIFY_OK;
899 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
900 .notifier_call = perf_counter_nmi_handler,
905 static struct pmc_x86_ops pmc_intel_ops = {
906 .save_disable_all = pmc_intel_save_disable_all,
907 .restore_all = pmc_intel_restore_all,
908 .get_status = pmc_intel_get_status,
909 .ack_status = pmc_intel_ack_status,
910 .enable = pmc_intel_enable,
911 .disable = pmc_intel_disable,
912 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
913 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
914 .event_map = pmc_intel_event_map,
915 .raw_event = pmc_intel_raw_event,
916 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
919 static struct pmc_x86_ops pmc_amd_ops = {
920 .save_disable_all = pmc_amd_save_disable_all,
921 .restore_all = pmc_amd_restore_all,
922 .get_status = pmc_amd_get_status,
923 .ack_status = pmc_amd_ack_status,
924 .enable = pmc_amd_enable,
925 .disable = pmc_amd_disable,
926 .eventsel = MSR_K7_EVNTSEL0,
927 .perfctr = MSR_K7_PERFCTR0,
928 .event_map = pmc_amd_event_map,
929 .raw_event = pmc_amd_raw_event,
930 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
933 static struct pmc_x86_ops *pmc_intel_init(void)
935 union cpuid10_edx edx;
936 union cpuid10_eax eax;
941 * Check whether the Architectural PerfMon supports
942 * Branch Misses Retired Event or not.
944 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
945 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
948 intel_perfmon_version = eax.split.version_id;
949 if (intel_perfmon_version < 2)
952 pr_info("Intel Performance Monitoring support detected.\n");
953 pr_info("... version: %d\n", intel_perfmon_version);
954 pr_info("... bit width: %d\n", eax.split.bit_width);
955 pr_info("... mask length: %d\n", eax.split.mask_length);
957 nr_counters_generic = eax.split.num_counters;
958 nr_counters_fixed = edx.split.num_counters_fixed;
959 counter_value_mask = (1ULL << eax.split.bit_width) - 1;
961 return &pmc_intel_ops;
964 static struct pmc_x86_ops *pmc_amd_init(void)
966 nr_counters_generic = 4;
967 nr_counters_fixed = 0;
968 counter_value_mask = 0x0000FFFFFFFFFFFFULL;
969 counter_value_bits = 48;
971 pr_info("AMD Performance Monitoring support detected.\n");
976 void __init init_hw_perf_counters(void)
978 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
981 switch (boot_cpu_data.x86_vendor) {
982 case X86_VENDOR_INTEL:
983 pmc_ops = pmc_intel_init();
986 pmc_ops = pmc_amd_init();
992 pr_info("... num counters: %d\n", nr_counters_generic);
993 if (nr_counters_generic > X86_PMC_MAX_GENERIC) {
994 nr_counters_generic = X86_PMC_MAX_GENERIC;
995 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
996 nr_counters_generic, X86_PMC_MAX_GENERIC);
998 perf_counter_mask = (1 << nr_counters_generic) - 1;
999 perf_max_counters = nr_counters_generic;
1001 pr_info("... value mask: %016Lx\n", counter_value_mask);
1003 if (nr_counters_fixed > X86_PMC_MAX_FIXED) {
1004 nr_counters_fixed = X86_PMC_MAX_FIXED;
1005 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1006 nr_counters_fixed, X86_PMC_MAX_FIXED);
1008 pr_info("... fixed counters: %d\n", nr_counters_fixed);
1010 perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1012 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
1013 perf_counters_initialized = true;
1015 perf_counters_lapic_init(0);
1016 register_die_notifier(&perf_counter_nmi_notifier);
1019 static void pmc_generic_read(struct perf_counter *counter)
1021 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1024 static const struct hw_perf_counter_ops x86_perf_counter_ops = {
1025 .enable = pmc_generic_enable,
1026 .disable = pmc_generic_disable,
1027 .read = pmc_generic_read,
1030 const struct hw_perf_counter_ops *
1031 hw_perf_counter_init(struct perf_counter *counter)
1035 err = __hw_perf_counter_init(counter);
1039 return &x86_perf_counter_ops;