2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kobject.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
33 #include <asm/processor.h>
34 #include <asm/uaccess.h>
44 #define MISC_MCELOG_MINOR 227
48 static int mce_dont_init;
52 * 0: always panic on uncorrected errors, log corrected errors
53 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
54 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
55 * 3: never panic or SIGBUS, log all errors (for testing only)
57 static int tolerant = 1;
60 static unsigned long notify_user;
62 static int mce_bootlog = -1;
63 static atomic_t mce_events;
65 static char trigger[128];
66 static char *trigger_argv[2] = { trigger, NULL };
68 static unsigned long dont_init_banks;
70 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
72 /* MCA banks polled by the period polling timer for corrected events */
73 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
74 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
77 static inline int skip_bank_init(int i)
79 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
82 /* Do initial initialization of a struct mce */
83 void mce_setup(struct mce *m)
85 memset(m, 0, sizeof(struct mce));
86 m->cpu = smp_processor_id();
91 * Lockless MCE logging infrastructure.
92 * This avoids deadlocks on printk locks without having to break locks. Also
93 * separate MCEs from kernel messages to avoid bogus bug reports.
96 static struct mce_log mcelog = {
101 void mce_log(struct mce *mce)
103 unsigned next, entry;
105 atomic_inc(&mce_events);
109 entry = rcu_dereference(mcelog.next);
112 * When the buffer fills up discard new entries.
113 * Assume that the earlier errors are the more
116 if (entry >= MCE_LOG_LEN) {
117 set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags);
120 /* Old left over entry. Skip: */
121 if (mcelog.entry[entry].finished) {
129 if (cmpxchg(&mcelog.next, entry, next) == entry)
132 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
134 mcelog.entry[entry].finished = 1;
137 set_bit(0, ¬ify_user);
140 static void print_mce(struct mce *m)
142 printk(KERN_EMERG "\n"
143 KERN_EMERG "HARDWARE ERROR\n"
145 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
146 m->cpu, m->mcgstatus, m->bank, m->status);
148 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
149 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
151 if (m->cs == __KERNEL_CS)
152 print_symbol("{%s}", m->ip);
155 printk(KERN_EMERG "TSC %llx ", m->tsc);
157 printk("ADDR %llx ", m->addr);
159 printk("MISC %llx ", m->misc);
161 printk(KERN_EMERG "This is not a software problem!\n");
162 printk(KERN_EMERG "Run through mcelog --ascii to decode "
163 "and contact your hardware vendor\n");
166 static void mce_panic(char *msg, struct mce *backup, u64 start)
171 for (i = 0; i < MCE_LOG_LEN; i++) {
172 u64 tsc = mcelog.entry[i].tsc;
174 if ((s64)(tsc - start) < 0)
176 print_mce(&mcelog.entry[i]);
177 if (backup && mcelog.entry[i].tsc == backup->tsc)
185 int mce_available(struct cpuinfo_x86 *c)
189 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
192 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
194 if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
202 /* Assume the RIP in the MSR is exact. Is this true? */
203 m->mcgstatus |= MCG_STATUS_EIPV;
204 rdmsrl(rip_msr, m->ip);
210 * Poll for corrected events or events that happened before reset.
211 * Those are just logged through /dev/mcelog.
213 * This is executed in standard interrupt context.
215 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
222 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
223 for (i = 0; i < banks; i++) {
224 if (!bank[i] || !test_bit(i, *b))
233 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
234 if (!(m.status & MCI_STATUS_VAL))
238 * Uncorrected events are handled by the exception handler
239 * when it is enabled. But when the exception is disabled log
242 * TBD do the same check for MCI_STATUS_EN here?
244 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
247 if (m.status & MCI_STATUS_MISCV)
248 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
249 if (m.status & MCI_STATUS_ADDRV)
250 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
252 if (!(flags & MCP_TIMESTAMP))
255 * Don't get the IP here because it's unlikely to
256 * have anything to do with the actual error location.
258 if (!(flags & MCP_DONTLOG)) {
260 add_taint(TAINT_MACHINE_CHECK);
264 * Clear state for this bank.
266 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
270 * Don't clear MCG_STATUS here because it's only defined for
276 * The actual machine check handler. This only handles real
277 * exceptions when something got corrupted coming in through int 18.
279 * This is executed in NMI context not subject to normal locking rules. This
280 * implies that most kernel services cannot be safely used. Don't even
281 * think about putting a printk in there!
283 void do_machine_check(struct pt_regs *regs, long error_code)
285 struct mce m, panicm;
286 int panicm_found = 0;
290 * If no_way_out gets set, there is no safe way to recover from this
291 * MCE. If tolerant is cranked up, we'll try anyway.
295 * If kill_it gets set, there might be a way to recover from this
299 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
301 atomic_inc(&mce_entry);
303 if (notify_die(DIE_NMI, "machine check", regs, error_code,
304 18, SIGKILL) == NOTIFY_STOP)
311 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
313 /* if the restart IP is not valid, we're done for */
314 if (!(m.mcgstatus & MCG_STATUS_RIPV))
320 for (i = 0; i < banks; i++) {
321 __clear_bit(i, toclear);
329 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
330 if ((m.status & MCI_STATUS_VAL) == 0)
334 * Non uncorrected errors are handled by machine_check_poll
337 if ((m.status & MCI_STATUS_UC) == 0)
341 * Set taint even when machine check was not enabled.
343 add_taint(TAINT_MACHINE_CHECK);
345 __set_bit(i, toclear);
347 if (m.status & MCI_STATUS_EN) {
348 /* if PCC was set, there's no way out */
349 no_way_out |= !!(m.status & MCI_STATUS_PCC);
351 * If this error was uncorrectable and there was
352 * an overflow, we're in trouble. If no overflow,
353 * we might get away with just killing a task.
355 if (m.status & MCI_STATUS_UC) {
356 if (tolerant < 1 || m.status & MCI_STATUS_OVER)
362 * Machine check event was not enabled. Clear, but
368 if (m.status & MCI_STATUS_MISCV)
369 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
370 if (m.status & MCI_STATUS_ADDRV)
371 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
373 mce_get_rip(&m, regs);
377 * Did this bank cause the exception?
379 * Assume that the bank with uncorrectable errors did it,
380 * and that there is only a single one:
382 if ((m.status & MCI_STATUS_UC) &&
383 (m.status & MCI_STATUS_EN)) {
390 * If we didn't find an uncorrectable error, pick
391 * the last one (shouldn't happen, just being safe).
397 * If we have decided that we just CAN'T continue, and the user
398 * has not set tolerant to an insane level, give up and die.
400 if (no_way_out && tolerant < 3)
401 mce_panic("Machine check", &panicm, mcestart);
404 * If the error seems to be unrecoverable, something should be
405 * done. Try to kill as little as possible. If we can kill just
406 * one task, do that. If the user has set the tolerance very
407 * high, don't try to do anything at all.
409 if (kill_it && tolerant < 3) {
413 * If the EIPV bit is set, it means the saved IP is the
414 * instruction which caused the MCE.
416 if (m.mcgstatus & MCG_STATUS_EIPV)
417 user_space = panicm.ip && (panicm.cs & 3);
420 * If we know that the error was in user space, send a
421 * SIGBUS. Otherwise, panic if tolerance is low.
423 * force_sig() takes an awful lot of locks and has a slight
424 * risk of deadlocking.
427 force_sig(SIGBUS, current);
428 } else if (panic_on_oops || tolerant < 2) {
429 mce_panic("Uncorrected machine check",
434 /* notify userspace ASAP */
435 set_thread_flag(TIF_MCE_NOTIFY);
437 /* the last thing we do is clear state */
438 for (i = 0; i < banks; i++) {
439 if (test_bit(i, toclear))
440 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
442 wrmsrl(MSR_IA32_MCG_STATUS, 0);
444 atomic_dec(&mce_entry);
447 #ifdef CONFIG_X86_MCE_INTEL
449 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
450 * @cpu: The CPU on which the event occurred.
451 * @status: Event status information
453 * This function should be called by the thermal interrupt after the
454 * event has been processed and the decision was made to log the event
457 * The status parameter will be saved to the 'status' field of 'struct mce'
458 * and historically has been the register value of the
459 * MSR_IA32_THERMAL_STATUS (Intel) msr.
461 void mce_log_therm_throt_event(__u64 status)
466 m.bank = MCE_THERMAL_BANK;
470 #endif /* CONFIG_X86_MCE_INTEL */
473 * Periodic polling timer for "silent" machine check errors. If the
474 * poller finds an MCE, poll 2x faster. When the poller finds no more
475 * errors, poll 2x slower (up to check_interval seconds).
477 static int check_interval = 5 * 60; /* 5 minutes */
479 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
480 static DEFINE_PER_CPU(struct timer_list, mce_timer);
482 static void mcheck_timer(unsigned long data)
484 struct timer_list *t = &per_cpu(mce_timer, data);
487 WARN_ON(smp_processor_id() != data);
489 if (mce_available(¤t_cpu_data)) {
490 machine_check_poll(MCP_TIMESTAMP,
491 &__get_cpu_var(mce_poll_banks));
495 * Alert userspace if needed. If we logged an MCE, reduce the
496 * polling interval, otherwise increase the polling interval.
498 n = &__get_cpu_var(next_interval);
499 if (mce_notify_user()) {
500 *n = max(*n/2, HZ/100);
502 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
505 t->expires = jiffies + *n;
509 static void mce_do_trigger(struct work_struct *work)
511 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
514 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
517 * Notify the user(s) about new machine check events.
518 * Can be called from interrupt context, but not from machine check/NMI
521 int mce_notify_user(void)
523 /* Not more than two messages every minute */
524 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
526 clear_thread_flag(TIF_MCE_NOTIFY);
528 if (test_and_clear_bit(0, ¬ify_user)) {
529 wake_up_interruptible(&mce_wait);
532 * There is no risk of missing notifications because
533 * work_pending is always cleared before the function is
536 if (trigger[0] && !work_pending(&mce_trigger_work))
537 schedule_work(&mce_trigger_work);
539 if (__ratelimit(&ratelimit))
540 printk(KERN_INFO "Machine check events logged\n");
547 /* see if the idle task needs to notify userspace: */
549 mce_idle_callback(struct notifier_block *nfb, unsigned long action,
552 /* IDLE_END should be safe - interrupts are back on */
553 if (action == IDLE_END && test_thread_flag(TIF_MCE_NOTIFY))
559 static struct notifier_block mce_idle_notifier = {
560 .notifier_call = mce_idle_callback,
563 static __init int periodic_mcheck_init(void)
565 idle_notifier_register(&mce_idle_notifier);
568 __initcall(periodic_mcheck_init);
571 * Initialize Machine Checks for a CPU.
573 static int mce_cap_init(void)
578 rdmsrl(MSR_IA32_MCG_CAP, cap);
580 b = cap & MCG_BANKCNT_MASK;
581 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
583 if (b > MAX_NR_BANKS) {
585 "MCE: Using only %u machine check banks out of %u\n",
590 /* Don't support asymmetric configurations today */
591 WARN_ON(banks != 0 && b != banks);
594 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
597 memset(bank, 0xff, banks * sizeof(u64));
600 /* Use accurate RIP reporting if available. */
601 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
602 rip_msr = MSR_IA32_MCG_EIP;
607 static void mce_init(void *dummy)
609 mce_banks_t all_banks;
614 * Log the machine checks left over from the previous reset.
616 bitmap_fill(all_banks, MAX_NR_BANKS);
617 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
619 set_in_cr4(X86_CR4_MCE);
621 rdmsrl(MSR_IA32_MCG_CAP, cap);
623 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
625 for (i = 0; i < banks; i++) {
626 if (skip_bank_init(i))
628 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
629 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
633 /* Add per CPU specific workarounds here */
634 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
636 /* This should be disabled by the BIOS, but isn't always */
637 if (c->x86_vendor == X86_VENDOR_AMD) {
638 if (c->x86 == 15 && banks > 4) {
640 * disable GART TBL walk error reporting, which
641 * trips off incorrectly with the IOMMU & 3ware
644 clear_bit(10, (unsigned long *)&bank[4]);
646 if (c->x86 <= 17 && mce_bootlog < 0) {
648 * Lots of broken BIOS around that don't clear them
649 * by default and leave crap in there. Don't log:
654 * Various K7s with broken bank 0 around. Always disable
661 if (c->x86_vendor == X86_VENDOR_INTEL) {
663 * SDM documents that on family 6 bank 0 should not be written
664 * because it aliases to another special BIOS controlled
666 * But it's not aliased anymore on model 0x1a+
667 * Don't ignore bank 0 completely because there could be a
668 * valid event later, merely don't write CTL0.
671 if (c->x86 == 6 && c->x86_model < 0x1A)
672 __set_bit(0, &dont_init_banks);
676 static void mce_cpu_features(struct cpuinfo_x86 *c)
678 switch (c->x86_vendor) {
679 case X86_VENDOR_INTEL:
680 mce_intel_feature_init(c);
683 mce_amd_feature_init(c);
690 static void mce_init_timer(void)
692 struct timer_list *t = &__get_cpu_var(mce_timer);
693 int *n = &__get_cpu_var(next_interval);
695 *n = check_interval * HZ;
698 setup_timer(t, mcheck_timer, smp_processor_id());
699 t->expires = round_jiffies(jiffies + *n);
704 * Called for each booted CPU to set up machine checks.
705 * Must be called with preempt off:
707 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
709 if (!mce_available(c))
712 if (mce_cap_init() < 0) {
724 * Character device to read and clear the MCE log.
727 static DEFINE_SPINLOCK(mce_state_lock);
728 static int open_count; /* #times opened */
729 static int open_exclu; /* already open exclusive? */
731 static int mce_open(struct inode *inode, struct file *file)
734 spin_lock(&mce_state_lock);
736 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
737 spin_unlock(&mce_state_lock);
743 if (file->f_flags & O_EXCL)
747 spin_unlock(&mce_state_lock);
750 return nonseekable_open(inode, file);
753 static int mce_release(struct inode *inode, struct file *file)
755 spin_lock(&mce_state_lock);
760 spin_unlock(&mce_state_lock);
765 static void collect_tscs(void *data)
767 unsigned long *cpu_tsc = (unsigned long *)data;
769 rdtscll(cpu_tsc[smp_processor_id()]);
772 static DEFINE_MUTEX(mce_read_mutex);
774 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
777 char __user *buf = ubuf;
778 unsigned long *cpu_tsc;
782 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
786 mutex_lock(&mce_read_mutex);
787 next = rcu_dereference(mcelog.next);
789 /* Only supports full reads right now */
790 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
791 mutex_unlock(&mce_read_mutex);
800 for (i = prev; i < next; i++) {
801 unsigned long start = jiffies;
803 while (!mcelog.entry[i].finished) {
804 if (time_after_eq(jiffies, start + 2)) {
805 memset(mcelog.entry + i, 0,
812 err |= copy_to_user(buf, mcelog.entry + i,
814 buf += sizeof(struct mce);
819 memset(mcelog.entry + prev, 0,
820 (next - prev) * sizeof(struct mce));
822 next = cmpxchg(&mcelog.next, prev, 0);
823 } while (next != prev);
828 * Collect entries that were still getting written before the
831 on_each_cpu(collect_tscs, cpu_tsc, 1);
833 for (i = next; i < MCE_LOG_LEN; i++) {
834 if (mcelog.entry[i].finished &&
835 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
836 err |= copy_to_user(buf, mcelog.entry+i,
839 buf += sizeof(struct mce);
840 memset(&mcelog.entry[i], 0, sizeof(struct mce));
843 mutex_unlock(&mce_read_mutex);
846 return err ? -EFAULT : buf - ubuf;
849 static unsigned int mce_poll(struct file *file, poll_table *wait)
851 poll_wait(file, &mce_wait, wait);
852 if (rcu_dereference(mcelog.next))
853 return POLLIN | POLLRDNORM;
857 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
859 int __user *p = (int __user *)arg;
861 if (!capable(CAP_SYS_ADMIN))
865 case MCE_GET_RECORD_LEN:
866 return put_user(sizeof(struct mce), p);
867 case MCE_GET_LOG_LEN:
868 return put_user(MCE_LOG_LEN, p);
869 case MCE_GETCLEAR_FLAGS: {
873 flags = mcelog.flags;
874 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
876 return put_user(flags, p);
883 static const struct file_operations mce_chrdev_ops = {
885 .release = mce_release,
888 .unlocked_ioctl = mce_ioctl,
891 static struct miscdevice mce_log_device = {
898 * Old style boot options parsing. Only for compatibility.
900 static int __init mcheck_disable(char *str)
905 __setup("nomce", mcheck_disable);
908 * mce=off disables machine check
909 * mce=TOLERANCELEVEL (number, see above)
910 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
911 * mce=nobootlog Don't log MCEs from before booting.
913 static int __init mcheck_enable(char *str)
915 if (!strcmp(str, "off"))
917 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
918 mce_bootlog = (str[0] == 'b');
919 else if (isdigit(str[0]))
920 get_option(&str, &tolerant);
922 printk(KERN_INFO "mce= argument %s ignored. Please use /sys\n",
928 __setup("mce=", mcheck_enable);
935 * Disable machine checks on suspend and shutdown. We can't really handle
938 static int mce_disable(void)
942 for (i = 0; i < banks; i++) {
943 if (!skip_bank_init(i))
944 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
949 static int mce_suspend(struct sys_device *dev, pm_message_t state)
951 return mce_disable();
954 static int mce_shutdown(struct sys_device *dev)
956 return mce_disable();
960 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
961 * Only one CPU is active at this time, the others get re-added later using
964 static int mce_resume(struct sys_device *dev)
967 mce_cpu_features(¤t_cpu_data);
972 static void mce_cpu_restart(void *data)
974 del_timer_sync(&__get_cpu_var(mce_timer));
975 if (mce_available(¤t_cpu_data))
980 /* Reinit MCEs after user configuration changes */
981 static void mce_restart(void)
983 on_each_cpu(mce_cpu_restart, NULL, 1);
986 static struct sysdev_class mce_sysclass = {
987 .suspend = mce_suspend,
988 .shutdown = mce_shutdown,
989 .resume = mce_resume,
990 .name = "machinecheck",
993 DEFINE_PER_CPU(struct sys_device, mce_dev);
996 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
998 /* Why are there no generic functions for this? */
999 #define ACCESSOR(name, var, start) \
1000 static ssize_t show_ ## name(struct sys_device *s, \
1001 struct sysdev_attribute *attr, \
1003 return sprintf(buf, "%Lx\n", (u64)var); \
1005 static ssize_t set_ ## name(struct sys_device *s, \
1006 struct sysdev_attribute *attr, \
1007 const char *buf, size_t siz) { \
1009 u64 new = simple_strtoull(buf, &end, 0); \
1018 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
1020 static struct sysdev_attribute *bank_attrs;
1022 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1025 u64 b = bank[attr - bank_attrs];
1027 return sprintf(buf, "%llx\n", b);
1030 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1031 const char *buf, size_t siz)
1034 u64 new = simple_strtoull(buf, &end, 0);
1039 bank[attr - bank_attrs] = new;
1046 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1048 strcpy(buf, trigger);
1050 return strlen(trigger) + 1;
1053 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1054 const char *buf, size_t siz)
1059 strncpy(trigger, buf, sizeof(trigger));
1060 trigger[sizeof(trigger)-1] = 0;
1061 len = strlen(trigger);
1062 p = strchr(trigger, '\n');
1070 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1071 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1073 ACCESSOR(check_interval, check_interval, mce_restart())
1075 static struct sysdev_attribute *mce_attrs[] = {
1076 &attr_tolerant.attr, &attr_check_interval, &attr_trigger,
1080 static cpumask_var_t mce_dev_initialized;
1082 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1083 static __cpuinit int mce_create_device(unsigned int cpu)
1088 if (!mce_available(&boot_cpu_data))
1091 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1092 per_cpu(mce_dev, cpu).id = cpu;
1093 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1095 err = sysdev_register(&per_cpu(mce_dev, cpu));
1099 for (i = 0; mce_attrs[i]; i++) {
1100 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1104 for (i = 0; i < banks; i++) {
1105 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1110 cpumask_set_cpu(cpu, mce_dev_initialized);
1115 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1118 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1120 sysdev_unregister(&per_cpu(mce_dev, cpu));
1125 static __cpuinit void mce_remove_device(unsigned int cpu)
1129 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1132 for (i = 0; mce_attrs[i]; i++)
1133 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1135 for (i = 0; i < banks; i++)
1136 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1138 sysdev_unregister(&per_cpu(mce_dev, cpu));
1139 cpumask_clear_cpu(cpu, mce_dev_initialized);
1142 /* Make sure there are no machine checks on offlined CPUs. */
1143 static void mce_disable_cpu(void *h)
1145 unsigned long action = *(unsigned long *)h;
1148 if (!mce_available(¤t_cpu_data))
1150 if (!(action & CPU_TASKS_FROZEN))
1152 for (i = 0; i < banks; i++) {
1153 if (!skip_bank_init(i))
1154 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1158 static void mce_reenable_cpu(void *h)
1160 unsigned long action = *(unsigned long *)h;
1163 if (!mce_available(¤t_cpu_data))
1166 if (!(action & CPU_TASKS_FROZEN))
1168 for (i = 0; i < banks; i++) {
1169 if (!skip_bank_init(i))
1170 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1174 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1175 static int __cpuinit
1176 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1178 unsigned int cpu = (unsigned long)hcpu;
1179 struct timer_list *t = &per_cpu(mce_timer, cpu);
1183 case CPU_ONLINE_FROZEN:
1184 mce_create_device(cpu);
1185 if (threshold_cpu_callback)
1186 threshold_cpu_callback(action, cpu);
1189 case CPU_DEAD_FROZEN:
1190 if (threshold_cpu_callback)
1191 threshold_cpu_callback(action, cpu);
1192 mce_remove_device(cpu);
1194 case CPU_DOWN_PREPARE:
1195 case CPU_DOWN_PREPARE_FROZEN:
1197 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1199 case CPU_DOWN_FAILED:
1200 case CPU_DOWN_FAILED_FROZEN:
1201 t->expires = round_jiffies(jiffies +
1202 __get_cpu_var(next_interval));
1203 add_timer_on(t, cpu);
1204 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1207 /* intentionally ignoring frozen here */
1208 cmci_rediscover(cpu);
1214 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1215 .notifier_call = mce_cpu_callback,
1218 static __init int mce_init_banks(void)
1222 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1227 for (i = 0; i < banks; i++) {
1228 struct sysdev_attribute *a = &bank_attrs[i];
1230 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1234 a->attr.mode = 0644;
1235 a->show = show_bank;
1236 a->store = set_bank;
1242 kfree(bank_attrs[i].attr.name);
1249 static __init int mce_init_device(void)
1254 if (!mce_available(&boot_cpu_data))
1257 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1259 err = mce_init_banks();
1263 err = sysdev_class_register(&mce_sysclass);
1267 for_each_online_cpu(i) {
1268 err = mce_create_device(i);
1273 register_hotcpu_notifier(&mce_cpu_notifier);
1274 misc_register(&mce_log_device);
1279 device_initcall(mce_init_device);
1281 #else /* CONFIG_X86_32: */
1286 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
1288 /* Handle unconfigured int18 (should never happen) */
1289 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1291 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1292 smp_processor_id());
1295 /* Call the installed machine check handler for this CPU setup. */
1296 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1297 unexpected_machine_check;
1299 /* This has to be run for each processor */
1300 void mcheck_init(struct cpuinfo_x86 *c)
1302 if (mce_disabled == 1)
1305 switch (c->x86_vendor) {
1306 case X86_VENDOR_AMD:
1310 case X86_VENDOR_INTEL:
1312 intel_p5_mcheck_init(c);
1314 intel_p6_mcheck_init(c);
1316 intel_p4_mcheck_init(c);
1319 case X86_VENDOR_CENTAUR:
1321 winchip_mcheck_init(c);
1327 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
1330 static int __init mcheck_disable(char *str)
1336 static int __init mcheck_enable(char *str)
1342 __setup("nomce", mcheck_disable);
1343 __setup("mce", mcheck_enable);
1345 #endif /* CONFIG_X86_32 */