1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
13 #include <asm/uaccess.h>
14 #include <asm/ptrace.h>
19 #ifdef CONFIG_X86_LOCAL_APIC
20 #include <asm/mpspec.h>
22 #include <mach_apic.h>
25 #ifdef CONFIG_X86_INTEL_USERCOPY
27 * Alignment at which movsl is preferred for bulk memory copies.
29 struct movsl_mask movsl_mask __read_mostly;
32 void __cpuinit early_intel_workaround(struct cpuinfo_x86 *c)
34 if (c->x86_vendor != X86_VENDOR_INTEL)
36 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
37 if (c->x86 == 15 && c->x86_cache_alignment == 64)
38 c->x86_cache_alignment = 128;
42 * Early probe support logic for ppro memory erratum #50
44 * This is called before we do cpu ident work
47 int __cpuinit ppro_with_ram_bug(void)
49 /* Uses data from early_cpu_detect now */
50 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
51 boot_cpu_data.x86 == 6 &&
52 boot_cpu_data.x86_model == 1 &&
53 boot_cpu_data.x86_mask < 8) {
54 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
62 * P4 Xeon errata 037 workaround.
63 * Hardware prefetcher may cause stale data to be loaded into the cache.
65 static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
69 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
70 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
71 if ((lo & (1<<9)) == 0) {
72 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
73 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
74 lo |= (1<<9); /* Disable hw prefetching */
75 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
82 * find out the number of processor cores on the die
84 static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
86 unsigned int eax, ebx, ecx, edx;
88 if (c->cpuid_level < 4)
91 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
92 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
94 return ((eax >> 26) + 1);
99 #ifdef CONFIG_X86_F00F_BUG
100 static void __cpuinit trap_init_f00f_bug(void)
102 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
105 * Update the IDT descriptor and reload the IDT so that
106 * it uses the read-only mapped virtual address.
108 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
109 load_idt(&idt_descr);
113 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
118 #ifdef CONFIG_X86_F00F_BUG
120 * All current models of Pentium and Pentium with MMX technology CPUs
121 * have the F0 0F bug, which lets nonprivileged users lock up the system.
122 * Note that the workaround only should be initialized once...
125 if (!paravirt_enabled() && c->x86 == 5) {
126 static int f00f_workaround_enabled = 0;
129 if ( !f00f_workaround_enabled ) {
130 trap_init_f00f_bug();
131 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
132 f00f_workaround_enabled = 1;
137 select_idle_routine(c);
138 l2 = init_intel_cacheinfo(c);
139 if (c->cpuid_level > 9 ) {
140 unsigned eax = cpuid_eax(10);
141 /* Check for version and the number of counters */
142 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
143 set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
146 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
147 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
148 clear_bit(X86_FEATURE_SEP, c->x86_capability);
150 /* Names for the Pentium II/Celeron processors
151 detectable only by also checking the cache size.
152 Dixon is NOT a Celeron. */
154 switch (c->x86_model) {
156 if (c->x86_mask == 0) {
158 p = "Celeron (Covington)";
160 p = "Mobile Pentium II (Dixon)";
166 p = "Celeron (Mendocino)";
167 else if (c->x86_mask == 0 || c->x86_mask == 5)
173 p = "Celeron (Coppermine)";
179 strcpy(c->x86_model_id, p);
181 c->x86_max_cores = num_cpu_cores(c);
185 /* Work around errata */
186 Intel_errata_workarounds(c);
188 #ifdef CONFIG_X86_INTEL_USERCOPY
190 * Set up the preferred alignment for movsl bulk memory moves
193 case 4: /* 486: untested */
195 case 5: /* Old Pentia: untested */
197 case 6: /* PII/PIII only like movsl with 8-byte alignment */
200 case 15: /* P4 is OK down to 8-byte alignment */
207 set_bit(X86_FEATURE_P4, c->x86_capability);
208 set_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
211 set_bit(X86_FEATURE_P3, c->x86_capability);
212 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
213 (c->x86 == 0x6 && c->x86_model >= 0x0e))
214 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
218 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
220 set_bit(X86_FEATURE_BTS, c->x86_capability);
222 set_bit(X86_FEATURE_PEBS, c->x86_capability);
229 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
231 /* Intel PIII Tualatin. This comes in two flavours.
232 * One has 256kb of cache, the other 512. We have no way
233 * to determine which, so we use a boottime override
234 * for the 512kb model, and assume 256 otherwise.
236 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
241 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
243 .c_ident = { "GenuineIntel" },
245 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
247 [0] = "486 DX-25/33",
258 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
260 [0] = "Pentium 60/66 A-step",
261 [1] = "Pentium 60/66",
262 [2] = "Pentium 75 - 200",
263 [3] = "OverDrive PODP5V83",
265 [7] = "Mobile Pentium 75 - 200",
266 [8] = "Mobile Pentium MMX"
269 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
271 [0] = "Pentium Pro A-step",
273 [3] = "Pentium II (Klamath)",
274 [4] = "Pentium II (Deschutes)",
275 [5] = "Pentium II (Deschutes)",
276 [6] = "Mobile Pentium II",
277 [7] = "Pentium III (Katmai)",
278 [8] = "Pentium III (Coppermine)",
279 [10] = "Pentium III (Cascades)",
280 [11] = "Pentium III (Tualatin)",
283 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
285 [0] = "Pentium 4 (Unknown)",
286 [1] = "Pentium 4 (Willamette)",
287 [2] = "Pentium 4 (Northwood)",
288 [4] = "Pentium 4 (Foster)",
289 [5] = "Pentium 4 (Foster)",
293 .c_init = init_intel,
294 .c_size_cache = intel_size_cache,
297 __init int intel_cpu_init(void)
299 cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
303 #ifndef CONFIG_X86_CMPXCHG
304 unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
309 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
310 local_irq_save(flags);
314 local_irq_restore(flags);
317 EXPORT_SYMBOL(cmpxchg_386_u8);
319 unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
324 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
325 local_irq_save(flags);
329 local_irq_restore(flags);
332 EXPORT_SYMBOL(cmpxchg_386_u16);
334 unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
339 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
340 local_irq_save(flags);
344 local_irq_restore(flags);
347 EXPORT_SYMBOL(cmpxchg_386_u32);
350 #ifndef CONFIG_X86_CMPXCHG64
351 unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
356 /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
357 local_irq_save(flags);
361 local_irq_restore(flags);
364 EXPORT_SYMBOL(cmpxchg_486_u64);
367 // arch_initcall(intel_cpu_init);