1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
13 #include <asm/uaccess.h>
14 #include <asm/ptrace.h>
20 #ifdef CONFIG_X86_LOCAL_APIC
21 #include <asm/mpspec.h>
23 #include <mach_apic.h>
26 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
28 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
29 if (c->x86 == 15 && c->x86_cache_alignment == 64)
30 c->x86_cache_alignment = 128;
31 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
32 (c->x86 == 0x6 && c->x86_model >= 0x0e))
33 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
37 * Early probe support logic for ppro memory erratum #50
39 * This is called before we do cpu ident work
42 int __cpuinit ppro_with_ram_bug(void)
44 /* Uses data from early_cpu_detect now */
45 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
46 boot_cpu_data.x86 == 6 &&
47 boot_cpu_data.x86_model == 1 &&
48 boot_cpu_data.x86_mask < 8) {
49 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
57 * P4 Xeon errata 037 workaround.
58 * Hardware prefetcher may cause stale data to be loaded into the cache.
60 static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
64 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
65 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
66 if ((lo & (1<<9)) == 0) {
67 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
68 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
69 lo |= (1<<9); /* Disable hw prefetching */
70 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
77 * find out the number of processor cores on the die
79 static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
81 unsigned int eax, ebx, ecx, edx;
83 if (c->cpuid_level < 4)
86 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
87 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
89 return ((eax >> 26) + 1);
94 #ifdef CONFIG_X86_F00F_BUG
95 static void __cpuinit trap_init_f00f_bug(void)
97 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
100 * Update the IDT descriptor and reload the IDT so that
101 * it uses the read-only mapped virtual address.
103 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
104 load_idt(&idt_descr);
108 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
115 #ifdef CONFIG_X86_F00F_BUG
117 * All current models of Pentium and Pentium with MMX technology CPUs
118 * have the F0 0F bug, which lets nonprivileged users lock up the system.
119 * Note that the workaround only should be initialized once...
122 if (!paravirt_enabled() && c->x86 == 5) {
123 static int f00f_workaround_enabled;
126 if (!f00f_workaround_enabled) {
127 trap_init_f00f_bug();
128 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
129 f00f_workaround_enabled = 1;
134 l2 = init_intel_cacheinfo(c);
135 if (c->cpuid_level > 9) {
136 unsigned eax = cpuid_eax(10);
137 /* Check for version and the number of counters */
138 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
139 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
142 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
143 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
144 clear_cpu_cap(c, X86_FEATURE_SEP);
147 * Names for the Pentium II/Celeron processors
148 * detectable only by also checking the cache size.
149 * Dixon is NOT a Celeron.
152 switch (c->x86_model) {
154 if (c->x86_mask == 0) {
156 p = "Celeron (Covington)";
158 p = "Mobile Pentium II (Dixon)";
164 p = "Celeron (Mendocino)";
165 else if (c->x86_mask == 0 || c->x86_mask == 5)
171 p = "Celeron (Coppermine)";
177 strcpy(c->x86_model_id, p);
179 c->x86_max_cores = num_cpu_cores(c);
183 /* Work around errata */
184 Intel_errata_workarounds(c);
186 #ifdef CONFIG_X86_INTEL_USERCOPY
188 * Set up the preferred alignment for movsl bulk memory moves
191 case 4: /* 486: untested */
193 case 5: /* Old Pentia: untested */
195 case 6: /* PII/PIII only like movsl with 8-byte alignment */
198 case 15: /* P4 is OK down to 8-byte alignment */
205 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
207 set_cpu_cap(c, X86_FEATURE_P4);
210 set_cpu_cap(c, X86_FEATURE_P3);
213 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
215 set_cpu_cap(c, X86_FEATURE_BTS);
217 set_cpu_cap(c, X86_FEATURE_PEBS);
224 * See if we have a good local APIC by checking for buggy Pentia,
225 * i.e. all B steppings and the C2 stepping of P54C when using their
226 * integrated APIC (see 11AP erratum in "Pentium Processor
227 * Specification Update").
229 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
230 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
231 set_cpu_cap(c, X86_FEATURE_11AP);
233 #ifdef CONFIG_X86_NUMAQ
238 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
241 * Intel PIII Tualatin. This comes in two flavours.
242 * One has 256kb of cache, the other 512. We have no way
243 * to determine which, so we use a boottime override
244 * for the 512kb model, and assume 256 otherwise.
246 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
251 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
253 .c_ident = { "GenuineIntel" },
255 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
257 [0] = "486 DX-25/33",
268 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
270 [0] = "Pentium 60/66 A-step",
271 [1] = "Pentium 60/66",
272 [2] = "Pentium 75 - 200",
273 [3] = "OverDrive PODP5V83",
275 [7] = "Mobile Pentium 75 - 200",
276 [8] = "Mobile Pentium MMX"
279 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
281 [0] = "Pentium Pro A-step",
283 [3] = "Pentium II (Klamath)",
284 [4] = "Pentium II (Deschutes)",
285 [5] = "Pentium II (Deschutes)",
286 [6] = "Mobile Pentium II",
287 [7] = "Pentium III (Katmai)",
288 [8] = "Pentium III (Coppermine)",
289 [10] = "Pentium III (Cascades)",
290 [11] = "Pentium III (Tualatin)",
293 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
295 [0] = "Pentium 4 (Unknown)",
296 [1] = "Pentium 4 (Willamette)",
297 [2] = "Pentium 4 (Northwood)",
298 [4] = "Pentium 4 (Foster)",
299 [5] = "Pentium 4 (Foster)",
303 .c_early_init = early_init_intel,
304 .c_init = init_intel,
305 .c_size_cache = intel_size_cache,
308 cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
310 /* arch_initcall(intel_cpu_init); */