SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpu.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/string.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/module.h>
  20 #include <linux/hardirq.h>
  21 #include <linux/timer.h>
  22 #include <linux/proc_fs.h>
  23 #include <asm/current.h>
  24 #include <asm/smp.h>
  25 #include <asm/apic.h>
  26 #include <asm/ipi.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/uv.h>
  29 #include <asm/uv/uv_mmrs.h>
  30 #include <asm/uv/uv_hub.h>
  31 #include <asm/uv/bios.h>
  32
  33 DEFINE_PER_CPU(int, x2apic_extra_bits);
  34
  35 static enum uv_system_type uv_system_type;
  36
  37 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  38 {
  39         if (!strcmp(oem_id, "SGI")) {
  40                 if (!strcmp(oem_table_id, "UVL"))
  41                         uv_system_type = UV_LEGACY_APIC;
  42                 else if (!strcmp(oem_table_id, "UVX"))
  43                         uv_system_type = UV_X2APIC;
  44                 else if (!strcmp(oem_table_id, "UVH")) {
  45                         uv_system_type = UV_NON_UNIQUE_APIC;
  46                         return 1;
  47                 }
  48         }
  49         return 0;
  50 }
  51
  52 enum uv_system_type get_uv_system_type(void)
  53 {
  54         return uv_system_type;
  55 }
  56
  57 int is_uv_system(void)
  58 {
  59         return uv_system_type != UV_NONE;
  60 }
  61 EXPORT_SYMBOL_GPL(is_uv_system);
  62
  63 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  65
  66 struct uv_blade_info *uv_blade_info;
  67 EXPORT_SYMBOL_GPL(uv_blade_info);
  68
  69 short *uv_node_to_blade;
  70 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  71
  72 short *uv_cpu_to_blade;
  73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  74
  75 short uv_possible_blades;
  76 EXPORT_SYMBOL_GPL(uv_possible_blades);
  77
  78 unsigned long sn_rtc_cycles_per_second;
  79 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  80
  81 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  82
  83 static const struct cpumask *uv_target_cpus(void)
  84 {
  85         return cpumask_of(0);
  86 }
  87
  88 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
  89 {
  90         cpumask_clear(retmask);
  91         cpumask_set_cpu(cpu, retmask);
  92 }
  93
  94 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
  95 {
  96         unsigned long val;
  97         int pnode;
  98
  99         pnode = uv_apicid_to_pnode(phys_apicid);
 100         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 101             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 102             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 103             APIC_DM_INIT;
 104         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 105         mdelay(10);
 106
 107         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 108             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 109             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 110             APIC_DM_STARTUP;
 111         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 112
 113         atomic_set(&init_deasserted, 1);
 114
 115         return 0;
 116 }
 117
 118 static void uv_send_IPI_one(int cpu, int vector)
 119 {
 120         unsigned long val, apicid;
 121         int pnode;
 122
 123         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 124         pnode = uv_apicid_to_pnode(apicid);
 125
 126         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 127               (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 128               (vector << UVH_IPI_INT_VECTOR_SHFT);
 129
 130         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 131 }
 132
 133 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 134 {
 135         unsigned int cpu;
 136
 137         for_each_cpu(cpu, mask)
 138                 uv_send_IPI_one(cpu, vector);
 139 }
 140
 141 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 142 {
 143         unsigned int this_cpu = smp_processor_id();
 144         unsigned int cpu;
 145
 146         for_each_cpu(cpu, mask) {
 147                 if (cpu != this_cpu)
 148                         uv_send_IPI_one(cpu, vector);
 149         }
 150 }
 151
 152 static void uv_send_IPI_allbutself(int vector)
 153 {
 154         unsigned int this_cpu = smp_processor_id();
 155         unsigned int cpu;
 156
 157         for_each_online_cpu(cpu) {
 158                 if (cpu != this_cpu)
 159                         uv_send_IPI_one(cpu, vector);
 160         }
 161 }
 162
 163 static void uv_send_IPI_all(int vector)
 164 {
 165         uv_send_IPI_mask(cpu_online_mask, vector);
 166 }
 167
 168 static int uv_apic_id_registered(void)
 169 {
 170         return 1;
 171 }
 172
 173 static void uv_init_apic_ldr(void)
 174 {
 175 }
 176
 177 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 178 {
 179         /*
 180          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 181          * May as well be the first.
 182          */
 183         int cpu = cpumask_first(cpumask);
 184
 185         if ((unsigned)cpu < nr_cpu_ids)
 186                 return per_cpu(x86_cpu_to_apicid, cpu);
 187         else
 188                 return BAD_APICID;
 189 }
 190
 191 static unsigned int
 192 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 193                           const struct cpumask *andmask)
 194 {
 195         int cpu;
 196
 197         /*
 198          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 199          * May as well be the first.
 200          */
 201         for_each_cpu_and(cpu, cpumask, andmask) {
 202                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 203                         break;
 204         }
 205         if (cpu < nr_cpu_ids)
 206                 return per_cpu(x86_cpu_to_apicid, cpu);
 207
 208         return BAD_APICID;
 209 }
 210
 211 static unsigned int x2apic_get_apic_id(unsigned long x)
 212 {
 213         unsigned int id;
 214
 215         WARN_ON(preemptible() && num_online_cpus() > 1);
 216         id = x | __get_cpu_var(x2apic_extra_bits);
 217
 218         return id;
 219 }
 220
 221 static unsigned long set_apic_id(unsigned int id)
 222 {
 223         unsigned long x;
 224
 225         /* maskout x2apic_extra_bits ? */
 226         x = id;
 227         return x;
 228 }
 229
 230 static unsigned int uv_read_apic_id(void)
 231 {
 232
 233         return x2apic_get_apic_id(apic_read(APIC_ID));
 234 }
 235
 236 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 237 {
 238         return uv_read_apic_id() >> index_msb;
 239 }
 240
 241 static void uv_send_IPI_self(int vector)
 242 {
 243         apic_write(APIC_SELF_IPI, vector);
 244 }
 245
 246 struct apic apic_x2apic_uv_x = {
 247
 248         .name                           = "UV large system",
 249         .probe                          = NULL,
 250         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 251         .apic_id_registered             = uv_apic_id_registered,
 252
 253         .irq_delivery_mode              = dest_Fixed,
 254         .irq_dest_mode                  = 1, /* logical */
 255
 256         .target_cpus                    = uv_target_cpus,
 257         .disable_esr                    = 0,
 258         .dest_logical                   = APIC_DEST_LOGICAL,
 259         .check_apicid_used              = NULL,
 260         .check_apicid_present           = NULL,
 261
 262         .vector_allocation_domain       = uv_vector_allocation_domain,
 263         .init_apic_ldr                  = uv_init_apic_ldr,
 264
 265         .ioapic_phys_id_map             = NULL,
 266         .setup_apic_routing             = NULL,
 267         .multi_timer_check              = NULL,
 268         .apicid_to_node                 = NULL,
 269         .cpu_to_logical_apicid          = NULL,
 270         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 271         .apicid_to_cpu_present          = NULL,
 272         .setup_portio_remap             = NULL,
 273         .check_phys_apicid_present      = default_check_phys_apicid_present,
 274         .enable_apic_mode               = NULL,
 275         .phys_pkg_id                    = uv_phys_pkg_id,
 276         .mps_oem_check                  = NULL,
 277
 278         .get_apic_id                    = x2apic_get_apic_id,
 279         .set_apic_id                    = set_apic_id,
 280         .apic_id_mask                   = 0xFFFFFFFFu,
 281
 282         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 283         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 284
 285         .send_IPI_mask                  = uv_send_IPI_mask,
 286         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 287         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 288         .send_IPI_all                   = uv_send_IPI_all,
 289         .send_IPI_self                  = uv_send_IPI_self,
 290
 291         .wakeup_cpu                     = uv_wakeup_secondary,
 292         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 293         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 294         .wait_for_init_deassert         = NULL,
 295         .smp_callin_clear_local_apic    = NULL,
 296         .inquire_remote_apic            = NULL,
 297
 298         .read                           = native_apic_msr_read,
 299         .write                          = native_apic_msr_write,
 300         .icr_read                       = native_x2apic_icr_read,
 301         .icr_write                      = native_x2apic_icr_write,
 302         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 303         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 304 };
 305
 306 static __cpuinit void set_x2apic_extra_bits(int pnode)
 307 {
 308         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 309 }
 310
 311 /*
 312  * Called on boot cpu.
 313  */
 314 static __init int boot_pnode_to_blade(int pnode)
 315 {
 316         int blade;
 317
 318         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 319                 if (pnode == uv_blade_info[blade].pnode)
 320                         return blade;
 321         BUG();
 322 }
 323
 324 struct redir_addr {
 325         unsigned long redirect;
 326         unsigned long alias;
 327 };
 328
 329 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 330
 331 static __initdata struct redir_addr redir_addrs[] = {
 332         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 333         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 334         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 335 };
 336
 337 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 338 {
 339         union uvh_si_alias0_overlay_config_u alias;
 340         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 341         int i;
 342
 343         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 344                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 345                 if (alias.s.base == 0) {
 346                         *size = (1UL << alias.s.m_alias);
 347                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 348                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 349                         return;
 350                 }
 351         }
 352         BUG();
 353 }
 354
 355 static __init void map_low_mmrs(void)
 356 {
 357         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 358         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 359 }
 360
 361 enum map_type {map_wb, map_uc};
 362
 363 static __init void map_high(char *id, unsigned long base, int shift,
 364                             int max_pnode, enum map_type map_type)
 365 {
 366         unsigned long bytes, paddr;
 367
 368         paddr = base << shift;
 369         bytes = (1UL << shift) * (max_pnode + 1);
 370         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 371                                                 paddr + bytes);
 372         if (map_type == map_uc)
 373                 init_extra_mapping_uc(paddr, bytes);
 374         else
 375                 init_extra_mapping_wb(paddr, bytes);
 376
 377 }
 378 static __init void map_gru_high(int max_pnode)
 379 {
 380         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 381         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 382
 383         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 384         if (gru.s.enable)
 385                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 386 }
 387
 388 static __init void map_config_high(int max_pnode)
 389 {
 390         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 391         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 392
 393         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 394         if (cfg.s.enable)
 395                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 396 }
 397
 398 static __init void map_mmr_high(int max_pnode)
 399 {
 400         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 401         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 402
 403         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 404         if (mmr.s.enable)
 405                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 406 }
 407
 408 static __init void map_mmioh_high(int max_pnode)
 409 {
 410         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 411         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 412
 413         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 414         if (mmioh.s.enable)
 415                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 416 }
 417
 418 static __init void uv_rtc_init(void)
 419 {
 420         long status;
 421         u64 ticks_per_sec;
 422
 423         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 424                                         &ticks_per_sec);
 425         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 426                 printk(KERN_WARNING
 427                         "unable to determine platform RTC clock frequency, "
 428                         "guessing.\n");
 429                 /* BIOS gives wrong value for clock freq. so guess */
 430                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 431         } else
 432                 sn_rtc_cycles_per_second = ticks_per_sec;
 433 }
 434
 435 /*
 436  * percpu heartbeat timer
 437  */
 438 static void uv_heartbeat(unsigned long ignored)
 439 {
 440         struct timer_list *timer = &uv_hub_info->scir.timer;
 441         unsigned char bits = uv_hub_info->scir.state;
 442
 443         /* flip heartbeat bit */
 444         bits ^= SCIR_CPU_HEARTBEAT;
 445
 446         /* is this cpu idle? */
 447         if (idle_cpu(raw_smp_processor_id()))
 448                 bits &= ~SCIR_CPU_ACTIVITY;
 449         else
 450                 bits |= SCIR_CPU_ACTIVITY;
 451
 452         /* update system controller interface reg */
 453         uv_set_scir_bits(bits);
 454
 455         /* enable next timer period */
 456         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 457 }
 458
 459 static void __cpuinit uv_heartbeat_enable(int cpu)
 460 {
 461         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 462                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 463
 464                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 465                 setup_timer(timer, uv_heartbeat, cpu);
 466                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 467                 add_timer_on(timer, cpu);
 468                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 469         }
 470
 471         /* check boot cpu */
 472         if (!uv_cpu_hub_info(0)->scir.enabled)
 473                 uv_heartbeat_enable(0);
 474 }
 475
 476 #ifdef CONFIG_HOTPLUG_CPU
 477 static void __cpuinit uv_heartbeat_disable(int cpu)
 478 {
 479         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 480                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 481                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 482         }
 483         uv_set_cpu_scir_bits(cpu, 0xff);
 484 }
 485
 486 /*
 487  * cpu hotplug notifier
 488  */
 489 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 490                                        unsigned long action, void *hcpu)
 491 {
 492         long cpu = (long)hcpu;
 493
 494         switch (action) {
 495         case CPU_ONLINE:
 496                 uv_heartbeat_enable(cpu);
 497                 break;
 498         case CPU_DOWN_PREPARE:
 499                 uv_heartbeat_disable(cpu);
 500                 break;
 501         default:
 502                 break;
 503         }
 504         return NOTIFY_OK;
 505 }
 506
 507 static __init void uv_scir_register_cpu_notifier(void)
 508 {
 509         hotcpu_notifier(uv_scir_cpu_notify, 0);
 510 }
 511
 512 #else /* !CONFIG_HOTPLUG_CPU */
 513
 514 static __init void uv_scir_register_cpu_notifier(void)
 515 {
 516 }
 517
 518 static __init int uv_init_heartbeat(void)
 519 {
 520         int cpu;
 521
 522         if (is_uv_system())
 523                 for_each_online_cpu(cpu)
 524                         uv_heartbeat_enable(cpu);
 525         return 0;
 526 }
 527
 528 late_initcall(uv_init_heartbeat);
 529
 530 #endif /* !CONFIG_HOTPLUG_CPU */
 531
 532 /*
 533  * Called on each cpu to initialize the per_cpu UV data area.
 534  *      ZZZ hotplug not supported yet
 535  */
 536 void __cpuinit uv_cpu_init(void)
 537 {
 538         /* CPU 0 initilization will be done via uv_system_init. */
 539         if (!uv_blade_info)
 540                 return;
 541
 542         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 543
 544         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 545                 set_x2apic_extra_bits(uv_hub_info->pnode);
 546 }
 547
 548
 549 void __init uv_system_init(void)
 550 {
 551         union uvh_si_addr_map_config_u m_n_config;
 552         union uvh_node_id_u node_id;
 553         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 554         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 555         int max_pnode = 0;
 556         unsigned long mmr_base, present;
 557
 558         map_low_mmrs();
 559
 560         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 561         m_val = m_n_config.s.m_skt;
 562         n_val = m_n_config.s.n_skt;
 563         mmr_base =
 564             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 565             ~UV_MMR_ENABLE;
 566         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 567
 568         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 569                 uv_possible_blades +=
 570                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 571         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 572
 573         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 574         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 575
 576         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 577
 578         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 579         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 580         memset(uv_node_to_blade, 255, bytes);
 581
 582         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 583         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 584         memset(uv_cpu_to_blade, 255, bytes);
 585
 586         blade = 0;
 587         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 588                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 589                 for (j = 0; j < 64; j++) {
 590                         if (!test_bit(j, &present))
 591                                 continue;
 592                         uv_blade_info[blade].pnode = (i * 64 + j);
 593                         uv_blade_info[blade].nr_possible_cpus = 0;
 594                         uv_blade_info[blade].nr_online_cpus = 0;
 595                         blade++;
 596                 }
 597         }
 598
 599         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 600         gnode_upper = (((unsigned long)node_id.s.node_id) &
 601                        ~((1 << n_val) - 1)) << m_val;
 602
 603         uv_bios_init();
 604         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 605                             &sn_coherency_id, &sn_region_size);
 606         uv_rtc_init();
 607
 608         for_each_present_cpu(cpu) {
 609                 nid = cpu_to_node(cpu);
 610                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 611                 blade = boot_pnode_to_blade(pnode);
 612                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 613                 uv_blade_info[blade].nr_possible_cpus++;
 614
 615                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 616                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 617                 uv_cpu_hub_info(cpu)->m_val = m_val;
 618                 uv_cpu_hub_info(cpu)->n_val = m_val;
 619                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 620                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 621                 uv_cpu_hub_info(cpu)->pnode = pnode;
 622                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 623                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 624                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 625                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 626                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 627                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
 628                 uv_node_to_blade[nid] = blade;
 629                 uv_cpu_to_blade[cpu] = blade;
 630                 max_pnode = max(pnode, max_pnode);
 631
 632                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 633                         "lcpu %d, blade %d\n",
 634                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 635                         lcpu, blade);
 636         }
 637
 638         map_gru_high(max_pnode);
 639         map_mmr_high(max_pnode);
 640         map_config_high(max_pnode);
 641         map_mmioh_high(max_pnode);
 642
 643         uv_cpu_init();
 644         uv_scir_register_cpu_notifier();
 645         proc_mkdir("sgi_uv", NULL);
 646 }