2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug = -1;
75 static DEFINE_SPINLOCK(ioapic_lock);
76 static DEFINE_SPINLOCK(vector_lock);
79 * # of IRQ routing registers
81 int nr_ioapic_registers[MAX_IO_APICS];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type[MAX_MP_BUSSES];
97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99 int skip_ioapic_setup;
101 void arch_disable_smp_support(void)
105 noioapicreroute = -1;
107 skip_ioapic_setup = 1;
110 static int __init parse_noapic(char *str)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list {
129 struct irq_pin_list *next;
132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
134 struct irq_pin_list *pin;
137 node = cpu_to_node(cpu);
139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
145 struct irq_pin_list *irq_2_pin;
146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
148 unsigned move_cleanup_count;
150 u8 move_in_progress : 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx[] = {
160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
180 int __init arch_early_irq_init(void)
183 struct irq_desc *desc;
188 count = ARRAY_SIZE(irq_cfgx);
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg *irq_cfg(unsigned int irq)
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
208 desc = irq_to_desc(irq);
210 cfg = desc->chip_data;
215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
220 node = cpu_to_node(cpu);
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
229 free_cpumask_var(cfg->domain);
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
245 cfg = desc->chip_data;
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
269 entry = get_one_free_irq_2_pin(cpu);
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
277 old_entry = old_entry->next;
279 entry = get_one_free_irq_2_pin(cpu);
287 /* still use the old one */
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
294 old_entry = old_entry->next;
298 cfg->irq_2_pin = head;
301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
303 struct irq_pin_list *entry, *next;
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
308 entry = old_cfg->irq_2_pin;
315 old_cfg->irq_2_pin = NULL;
318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
322 struct irq_cfg *old_cfg;
324 cfg = get_one_free_irq_cfg(cpu);
329 desc->chip_data = cfg;
331 old_cfg = old_desc->chip_data;
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
338 static void free_irq_cfg(struct irq_cfg *old_cfg)
343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
345 struct irq_cfg *old_cfg, *cfg;
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
363 struct irq_cfg *cfg = desc->chip_data;
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc->affinity, mask))
368 cfg->move_desc_pending = 1;
374 static struct irq_cfg *irq_cfg(unsigned int irq)
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
390 unsigned int unused[3];
392 unsigned int unused2[11];
396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
398 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
399 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(vector, &io_apic->eoi);
408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
410 struct io_apic __iomem *io_apic = io_apic_base(apic);
411 writel(reg, &io_apic->index);
412 return readl(&io_apic->data);
415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
417 struct io_apic __iomem *io_apic = io_apic_base(apic);
418 writel(reg, &io_apic->index);
419 writel(value, &io_apic->data);
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
426 * Older SiS APIC requires we rewrite the index register
428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
430 struct io_apic __iomem *io_apic = io_apic_base(apic);
433 writel(reg, &io_apic->index);
434 writel(value, &io_apic->data);
437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
439 struct irq_pin_list *entry;
442 spin_lock_irqsave(&ioapic_lock, flags);
443 entry = cfg->irq_2_pin;
451 reg = io_apic_read(entry->apic, 0x10 + pin*2);
452 /* Is the remote IRR bit set? */
453 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
454 spin_unlock_irqrestore(&ioapic_lock, flags);
461 spin_unlock_irqrestore(&ioapic_lock, flags);
467 struct { u32 w1, w2; };
468 struct IO_APIC_route_entry entry;
471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
473 union entry_union eu;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
477 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
478 spin_unlock_irqrestore(&ioapic_lock, flags);
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
491 union entry_union eu;
493 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
494 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
500 spin_lock_irqsave(&ioapic_lock, flags);
501 __ioapic_write_entry(apic, pin, e);
502 spin_unlock_irqrestore(&ioapic_lock, flags);
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
510 static void ioapic_mask_entry(int apic, int pin)
513 union entry_union eu = { .entry.mask = 1 };
515 spin_lock_irqsave(&ioapic_lock, flags);
516 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
517 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
518 spin_unlock_irqrestore(&ioapic_lock, flags);
522 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
523 * shared ISA-space IRQs, so we have to support them. We are super
524 * fast in the common case, and fast for shared ISA-space IRQs.
526 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
528 struct irq_pin_list *entry;
530 entry = cfg->irq_2_pin;
532 entry = get_one_free_irq_2_pin(cpu);
534 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
538 cfg->irq_2_pin = entry;
544 while (entry->next) {
545 /* not again, please */
546 if (entry->apic == apic && entry->pin == pin)
552 entry->next = get_one_free_irq_2_pin(cpu);
559 * Reroute an IRQ to a different pin.
561 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
562 int oldapic, int oldpin,
563 int newapic, int newpin)
565 struct irq_pin_list *entry = cfg->irq_2_pin;
569 if (entry->apic == oldapic && entry->pin == oldpin) {
570 entry->apic = newapic;
573 /* every one is different, right? */
579 /* why? call replace before add? */
581 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
584 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
585 int mask_and, int mask_or,
586 void (*final)(struct irq_pin_list *entry))
589 struct irq_pin_list *entry;
591 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
594 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
597 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
603 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
605 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
609 static void io_apic_sync(struct irq_pin_list *entry)
612 * Synchronize the IO-APIC and the CPU by doing
613 * a dummy read from the IO-APIC
615 struct io_apic __iomem *io_apic;
616 io_apic = io_apic_base(entry->apic);
617 readl(&io_apic->data);
620 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
622 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
624 #else /* CONFIG_X86_32 */
625 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
627 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
630 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
632 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
633 IO_APIC_REDIR_MASKED, NULL);
636 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
638 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
639 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
641 #endif /* CONFIG_X86_32 */
643 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
645 struct irq_cfg *cfg = desc->chip_data;
650 spin_lock_irqsave(&ioapic_lock, flags);
651 __mask_IO_APIC_irq(cfg);
652 spin_unlock_irqrestore(&ioapic_lock, flags);
655 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
657 struct irq_cfg *cfg = desc->chip_data;
660 spin_lock_irqsave(&ioapic_lock, flags);
661 __unmask_IO_APIC_irq(cfg);
662 spin_unlock_irqrestore(&ioapic_lock, flags);
665 static void mask_IO_APIC_irq(unsigned int irq)
667 struct irq_desc *desc = irq_to_desc(irq);
669 mask_IO_APIC_irq_desc(desc);
671 static void unmask_IO_APIC_irq(unsigned int irq)
673 struct irq_desc *desc = irq_to_desc(irq);
675 unmask_IO_APIC_irq_desc(desc);
678 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
680 struct IO_APIC_route_entry entry;
682 /* Check delivery_mode to be sure we're not clearing an SMI pin */
683 entry = ioapic_read_entry(apic, pin);
684 if (entry.delivery_mode == dest_SMI)
687 * Disable it in the IO-APIC irq-routing table:
689 ioapic_mask_entry(apic, pin);
692 static void clear_IO_APIC (void)
696 for (apic = 0; apic < nr_ioapics; apic++)
697 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
698 clear_IO_APIC_pin(apic, pin);
703 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
704 * specific CPU-side IRQs.
708 static int pirq_entries[MAX_PIRQS] = {
709 [0 ... MAX_PIRQS - 1] = -1
712 static int __init ioapic_pirq_setup(char *str)
715 int ints[MAX_PIRQS+1];
717 get_options(str, ARRAY_SIZE(ints), ints);
719 apic_printk(APIC_VERBOSE, KERN_INFO
720 "PIRQ redirection, working around broken MP-BIOS.\n");
722 if (ints[0] < MAX_PIRQS)
725 for (i = 0; i < max; i++) {
726 apic_printk(APIC_VERBOSE, KERN_DEBUG
727 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
729 * PIRQs are mapped upside down, usually.
731 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
736 __setup("pirq=", ioapic_pirq_setup);
737 #endif /* CONFIG_X86_32 */
739 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
742 struct IO_APIC_route_entry **ioapic_entries;
744 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
749 for (apic = 0; apic < nr_ioapics; apic++) {
750 ioapic_entries[apic] =
751 kzalloc(sizeof(struct IO_APIC_route_entry) *
752 nr_ioapic_registers[apic], GFP_ATOMIC);
753 if (!ioapic_entries[apic])
757 return ioapic_entries;
761 kfree(ioapic_entries[apic]);
762 kfree(ioapic_entries);
768 * Saves all the IO-APIC RTE's
770 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
777 for (apic = 0; apic < nr_ioapics; apic++) {
778 if (!ioapic_entries[apic])
781 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
782 ioapic_entries[apic][pin] =
783 ioapic_read_entry(apic, pin);
790 * Mask all IO APIC entries.
792 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
799 for (apic = 0; apic < nr_ioapics; apic++) {
800 if (!ioapic_entries[apic])
803 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
804 struct IO_APIC_route_entry entry;
806 entry = ioapic_entries[apic][pin];
809 ioapic_write_entry(apic, pin, entry);
816 * Restore IO APIC entries which was saved in ioapic_entries.
818 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
825 for (apic = 0; apic < nr_ioapics; apic++) {
826 if (!ioapic_entries[apic])
829 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
830 ioapic_write_entry(apic, pin,
831 ioapic_entries[apic][pin]);
836 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
840 for (apic = 0; apic < nr_ioapics; apic++)
841 kfree(ioapic_entries[apic]);
843 kfree(ioapic_entries);
847 * Find the IRQ entry number of a certain pin.
849 static int find_irq_entry(int apic, int pin, int type)
853 for (i = 0; i < mp_irq_entries; i++)
854 if (mp_irqs[i].irqtype == type &&
855 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
856 mp_irqs[i].dstapic == MP_APIC_ALL) &&
857 mp_irqs[i].dstirq == pin)
864 * Find the pin to which IRQ[irq] (ISA) is connected
866 static int __init find_isa_irq_pin(int irq, int type)
870 for (i = 0; i < mp_irq_entries; i++) {
871 int lbus = mp_irqs[i].srcbus;
873 if (test_bit(lbus, mp_bus_not_pci) &&
874 (mp_irqs[i].irqtype == type) &&
875 (mp_irqs[i].srcbusirq == irq))
877 return mp_irqs[i].dstirq;
882 static int __init find_isa_irq_apic(int irq, int type)
886 for (i = 0; i < mp_irq_entries; i++) {
887 int lbus = mp_irqs[i].srcbus;
889 if (test_bit(lbus, mp_bus_not_pci) &&
890 (mp_irqs[i].irqtype == type) &&
891 (mp_irqs[i].srcbusirq == irq))
894 if (i < mp_irq_entries) {
896 for(apic = 0; apic < nr_ioapics; apic++) {
897 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
906 * Find a specific PCI IRQ entry.
907 * Not an __init, possibly needed by modules
909 static int pin_2_irq(int idx, int apic, int pin);
911 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
913 int apic, i, best_guess = -1;
915 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
917 if (test_bit(bus, mp_bus_not_pci)) {
918 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
921 for (i = 0; i < mp_irq_entries; i++) {
922 int lbus = mp_irqs[i].srcbus;
924 for (apic = 0; apic < nr_ioapics; apic++)
925 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
926 mp_irqs[i].dstapic == MP_APIC_ALL)
929 if (!test_bit(lbus, mp_bus_not_pci) &&
930 !mp_irqs[i].irqtype &&
932 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
933 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
935 if (!(apic || IO_APIC_IRQ(irq)))
938 if (pin == (mp_irqs[i].srcbusirq & 3))
941 * Use the first all-but-pin matching entry as a
942 * best-guess fuzzy result for broken mptables.
951 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
953 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
955 * EISA Edge/Level control register, ELCR
957 static int EISA_ELCR(unsigned int irq)
959 if (irq < NR_IRQS_LEGACY) {
960 unsigned int port = 0x4d0 + (irq >> 3);
961 return (inb(port) >> (irq & 7)) & 1;
963 apic_printk(APIC_VERBOSE, KERN_INFO
964 "Broken MPtable reports ISA irq %d\n", irq);
970 /* ISA interrupts are always polarity zero edge triggered,
971 * when listed as conforming in the MP table. */
973 #define default_ISA_trigger(idx) (0)
974 #define default_ISA_polarity(idx) (0)
976 /* EISA interrupts are always polarity zero and can be edge or level
977 * trigger depending on the ELCR value. If an interrupt is listed as
978 * EISA conforming in the MP table, that means its trigger type must
979 * be read in from the ELCR */
981 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
982 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
984 /* PCI interrupts are always polarity one level triggered,
985 * when listed as conforming in the MP table. */
987 #define default_PCI_trigger(idx) (1)
988 #define default_PCI_polarity(idx) (1)
990 /* MCA interrupts are always polarity zero level triggered,
991 * when listed as conforming in the MP table. */
993 #define default_MCA_trigger(idx) (1)
994 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
996 static int MPBIOS_polarity(int idx)
998 int bus = mp_irqs[idx].srcbus;
1002 * Determine IRQ line polarity (high active or low active):
1004 switch (mp_irqs[idx].irqflag & 3)
1006 case 0: /* conforms, ie. bus-type dependent polarity */
1007 if (test_bit(bus, mp_bus_not_pci))
1008 polarity = default_ISA_polarity(idx);
1010 polarity = default_PCI_polarity(idx);
1012 case 1: /* high active */
1017 case 2: /* reserved */
1019 printk(KERN_WARNING "broken BIOS!!\n");
1023 case 3: /* low active */
1028 default: /* invalid */
1030 printk(KERN_WARNING "broken BIOS!!\n");
1038 static int MPBIOS_trigger(int idx)
1040 int bus = mp_irqs[idx].srcbus;
1044 * Determine IRQ trigger mode (edge or level sensitive):
1046 switch ((mp_irqs[idx].irqflag>>2) & 3)
1048 case 0: /* conforms, ie. bus-type dependent */
1049 if (test_bit(bus, mp_bus_not_pci))
1050 trigger = default_ISA_trigger(idx);
1052 trigger = default_PCI_trigger(idx);
1053 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1054 switch (mp_bus_id_to_type[bus]) {
1055 case MP_BUS_ISA: /* ISA pin */
1057 /* set before the switch */
1060 case MP_BUS_EISA: /* EISA pin */
1062 trigger = default_EISA_trigger(idx);
1065 case MP_BUS_PCI: /* PCI pin */
1067 /* set before the switch */
1070 case MP_BUS_MCA: /* MCA pin */
1072 trigger = default_MCA_trigger(idx);
1077 printk(KERN_WARNING "broken BIOS!!\n");
1089 case 2: /* reserved */
1091 printk(KERN_WARNING "broken BIOS!!\n");
1100 default: /* invalid */
1102 printk(KERN_WARNING "broken BIOS!!\n");
1110 static inline int irq_polarity(int idx)
1112 return MPBIOS_polarity(idx);
1115 static inline int irq_trigger(int idx)
1117 return MPBIOS_trigger(idx);
1120 int (*ioapic_renumber_irq)(int ioapic, int irq);
1121 static int pin_2_irq(int idx, int apic, int pin)
1124 int bus = mp_irqs[idx].srcbus;
1127 * Debugging check, we are in big trouble if this message pops up!
1129 if (mp_irqs[idx].dstirq != pin)
1130 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1132 if (test_bit(bus, mp_bus_not_pci)) {
1133 irq = mp_irqs[idx].srcbusirq;
1136 * PCI IRQs are mapped in order
1140 irq += nr_ioapic_registers[i++];
1143 * For MPS mode, so far only needed by ES7000 platform
1145 if (ioapic_renumber_irq)
1146 irq = ioapic_renumber_irq(apic, irq);
1149 #ifdef CONFIG_X86_32
1151 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1153 if ((pin >= 16) && (pin <= 23)) {
1154 if (pirq_entries[pin-16] != -1) {
1155 if (!pirq_entries[pin-16]) {
1156 apic_printk(APIC_VERBOSE, KERN_DEBUG
1157 "disabling PIRQ%d\n", pin-16);
1159 irq = pirq_entries[pin-16];
1160 apic_printk(APIC_VERBOSE, KERN_DEBUG
1161 "using PIRQ%d -> IRQ %d\n",
1171 void lock_vector_lock(void)
1173 /* Used to the online set of cpus does not change
1174 * during assign_irq_vector.
1176 spin_lock(&vector_lock);
1179 void unlock_vector_lock(void)
1181 spin_unlock(&vector_lock);
1185 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1188 * NOTE! The local APIC isn't very good at handling
1189 * multiple interrupts at the same interrupt level.
1190 * As the interrupt level is determined by taking the
1191 * vector number and shifting that right by 4, we
1192 * want to spread these out a bit so that they don't
1193 * all fall in the same interrupt level.
1195 * Also, we've got to be careful not to trash gate
1196 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1198 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1199 unsigned int old_vector;
1201 cpumask_var_t tmp_mask;
1203 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1206 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1209 old_vector = cfg->vector;
1211 cpumask_and(tmp_mask, mask, cpu_online_mask);
1212 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1213 if (!cpumask_empty(tmp_mask)) {
1214 free_cpumask_var(tmp_mask);
1219 /* Only try and allocate irqs on cpus that are present */
1221 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1225 apic->vector_allocation_domain(cpu, tmp_mask);
1227 vector = current_vector;
1228 offset = current_offset;
1231 if (vector >= first_system_vector) {
1232 /* If out of vectors on large boxen, must share them. */
1233 offset = (offset + 1) % 8;
1234 vector = FIRST_DEVICE_VECTOR + offset;
1236 if (unlikely(current_vector == vector))
1239 if (test_bit(vector, used_vectors))
1242 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1243 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1246 current_vector = vector;
1247 current_offset = offset;
1249 cfg->move_in_progress = 1;
1250 cpumask_copy(cfg->old_domain, cfg->domain);
1252 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1253 per_cpu(vector_irq, new_cpu)[vector] = irq;
1254 cfg->vector = vector;
1255 cpumask_copy(cfg->domain, tmp_mask);
1259 free_cpumask_var(tmp_mask);
1264 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1267 unsigned long flags;
1269 spin_lock_irqsave(&vector_lock, flags);
1270 err = __assign_irq_vector(irq, cfg, mask);
1271 spin_unlock_irqrestore(&vector_lock, flags);
1275 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1279 BUG_ON(!cfg->vector);
1281 vector = cfg->vector;
1282 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1283 per_cpu(vector_irq, cpu)[vector] = -1;
1286 cpumask_clear(cfg->domain);
1288 if (likely(!cfg->move_in_progress))
1290 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1291 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1293 if (per_cpu(vector_irq, cpu)[vector] != irq)
1295 per_cpu(vector_irq, cpu)[vector] = -1;
1299 cfg->move_in_progress = 0;
1302 void __setup_vector_irq(int cpu)
1304 /* Initialize vector_irq on a new cpu */
1305 /* This function must be called with vector_lock held */
1307 struct irq_cfg *cfg;
1308 struct irq_desc *desc;
1310 /* Mark the inuse vectors */
1311 for_each_irq_desc(irq, desc) {
1312 cfg = desc->chip_data;
1313 if (!cpumask_test_cpu(cpu, cfg->domain))
1315 vector = cfg->vector;
1316 per_cpu(vector_irq, cpu)[vector] = irq;
1318 /* Mark the free vectors */
1319 for (vector = 0; vector < NR_VECTORS; ++vector) {
1320 irq = per_cpu(vector_irq, cpu)[vector];
1325 if (!cpumask_test_cpu(cpu, cfg->domain))
1326 per_cpu(vector_irq, cpu)[vector] = -1;
1330 static struct irq_chip ioapic_chip;
1331 static struct irq_chip ir_ioapic_chip;
1333 #define IOAPIC_AUTO -1
1334 #define IOAPIC_EDGE 0
1335 #define IOAPIC_LEVEL 1
1337 #ifdef CONFIG_X86_32
1338 static inline int IO_APIC_irq_trigger(int irq)
1342 for (apic = 0; apic < nr_ioapics; apic++) {
1343 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1344 idx = find_irq_entry(apic, pin, mp_INT);
1345 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1346 return irq_trigger(idx);
1350 * nonexistent IRQs are edge default
1355 static inline int IO_APIC_irq_trigger(int irq)
1361 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1364 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1365 trigger == IOAPIC_LEVEL)
1366 desc->status |= IRQ_LEVEL;
1368 desc->status &= ~IRQ_LEVEL;
1370 if (irq_remapped(irq)) {
1371 desc->status |= IRQ_MOVE_PCNTXT;
1373 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1377 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1378 handle_edge_irq, "edge");
1382 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1383 trigger == IOAPIC_LEVEL)
1384 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1388 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1389 handle_edge_irq, "edge");
1392 int setup_ioapic_entry(int apic_id, int irq,
1393 struct IO_APIC_route_entry *entry,
1394 unsigned int destination, int trigger,
1395 int polarity, int vector, int pin)
1398 * add it to the IO-APIC irq-routing table:
1400 memset(entry,0,sizeof(*entry));
1402 if (intr_remapping_enabled) {
1403 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1405 struct IR_IO_APIC_route_entry *ir_entry =
1406 (struct IR_IO_APIC_route_entry *) entry;
1410 panic("No mapping iommu for ioapic %d\n", apic_id);
1412 index = alloc_irte(iommu, irq, 1);
1414 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1416 memset(&irte, 0, sizeof(irte));
1419 irte.dst_mode = apic->irq_dest_mode;
1421 * Trigger mode in the IRTE will always be edge, and the
1422 * actual level or edge trigger will be setup in the IO-APIC
1423 * RTE. This will help simplify level triggered irq migration.
1424 * For more details, see the comments above explainig IO-APIC
1425 * irq migration in the presence of interrupt-remapping.
1427 irte.trigger_mode = 0;
1428 irte.dlvry_mode = apic->irq_delivery_mode;
1429 irte.vector = vector;
1430 irte.dest_id = IRTE_DEST(destination);
1432 modify_irte(irq, &irte);
1434 ir_entry->index2 = (index >> 15) & 0x1;
1436 ir_entry->format = 1;
1437 ir_entry->index = (index & 0x7fff);
1439 * IO-APIC RTE will be configured with virtual vector.
1440 * irq handler will do the explicit EOI to the io-apic.
1442 ir_entry->vector = pin;
1444 entry->delivery_mode = apic->irq_delivery_mode;
1445 entry->dest_mode = apic->irq_dest_mode;
1446 entry->dest = destination;
1447 entry->vector = vector;
1450 entry->mask = 0; /* enable IRQ */
1451 entry->trigger = trigger;
1452 entry->polarity = polarity;
1454 /* Mask level triggered irqs.
1455 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1462 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1463 int trigger, int polarity)
1465 struct irq_cfg *cfg;
1466 struct IO_APIC_route_entry entry;
1469 if (!IO_APIC_IRQ(irq))
1472 cfg = desc->chip_data;
1474 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1477 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1479 apic_printk(APIC_VERBOSE,KERN_DEBUG
1480 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1481 "IRQ %d Mode:%i Active:%i)\n",
1482 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1483 irq, trigger, polarity);
1486 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1487 dest, trigger, polarity, cfg->vector, pin)) {
1488 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1489 mp_ioapics[apic_id].apicid, pin);
1490 __clear_irq_vector(irq, cfg);
1494 ioapic_register_intr(irq, desc, trigger);
1495 if (irq < NR_IRQS_LEGACY)
1496 disable_8259A_irq(irq);
1498 ioapic_write_entry(apic_id, pin, entry);
1501 static void __init setup_IO_APIC_irqs(void)
1503 int apic_id, pin, idx, irq;
1505 struct irq_desc *desc;
1506 struct irq_cfg *cfg;
1507 int cpu = boot_cpu_id;
1509 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1511 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1512 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1514 idx = find_irq_entry(apic_id, pin, mp_INT);
1518 apic_printk(APIC_VERBOSE,
1519 KERN_DEBUG " %d-%d",
1520 mp_ioapics[apic_id].apicid, pin);
1522 apic_printk(APIC_VERBOSE, " %d-%d",
1523 mp_ioapics[apic_id].apicid, pin);
1527 apic_printk(APIC_VERBOSE,
1528 " (apicid-pin) not connected\n");
1532 irq = pin_2_irq(idx, apic_id, pin);
1535 * Skip the timer IRQ if there's a quirk handler
1536 * installed and if it returns 1:
1538 if (apic->multi_timer_check &&
1539 apic->multi_timer_check(apic_id, irq))
1542 desc = irq_to_desc_alloc_cpu(irq, cpu);
1544 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1547 cfg = desc->chip_data;
1548 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1550 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1551 irq_trigger(idx), irq_polarity(idx));
1556 apic_printk(APIC_VERBOSE,
1557 " (apicid-pin) not connected\n");
1561 * Set up the timer pin, possibly with the 8259A-master behind.
1563 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1566 struct IO_APIC_route_entry entry;
1568 if (intr_remapping_enabled)
1571 memset(&entry, 0, sizeof(entry));
1574 * We use logical delivery to get the timer IRQ
1577 entry.dest_mode = apic->irq_dest_mode;
1578 entry.mask = 0; /* don't mask IRQ for edge */
1579 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1580 entry.delivery_mode = apic->irq_delivery_mode;
1583 entry.vector = vector;
1586 * The timer IRQ doesn't have to know that behind the
1587 * scene we may have a 8259A-master in AEOI mode ...
1589 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1592 * Add it to the IO-APIC irq-routing table:
1594 ioapic_write_entry(apic_id, pin, entry);
1598 __apicdebuginit(void) print_IO_APIC(void)
1601 union IO_APIC_reg_00 reg_00;
1602 union IO_APIC_reg_01 reg_01;
1603 union IO_APIC_reg_02 reg_02;
1604 union IO_APIC_reg_03 reg_03;
1605 unsigned long flags;
1606 struct irq_cfg *cfg;
1607 struct irq_desc *desc;
1610 if (apic_verbosity == APIC_QUIET)
1613 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1614 for (i = 0; i < nr_ioapics; i++)
1615 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1616 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1619 * We are a bit conservative about what we expect. We have to
1620 * know about every hardware change ASAP.
1622 printk(KERN_INFO "testing the IO APIC.......................\n");
1624 for (apic = 0; apic < nr_ioapics; apic++) {
1626 spin_lock_irqsave(&ioapic_lock, flags);
1627 reg_00.raw = io_apic_read(apic, 0);
1628 reg_01.raw = io_apic_read(apic, 1);
1629 if (reg_01.bits.version >= 0x10)
1630 reg_02.raw = io_apic_read(apic, 2);
1631 if (reg_01.bits.version >= 0x20)
1632 reg_03.raw = io_apic_read(apic, 3);
1633 spin_unlock_irqrestore(&ioapic_lock, flags);
1636 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1637 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1638 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1639 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1640 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1642 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1643 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1645 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1646 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1649 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1650 * but the value of reg_02 is read as the previous read register
1651 * value, so ignore it if reg_02 == reg_01.
1653 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1654 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1655 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1659 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1660 * or reg_03, but the value of reg_0[23] is read as the previous read
1661 * register value, so ignore it if reg_03 == reg_0[12].
1663 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1664 reg_03.raw != reg_01.raw) {
1665 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1666 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1669 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1671 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1672 " Stat Dmod Deli Vect: \n");
1674 for (i = 0; i <= reg_01.bits.entries; i++) {
1675 struct IO_APIC_route_entry entry;
1677 entry = ioapic_read_entry(apic, i);
1679 printk(KERN_DEBUG " %02x %03X ",
1684 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1689 entry.delivery_status,
1691 entry.delivery_mode,
1696 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1697 for_each_irq_desc(irq, desc) {
1698 struct irq_pin_list *entry;
1700 cfg = desc->chip_data;
1701 entry = cfg->irq_2_pin;
1704 printk(KERN_DEBUG "IRQ%d ", irq);
1706 printk("-> %d:%d", entry->apic, entry->pin);
1709 entry = entry->next;
1714 printk(KERN_INFO ".................................... done.\n");
1719 __apicdebuginit(void) print_APIC_bitfield(int base)
1724 if (apic_verbosity == APIC_QUIET)
1727 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1728 for (i = 0; i < 8; i++) {
1729 v = apic_read(base + i*0x10);
1730 for (j = 0; j < 32; j++) {
1740 __apicdebuginit(void) print_local_APIC(void *dummy)
1742 unsigned int i, v, ver, maxlvt;
1745 if (apic_verbosity == APIC_QUIET)
1748 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1749 smp_processor_id(), hard_smp_processor_id());
1750 v = apic_read(APIC_ID);
1751 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1752 v = apic_read(APIC_LVR);
1753 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1754 ver = GET_APIC_VERSION(v);
1755 maxlvt = lapic_get_maxlvt();
1757 v = apic_read(APIC_TASKPRI);
1758 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1760 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1761 if (!APIC_XAPIC(ver)) {
1762 v = apic_read(APIC_ARBPRI);
1763 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1764 v & APIC_ARBPRI_MASK);
1766 v = apic_read(APIC_PROCPRI);
1767 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1771 * Remote read supported only in the 82489DX and local APIC for
1772 * Pentium processors.
1774 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1775 v = apic_read(APIC_RRR);
1776 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1779 v = apic_read(APIC_LDR);
1780 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1781 if (!x2apic_enabled()) {
1782 v = apic_read(APIC_DFR);
1783 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1785 v = apic_read(APIC_SPIV);
1786 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1788 printk(KERN_DEBUG "... APIC ISR field:\n");
1789 print_APIC_bitfield(APIC_ISR);
1790 printk(KERN_DEBUG "... APIC TMR field:\n");
1791 print_APIC_bitfield(APIC_TMR);
1792 printk(KERN_DEBUG "... APIC IRR field:\n");
1793 print_APIC_bitfield(APIC_IRR);
1795 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1796 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1797 apic_write(APIC_ESR, 0);
1799 v = apic_read(APIC_ESR);
1800 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1803 icr = apic_icr_read();
1804 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1805 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1807 v = apic_read(APIC_LVTT);
1808 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1810 if (maxlvt > 3) { /* PC is LVT#4. */
1811 v = apic_read(APIC_LVTPC);
1812 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1814 v = apic_read(APIC_LVT0);
1815 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1816 v = apic_read(APIC_LVT1);
1817 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1819 if (maxlvt > 2) { /* ERR is LVT#3. */
1820 v = apic_read(APIC_LVTERR);
1821 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1824 v = apic_read(APIC_TMICT);
1825 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1826 v = apic_read(APIC_TMCCT);
1827 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1828 v = apic_read(APIC_TDCR);
1829 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1831 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1832 v = apic_read(APIC_EFEAT);
1833 maxlvt = (v >> 16) & 0xff;
1834 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1835 v = apic_read(APIC_ECTRL);
1836 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1837 for (i = 0; i < maxlvt; i++) {
1838 v = apic_read(APIC_EILVTn(i));
1839 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1845 __apicdebuginit(void) print_all_local_APICs(void)
1850 for_each_online_cpu(cpu)
1851 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1855 __apicdebuginit(void) print_PIC(void)
1858 unsigned long flags;
1860 if (apic_verbosity == APIC_QUIET)
1863 printk(KERN_DEBUG "\nprinting PIC contents\n");
1865 spin_lock_irqsave(&i8259A_lock, flags);
1867 v = inb(0xa1) << 8 | inb(0x21);
1868 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1870 v = inb(0xa0) << 8 | inb(0x20);
1871 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1875 v = inb(0xa0) << 8 | inb(0x20);
1879 spin_unlock_irqrestore(&i8259A_lock, flags);
1881 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1883 v = inb(0x4d1) << 8 | inb(0x4d0);
1884 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1887 __apicdebuginit(int) print_all_ICs(void)
1890 print_all_local_APICs();
1896 fs_initcall(print_all_ICs);
1899 /* Where if anywhere is the i8259 connect in external int mode */
1900 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1902 void __init enable_IO_APIC(void)
1904 union IO_APIC_reg_01 reg_01;
1905 int i8259_apic, i8259_pin;
1907 unsigned long flags;
1910 * The number of IO-APIC IRQ registers (== #pins):
1912 for (apic = 0; apic < nr_ioapics; apic++) {
1913 spin_lock_irqsave(&ioapic_lock, flags);
1914 reg_01.raw = io_apic_read(apic, 1);
1915 spin_unlock_irqrestore(&ioapic_lock, flags);
1916 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1918 for(apic = 0; apic < nr_ioapics; apic++) {
1920 /* See if any of the pins is in ExtINT mode */
1921 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1922 struct IO_APIC_route_entry entry;
1923 entry = ioapic_read_entry(apic, pin);
1925 /* If the interrupt line is enabled and in ExtInt mode
1926 * I have found the pin where the i8259 is connected.
1928 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1929 ioapic_i8259.apic = apic;
1930 ioapic_i8259.pin = pin;
1936 /* Look to see what if the MP table has reported the ExtINT */
1937 /* If we could not find the appropriate pin by looking at the ioapic
1938 * the i8259 probably is not connected the ioapic but give the
1939 * mptable a chance anyway.
1941 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1942 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1943 /* Trust the MP table if nothing is setup in the hardware */
1944 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1945 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1946 ioapic_i8259.pin = i8259_pin;
1947 ioapic_i8259.apic = i8259_apic;
1949 /* Complain if the MP table and the hardware disagree */
1950 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1951 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1953 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1957 * Do not trust the IO-APIC being empty at bootup
1963 * Not an __init, needed by the reboot code
1965 void disable_IO_APIC(void)
1968 * Clear the IO-APIC before rebooting:
1973 * If the i8259 is routed through an IOAPIC
1974 * Put that IOAPIC in virtual wire mode
1975 * so legacy interrupts can be delivered.
1977 * With interrupt-remapping, for now we will use virtual wire A mode,
1978 * as virtual wire B is little complex (need to configure both
1979 * IOAPIC RTE aswell as interrupt-remapping table entry).
1980 * As this gets called during crash dump, keep this simple for now.
1982 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1983 struct IO_APIC_route_entry entry;
1985 memset(&entry, 0, sizeof(entry));
1986 entry.mask = 0; /* Enabled */
1987 entry.trigger = 0; /* Edge */
1989 entry.polarity = 0; /* High */
1990 entry.delivery_status = 0;
1991 entry.dest_mode = 0; /* Physical */
1992 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1994 entry.dest = read_apic_id();
1997 * Add it to the IO-APIC irq-routing table:
1999 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2003 * Use virtual wire A mode when interrupt remapping is enabled.
2005 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2008 #ifdef CONFIG_X86_32
2010 * function to set the IO-APIC physical IDs based on the
2011 * values stored in the MPC table.
2013 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2016 static void __init setup_ioapic_ids_from_mpc(void)
2018 union IO_APIC_reg_00 reg_00;
2019 physid_mask_t phys_id_present_map;
2022 unsigned char old_id;
2023 unsigned long flags;
2025 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2029 * Don't check I/O APIC IDs for xAPIC systems. They have
2030 * no meaning without the serial APIC bus.
2032 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2033 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2036 * This is broken; anything with a real cpu count has to
2037 * circumvent this idiocy regardless.
2039 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2042 * Set the IOAPIC ID to the value stored in the MPC table.
2044 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2046 /* Read the register 0 value */
2047 spin_lock_irqsave(&ioapic_lock, flags);
2048 reg_00.raw = io_apic_read(apic_id, 0);
2049 spin_unlock_irqrestore(&ioapic_lock, flags);
2051 old_id = mp_ioapics[apic_id].apicid;
2053 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2054 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2055 apic_id, mp_ioapics[apic_id].apicid);
2056 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2058 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2062 * Sanity check, is the ID really free? Every APIC in a
2063 * system must have a unique ID or we get lots of nice
2064 * 'stuck on smp_invalidate_needed IPI wait' messages.
2066 if (apic->check_apicid_used(phys_id_present_map,
2067 mp_ioapics[apic_id].apicid)) {
2068 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2069 apic_id, mp_ioapics[apic_id].apicid);
2070 for (i = 0; i < get_physical_broadcast(); i++)
2071 if (!physid_isset(i, phys_id_present_map))
2073 if (i >= get_physical_broadcast())
2074 panic("Max APIC ID exceeded!\n");
2075 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2077 physid_set(i, phys_id_present_map);
2078 mp_ioapics[apic_id].apicid = i;
2081 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2082 apic_printk(APIC_VERBOSE, "Setting %d in the "
2083 "phys_id_present_map\n",
2084 mp_ioapics[apic_id].apicid);
2085 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2090 * We need to adjust the IRQ routing table
2091 * if the ID changed.
2093 if (old_id != mp_ioapics[apic_id].apicid)
2094 for (i = 0; i < mp_irq_entries; i++)
2095 if (mp_irqs[i].dstapic == old_id)
2097 = mp_ioapics[apic_id].apicid;
2100 * Read the right value from the MPC table and
2101 * write it into the ID register.
2103 apic_printk(APIC_VERBOSE, KERN_INFO
2104 "...changing IO-APIC physical APIC ID to %d ...",
2105 mp_ioapics[apic_id].apicid);
2107 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2108 spin_lock_irqsave(&ioapic_lock, flags);
2109 io_apic_write(apic_id, 0, reg_00.raw);
2110 spin_unlock_irqrestore(&ioapic_lock, flags);
2115 spin_lock_irqsave(&ioapic_lock, flags);
2116 reg_00.raw = io_apic_read(apic_id, 0);
2117 spin_unlock_irqrestore(&ioapic_lock, flags);
2118 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2119 printk("could not set ID!\n");
2121 apic_printk(APIC_VERBOSE, " ok.\n");
2126 int no_timer_check __initdata;
2128 static int __init notimercheck(char *s)
2133 __setup("no_timer_check", notimercheck);
2136 * There is a nasty bug in some older SMP boards, their mptable lies
2137 * about the timer IRQ. We do the following to work around the situation:
2139 * - timer IRQ defaults to IO-APIC IRQ
2140 * - if this function detects that timer IRQs are defunct, then we fall
2141 * back to ISA timer IRQs
2143 static int __init timer_irq_works(void)
2145 unsigned long t1 = jiffies;
2146 unsigned long flags;
2151 local_save_flags(flags);
2153 /* Let ten ticks pass... */
2154 mdelay((10 * 1000) / HZ);
2155 local_irq_restore(flags);
2158 * Expect a few ticks at least, to be sure some possible
2159 * glue logic does not lock up after one or two first
2160 * ticks in a non-ExtINT mode. Also the local APIC
2161 * might have cached one ExtINT interrupt. Finally, at
2162 * least one tick may be lost due to delays.
2166 if (time_after(jiffies, t1 + 4))
2172 * In the SMP+IOAPIC case it might happen that there are an unspecified
2173 * number of pending IRQ events unhandled. These cases are very rare,
2174 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2175 * better to do it this way as thus we do not have to be aware of
2176 * 'pending' interrupts in the IRQ path, except at this point.
2179 * Edge triggered needs to resend any interrupt
2180 * that was delayed but this is now handled in the device
2185 * Starting up a edge-triggered IO-APIC interrupt is
2186 * nasty - we need to make sure that we get the edge.
2187 * If it is already asserted for some reason, we need
2188 * return 1 to indicate that is was pending.
2190 * This is not complete - we should be able to fake
2191 * an edge even if it isn't on the 8259A...
2194 static unsigned int startup_ioapic_irq(unsigned int irq)
2196 int was_pending = 0;
2197 unsigned long flags;
2198 struct irq_cfg *cfg;
2200 spin_lock_irqsave(&ioapic_lock, flags);
2201 if (irq < NR_IRQS_LEGACY) {
2202 disable_8259A_irq(irq);
2203 if (i8259A_irq_pending(irq))
2207 __unmask_IO_APIC_irq(cfg);
2208 spin_unlock_irqrestore(&ioapic_lock, flags);
2213 #ifdef CONFIG_X86_64
2214 static int ioapic_retrigger_irq(unsigned int irq)
2217 struct irq_cfg *cfg = irq_cfg(irq);
2218 unsigned long flags;
2220 spin_lock_irqsave(&vector_lock, flags);
2221 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2222 spin_unlock_irqrestore(&vector_lock, flags);
2227 static int ioapic_retrigger_irq(unsigned int irq)
2229 apic->send_IPI_self(irq_cfg(irq)->vector);
2236 * Level and edge triggered IO-APIC interrupts need different handling,
2237 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2238 * handled with the level-triggered descriptor, but that one has slightly
2239 * more overhead. Level-triggered interrupts cannot be handled with the
2240 * edge-triggered handler, without risking IRQ storms and other ugly
2245 static void send_cleanup_vector(struct irq_cfg *cfg)
2247 cpumask_var_t cleanup_mask;
2249 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2251 cfg->move_cleanup_count = 0;
2252 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2253 cfg->move_cleanup_count++;
2254 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2255 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2257 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2258 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2259 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2260 free_cpumask_var(cleanup_mask);
2262 cfg->move_in_progress = 0;
2266 __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2269 struct irq_pin_list *entry;
2270 u8 vector = cfg->vector;
2272 entry = cfg->irq_2_pin;
2282 * With interrupt-remapping, destination information comes
2283 * from interrupt-remapping table entry.
2285 if (!irq_remapped(irq))
2286 io_apic_write(apic, 0x11 + pin*2, dest);
2287 reg = io_apic_read(apic, 0x10 + pin*2);
2288 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2290 io_apic_modify(apic, 0x10 + pin*2, reg);
2293 entry = entry->next;
2298 * Either sets desc->affinity to a valid value, and returns
2299 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2300 * leaves desc->affinity untouched.
2303 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2305 struct irq_cfg *cfg;
2308 if (!cpumask_intersects(mask, cpu_online_mask))
2312 cfg = desc->chip_data;
2313 if (assign_irq_vector(irq, cfg, mask))
2316 /* check that before desc->addinity get updated */
2317 set_extra_move_desc(desc, mask);
2319 cpumask_copy(desc->affinity, mask);
2321 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2325 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2327 struct irq_cfg *cfg;
2328 unsigned long flags;
2333 cfg = desc->chip_data;
2335 spin_lock_irqsave(&ioapic_lock, flags);
2336 dest = set_desc_affinity(desc, mask);
2337 if (dest != BAD_APICID) {
2338 /* Only the high 8 bits are valid. */
2339 dest = SET_APIC_LOGICAL_ID(dest);
2340 __target_IO_APIC_irq(irq, dest, cfg);
2342 spin_unlock_irqrestore(&ioapic_lock, flags);
2346 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2348 struct irq_desc *desc;
2350 desc = irq_to_desc(irq);
2352 set_ioapic_affinity_irq_desc(desc, mask);
2355 #ifdef CONFIG_INTR_REMAP
2358 * Migrate the IO-APIC irq in the presence of intr-remapping.
2360 * For both level and edge triggered, irq migration is a simple atomic
2361 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2363 * For level triggered, we eliminate the io-apic RTE modification (with the
2364 * updated vector information), by using a virtual vector (io-apic pin number).
2365 * Real vector that is used for interrupting cpu will be coming from
2366 * the interrupt-remapping table entry.
2369 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2371 struct irq_cfg *cfg;
2376 if (!cpumask_intersects(mask, cpu_online_mask))
2380 if (get_irte(irq, &irte))
2383 cfg = desc->chip_data;
2384 if (assign_irq_vector(irq, cfg, mask))
2387 set_extra_move_desc(desc, mask);
2389 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2391 irte.vector = cfg->vector;
2392 irte.dest_id = IRTE_DEST(dest);
2395 * Modified the IRTE and flushes the Interrupt entry cache.
2397 modify_irte(irq, &irte);
2399 if (cfg->move_in_progress)
2400 send_cleanup_vector(cfg);
2402 cpumask_copy(desc->affinity, mask);
2406 * Migrates the IRQ destination in the process context.
2408 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2409 const struct cpumask *mask)
2411 migrate_ioapic_irq_desc(desc, mask);
2413 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2414 const struct cpumask *mask)
2416 struct irq_desc *desc = irq_to_desc(irq);
2418 set_ir_ioapic_affinity_irq_desc(desc, mask);
2421 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2422 const struct cpumask *mask)
2427 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2429 unsigned vector, me;
2435 me = smp_processor_id();
2436 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2439 struct irq_desc *desc;
2440 struct irq_cfg *cfg;
2441 irq = __get_cpu_var(vector_irq)[vector];
2446 desc = irq_to_desc(irq);
2451 spin_lock(&desc->lock);
2452 if (!cfg->move_cleanup_count)
2455 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2458 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2460 * Check if the vector that needs to be cleanedup is
2461 * registered at the cpu's IRR. If so, then this is not
2462 * the best time to clean it up. Lets clean it up in the
2463 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2466 if (irr & (1 << (vector % 32))) {
2467 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2470 __get_cpu_var(vector_irq)[vector] = -1;
2471 cfg->move_cleanup_count--;
2473 spin_unlock(&desc->lock);
2479 static void irq_complete_move(struct irq_desc **descp)
2481 struct irq_desc *desc = *descp;
2482 struct irq_cfg *cfg = desc->chip_data;
2483 unsigned vector, me;
2485 if (likely(!cfg->move_in_progress)) {
2486 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2487 if (likely(!cfg->move_desc_pending))
2490 /* domain has not changed, but affinity did */
2491 me = smp_processor_id();
2492 if (cpumask_test_cpu(me, desc->affinity)) {
2493 *descp = desc = move_irq_desc(desc, me);
2494 /* get the new one */
2495 cfg = desc->chip_data;
2496 cfg->move_desc_pending = 0;
2502 vector = ~get_irq_regs()->orig_ax;
2503 me = smp_processor_id();
2505 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2506 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2507 *descp = desc = move_irq_desc(desc, me);
2508 /* get the new one */
2509 cfg = desc->chip_data;
2511 send_cleanup_vector(cfg);
2515 static inline void irq_complete_move(struct irq_desc **descp) {}
2518 static void ack_apic_edge(unsigned int irq)
2520 struct irq_desc *desc = irq_to_desc(irq);
2522 irq_complete_move(&desc);
2523 move_native_irq(irq);
2527 atomic_t irq_mis_count;
2529 static void ack_apic_level(unsigned int irq)
2531 struct irq_desc *desc = irq_to_desc(irq);
2533 #ifdef CONFIG_X86_32
2537 struct irq_cfg *cfg;
2538 int do_unmask_irq = 0;
2540 irq_complete_move(&desc);
2541 #ifdef CONFIG_GENERIC_PENDING_IRQ
2542 /* If we are moving the irq we need to mask it */
2543 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2545 mask_IO_APIC_irq_desc(desc);
2549 #ifdef CONFIG_X86_32
2551 * It appears there is an erratum which affects at least version 0x11
2552 * of I/O APIC (that's the 82093AA and cores integrated into various
2553 * chipsets). Under certain conditions a level-triggered interrupt is
2554 * erroneously delivered as edge-triggered one but the respective IRR
2555 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2556 * message but it will never arrive and further interrupts are blocked
2557 * from the source. The exact reason is so far unknown, but the
2558 * phenomenon was observed when two consecutive interrupt requests
2559 * from a given source get delivered to the same CPU and the source is
2560 * temporarily disabled in between.
2562 * A workaround is to simulate an EOI message manually. We achieve it
2563 * by setting the trigger mode to edge and then to level when the edge
2564 * trigger mode gets detected in the TMR of a local APIC for a
2565 * level-triggered interrupt. We mask the source for the time of the
2566 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2567 * The idea is from Manfred Spraul. --macro
2569 cfg = desc->chip_data;
2572 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2576 * We must acknowledge the irq before we move it or the acknowledge will
2577 * not propagate properly.
2581 /* Now we can move and renable the irq */
2582 if (unlikely(do_unmask_irq)) {
2583 /* Only migrate the irq if the ack has been received.
2585 * On rare occasions the broadcast level triggered ack gets
2586 * delayed going to ioapics, and if we reprogram the
2587 * vector while Remote IRR is still set the irq will never
2590 * To prevent this scenario we read the Remote IRR bit
2591 * of the ioapic. This has two effects.
2592 * - On any sane system the read of the ioapic will
2593 * flush writes (and acks) going to the ioapic from
2595 * - We get to see if the ACK has actually been delivered.
2597 * Based on failed experiments of reprogramming the
2598 * ioapic entry from outside of irq context starting
2599 * with masking the ioapic entry and then polling until
2600 * Remote IRR was clear before reprogramming the
2601 * ioapic I don't trust the Remote IRR bit to be
2602 * completey accurate.
2604 * However there appears to be no other way to plug
2605 * this race, so if the Remote IRR bit is not
2606 * accurate and is causing problems then it is a hardware bug
2607 * and you can go talk to the chipset vendor about it.
2609 cfg = desc->chip_data;
2610 if (!io_apic_level_ack_pending(cfg))
2611 move_masked_irq(irq);
2612 unmask_IO_APIC_irq_desc(desc);
2615 #ifdef CONFIG_X86_32
2616 if (!(v & (1 << (i & 0x1f)))) {
2617 atomic_inc(&irq_mis_count);
2618 spin_lock(&ioapic_lock);
2619 __mask_and_edge_IO_APIC_irq(cfg);
2620 __unmask_and_level_IO_APIC_irq(cfg);
2621 spin_unlock(&ioapic_lock);
2626 #ifdef CONFIG_INTR_REMAP
2627 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2630 struct irq_pin_list *entry;
2632 entry = cfg->irq_2_pin;
2640 io_apic_eoi(apic, pin);
2641 entry = entry->next;
2646 eoi_ioapic_irq(struct irq_desc *desc)
2648 struct irq_cfg *cfg;
2649 unsigned long flags;
2653 cfg = desc->chip_data;
2655 spin_lock_irqsave(&ioapic_lock, flags);
2656 __eoi_ioapic_irq(irq, cfg);
2657 spin_unlock_irqrestore(&ioapic_lock, flags);
2660 static void ir_ack_apic_edge(unsigned int irq)
2665 static void ir_ack_apic_level(unsigned int irq)
2667 struct irq_desc *desc = irq_to_desc(irq);
2670 eoi_ioapic_irq(desc);
2672 #endif /* CONFIG_INTR_REMAP */
2674 static struct irq_chip ioapic_chip __read_mostly = {
2676 .startup = startup_ioapic_irq,
2677 .mask = mask_IO_APIC_irq,
2678 .unmask = unmask_IO_APIC_irq,
2679 .ack = ack_apic_edge,
2680 .eoi = ack_apic_level,
2682 .set_affinity = set_ioapic_affinity_irq,
2684 .retrigger = ioapic_retrigger_irq,
2687 static struct irq_chip ir_ioapic_chip __read_mostly = {
2688 .name = "IR-IO-APIC",
2689 .startup = startup_ioapic_irq,
2690 .mask = mask_IO_APIC_irq,
2691 .unmask = unmask_IO_APIC_irq,
2692 #ifdef CONFIG_INTR_REMAP
2693 .ack = ir_ack_apic_edge,
2694 .eoi = ir_ack_apic_level,
2696 .set_affinity = set_ir_ioapic_affinity_irq,
2699 .retrigger = ioapic_retrigger_irq,
2702 static inline void init_IO_APIC_traps(void)
2705 struct irq_desc *desc;
2706 struct irq_cfg *cfg;
2709 * NOTE! The local APIC isn't very good at handling
2710 * multiple interrupts at the same interrupt level.
2711 * As the interrupt level is determined by taking the
2712 * vector number and shifting that right by 4, we
2713 * want to spread these out a bit so that they don't
2714 * all fall in the same interrupt level.
2716 * Also, we've got to be careful not to trash gate
2717 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2719 for_each_irq_desc(irq, desc) {
2720 cfg = desc->chip_data;
2721 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2723 * Hmm.. We don't have an entry for this,
2724 * so default to an old-fashioned 8259
2725 * interrupt if we can..
2727 if (irq < NR_IRQS_LEGACY)
2728 make_8259A_irq(irq);
2730 /* Strange. Oh, well.. */
2731 desc->chip = &no_irq_chip;
2737 * The local APIC irq-chip implementation:
2740 static void mask_lapic_irq(unsigned int irq)
2744 v = apic_read(APIC_LVT0);
2745 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2748 static void unmask_lapic_irq(unsigned int irq)
2752 v = apic_read(APIC_LVT0);
2753 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2756 static void ack_lapic_irq(unsigned int irq)
2761 static struct irq_chip lapic_chip __read_mostly = {
2762 .name = "local-APIC",
2763 .mask = mask_lapic_irq,
2764 .unmask = unmask_lapic_irq,
2765 .ack = ack_lapic_irq,
2768 static void lapic_register_intr(int irq, struct irq_desc *desc)
2770 desc->status &= ~IRQ_LEVEL;
2771 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2775 static void __init setup_nmi(void)
2778 * Dirty trick to enable the NMI watchdog ...
2779 * We put the 8259A master into AEOI mode and
2780 * unmask on all local APICs LVT0 as NMI.
2782 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2783 * is from Maciej W. Rozycki - so we do not have to EOI from
2784 * the NMI handler or the timer interrupt.
2786 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2788 enable_NMI_through_LVT0();
2790 apic_printk(APIC_VERBOSE, " done.\n");
2794 * This looks a bit hackish but it's about the only one way of sending
2795 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2796 * not support the ExtINT mode, unfortunately. We need to send these
2797 * cycles as some i82489DX-based boards have glue logic that keeps the
2798 * 8259A interrupt line asserted until INTA. --macro
2800 static inline void __init unlock_ExtINT_logic(void)
2803 struct IO_APIC_route_entry entry0, entry1;
2804 unsigned char save_control, save_freq_select;
2806 pin = find_isa_irq_pin(8, mp_INT);
2811 apic = find_isa_irq_apic(8, mp_INT);
2817 entry0 = ioapic_read_entry(apic, pin);
2818 clear_IO_APIC_pin(apic, pin);
2820 memset(&entry1, 0, sizeof(entry1));
2822 entry1.dest_mode = 0; /* physical delivery */
2823 entry1.mask = 0; /* unmask IRQ now */
2824 entry1.dest = hard_smp_processor_id();
2825 entry1.delivery_mode = dest_ExtINT;
2826 entry1.polarity = entry0.polarity;
2830 ioapic_write_entry(apic, pin, entry1);
2832 save_control = CMOS_READ(RTC_CONTROL);
2833 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2834 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2836 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2841 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2845 CMOS_WRITE(save_control, RTC_CONTROL);
2846 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2847 clear_IO_APIC_pin(apic, pin);
2849 ioapic_write_entry(apic, pin, entry0);
2852 static int disable_timer_pin_1 __initdata;
2853 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2854 static int __init disable_timer_pin_setup(char *arg)
2856 disable_timer_pin_1 = 1;
2859 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2861 int timer_through_8259 __initdata;
2864 * This code may look a bit paranoid, but it's supposed to cooperate with
2865 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2866 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2867 * fanatically on his truly buggy board.
2869 * FIXME: really need to revamp this for all platforms.
2871 static inline void __init check_timer(void)
2873 struct irq_desc *desc = irq_to_desc(0);
2874 struct irq_cfg *cfg = desc->chip_data;
2875 int cpu = boot_cpu_id;
2876 int apic1, pin1, apic2, pin2;
2877 unsigned long flags;
2880 local_irq_save(flags);
2883 * get/set the timer IRQ vector:
2885 disable_8259A_irq(0);
2886 assign_irq_vector(0, cfg, apic->target_cpus());
2889 * As IRQ0 is to be enabled in the 8259A, the virtual
2890 * wire has to be disabled in the local APIC. Also
2891 * timer interrupts need to be acknowledged manually in
2892 * the 8259A for the i82489DX when using the NMI
2893 * watchdog as that APIC treats NMIs as level-triggered.
2894 * The AEOI mode will finish them in the 8259A
2897 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2899 #ifdef CONFIG_X86_32
2903 ver = apic_read(APIC_LVR);
2904 ver = GET_APIC_VERSION(ver);
2905 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2909 pin1 = find_isa_irq_pin(0, mp_INT);
2910 apic1 = find_isa_irq_apic(0, mp_INT);
2911 pin2 = ioapic_i8259.pin;
2912 apic2 = ioapic_i8259.apic;
2914 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2915 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2916 cfg->vector, apic1, pin1, apic2, pin2);
2919 * Some BIOS writers are clueless and report the ExtINTA
2920 * I/O APIC input from the cascaded 8259A as the timer
2921 * interrupt input. So just in case, if only one pin
2922 * was found above, try it both directly and through the
2926 if (intr_remapping_enabled)
2927 panic("BIOS bug: timer not connected to IO-APIC");
2931 } else if (pin2 == -1) {
2938 * Ok, does IRQ0 through the IOAPIC work?
2941 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2942 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2944 /* for edge trigger, setup_IO_APIC_irq already
2945 * leave it unmasked.
2946 * so only need to unmask if it is level-trigger
2947 * do we really have level trigger timer?
2950 idx = find_irq_entry(apic1, pin1, mp_INT);
2951 if (idx != -1 && irq_trigger(idx))
2952 unmask_IO_APIC_irq_desc(desc);
2954 if (timer_irq_works()) {
2955 if (nmi_watchdog == NMI_IO_APIC) {
2957 enable_8259A_irq(0);
2959 if (disable_timer_pin_1 > 0)
2960 clear_IO_APIC_pin(0, pin1);
2963 if (intr_remapping_enabled)
2964 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2965 local_irq_disable();
2966 clear_IO_APIC_pin(apic1, pin1);
2968 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2969 "8254 timer not connected to IO-APIC\n");
2971 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2972 "(IRQ0) through the 8259A ...\n");
2973 apic_printk(APIC_QUIET, KERN_INFO
2974 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2976 * legacy devices should be connected to IO APIC #0
2978 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2979 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2980 enable_8259A_irq(0);
2981 if (timer_irq_works()) {
2982 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2983 timer_through_8259 = 1;
2984 if (nmi_watchdog == NMI_IO_APIC) {
2985 disable_8259A_irq(0);
2987 enable_8259A_irq(0);
2992 * Cleanup, just in case ...
2994 local_irq_disable();
2995 disable_8259A_irq(0);
2996 clear_IO_APIC_pin(apic2, pin2);
2997 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3000 if (nmi_watchdog == NMI_IO_APIC) {
3001 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3002 "through the IO-APIC - disabling NMI Watchdog!\n");
3003 nmi_watchdog = NMI_NONE;
3005 #ifdef CONFIG_X86_32
3009 apic_printk(APIC_QUIET, KERN_INFO
3010 "...trying to set up timer as Virtual Wire IRQ...\n");
3012 lapic_register_intr(0, desc);
3013 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3014 enable_8259A_irq(0);
3016 if (timer_irq_works()) {
3017 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3020 local_irq_disable();
3021 disable_8259A_irq(0);
3022 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3023 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3025 apic_printk(APIC_QUIET, KERN_INFO
3026 "...trying to set up timer as ExtINT IRQ...\n");
3030 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3032 unlock_ExtINT_logic();
3034 if (timer_irq_works()) {
3035 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3038 local_irq_disable();
3039 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3040 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3041 "report. Then try booting with the 'noapic' option.\n");
3043 local_irq_restore(flags);
3047 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3048 * to devices. However there may be an I/O APIC pin available for
3049 * this interrupt regardless. The pin may be left unconnected, but
3050 * typically it will be reused as an ExtINT cascade interrupt for
3051 * the master 8259A. In the MPS case such a pin will normally be
3052 * reported as an ExtINT interrupt in the MP table. With ACPI
3053 * there is no provision for ExtINT interrupts, and in the absence
3054 * of an override it would be treated as an ordinary ISA I/O APIC
3055 * interrupt, that is edge-triggered and unmasked by default. We
3056 * used to do this, but it caused problems on some systems because
3057 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3058 * the same ExtINT cascade interrupt to drive the local APIC of the
3059 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3060 * the I/O APIC in all cases now. No actual device should request
3061 * it anyway. --macro
3063 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3065 void __init setup_IO_APIC(void)
3069 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3072 io_apic_irqs = ~PIC_IRQS;
3074 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3076 * Set up IO-APIC IRQ routing.
3078 #ifdef CONFIG_X86_32
3080 setup_ioapic_ids_from_mpc();
3083 setup_IO_APIC_irqs();
3084 init_IO_APIC_traps();
3089 * Called after all the initialization is done. If we didnt find any
3090 * APIC bugs then we can allow the modify fast path
3093 static int __init io_apic_bug_finalize(void)
3095 if (sis_apic_bug == -1)
3100 late_initcall(io_apic_bug_finalize);
3102 struct sysfs_ioapic_data {
3103 struct sys_device dev;
3104 struct IO_APIC_route_entry entry[0];
3106 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3108 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3110 struct IO_APIC_route_entry *entry;
3111 struct sysfs_ioapic_data *data;
3114 data = container_of(dev, struct sysfs_ioapic_data, dev);
3115 entry = data->entry;
3116 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3117 *entry = ioapic_read_entry(dev->id, i);
3122 static int ioapic_resume(struct sys_device *dev)
3124 struct IO_APIC_route_entry *entry;
3125 struct sysfs_ioapic_data *data;
3126 unsigned long flags;
3127 union IO_APIC_reg_00 reg_00;
3130 data = container_of(dev, struct sysfs_ioapic_data, dev);
3131 entry = data->entry;
3133 spin_lock_irqsave(&ioapic_lock, flags);
3134 reg_00.raw = io_apic_read(dev->id, 0);
3135 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3136 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3137 io_apic_write(dev->id, 0, reg_00.raw);
3139 spin_unlock_irqrestore(&ioapic_lock, flags);
3140 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3141 ioapic_write_entry(dev->id, i, entry[i]);
3146 static struct sysdev_class ioapic_sysdev_class = {
3148 .suspend = ioapic_suspend,
3149 .resume = ioapic_resume,
3152 static int __init ioapic_init_sysfs(void)
3154 struct sys_device * dev;
3157 error = sysdev_class_register(&ioapic_sysdev_class);
3161 for (i = 0; i < nr_ioapics; i++ ) {
3162 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3163 * sizeof(struct IO_APIC_route_entry);
3164 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3165 if (!mp_ioapic_data[i]) {
3166 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3169 dev = &mp_ioapic_data[i]->dev;
3171 dev->cls = &ioapic_sysdev_class;
3172 error = sysdev_register(dev);
3174 kfree(mp_ioapic_data[i]);
3175 mp_ioapic_data[i] = NULL;
3176 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3184 device_initcall(ioapic_init_sysfs);
3186 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3188 * Dynamic irq allocate and deallocation
3190 unsigned int create_irq_nr(unsigned int irq_want)
3192 /* Allocate an unused irq */
3195 unsigned long flags;
3196 struct irq_cfg *cfg_new = NULL;
3197 int cpu = boot_cpu_id;
3198 struct irq_desc *desc_new = NULL;
3201 if (irq_want < nr_irqs_gsi)
3202 irq_want = nr_irqs_gsi;
3204 spin_lock_irqsave(&vector_lock, flags);
3205 for (new = irq_want; new < nr_irqs; new++) {
3206 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3208 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3211 cfg_new = desc_new->chip_data;
3213 if (cfg_new->vector != 0)
3215 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3219 spin_unlock_irqrestore(&vector_lock, flags);
3222 dynamic_irq_init(irq);
3223 /* restore it, in case dynamic_irq_init clear it */
3225 desc_new->chip_data = cfg_new;
3230 int create_irq(void)
3232 unsigned int irq_want;
3235 irq_want = nr_irqs_gsi;
3236 irq = create_irq_nr(irq_want);
3244 void destroy_irq(unsigned int irq)
3246 unsigned long flags;
3247 struct irq_cfg *cfg;
3248 struct irq_desc *desc;
3250 /* store it, in case dynamic_irq_cleanup clear it */
3251 desc = irq_to_desc(irq);
3252 cfg = desc->chip_data;
3253 dynamic_irq_cleanup(irq);
3254 /* connect back irq_cfg */
3256 desc->chip_data = cfg;
3259 spin_lock_irqsave(&vector_lock, flags);
3260 __clear_irq_vector(irq, cfg);
3261 spin_unlock_irqrestore(&vector_lock, flags);
3265 * MSI message composition
3267 #ifdef CONFIG_PCI_MSI
3268 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3270 struct irq_cfg *cfg;
3278 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3282 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3284 if (irq_remapped(irq)) {
3289 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3290 BUG_ON(ir_index == -1);
3292 memset (&irte, 0, sizeof(irte));
3295 irte.dst_mode = apic->irq_dest_mode;
3296 irte.trigger_mode = 0; /* edge */
3297 irte.dlvry_mode = apic->irq_delivery_mode;
3298 irte.vector = cfg->vector;
3299 irte.dest_id = IRTE_DEST(dest);
3301 modify_irte(irq, &irte);
3303 msg->address_hi = MSI_ADDR_BASE_HI;
3304 msg->data = sub_handle;
3305 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3307 MSI_ADDR_IR_INDEX1(ir_index) |
3308 MSI_ADDR_IR_INDEX2(ir_index);
3310 if (x2apic_enabled())
3311 msg->address_hi = MSI_ADDR_BASE_HI |
3312 MSI_ADDR_EXT_DEST_ID(dest);
3314 msg->address_hi = MSI_ADDR_BASE_HI;
3318 ((apic->irq_dest_mode == 0) ?
3319 MSI_ADDR_DEST_MODE_PHYSICAL:
3320 MSI_ADDR_DEST_MODE_LOGICAL) |
3321 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3322 MSI_ADDR_REDIRECTION_CPU:
3323 MSI_ADDR_REDIRECTION_LOWPRI) |
3324 MSI_ADDR_DEST_ID(dest);
3327 MSI_DATA_TRIGGER_EDGE |
3328 MSI_DATA_LEVEL_ASSERT |
3329 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3330 MSI_DATA_DELIVERY_FIXED:
3331 MSI_DATA_DELIVERY_LOWPRI) |
3332 MSI_DATA_VECTOR(cfg->vector);
3338 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3340 struct irq_desc *desc = irq_to_desc(irq);
3341 struct irq_cfg *cfg;
3345 dest = set_desc_affinity(desc, mask);
3346 if (dest == BAD_APICID)
3349 cfg = desc->chip_data;
3351 read_msi_msg_desc(desc, &msg);
3353 msg.data &= ~MSI_DATA_VECTOR_MASK;
3354 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3355 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3356 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3358 write_msi_msg_desc(desc, &msg);
3360 #ifdef CONFIG_INTR_REMAP
3362 * Migrate the MSI irq to another cpumask. This migration is
3363 * done in the process context using interrupt-remapping hardware.
3366 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3368 struct irq_desc *desc = irq_to_desc(irq);
3369 struct irq_cfg *cfg = desc->chip_data;
3373 if (get_irte(irq, &irte))
3376 dest = set_desc_affinity(desc, mask);
3377 if (dest == BAD_APICID)
3380 irte.vector = cfg->vector;
3381 irte.dest_id = IRTE_DEST(dest);
3384 * atomically update the IRTE with the new destination and vector.
3386 modify_irte(irq, &irte);
3389 * After this point, all the interrupts will start arriving
3390 * at the new destination. So, time to cleanup the previous
3391 * vector allocation.
3393 if (cfg->move_in_progress)
3394 send_cleanup_vector(cfg);
3398 #endif /* CONFIG_SMP */
3401 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3402 * which implement the MSI or MSI-X Capability Structure.
3404 static struct irq_chip msi_chip = {
3406 .unmask = unmask_msi_irq,
3407 .mask = mask_msi_irq,
3408 .ack = ack_apic_edge,
3410 .set_affinity = set_msi_irq_affinity,
3412 .retrigger = ioapic_retrigger_irq,
3415 static struct irq_chip msi_ir_chip = {
3416 .name = "IR-PCI-MSI",
3417 .unmask = unmask_msi_irq,
3418 .mask = mask_msi_irq,
3419 #ifdef CONFIG_INTR_REMAP
3420 .ack = ir_ack_apic_edge,
3422 .set_affinity = ir_set_msi_irq_affinity,
3425 .retrigger = ioapic_retrigger_irq,
3429 * Map the PCI dev to the corresponding remapping hardware unit
3430 * and allocate 'nvec' consecutive interrupt-remapping table entries
3433 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3435 struct intel_iommu *iommu;
3438 iommu = map_dev_to_ir(dev);
3441 "Unable to map PCI %s to iommu\n", pci_name(dev));
3445 index = alloc_irte(iommu, irq, nvec);
3448 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3455 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3460 ret = msi_compose_msg(dev, irq, &msg);
3464 set_irq_msi(irq, msidesc);
3465 write_msi_msg(irq, &msg);
3467 if (irq_remapped(irq)) {
3468 struct irq_desc *desc = irq_to_desc(irq);
3470 * irq migration in process context
3472 desc->status |= IRQ_MOVE_PCNTXT;
3473 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3475 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3477 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3482 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3485 int ret, sub_handle;
3486 struct msi_desc *msidesc;
3487 unsigned int irq_want;
3488 struct intel_iommu *iommu = NULL;
3491 /* x86 doesn't support multiple MSI yet */
3492 if (type == PCI_CAP_ID_MSI && nvec > 1)
3495 irq_want = nr_irqs_gsi;
3497 list_for_each_entry(msidesc, &dev->msi_list, list) {
3498 irq = create_irq_nr(irq_want);
3502 if (!intr_remapping_enabled)
3507 * allocate the consecutive block of IRTE's
3510 index = msi_alloc_irte(dev, irq, nvec);
3516 iommu = map_dev_to_ir(dev);
3522 * setup the mapping between the irq and the IRTE
3523 * base index, the sub_handle pointing to the
3524 * appropriate interrupt remap table entry.
3526 set_irte_irq(irq, iommu, index, sub_handle);
3529 ret = setup_msi_irq(dev, msidesc, irq);
3541 void arch_teardown_msi_irq(unsigned int irq)
3546 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3548 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3550 struct irq_desc *desc = irq_to_desc(irq);
3551 struct irq_cfg *cfg;
3555 dest = set_desc_affinity(desc, mask);
3556 if (dest == BAD_APICID)
3559 cfg = desc->chip_data;
3561 dmar_msi_read(irq, &msg);
3563 msg.data &= ~MSI_DATA_VECTOR_MASK;
3564 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3565 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3566 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3568 dmar_msi_write(irq, &msg);
3571 #endif /* CONFIG_SMP */
3573 struct irq_chip dmar_msi_type = {
3575 .unmask = dmar_msi_unmask,
3576 .mask = dmar_msi_mask,
3577 .ack = ack_apic_edge,
3579 .set_affinity = dmar_msi_set_affinity,
3581 .retrigger = ioapic_retrigger_irq,
3584 int arch_setup_dmar_msi(unsigned int irq)
3589 ret = msi_compose_msg(NULL, irq, &msg);
3592 dmar_msi_write(irq, &msg);
3593 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3599 #ifdef CONFIG_HPET_TIMER
3602 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3604 struct irq_desc *desc = irq_to_desc(irq);
3605 struct irq_cfg *cfg;
3609 dest = set_desc_affinity(desc, mask);
3610 if (dest == BAD_APICID)
3613 cfg = desc->chip_data;
3615 hpet_msi_read(irq, &msg);
3617 msg.data &= ~MSI_DATA_VECTOR_MASK;
3618 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3619 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3620 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3622 hpet_msi_write(irq, &msg);
3625 #endif /* CONFIG_SMP */
3627 static struct irq_chip hpet_msi_type = {
3629 .unmask = hpet_msi_unmask,
3630 .mask = hpet_msi_mask,
3631 .ack = ack_apic_edge,
3633 .set_affinity = hpet_msi_set_affinity,
3635 .retrigger = ioapic_retrigger_irq,
3638 int arch_setup_hpet_msi(unsigned int irq)
3642 struct irq_desc *desc = irq_to_desc(irq);
3644 ret = msi_compose_msg(NULL, irq, &msg);
3648 hpet_msi_write(irq, &msg);
3649 desc->status |= IRQ_MOVE_PCNTXT;
3650 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3657 #endif /* CONFIG_PCI_MSI */
3659 * Hypertransport interrupt support
3661 #ifdef CONFIG_HT_IRQ
3665 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3667 struct ht_irq_msg msg;
3668 fetch_ht_irq_msg(irq, &msg);
3670 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3671 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3673 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3674 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3676 write_ht_irq_msg(irq, &msg);
3679 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3681 struct irq_desc *desc = irq_to_desc(irq);
3682 struct irq_cfg *cfg;
3685 dest = set_desc_affinity(desc, mask);
3686 if (dest == BAD_APICID)
3689 cfg = desc->chip_data;
3691 target_ht_irq(irq, dest, cfg->vector);
3696 static struct irq_chip ht_irq_chip = {
3698 .mask = mask_ht_irq,
3699 .unmask = unmask_ht_irq,
3700 .ack = ack_apic_edge,
3702 .set_affinity = set_ht_irq_affinity,
3704 .retrigger = ioapic_retrigger_irq,
3707 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3709 struct irq_cfg *cfg;
3716 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3718 struct ht_irq_msg msg;
3721 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3722 apic->target_cpus());
3724 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3728 HT_IRQ_LOW_DEST_ID(dest) |
3729 HT_IRQ_LOW_VECTOR(cfg->vector) |
3730 ((apic->irq_dest_mode == 0) ?
3731 HT_IRQ_LOW_DM_PHYSICAL :
3732 HT_IRQ_LOW_DM_LOGICAL) |
3733 HT_IRQ_LOW_RQEOI_EDGE |
3734 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3735 HT_IRQ_LOW_MT_FIXED :
3736 HT_IRQ_LOW_MT_ARBITRATED) |
3737 HT_IRQ_LOW_IRQ_MASKED;
3739 write_ht_irq_msg(irq, &msg);
3741 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3742 handle_edge_irq, "edge");
3744 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3748 #endif /* CONFIG_HT_IRQ */
3750 #ifdef CONFIG_X86_UV
3752 * Re-target the irq to the specified CPU and enable the specified MMR located
3753 * on the specified blade to allow the sending of MSIs to the specified CPU.
3755 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3756 unsigned long mmr_offset)
3758 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3759 struct irq_cfg *cfg;
3761 unsigned long mmr_value;
3762 struct uv_IO_APIC_route_entry *entry;
3763 unsigned long flags;
3766 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3770 err = assign_irq_vector(irq, cfg, eligible_cpu);
3774 spin_lock_irqsave(&vector_lock, flags);
3775 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3777 spin_unlock_irqrestore(&vector_lock, flags);
3780 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3781 entry->vector = cfg->vector;
3782 entry->delivery_mode = apic->irq_delivery_mode;
3783 entry->dest_mode = apic->irq_dest_mode;
3784 entry->polarity = 0;
3787 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3789 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3790 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3796 * Disable the specified MMR located on the specified blade so that MSIs are
3797 * longer allowed to be sent.
3799 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3801 unsigned long mmr_value;
3802 struct uv_IO_APIC_route_entry *entry;
3805 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3808 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3811 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3812 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3814 #endif /* CONFIG_X86_64 */
3816 int __init io_apic_get_redir_entries (int ioapic)
3818 union IO_APIC_reg_01 reg_01;
3819 unsigned long flags;
3821 spin_lock_irqsave(&ioapic_lock, flags);
3822 reg_01.raw = io_apic_read(ioapic, 1);
3823 spin_unlock_irqrestore(&ioapic_lock, flags);
3825 return reg_01.bits.entries;
3828 void __init probe_nr_irqs_gsi(void)
3832 nr = acpi_probe_gsi();
3833 if (nr > nr_irqs_gsi) {
3836 /* for acpi=off or acpi is not compiled in */
3840 for (idx = 0; idx < nr_ioapics; idx++)
3841 nr += io_apic_get_redir_entries(idx) + 1;
3843 if (nr > nr_irqs_gsi)
3847 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3850 #ifdef CONFIG_SPARSE_IRQ
3851 int __init arch_probe_nr_irqs(void)
3855 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3856 nr_irqs = NR_VECTORS * nr_cpu_ids;
3858 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3859 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3861 * for MSI and HT dyn irq
3863 nr += nr_irqs_gsi * 16;
3872 /* --------------------------------------------------------------------------
3873 ACPI-based IOAPIC Configuration
3874 -------------------------------------------------------------------------- */
3878 #ifdef CONFIG_X86_32
3879 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3881 union IO_APIC_reg_00 reg_00;
3882 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3884 unsigned long flags;
3888 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3889 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3890 * supports up to 16 on one shared APIC bus.
3892 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3893 * advantage of new APIC bus architecture.
3896 if (physids_empty(apic_id_map))
3897 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3899 spin_lock_irqsave(&ioapic_lock, flags);
3900 reg_00.raw = io_apic_read(ioapic, 0);
3901 spin_unlock_irqrestore(&ioapic_lock, flags);
3903 if (apic_id >= get_physical_broadcast()) {
3904 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3905 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3906 apic_id = reg_00.bits.ID;
3910 * Every APIC in a system must have a unique ID or we get lots of nice
3911 * 'stuck on smp_invalidate_needed IPI wait' messages.
3913 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3915 for (i = 0; i < get_physical_broadcast(); i++) {
3916 if (!apic->check_apicid_used(apic_id_map, i))
3920 if (i == get_physical_broadcast())
3921 panic("Max apic_id exceeded!\n");
3923 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3924 "trying %d\n", ioapic, apic_id, i);
3929 tmp = apic->apicid_to_cpu_present(apic_id);
3930 physids_or(apic_id_map, apic_id_map, tmp);
3932 if (reg_00.bits.ID != apic_id) {
3933 reg_00.bits.ID = apic_id;
3935 spin_lock_irqsave(&ioapic_lock, flags);
3936 io_apic_write(ioapic, 0, reg_00.raw);
3937 reg_00.raw = io_apic_read(ioapic, 0);
3938 spin_unlock_irqrestore(&ioapic_lock, flags);
3941 if (reg_00.bits.ID != apic_id) {
3942 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3947 apic_printk(APIC_VERBOSE, KERN_INFO
3948 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3953 int __init io_apic_get_version(int ioapic)
3955 union IO_APIC_reg_01 reg_01;
3956 unsigned long flags;
3958 spin_lock_irqsave(&ioapic_lock, flags);
3959 reg_01.raw = io_apic_read(ioapic, 1);
3960 spin_unlock_irqrestore(&ioapic_lock, flags);
3962 return reg_01.bits.version;
3966 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3968 struct irq_desc *desc;
3969 struct irq_cfg *cfg;
3970 int cpu = boot_cpu_id;
3972 if (!IO_APIC_IRQ(irq)) {
3973 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3978 desc = irq_to_desc_alloc_cpu(irq, cpu);
3980 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3985 * IRQs < 16 are already in the irq_2_pin[] map
3987 if (irq >= NR_IRQS_LEGACY) {
3988 cfg = desc->chip_data;
3989 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3992 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3998 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4002 if (skip_ioapic_setup)
4005 for (i = 0; i < mp_irq_entries; i++)
4006 if (mp_irqs[i].irqtype == mp_INT &&
4007 mp_irqs[i].srcbusirq == bus_irq)
4009 if (i >= mp_irq_entries)
4012 *trigger = irq_trigger(i);
4013 *polarity = irq_polarity(i);
4017 #endif /* CONFIG_ACPI */
4020 * This function currently is only a helper for the i386 smp boot process where
4021 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4022 * so mask in all cases should simply be apic->target_cpus()
4025 void __init setup_ioapic_dest(void)
4027 int pin, ioapic, irq, irq_entry;
4028 struct irq_desc *desc;
4029 struct irq_cfg *cfg;
4030 const struct cpumask *mask;
4032 if (skip_ioapic_setup == 1)
4035 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4036 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4037 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4038 if (irq_entry == -1)
4040 irq = pin_2_irq(irq_entry, ioapic, pin);
4042 /* setup_IO_APIC_irqs could fail to get vector for some device
4043 * when you have too many devices, because at that time only boot
4046 desc = irq_to_desc(irq);
4047 cfg = desc->chip_data;
4049 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4050 irq_trigger(irq_entry),
4051 irq_polarity(irq_entry));
4057 * Honour affinities which have been set in early boot
4060 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4061 mask = desc->affinity;
4063 mask = apic->target_cpus();
4065 if (intr_remapping_enabled)
4066 set_ir_ioapic_affinity_irq_desc(desc, mask);
4068 set_ioapic_affinity_irq_desc(desc, mask);
4075 #define IOAPIC_RESOURCE_NAME_SIZE 11
4077 static struct resource *ioapic_resources;
4079 static struct resource * __init ioapic_setup_resources(void)
4082 struct resource *res;
4086 if (nr_ioapics <= 0)
4089 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4092 mem = alloc_bootmem(n);
4096 mem += sizeof(struct resource) * nr_ioapics;
4098 for (i = 0; i < nr_ioapics; i++) {
4100 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4101 sprintf(mem, "IOAPIC %u", i);
4102 mem += IOAPIC_RESOURCE_NAME_SIZE;
4106 ioapic_resources = res;
4111 void __init ioapic_init_mappings(void)
4113 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4114 struct resource *ioapic_res;
4117 ioapic_res = ioapic_setup_resources();
4118 for (i = 0; i < nr_ioapics; i++) {
4119 if (smp_found_config) {
4120 ioapic_phys = mp_ioapics[i].apicaddr;
4121 #ifdef CONFIG_X86_32
4124 "WARNING: bogus zero IO-APIC "
4125 "address found in MPTABLE, "
4126 "disabling IO/APIC support!\n");
4127 smp_found_config = 0;
4128 skip_ioapic_setup = 1;
4129 goto fake_ioapic_page;
4133 #ifdef CONFIG_X86_32
4136 ioapic_phys = (unsigned long)
4137 alloc_bootmem_pages(PAGE_SIZE);
4138 ioapic_phys = __pa(ioapic_phys);
4140 set_fixmap_nocache(idx, ioapic_phys);
4141 apic_printk(APIC_VERBOSE,
4142 "mapped IOAPIC to %08lx (%08lx)\n",
4143 __fix_to_virt(idx), ioapic_phys);
4146 if (ioapic_res != NULL) {
4147 ioapic_res->start = ioapic_phys;
4148 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4154 static int __init ioapic_insert_resources(void)
4157 struct resource *r = ioapic_resources;
4160 if (nr_ioapics > 0) {
4162 "IO APIC resources couldn't be allocated.\n");
4168 for (i = 0; i < nr_ioapics; i++) {
4169 insert_resource(&iomem_resource, r);
4176 /* Insert the IO APIC resources after PCI initialization has occured to handle
4177 * IO APICS that are mapped in on a BAR in PCI space. */
4178 late_initcall(ioapic_insert_resources);