2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 void arch_disable_smp_support(void)
106 noioapicreroute = -1;
108 skip_ioapic_setup = 1;
111 static int __init parse_noapic(char *str)
113 /* disable IO-APIC */
114 arch_disable_smp_support();
117 early_param("noapic", parse_noapic);
122 * This is performance-critical, we want to do it O(1)
124 * the indexing order of this array favors 1:1 mappings
125 * between pins and IRQs.
128 struct irq_pin_list {
130 struct irq_pin_list *next;
133 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
135 struct irq_pin_list *pin;
137 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
143 struct irq_pin_list *irq_2_pin;
144 cpumask_var_t domain;
145 cpumask_var_t old_domain;
146 unsigned move_cleanup_count;
148 u8 move_in_progress : 1;
151 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
152 #ifdef CONFIG_SPARSE_IRQ
153 static struct irq_cfg irq_cfgx[] = {
155 static struct irq_cfg irq_cfgx[NR_IRQS] = {
157 [0] = { .vector = IRQ0_VECTOR, },
158 [1] = { .vector = IRQ1_VECTOR, },
159 [2] = { .vector = IRQ2_VECTOR, },
160 [3] = { .vector = IRQ3_VECTOR, },
161 [4] = { .vector = IRQ4_VECTOR, },
162 [5] = { .vector = IRQ5_VECTOR, },
163 [6] = { .vector = IRQ6_VECTOR, },
164 [7] = { .vector = IRQ7_VECTOR, },
165 [8] = { .vector = IRQ8_VECTOR, },
166 [9] = { .vector = IRQ9_VECTOR, },
167 [10] = { .vector = IRQ10_VECTOR, },
168 [11] = { .vector = IRQ11_VECTOR, },
169 [12] = { .vector = IRQ12_VECTOR, },
170 [13] = { .vector = IRQ13_VECTOR, },
171 [14] = { .vector = IRQ14_VECTOR, },
172 [15] = { .vector = IRQ15_VECTOR, },
175 int __init arch_early_irq_init(void)
178 struct irq_desc *desc;
184 count = ARRAY_SIZE(irq_cfgx);
185 node= cpu_to_node(boot_cpu_id);
187 for (i = 0; i < count; i++) {
188 desc = irq_to_desc(i);
189 desc->chip_data = &cfg[i];
190 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
191 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
192 if (i < NR_IRQS_LEGACY)
193 cpumask_setall(cfg[i].domain);
199 #ifdef CONFIG_SPARSE_IRQ
200 static struct irq_cfg *irq_cfg(unsigned int irq)
202 struct irq_cfg *cfg = NULL;
203 struct irq_desc *desc;
205 desc = irq_to_desc(irq);
207 cfg = desc->chip_data;
212 static struct irq_cfg *get_one_free_irq_cfg(int node)
216 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
218 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
221 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
223 free_cpumask_var(cfg->domain);
227 cpumask_clear(cfg->domain);
228 cpumask_clear(cfg->old_domain);
235 int arch_init_chip_data(struct irq_desc *desc, int node)
239 cfg = desc->chip_data;
241 desc->chip_data = get_one_free_irq_cfg(node);
242 if (!desc->chip_data) {
243 printk(KERN_ERR "can not alloc irq_cfg\n");
251 /* for move_irq_desc */
253 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
255 struct irq_pin_list *old_entry, *head, *tail, *entry;
257 cfg->irq_2_pin = NULL;
258 old_entry = old_cfg->irq_2_pin;
262 entry = get_one_free_irq_2_pin(node);
266 entry->apic = old_entry->apic;
267 entry->pin = old_entry->pin;
270 old_entry = old_entry->next;
272 entry = get_one_free_irq_2_pin(node);
280 /* still use the old one */
283 entry->apic = old_entry->apic;
284 entry->pin = old_entry->pin;
287 old_entry = old_entry->next;
291 cfg->irq_2_pin = head;
294 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
296 struct irq_pin_list *entry, *next;
298 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
301 entry = old_cfg->irq_2_pin;
308 old_cfg->irq_2_pin = NULL;
311 void arch_init_copy_chip_data(struct irq_desc *old_desc,
312 struct irq_desc *desc, int node)
315 struct irq_cfg *old_cfg;
317 cfg = get_one_free_irq_cfg(node);
322 desc->chip_data = cfg;
324 old_cfg = old_desc->chip_data;
326 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
328 init_copy_irq_2_pin(old_cfg, cfg, node);
331 static void free_irq_cfg(struct irq_cfg *old_cfg)
336 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
338 struct irq_cfg *old_cfg, *cfg;
340 old_cfg = old_desc->chip_data;
341 cfg = desc->chip_data;
347 free_irq_2_pin(old_cfg, cfg);
348 free_irq_cfg(old_cfg);
349 old_desc->chip_data = NULL;
352 /* end for move_irq_desc */
355 static struct irq_cfg *irq_cfg(unsigned int irq)
357 return irq < nr_irqs ? irq_cfgx + irq : NULL;
364 unsigned int unused[3];
366 unsigned int unused2[11];
370 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
372 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
373 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
376 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
378 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(vector, &io_apic->eoi);
382 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 return readl(&io_apic->data);
389 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
391 struct io_apic __iomem *io_apic = io_apic_base(apic);
392 writel(reg, &io_apic->index);
393 writel(value, &io_apic->data);
397 * Re-write a value: to be used for read-modify-write
398 * cycles where the read already set up the index register.
400 * Older SiS APIC requires we rewrite the index register
402 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
407 writel(reg, &io_apic->index);
408 writel(value, &io_apic->data);
411 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
413 struct irq_pin_list *entry;
416 spin_lock_irqsave(&ioapic_lock, flags);
417 entry = cfg->irq_2_pin;
425 reg = io_apic_read(entry->apic, 0x10 + pin*2);
426 /* Is the remote IRR bit set? */
427 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
428 spin_unlock_irqrestore(&ioapic_lock, flags);
435 spin_unlock_irqrestore(&ioapic_lock, flags);
441 struct { u32 w1, w2; };
442 struct IO_APIC_route_entry entry;
445 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
447 union entry_union eu;
449 spin_lock_irqsave(&ioapic_lock, flags);
450 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
451 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
452 spin_unlock_irqrestore(&ioapic_lock, flags);
457 * When we write a new IO APIC routing entry, we need to write the high
458 * word first! If the mask bit in the low word is clear, we will enable
459 * the interrupt, and we need to make sure the entry is fully populated
460 * before that happens.
463 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
465 union entry_union eu = {{0, 0}};
468 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
469 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
472 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
475 spin_lock_irqsave(&ioapic_lock, flags);
476 __ioapic_write_entry(apic, pin, e);
477 spin_unlock_irqrestore(&ioapic_lock, flags);
481 * When we mask an IO APIC routing entry, we need to write the low
482 * word first, in order to set the mask bit before we change the
485 static void ioapic_mask_entry(int apic, int pin)
488 union entry_union eu = { .entry.mask = 1 };
490 spin_lock_irqsave(&ioapic_lock, flags);
491 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
492 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
493 spin_unlock_irqrestore(&ioapic_lock, flags);
497 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
498 * shared ISA-space IRQs, so we have to support them. We are super
499 * fast in the common case, and fast for shared ISA-space IRQs.
501 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
503 struct irq_pin_list *entry;
505 entry = cfg->irq_2_pin;
507 entry = get_one_free_irq_2_pin(node);
509 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
513 cfg->irq_2_pin = entry;
519 while (entry->next) {
520 /* not again, please */
521 if (entry->apic == apic && entry->pin == pin)
527 entry->next = get_one_free_irq_2_pin(node);
534 * Reroute an IRQ to a different pin.
536 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
537 int oldapic, int oldpin,
538 int newapic, int newpin)
540 struct irq_pin_list *entry = cfg->irq_2_pin;
544 if (entry->apic == oldapic && entry->pin == oldpin) {
545 entry->apic = newapic;
548 /* every one is different, right? */
554 /* why? call replace before add? */
556 add_pin_to_irq_node(cfg, node, newapic, newpin);
559 static void io_apic_modify_irq(struct irq_cfg *cfg,
560 int mask_and, int mask_or,
561 void (*final)(struct irq_pin_list *entry))
564 struct irq_pin_list *entry;
566 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
569 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
572 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
578 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
580 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
583 static void io_apic_sync(struct irq_pin_list *entry)
586 * Synchronize the IO-APIC and the CPU by doing
587 * a dummy read from the IO-APIC
589 struct io_apic __iomem *io_apic;
590 io_apic = io_apic_base(entry->apic);
591 readl(&io_apic->data);
594 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
596 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
600 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
602 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
603 IO_APIC_REDIR_MASKED, NULL);
606 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
608 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
609 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
611 #endif /* CONFIG_X86_32 */
613 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
615 struct irq_cfg *cfg = desc->chip_data;
620 spin_lock_irqsave(&ioapic_lock, flags);
621 __mask_IO_APIC_irq(cfg);
622 spin_unlock_irqrestore(&ioapic_lock, flags);
625 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
627 struct irq_cfg *cfg = desc->chip_data;
630 spin_lock_irqsave(&ioapic_lock, flags);
631 __unmask_IO_APIC_irq(cfg);
632 spin_unlock_irqrestore(&ioapic_lock, flags);
635 static void mask_IO_APIC_irq(unsigned int irq)
637 struct irq_desc *desc = irq_to_desc(irq);
639 mask_IO_APIC_irq_desc(desc);
641 static void unmask_IO_APIC_irq(unsigned int irq)
643 struct irq_desc *desc = irq_to_desc(irq);
645 unmask_IO_APIC_irq_desc(desc);
648 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
650 struct IO_APIC_route_entry entry;
652 /* Check delivery_mode to be sure we're not clearing an SMI pin */
653 entry = ioapic_read_entry(apic, pin);
654 if (entry.delivery_mode == dest_SMI)
657 * Disable it in the IO-APIC irq-routing table:
659 ioapic_mask_entry(apic, pin);
662 static void clear_IO_APIC (void)
666 for (apic = 0; apic < nr_ioapics; apic++)
667 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
668 clear_IO_APIC_pin(apic, pin);
673 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
674 * specific CPU-side IRQs.
678 static int pirq_entries[MAX_PIRQS] = {
679 [0 ... MAX_PIRQS - 1] = -1
682 static int __init ioapic_pirq_setup(char *str)
685 int ints[MAX_PIRQS+1];
687 get_options(str, ARRAY_SIZE(ints), ints);
689 apic_printk(APIC_VERBOSE, KERN_INFO
690 "PIRQ redirection, working around broken MP-BIOS.\n");
692 if (ints[0] < MAX_PIRQS)
695 for (i = 0; i < max; i++) {
696 apic_printk(APIC_VERBOSE, KERN_DEBUG
697 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
699 * PIRQs are mapped upside down, usually.
701 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
706 __setup("pirq=", ioapic_pirq_setup);
707 #endif /* CONFIG_X86_32 */
709 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
712 struct IO_APIC_route_entry **ioapic_entries;
714 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
719 for (apic = 0; apic < nr_ioapics; apic++) {
720 ioapic_entries[apic] =
721 kzalloc(sizeof(struct IO_APIC_route_entry) *
722 nr_ioapic_registers[apic], GFP_ATOMIC);
723 if (!ioapic_entries[apic])
727 return ioapic_entries;
731 kfree(ioapic_entries[apic]);
732 kfree(ioapic_entries);
738 * Saves all the IO-APIC RTE's
740 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
747 for (apic = 0; apic < nr_ioapics; apic++) {
748 if (!ioapic_entries[apic])
751 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
752 ioapic_entries[apic][pin] =
753 ioapic_read_entry(apic, pin);
760 * Mask all IO APIC entries.
762 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
769 for (apic = 0; apic < nr_ioapics; apic++) {
770 if (!ioapic_entries[apic])
773 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
774 struct IO_APIC_route_entry entry;
776 entry = ioapic_entries[apic][pin];
779 ioapic_write_entry(apic, pin, entry);
786 * Restore IO APIC entries which was saved in ioapic_entries.
788 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
795 for (apic = 0; apic < nr_ioapics; apic++) {
796 if (!ioapic_entries[apic])
799 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
800 ioapic_write_entry(apic, pin,
801 ioapic_entries[apic][pin]);
806 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
810 for (apic = 0; apic < nr_ioapics; apic++)
811 kfree(ioapic_entries[apic]);
813 kfree(ioapic_entries);
817 * Find the IRQ entry number of a certain pin.
819 static int find_irq_entry(int apic, int pin, int type)
823 for (i = 0; i < mp_irq_entries; i++)
824 if (mp_irqs[i].irqtype == type &&
825 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
826 mp_irqs[i].dstapic == MP_APIC_ALL) &&
827 mp_irqs[i].dstirq == pin)
834 * Find the pin to which IRQ[irq] (ISA) is connected
836 static int __init find_isa_irq_pin(int irq, int type)
840 for (i = 0; i < mp_irq_entries; i++) {
841 int lbus = mp_irqs[i].srcbus;
843 if (test_bit(lbus, mp_bus_not_pci) &&
844 (mp_irqs[i].irqtype == type) &&
845 (mp_irqs[i].srcbusirq == irq))
847 return mp_irqs[i].dstirq;
852 static int __init find_isa_irq_apic(int irq, int type)
856 for (i = 0; i < mp_irq_entries; i++) {
857 int lbus = mp_irqs[i].srcbus;
859 if (test_bit(lbus, mp_bus_not_pci) &&
860 (mp_irqs[i].irqtype == type) &&
861 (mp_irqs[i].srcbusirq == irq))
864 if (i < mp_irq_entries) {
866 for(apic = 0; apic < nr_ioapics; apic++) {
867 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
875 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
877 * EISA Edge/Level control register, ELCR
879 static int EISA_ELCR(unsigned int irq)
881 if (irq < NR_IRQS_LEGACY) {
882 unsigned int port = 0x4d0 + (irq >> 3);
883 return (inb(port) >> (irq & 7)) & 1;
885 apic_printk(APIC_VERBOSE, KERN_INFO
886 "Broken MPtable reports ISA irq %d\n", irq);
892 /* ISA interrupts are always polarity zero edge triggered,
893 * when listed as conforming in the MP table. */
895 #define default_ISA_trigger(idx) (0)
896 #define default_ISA_polarity(idx) (0)
898 /* EISA interrupts are always polarity zero and can be edge or level
899 * trigger depending on the ELCR value. If an interrupt is listed as
900 * EISA conforming in the MP table, that means its trigger type must
901 * be read in from the ELCR */
903 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
904 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
906 /* PCI interrupts are always polarity one level triggered,
907 * when listed as conforming in the MP table. */
909 #define default_PCI_trigger(idx) (1)
910 #define default_PCI_polarity(idx) (1)
912 /* MCA interrupts are always polarity zero level triggered,
913 * when listed as conforming in the MP table. */
915 #define default_MCA_trigger(idx) (1)
916 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
918 static int MPBIOS_polarity(int idx)
920 int bus = mp_irqs[idx].srcbus;
924 * Determine IRQ line polarity (high active or low active):
926 switch (mp_irqs[idx].irqflag & 3)
928 case 0: /* conforms, ie. bus-type dependent polarity */
929 if (test_bit(bus, mp_bus_not_pci))
930 polarity = default_ISA_polarity(idx);
932 polarity = default_PCI_polarity(idx);
934 case 1: /* high active */
939 case 2: /* reserved */
941 printk(KERN_WARNING "broken BIOS!!\n");
945 case 3: /* low active */
950 default: /* invalid */
952 printk(KERN_WARNING "broken BIOS!!\n");
960 static int MPBIOS_trigger(int idx)
962 int bus = mp_irqs[idx].srcbus;
966 * Determine IRQ trigger mode (edge or level sensitive):
968 switch ((mp_irqs[idx].irqflag>>2) & 3)
970 case 0: /* conforms, ie. bus-type dependent */
971 if (test_bit(bus, mp_bus_not_pci))
972 trigger = default_ISA_trigger(idx);
974 trigger = default_PCI_trigger(idx);
975 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
976 switch (mp_bus_id_to_type[bus]) {
977 case MP_BUS_ISA: /* ISA pin */
979 /* set before the switch */
982 case MP_BUS_EISA: /* EISA pin */
984 trigger = default_EISA_trigger(idx);
987 case MP_BUS_PCI: /* PCI pin */
989 /* set before the switch */
992 case MP_BUS_MCA: /* MCA pin */
994 trigger = default_MCA_trigger(idx);
999 printk(KERN_WARNING "broken BIOS!!\n");
1011 case 2: /* reserved */
1013 printk(KERN_WARNING "broken BIOS!!\n");
1022 default: /* invalid */
1024 printk(KERN_WARNING "broken BIOS!!\n");
1032 static inline int irq_polarity(int idx)
1034 return MPBIOS_polarity(idx);
1037 static inline int irq_trigger(int idx)
1039 return MPBIOS_trigger(idx);
1042 int (*ioapic_renumber_irq)(int ioapic, int irq);
1043 static int pin_2_irq(int idx, int apic, int pin)
1046 int bus = mp_irqs[idx].srcbus;
1049 * Debugging check, we are in big trouble if this message pops up!
1051 if (mp_irqs[idx].dstirq != pin)
1052 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1054 if (test_bit(bus, mp_bus_not_pci)) {
1055 irq = mp_irqs[idx].srcbusirq;
1058 * PCI IRQs are mapped in order
1062 irq += nr_ioapic_registers[i++];
1065 * For MPS mode, so far only needed by ES7000 platform
1067 if (ioapic_renumber_irq)
1068 irq = ioapic_renumber_irq(apic, irq);
1071 #ifdef CONFIG_X86_32
1073 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1075 if ((pin >= 16) && (pin <= 23)) {
1076 if (pirq_entries[pin-16] != -1) {
1077 if (!pirq_entries[pin-16]) {
1078 apic_printk(APIC_VERBOSE, KERN_DEBUG
1079 "disabling PIRQ%d\n", pin-16);
1081 irq = pirq_entries[pin-16];
1082 apic_printk(APIC_VERBOSE, KERN_DEBUG
1083 "using PIRQ%d -> IRQ %d\n",
1094 * Find a specific PCI IRQ entry.
1095 * Not an __init, possibly needed by modules
1097 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1098 struct io_apic_irq_attr *irq_attr)
1100 int apic, i, best_guess = -1;
1102 apic_printk(APIC_DEBUG,
1103 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1105 if (test_bit(bus, mp_bus_not_pci)) {
1106 apic_printk(APIC_VERBOSE,
1107 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1110 for (i = 0; i < mp_irq_entries; i++) {
1111 int lbus = mp_irqs[i].srcbus;
1113 for (apic = 0; apic < nr_ioapics; apic++)
1114 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1115 mp_irqs[i].dstapic == MP_APIC_ALL)
1118 if (!test_bit(lbus, mp_bus_not_pci) &&
1119 !mp_irqs[i].irqtype &&
1121 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1122 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1124 if (!(apic || IO_APIC_IRQ(irq)))
1127 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1128 set_io_apic_irq_attr(irq_attr, apic,
1135 * Use the first all-but-pin matching entry as a
1136 * best-guess fuzzy result for broken mptables.
1138 if (best_guess < 0) {
1139 set_io_apic_irq_attr(irq_attr, apic,
1149 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1151 void lock_vector_lock(void)
1153 /* Used to the online set of cpus does not change
1154 * during assign_irq_vector.
1156 spin_lock(&vector_lock);
1159 void unlock_vector_lock(void)
1161 spin_unlock(&vector_lock);
1165 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1168 * NOTE! The local APIC isn't very good at handling
1169 * multiple interrupts at the same interrupt level.
1170 * As the interrupt level is determined by taking the
1171 * vector number and shifting that right by 4, we
1172 * want to spread these out a bit so that they don't
1173 * all fall in the same interrupt level.
1175 * Also, we've got to be careful not to trash gate
1176 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1178 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1179 unsigned int old_vector;
1181 cpumask_var_t tmp_mask;
1183 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1186 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1189 old_vector = cfg->vector;
1191 cpumask_and(tmp_mask, mask, cpu_online_mask);
1192 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1193 if (!cpumask_empty(tmp_mask)) {
1194 free_cpumask_var(tmp_mask);
1199 /* Only try and allocate irqs on cpus that are present */
1201 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1205 apic->vector_allocation_domain(cpu, tmp_mask);
1207 vector = current_vector;
1208 offset = current_offset;
1211 if (vector >= first_system_vector) {
1212 /* If out of vectors on large boxen, must share them. */
1213 offset = (offset + 1) % 8;
1214 vector = FIRST_DEVICE_VECTOR + offset;
1216 if (unlikely(current_vector == vector))
1219 if (test_bit(vector, used_vectors))
1222 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1223 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1226 current_vector = vector;
1227 current_offset = offset;
1229 cfg->move_in_progress = 1;
1230 cpumask_copy(cfg->old_domain, cfg->domain);
1232 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1233 per_cpu(vector_irq, new_cpu)[vector] = irq;
1234 cfg->vector = vector;
1235 cpumask_copy(cfg->domain, tmp_mask);
1239 free_cpumask_var(tmp_mask);
1244 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1247 unsigned long flags;
1249 spin_lock_irqsave(&vector_lock, flags);
1250 err = __assign_irq_vector(irq, cfg, mask);
1251 spin_unlock_irqrestore(&vector_lock, flags);
1255 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1259 BUG_ON(!cfg->vector);
1261 vector = cfg->vector;
1262 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1263 per_cpu(vector_irq, cpu)[vector] = -1;
1266 cpumask_clear(cfg->domain);
1268 if (likely(!cfg->move_in_progress))
1270 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1271 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1273 if (per_cpu(vector_irq, cpu)[vector] != irq)
1275 per_cpu(vector_irq, cpu)[vector] = -1;
1279 cfg->move_in_progress = 0;
1282 void __setup_vector_irq(int cpu)
1284 /* Initialize vector_irq on a new cpu */
1285 /* This function must be called with vector_lock held */
1287 struct irq_cfg *cfg;
1288 struct irq_desc *desc;
1290 /* Mark the inuse vectors */
1291 for_each_irq_desc(irq, desc) {
1292 cfg = desc->chip_data;
1293 if (!cpumask_test_cpu(cpu, cfg->domain))
1295 vector = cfg->vector;
1296 per_cpu(vector_irq, cpu)[vector] = irq;
1298 /* Mark the free vectors */
1299 for (vector = 0; vector < NR_VECTORS; ++vector) {
1300 irq = per_cpu(vector_irq, cpu)[vector];
1305 if (!cpumask_test_cpu(cpu, cfg->domain))
1306 per_cpu(vector_irq, cpu)[vector] = -1;
1310 static struct irq_chip ioapic_chip;
1311 static struct irq_chip ir_ioapic_chip;
1313 #define IOAPIC_AUTO -1
1314 #define IOAPIC_EDGE 0
1315 #define IOAPIC_LEVEL 1
1317 #ifdef CONFIG_X86_32
1318 static inline int IO_APIC_irq_trigger(int irq)
1322 for (apic = 0; apic < nr_ioapics; apic++) {
1323 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1324 idx = find_irq_entry(apic, pin, mp_INT);
1325 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1326 return irq_trigger(idx);
1330 * nonexistent IRQs are edge default
1335 static inline int IO_APIC_irq_trigger(int irq)
1341 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1344 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1345 trigger == IOAPIC_LEVEL)
1346 desc->status |= IRQ_LEVEL;
1348 desc->status &= ~IRQ_LEVEL;
1350 if (irq_remapped(irq)) {
1351 desc->status |= IRQ_MOVE_PCNTXT;
1353 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1357 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1358 handle_edge_irq, "edge");
1362 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1363 trigger == IOAPIC_LEVEL)
1364 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1368 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1369 handle_edge_irq, "edge");
1372 int setup_ioapic_entry(int apic_id, int irq,
1373 struct IO_APIC_route_entry *entry,
1374 unsigned int destination, int trigger,
1375 int polarity, int vector, int pin)
1378 * add it to the IO-APIC irq-routing table:
1380 memset(entry,0,sizeof(*entry));
1382 if (intr_remapping_enabled) {
1383 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1385 struct IR_IO_APIC_route_entry *ir_entry =
1386 (struct IR_IO_APIC_route_entry *) entry;
1390 panic("No mapping iommu for ioapic %d\n", apic_id);
1392 index = alloc_irte(iommu, irq, 1);
1394 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1396 memset(&irte, 0, sizeof(irte));
1399 irte.dst_mode = apic->irq_dest_mode;
1401 * Trigger mode in the IRTE will always be edge, and the
1402 * actual level or edge trigger will be setup in the IO-APIC
1403 * RTE. This will help simplify level triggered irq migration.
1404 * For more details, see the comments above explainig IO-APIC
1405 * irq migration in the presence of interrupt-remapping.
1407 irte.trigger_mode = 0;
1408 irte.dlvry_mode = apic->irq_delivery_mode;
1409 irte.vector = vector;
1410 irte.dest_id = IRTE_DEST(destination);
1412 /* Set source-id of interrupt request */
1413 set_ioapic_sid(&irte, apic_id);
1415 modify_irte(irq, &irte);
1417 ir_entry->index2 = (index >> 15) & 0x1;
1419 ir_entry->format = 1;
1420 ir_entry->index = (index & 0x7fff);
1422 * IO-APIC RTE will be configured with virtual vector.
1423 * irq handler will do the explicit EOI to the io-apic.
1425 ir_entry->vector = pin;
1427 entry->delivery_mode = apic->irq_delivery_mode;
1428 entry->dest_mode = apic->irq_dest_mode;
1429 entry->dest = destination;
1430 entry->vector = vector;
1433 entry->mask = 0; /* enable IRQ */
1434 entry->trigger = trigger;
1435 entry->polarity = polarity;
1437 /* Mask level triggered irqs.
1438 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1445 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1446 int trigger, int polarity)
1448 struct irq_cfg *cfg;
1449 struct IO_APIC_route_entry entry;
1452 if (!IO_APIC_IRQ(irq))
1455 cfg = desc->chip_data;
1457 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1460 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1462 apic_printk(APIC_VERBOSE,KERN_DEBUG
1463 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1464 "IRQ %d Mode:%i Active:%i)\n",
1465 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1466 irq, trigger, polarity);
1469 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1470 dest, trigger, polarity, cfg->vector, pin)) {
1471 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1472 mp_ioapics[apic_id].apicid, pin);
1473 __clear_irq_vector(irq, cfg);
1477 ioapic_register_intr(irq, desc, trigger);
1478 if (irq < NR_IRQS_LEGACY)
1479 disable_8259A_irq(irq);
1481 ioapic_write_entry(apic_id, pin, entry);
1485 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1486 } mp_ioapic_routing[MAX_IO_APICS];
1488 static void __init setup_IO_APIC_irqs(void)
1490 int apic_id = 0, pin, idx, irq;
1492 struct irq_desc *desc;
1493 struct irq_cfg *cfg;
1494 int node = cpu_to_node(boot_cpu_id);
1496 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1499 if (!acpi_disabled && acpi_ioapic) {
1500 apic_id = mp_find_ioapic(0);
1506 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1507 idx = find_irq_entry(apic_id, pin, mp_INT);
1511 apic_printk(APIC_VERBOSE,
1512 KERN_DEBUG " %d-%d",
1513 mp_ioapics[apic_id].apicid, pin);
1515 apic_printk(APIC_VERBOSE, " %d-%d",
1516 mp_ioapics[apic_id].apicid, pin);
1520 apic_printk(APIC_VERBOSE,
1521 " (apicid-pin) not connected\n");
1525 irq = pin_2_irq(idx, apic_id, pin);
1528 * Skip the timer IRQ if there's a quirk handler
1529 * installed and if it returns 1:
1531 if (apic->multi_timer_check &&
1532 apic->multi_timer_check(apic_id, irq))
1535 desc = irq_to_desc_alloc_node(irq, node);
1537 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1540 cfg = desc->chip_data;
1541 add_pin_to_irq_node(cfg, node, apic_id, pin);
1543 * don't mark it in pin_programmed, so later acpi could
1544 * set it correctly when irq < 16
1546 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1547 irq_trigger(idx), irq_polarity(idx));
1551 apic_printk(APIC_VERBOSE,
1552 " (apicid-pin) not connected\n");
1556 * Set up the timer pin, possibly with the 8259A-master behind.
1558 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1561 struct IO_APIC_route_entry entry;
1563 if (intr_remapping_enabled)
1566 memset(&entry, 0, sizeof(entry));
1569 * We use logical delivery to get the timer IRQ
1572 entry.dest_mode = apic->irq_dest_mode;
1573 entry.mask = 0; /* don't mask IRQ for edge */
1574 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1575 entry.delivery_mode = apic->irq_delivery_mode;
1578 entry.vector = vector;
1581 * The timer IRQ doesn't have to know that behind the
1582 * scene we may have a 8259A-master in AEOI mode ...
1584 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1587 * Add it to the IO-APIC irq-routing table:
1589 ioapic_write_entry(apic_id, pin, entry);
1593 __apicdebuginit(void) print_IO_APIC(void)
1596 union IO_APIC_reg_00 reg_00;
1597 union IO_APIC_reg_01 reg_01;
1598 union IO_APIC_reg_02 reg_02;
1599 union IO_APIC_reg_03 reg_03;
1600 unsigned long flags;
1601 struct irq_cfg *cfg;
1602 struct irq_desc *desc;
1605 if (apic_verbosity == APIC_QUIET)
1608 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1609 for (i = 0; i < nr_ioapics; i++)
1610 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1611 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1614 * We are a bit conservative about what we expect. We have to
1615 * know about every hardware change ASAP.
1617 printk(KERN_INFO "testing the IO APIC.......................\n");
1619 for (apic = 0; apic < nr_ioapics; apic++) {
1621 spin_lock_irqsave(&ioapic_lock, flags);
1622 reg_00.raw = io_apic_read(apic, 0);
1623 reg_01.raw = io_apic_read(apic, 1);
1624 if (reg_01.bits.version >= 0x10)
1625 reg_02.raw = io_apic_read(apic, 2);
1626 if (reg_01.bits.version >= 0x20)
1627 reg_03.raw = io_apic_read(apic, 3);
1628 spin_unlock_irqrestore(&ioapic_lock, flags);
1631 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1632 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1633 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1634 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1635 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1637 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1638 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1640 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1641 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1644 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1645 * but the value of reg_02 is read as the previous read register
1646 * value, so ignore it if reg_02 == reg_01.
1648 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1649 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1650 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1654 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1655 * or reg_03, but the value of reg_0[23] is read as the previous read
1656 * register value, so ignore it if reg_03 == reg_0[12].
1658 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1659 reg_03.raw != reg_01.raw) {
1660 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1661 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1664 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1666 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1667 " Stat Dmod Deli Vect: \n");
1669 for (i = 0; i <= reg_01.bits.entries; i++) {
1670 struct IO_APIC_route_entry entry;
1672 entry = ioapic_read_entry(apic, i);
1674 printk(KERN_DEBUG " %02x %03X ",
1679 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1684 entry.delivery_status,
1686 entry.delivery_mode,
1691 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1692 for_each_irq_desc(irq, desc) {
1693 struct irq_pin_list *entry;
1695 cfg = desc->chip_data;
1696 entry = cfg->irq_2_pin;
1699 printk(KERN_DEBUG "IRQ%d ", irq);
1701 printk("-> %d:%d", entry->apic, entry->pin);
1704 entry = entry->next;
1709 printk(KERN_INFO ".................................... done.\n");
1714 __apicdebuginit(void) print_APIC_field(int base)
1718 if (apic_verbosity == APIC_QUIET)
1723 for (i = 0; i < 8; i++)
1724 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1726 printk(KERN_CONT "\n");
1729 __apicdebuginit(void) print_local_APIC(void *dummy)
1731 unsigned int i, v, ver, maxlvt;
1734 if (apic_verbosity == APIC_QUIET)
1737 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1738 smp_processor_id(), hard_smp_processor_id());
1739 v = apic_read(APIC_ID);
1740 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1741 v = apic_read(APIC_LVR);
1742 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1743 ver = GET_APIC_VERSION(v);
1744 maxlvt = lapic_get_maxlvt();
1746 v = apic_read(APIC_TASKPRI);
1747 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1749 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1750 if (!APIC_XAPIC(ver)) {
1751 v = apic_read(APIC_ARBPRI);
1752 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1753 v & APIC_ARBPRI_MASK);
1755 v = apic_read(APIC_PROCPRI);
1756 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1760 * Remote read supported only in the 82489DX and local APIC for
1761 * Pentium processors.
1763 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1764 v = apic_read(APIC_RRR);
1765 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1768 v = apic_read(APIC_LDR);
1769 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1770 if (!x2apic_enabled()) {
1771 v = apic_read(APIC_DFR);
1772 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1774 v = apic_read(APIC_SPIV);
1775 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1777 printk(KERN_DEBUG "... APIC ISR field:\n");
1778 print_APIC_field(APIC_ISR);
1779 printk(KERN_DEBUG "... APIC TMR field:\n");
1780 print_APIC_field(APIC_TMR);
1781 printk(KERN_DEBUG "... APIC IRR field:\n");
1782 print_APIC_field(APIC_IRR);
1784 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1785 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1786 apic_write(APIC_ESR, 0);
1788 v = apic_read(APIC_ESR);
1789 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1792 icr = apic_icr_read();
1793 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1794 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1796 v = apic_read(APIC_LVTT);
1797 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1799 if (maxlvt > 3) { /* PC is LVT#4. */
1800 v = apic_read(APIC_LVTPC);
1801 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1803 v = apic_read(APIC_LVT0);
1804 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1805 v = apic_read(APIC_LVT1);
1806 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1808 if (maxlvt > 2) { /* ERR is LVT#3. */
1809 v = apic_read(APIC_LVTERR);
1810 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1813 v = apic_read(APIC_TMICT);
1814 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1815 v = apic_read(APIC_TMCCT);
1816 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1817 v = apic_read(APIC_TDCR);
1818 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1820 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1821 v = apic_read(APIC_EFEAT);
1822 maxlvt = (v >> 16) & 0xff;
1823 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1824 v = apic_read(APIC_ECTRL);
1825 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1826 for (i = 0; i < maxlvt; i++) {
1827 v = apic_read(APIC_EILVTn(i));
1828 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1834 __apicdebuginit(void) print_all_local_APICs(void)
1839 for_each_online_cpu(cpu)
1840 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1844 __apicdebuginit(void) print_PIC(void)
1847 unsigned long flags;
1849 if (apic_verbosity == APIC_QUIET)
1852 printk(KERN_DEBUG "\nprinting PIC contents\n");
1854 spin_lock_irqsave(&i8259A_lock, flags);
1856 v = inb(0xa1) << 8 | inb(0x21);
1857 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1859 v = inb(0xa0) << 8 | inb(0x20);
1860 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1864 v = inb(0xa0) << 8 | inb(0x20);
1868 spin_unlock_irqrestore(&i8259A_lock, flags);
1870 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1872 v = inb(0x4d1) << 8 | inb(0x4d0);
1873 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1876 __apicdebuginit(int) print_all_ICs(void)
1880 /* don't print out if apic is not there */
1881 if (!cpu_has_apic || disable_apic)
1884 print_all_local_APICs();
1890 fs_initcall(print_all_ICs);
1893 /* Where if anywhere is the i8259 connect in external int mode */
1894 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1896 void __init enable_IO_APIC(void)
1898 union IO_APIC_reg_01 reg_01;
1899 int i8259_apic, i8259_pin;
1901 unsigned long flags;
1904 * The number of IO-APIC IRQ registers (== #pins):
1906 for (apic = 0; apic < nr_ioapics; apic++) {
1907 spin_lock_irqsave(&ioapic_lock, flags);
1908 reg_01.raw = io_apic_read(apic, 1);
1909 spin_unlock_irqrestore(&ioapic_lock, flags);
1910 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1912 for(apic = 0; apic < nr_ioapics; apic++) {
1914 /* See if any of the pins is in ExtINT mode */
1915 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1916 struct IO_APIC_route_entry entry;
1917 entry = ioapic_read_entry(apic, pin);
1919 /* If the interrupt line is enabled and in ExtInt mode
1920 * I have found the pin where the i8259 is connected.
1922 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1923 ioapic_i8259.apic = apic;
1924 ioapic_i8259.pin = pin;
1930 /* Look to see what if the MP table has reported the ExtINT */
1931 /* If we could not find the appropriate pin by looking at the ioapic
1932 * the i8259 probably is not connected the ioapic but give the
1933 * mptable a chance anyway.
1935 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1936 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1937 /* Trust the MP table if nothing is setup in the hardware */
1938 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1939 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1940 ioapic_i8259.pin = i8259_pin;
1941 ioapic_i8259.apic = i8259_apic;
1943 /* Complain if the MP table and the hardware disagree */
1944 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1945 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1947 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1951 * Do not trust the IO-APIC being empty at bootup
1957 * Not an __init, needed by the reboot code
1959 void disable_IO_APIC(void)
1962 * Clear the IO-APIC before rebooting:
1967 * If the i8259 is routed through an IOAPIC
1968 * Put that IOAPIC in virtual wire mode
1969 * so legacy interrupts can be delivered.
1971 * With interrupt-remapping, for now we will use virtual wire A mode,
1972 * as virtual wire B is little complex (need to configure both
1973 * IOAPIC RTE aswell as interrupt-remapping table entry).
1974 * As this gets called during crash dump, keep this simple for now.
1976 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1977 struct IO_APIC_route_entry entry;
1979 memset(&entry, 0, sizeof(entry));
1980 entry.mask = 0; /* Enabled */
1981 entry.trigger = 0; /* Edge */
1983 entry.polarity = 0; /* High */
1984 entry.delivery_status = 0;
1985 entry.dest_mode = 0; /* Physical */
1986 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1988 entry.dest = read_apic_id();
1991 * Add it to the IO-APIC irq-routing table:
1993 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1997 * Use virtual wire A mode when interrupt remapping is enabled.
2000 disconnect_bsp_APIC(!intr_remapping_enabled &&
2001 ioapic_i8259.pin != -1);
2004 #ifdef CONFIG_X86_32
2006 * function to set the IO-APIC physical IDs based on the
2007 * values stored in the MPC table.
2009 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2012 static void __init setup_ioapic_ids_from_mpc(void)
2014 union IO_APIC_reg_00 reg_00;
2015 physid_mask_t phys_id_present_map;
2018 unsigned char old_id;
2019 unsigned long flags;
2021 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2025 * Don't check I/O APIC IDs for xAPIC systems. They have
2026 * no meaning without the serial APIC bus.
2028 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2029 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2032 * This is broken; anything with a real cpu count has to
2033 * circumvent this idiocy regardless.
2035 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2038 * Set the IOAPIC ID to the value stored in the MPC table.
2040 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2042 /* Read the register 0 value */
2043 spin_lock_irqsave(&ioapic_lock, flags);
2044 reg_00.raw = io_apic_read(apic_id, 0);
2045 spin_unlock_irqrestore(&ioapic_lock, flags);
2047 old_id = mp_ioapics[apic_id].apicid;
2049 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2050 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2051 apic_id, mp_ioapics[apic_id].apicid);
2052 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2054 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2058 * Sanity check, is the ID really free? Every APIC in a
2059 * system must have a unique ID or we get lots of nice
2060 * 'stuck on smp_invalidate_needed IPI wait' messages.
2062 if (apic->check_apicid_used(phys_id_present_map,
2063 mp_ioapics[apic_id].apicid)) {
2064 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2065 apic_id, mp_ioapics[apic_id].apicid);
2066 for (i = 0; i < get_physical_broadcast(); i++)
2067 if (!physid_isset(i, phys_id_present_map))
2069 if (i >= get_physical_broadcast())
2070 panic("Max APIC ID exceeded!\n");
2071 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2073 physid_set(i, phys_id_present_map);
2074 mp_ioapics[apic_id].apicid = i;
2077 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2078 apic_printk(APIC_VERBOSE, "Setting %d in the "
2079 "phys_id_present_map\n",
2080 mp_ioapics[apic_id].apicid);
2081 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2086 * We need to adjust the IRQ routing table
2087 * if the ID changed.
2089 if (old_id != mp_ioapics[apic_id].apicid)
2090 for (i = 0; i < mp_irq_entries; i++)
2091 if (mp_irqs[i].dstapic == old_id)
2093 = mp_ioapics[apic_id].apicid;
2096 * Read the right value from the MPC table and
2097 * write it into the ID register.
2099 apic_printk(APIC_VERBOSE, KERN_INFO
2100 "...changing IO-APIC physical APIC ID to %d ...",
2101 mp_ioapics[apic_id].apicid);
2103 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2104 spin_lock_irqsave(&ioapic_lock, flags);
2105 io_apic_write(apic_id, 0, reg_00.raw);
2106 spin_unlock_irqrestore(&ioapic_lock, flags);
2111 spin_lock_irqsave(&ioapic_lock, flags);
2112 reg_00.raw = io_apic_read(apic_id, 0);
2113 spin_unlock_irqrestore(&ioapic_lock, flags);
2114 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2115 printk("could not set ID!\n");
2117 apic_printk(APIC_VERBOSE, " ok.\n");
2122 int no_timer_check __initdata;
2124 static int __init notimercheck(char *s)
2129 __setup("no_timer_check", notimercheck);
2132 * There is a nasty bug in some older SMP boards, their mptable lies
2133 * about the timer IRQ. We do the following to work around the situation:
2135 * - timer IRQ defaults to IO-APIC IRQ
2136 * - if this function detects that timer IRQs are defunct, then we fall
2137 * back to ISA timer IRQs
2139 static int __init timer_irq_works(void)
2141 unsigned long t1 = jiffies;
2142 unsigned long flags;
2147 local_save_flags(flags);
2149 /* Let ten ticks pass... */
2150 mdelay((10 * 1000) / HZ);
2151 local_irq_restore(flags);
2154 * Expect a few ticks at least, to be sure some possible
2155 * glue logic does not lock up after one or two first
2156 * ticks in a non-ExtINT mode. Also the local APIC
2157 * might have cached one ExtINT interrupt. Finally, at
2158 * least one tick may be lost due to delays.
2162 if (time_after(jiffies, t1 + 4))
2168 * In the SMP+IOAPIC case it might happen that there are an unspecified
2169 * number of pending IRQ events unhandled. These cases are very rare,
2170 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2171 * better to do it this way as thus we do not have to be aware of
2172 * 'pending' interrupts in the IRQ path, except at this point.
2175 * Edge triggered needs to resend any interrupt
2176 * that was delayed but this is now handled in the device
2181 * Starting up a edge-triggered IO-APIC interrupt is
2182 * nasty - we need to make sure that we get the edge.
2183 * If it is already asserted for some reason, we need
2184 * return 1 to indicate that is was pending.
2186 * This is not complete - we should be able to fake
2187 * an edge even if it isn't on the 8259A...
2190 static unsigned int startup_ioapic_irq(unsigned int irq)
2192 int was_pending = 0;
2193 unsigned long flags;
2194 struct irq_cfg *cfg;
2196 spin_lock_irqsave(&ioapic_lock, flags);
2197 if (irq < NR_IRQS_LEGACY) {
2198 disable_8259A_irq(irq);
2199 if (i8259A_irq_pending(irq))
2203 __unmask_IO_APIC_irq(cfg);
2204 spin_unlock_irqrestore(&ioapic_lock, flags);
2209 #ifdef CONFIG_X86_64
2210 static int ioapic_retrigger_irq(unsigned int irq)
2213 struct irq_cfg *cfg = irq_cfg(irq);
2214 unsigned long flags;
2216 spin_lock_irqsave(&vector_lock, flags);
2217 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2218 spin_unlock_irqrestore(&vector_lock, flags);
2223 static int ioapic_retrigger_irq(unsigned int irq)
2225 apic->send_IPI_self(irq_cfg(irq)->vector);
2232 * Level and edge triggered IO-APIC interrupts need different handling,
2233 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2234 * handled with the level-triggered descriptor, but that one has slightly
2235 * more overhead. Level-triggered interrupts cannot be handled with the
2236 * edge-triggered handler, without risking IRQ storms and other ugly
2241 static void send_cleanup_vector(struct irq_cfg *cfg)
2243 cpumask_var_t cleanup_mask;
2245 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2247 cfg->move_cleanup_count = 0;
2248 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2249 cfg->move_cleanup_count++;
2250 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2251 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2253 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2254 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2255 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2256 free_cpumask_var(cleanup_mask);
2258 cfg->move_in_progress = 0;
2261 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2264 struct irq_pin_list *entry;
2265 u8 vector = cfg->vector;
2267 entry = cfg->irq_2_pin;
2277 * With interrupt-remapping, destination information comes
2278 * from interrupt-remapping table entry.
2280 if (!irq_remapped(irq))
2281 io_apic_write(apic, 0x11 + pin*2, dest);
2282 reg = io_apic_read(apic, 0x10 + pin*2);
2283 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2285 io_apic_modify(apic, 0x10 + pin*2, reg);
2288 entry = entry->next;
2293 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2296 * Either sets desc->affinity to a valid value, and returns
2297 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2298 * leaves desc->affinity untouched.
2301 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2303 struct irq_cfg *cfg;
2306 if (!cpumask_intersects(mask, cpu_online_mask))
2310 cfg = desc->chip_data;
2311 if (assign_irq_vector(irq, cfg, mask))
2314 cpumask_copy(desc->affinity, mask);
2316 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2320 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2322 struct irq_cfg *cfg;
2323 unsigned long flags;
2329 cfg = desc->chip_data;
2331 spin_lock_irqsave(&ioapic_lock, flags);
2332 dest = set_desc_affinity(desc, mask);
2333 if (dest != BAD_APICID) {
2334 /* Only the high 8 bits are valid. */
2335 dest = SET_APIC_LOGICAL_ID(dest);
2336 __target_IO_APIC_irq(irq, dest, cfg);
2339 spin_unlock_irqrestore(&ioapic_lock, flags);
2345 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2347 struct irq_desc *desc;
2349 desc = irq_to_desc(irq);
2351 return set_ioapic_affinity_irq_desc(desc, mask);
2354 #ifdef CONFIG_INTR_REMAP
2357 * Migrate the IO-APIC irq in the presence of intr-remapping.
2359 * For both level and edge triggered, irq migration is a simple atomic
2360 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2362 * For level triggered, we eliminate the io-apic RTE modification (with the
2363 * updated vector information), by using a virtual vector (io-apic pin number).
2364 * Real vector that is used for interrupting cpu will be coming from
2365 * the interrupt-remapping table entry.
2368 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2370 struct irq_cfg *cfg;
2376 if (!cpumask_intersects(mask, cpu_online_mask))
2380 if (get_irte(irq, &irte))
2383 cfg = desc->chip_data;
2384 if (assign_irq_vector(irq, cfg, mask))
2387 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2389 irte.vector = cfg->vector;
2390 irte.dest_id = IRTE_DEST(dest);
2393 * Modified the IRTE and flushes the Interrupt entry cache.
2395 modify_irte(irq, &irte);
2397 if (cfg->move_in_progress)
2398 send_cleanup_vector(cfg);
2400 cpumask_copy(desc->affinity, mask);
2406 * Migrates the IRQ destination in the process context.
2408 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2409 const struct cpumask *mask)
2411 return migrate_ioapic_irq_desc(desc, mask);
2413 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2414 const struct cpumask *mask)
2416 struct irq_desc *desc = irq_to_desc(irq);
2418 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2421 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2422 const struct cpumask *mask)
2428 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2430 unsigned vector, me;
2436 me = smp_processor_id();
2437 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2440 struct irq_desc *desc;
2441 struct irq_cfg *cfg;
2442 irq = __get_cpu_var(vector_irq)[vector];
2447 desc = irq_to_desc(irq);
2452 spin_lock(&desc->lock);
2453 if (!cfg->move_cleanup_count)
2456 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2459 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2461 * Check if the vector that needs to be cleanedup is
2462 * registered at the cpu's IRR. If so, then this is not
2463 * the best time to clean it up. Lets clean it up in the
2464 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2467 if (irr & (1 << (vector % 32))) {
2468 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2471 __get_cpu_var(vector_irq)[vector] = -1;
2472 cfg->move_cleanup_count--;
2474 spin_unlock(&desc->lock);
2480 static void irq_complete_move(struct irq_desc **descp)
2482 struct irq_desc *desc = *descp;
2483 struct irq_cfg *cfg = desc->chip_data;
2484 unsigned vector, me;
2486 if (likely(!cfg->move_in_progress))
2489 vector = ~get_irq_regs()->orig_ax;
2490 me = smp_processor_id();
2492 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2493 send_cleanup_vector(cfg);
2496 static inline void irq_complete_move(struct irq_desc **descp) {}
2499 static void ack_apic_edge(unsigned int irq)
2501 struct irq_desc *desc = irq_to_desc(irq);
2503 irq_complete_move(&desc);
2504 move_native_irq(irq);
2508 atomic_t irq_mis_count;
2510 static void ack_apic_level(unsigned int irq)
2512 struct irq_desc *desc = irq_to_desc(irq);
2514 #ifdef CONFIG_X86_32
2518 struct irq_cfg *cfg;
2519 int do_unmask_irq = 0;
2521 irq_complete_move(&desc);
2522 #ifdef CONFIG_GENERIC_PENDING_IRQ
2523 /* If we are moving the irq we need to mask it */
2524 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2526 mask_IO_APIC_irq_desc(desc);
2530 #ifdef CONFIG_X86_32
2532 * It appears there is an erratum which affects at least version 0x11
2533 * of I/O APIC (that's the 82093AA and cores integrated into various
2534 * chipsets). Under certain conditions a level-triggered interrupt is
2535 * erroneously delivered as edge-triggered one but the respective IRR
2536 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2537 * message but it will never arrive and further interrupts are blocked
2538 * from the source. The exact reason is so far unknown, but the
2539 * phenomenon was observed when two consecutive interrupt requests
2540 * from a given source get delivered to the same CPU and the source is
2541 * temporarily disabled in between.
2543 * A workaround is to simulate an EOI message manually. We achieve it
2544 * by setting the trigger mode to edge and then to level when the edge
2545 * trigger mode gets detected in the TMR of a local APIC for a
2546 * level-triggered interrupt. We mask the source for the time of the
2547 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2548 * The idea is from Manfred Spraul. --macro
2550 cfg = desc->chip_data;
2553 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2557 * We must acknowledge the irq before we move it or the acknowledge will
2558 * not propagate properly.
2562 /* Now we can move and renable the irq */
2563 if (unlikely(do_unmask_irq)) {
2564 /* Only migrate the irq if the ack has been received.
2566 * On rare occasions the broadcast level triggered ack gets
2567 * delayed going to ioapics, and if we reprogram the
2568 * vector while Remote IRR is still set the irq will never
2571 * To prevent this scenario we read the Remote IRR bit
2572 * of the ioapic. This has two effects.
2573 * - On any sane system the read of the ioapic will
2574 * flush writes (and acks) going to the ioapic from
2576 * - We get to see if the ACK has actually been delivered.
2578 * Based on failed experiments of reprogramming the
2579 * ioapic entry from outside of irq context starting
2580 * with masking the ioapic entry and then polling until
2581 * Remote IRR was clear before reprogramming the
2582 * ioapic I don't trust the Remote IRR bit to be
2583 * completey accurate.
2585 * However there appears to be no other way to plug
2586 * this race, so if the Remote IRR bit is not
2587 * accurate and is causing problems then it is a hardware bug
2588 * and you can go talk to the chipset vendor about it.
2590 cfg = desc->chip_data;
2591 if (!io_apic_level_ack_pending(cfg))
2592 move_masked_irq(irq);
2593 unmask_IO_APIC_irq_desc(desc);
2596 #ifdef CONFIG_X86_32
2597 if (!(v & (1 << (i & 0x1f)))) {
2598 atomic_inc(&irq_mis_count);
2599 spin_lock(&ioapic_lock);
2600 __mask_and_edge_IO_APIC_irq(cfg);
2601 __unmask_and_level_IO_APIC_irq(cfg);
2602 spin_unlock(&ioapic_lock);
2607 #ifdef CONFIG_INTR_REMAP
2608 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2611 struct irq_pin_list *entry;
2613 entry = cfg->irq_2_pin;
2621 io_apic_eoi(apic, pin);
2622 entry = entry->next;
2627 eoi_ioapic_irq(struct irq_desc *desc)
2629 struct irq_cfg *cfg;
2630 unsigned long flags;
2634 cfg = desc->chip_data;
2636 spin_lock_irqsave(&ioapic_lock, flags);
2637 __eoi_ioapic_irq(irq, cfg);
2638 spin_unlock_irqrestore(&ioapic_lock, flags);
2641 static void ir_ack_apic_edge(unsigned int irq)
2646 static void ir_ack_apic_level(unsigned int irq)
2648 struct irq_desc *desc = irq_to_desc(irq);
2651 eoi_ioapic_irq(desc);
2653 #endif /* CONFIG_INTR_REMAP */
2655 static struct irq_chip ioapic_chip __read_mostly = {
2657 .startup = startup_ioapic_irq,
2658 .mask = mask_IO_APIC_irq,
2659 .unmask = unmask_IO_APIC_irq,
2660 .ack = ack_apic_edge,
2661 .eoi = ack_apic_level,
2663 .set_affinity = set_ioapic_affinity_irq,
2665 .retrigger = ioapic_retrigger_irq,
2668 static struct irq_chip ir_ioapic_chip __read_mostly = {
2669 .name = "IR-IO-APIC",
2670 .startup = startup_ioapic_irq,
2671 .mask = mask_IO_APIC_irq,
2672 .unmask = unmask_IO_APIC_irq,
2673 #ifdef CONFIG_INTR_REMAP
2674 .ack = ir_ack_apic_edge,
2675 .eoi = ir_ack_apic_level,
2677 .set_affinity = set_ir_ioapic_affinity_irq,
2680 .retrigger = ioapic_retrigger_irq,
2683 static inline void init_IO_APIC_traps(void)
2686 struct irq_desc *desc;
2687 struct irq_cfg *cfg;
2690 * NOTE! The local APIC isn't very good at handling
2691 * multiple interrupts at the same interrupt level.
2692 * As the interrupt level is determined by taking the
2693 * vector number and shifting that right by 4, we
2694 * want to spread these out a bit so that they don't
2695 * all fall in the same interrupt level.
2697 * Also, we've got to be careful not to trash gate
2698 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2700 for_each_irq_desc(irq, desc) {
2701 cfg = desc->chip_data;
2702 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2704 * Hmm.. We don't have an entry for this,
2705 * so default to an old-fashioned 8259
2706 * interrupt if we can..
2708 if (irq < NR_IRQS_LEGACY)
2709 make_8259A_irq(irq);
2711 /* Strange. Oh, well.. */
2712 desc->chip = &no_irq_chip;
2718 * The local APIC irq-chip implementation:
2721 static void mask_lapic_irq(unsigned int irq)
2725 v = apic_read(APIC_LVT0);
2726 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2729 static void unmask_lapic_irq(unsigned int irq)
2733 v = apic_read(APIC_LVT0);
2734 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2737 static void ack_lapic_irq(unsigned int irq)
2742 static struct irq_chip lapic_chip __read_mostly = {
2743 .name = "local-APIC",
2744 .mask = mask_lapic_irq,
2745 .unmask = unmask_lapic_irq,
2746 .ack = ack_lapic_irq,
2749 static void lapic_register_intr(int irq, struct irq_desc *desc)
2751 desc->status &= ~IRQ_LEVEL;
2752 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2756 static void __init setup_nmi(void)
2759 * Dirty trick to enable the NMI watchdog ...
2760 * We put the 8259A master into AEOI mode and
2761 * unmask on all local APICs LVT0 as NMI.
2763 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2764 * is from Maciej W. Rozycki - so we do not have to EOI from
2765 * the NMI handler or the timer interrupt.
2767 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2769 enable_NMI_through_LVT0();
2771 apic_printk(APIC_VERBOSE, " done.\n");
2775 * This looks a bit hackish but it's about the only one way of sending
2776 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2777 * not support the ExtINT mode, unfortunately. We need to send these
2778 * cycles as some i82489DX-based boards have glue logic that keeps the
2779 * 8259A interrupt line asserted until INTA. --macro
2781 static inline void __init unlock_ExtINT_logic(void)
2784 struct IO_APIC_route_entry entry0, entry1;
2785 unsigned char save_control, save_freq_select;
2787 pin = find_isa_irq_pin(8, mp_INT);
2792 apic = find_isa_irq_apic(8, mp_INT);
2798 entry0 = ioapic_read_entry(apic, pin);
2799 clear_IO_APIC_pin(apic, pin);
2801 memset(&entry1, 0, sizeof(entry1));
2803 entry1.dest_mode = 0; /* physical delivery */
2804 entry1.mask = 0; /* unmask IRQ now */
2805 entry1.dest = hard_smp_processor_id();
2806 entry1.delivery_mode = dest_ExtINT;
2807 entry1.polarity = entry0.polarity;
2811 ioapic_write_entry(apic, pin, entry1);
2813 save_control = CMOS_READ(RTC_CONTROL);
2814 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2815 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2817 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2822 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2826 CMOS_WRITE(save_control, RTC_CONTROL);
2827 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2828 clear_IO_APIC_pin(apic, pin);
2830 ioapic_write_entry(apic, pin, entry0);
2833 static int disable_timer_pin_1 __initdata;
2834 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2835 static int __init disable_timer_pin_setup(char *arg)
2837 disable_timer_pin_1 = 1;
2840 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2842 int timer_through_8259 __initdata;
2845 * This code may look a bit paranoid, but it's supposed to cooperate with
2846 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2847 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2848 * fanatically on his truly buggy board.
2850 * FIXME: really need to revamp this for all platforms.
2852 static inline void __init check_timer(void)
2854 struct irq_desc *desc = irq_to_desc(0);
2855 struct irq_cfg *cfg = desc->chip_data;
2856 int node = cpu_to_node(boot_cpu_id);
2857 int apic1, pin1, apic2, pin2;
2858 unsigned long flags;
2861 local_irq_save(flags);
2864 * get/set the timer IRQ vector:
2866 disable_8259A_irq(0);
2867 assign_irq_vector(0, cfg, apic->target_cpus());
2870 * As IRQ0 is to be enabled in the 8259A, the virtual
2871 * wire has to be disabled in the local APIC. Also
2872 * timer interrupts need to be acknowledged manually in
2873 * the 8259A for the i82489DX when using the NMI
2874 * watchdog as that APIC treats NMIs as level-triggered.
2875 * The AEOI mode will finish them in the 8259A
2878 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2880 #ifdef CONFIG_X86_32
2884 ver = apic_read(APIC_LVR);
2885 ver = GET_APIC_VERSION(ver);
2886 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2890 pin1 = find_isa_irq_pin(0, mp_INT);
2891 apic1 = find_isa_irq_apic(0, mp_INT);
2892 pin2 = ioapic_i8259.pin;
2893 apic2 = ioapic_i8259.apic;
2895 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2896 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2897 cfg->vector, apic1, pin1, apic2, pin2);
2900 * Some BIOS writers are clueless and report the ExtINTA
2901 * I/O APIC input from the cascaded 8259A as the timer
2902 * interrupt input. So just in case, if only one pin
2903 * was found above, try it both directly and through the
2907 if (intr_remapping_enabled)
2908 panic("BIOS bug: timer not connected to IO-APIC");
2912 } else if (pin2 == -1) {
2919 * Ok, does IRQ0 through the IOAPIC work?
2922 add_pin_to_irq_node(cfg, node, apic1, pin1);
2923 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2925 /* for edge trigger, setup_IO_APIC_irq already
2926 * leave it unmasked.
2927 * so only need to unmask if it is level-trigger
2928 * do we really have level trigger timer?
2931 idx = find_irq_entry(apic1, pin1, mp_INT);
2932 if (idx != -1 && irq_trigger(idx))
2933 unmask_IO_APIC_irq_desc(desc);
2935 if (timer_irq_works()) {
2936 if (nmi_watchdog == NMI_IO_APIC) {
2938 enable_8259A_irq(0);
2940 if (disable_timer_pin_1 > 0)
2941 clear_IO_APIC_pin(0, pin1);
2944 if (intr_remapping_enabled)
2945 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2946 local_irq_disable();
2947 clear_IO_APIC_pin(apic1, pin1);
2949 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2950 "8254 timer not connected to IO-APIC\n");
2952 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2953 "(IRQ0) through the 8259A ...\n");
2954 apic_printk(APIC_QUIET, KERN_INFO
2955 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2957 * legacy devices should be connected to IO APIC #0
2959 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2960 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2961 enable_8259A_irq(0);
2962 if (timer_irq_works()) {
2963 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2964 timer_through_8259 = 1;
2965 if (nmi_watchdog == NMI_IO_APIC) {
2966 disable_8259A_irq(0);
2968 enable_8259A_irq(0);
2973 * Cleanup, just in case ...
2975 local_irq_disable();
2976 disable_8259A_irq(0);
2977 clear_IO_APIC_pin(apic2, pin2);
2978 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2981 if (nmi_watchdog == NMI_IO_APIC) {
2982 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2983 "through the IO-APIC - disabling NMI Watchdog!\n");
2984 nmi_watchdog = NMI_NONE;
2986 #ifdef CONFIG_X86_32
2990 apic_printk(APIC_QUIET, KERN_INFO
2991 "...trying to set up timer as Virtual Wire IRQ...\n");
2993 lapic_register_intr(0, desc);
2994 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2995 enable_8259A_irq(0);
2997 if (timer_irq_works()) {
2998 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3001 local_irq_disable();
3002 disable_8259A_irq(0);
3003 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3004 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3006 apic_printk(APIC_QUIET, KERN_INFO
3007 "...trying to set up timer as ExtINT IRQ...\n");
3011 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3013 unlock_ExtINT_logic();
3015 if (timer_irq_works()) {
3016 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3019 local_irq_disable();
3020 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3021 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3022 "report. Then try booting with the 'noapic' option.\n");
3024 local_irq_restore(flags);
3028 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3029 * to devices. However there may be an I/O APIC pin available for
3030 * this interrupt regardless. The pin may be left unconnected, but
3031 * typically it will be reused as an ExtINT cascade interrupt for
3032 * the master 8259A. In the MPS case such a pin will normally be
3033 * reported as an ExtINT interrupt in the MP table. With ACPI
3034 * there is no provision for ExtINT interrupts, and in the absence
3035 * of an override it would be treated as an ordinary ISA I/O APIC
3036 * interrupt, that is edge-triggered and unmasked by default. We
3037 * used to do this, but it caused problems on some systems because
3038 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3039 * the same ExtINT cascade interrupt to drive the local APIC of the
3040 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3041 * the I/O APIC in all cases now. No actual device should request
3042 * it anyway. --macro
3044 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3046 void __init setup_IO_APIC(void)
3050 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3053 io_apic_irqs = ~PIC_IRQS;
3055 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3057 * Set up IO-APIC IRQ routing.
3059 #ifdef CONFIG_X86_32
3061 setup_ioapic_ids_from_mpc();
3064 setup_IO_APIC_irqs();
3065 init_IO_APIC_traps();
3070 * Called after all the initialization is done. If we didnt find any
3071 * APIC bugs then we can allow the modify fast path
3074 static int __init io_apic_bug_finalize(void)
3076 if (sis_apic_bug == -1)
3081 late_initcall(io_apic_bug_finalize);
3083 struct sysfs_ioapic_data {
3084 struct sys_device dev;
3085 struct IO_APIC_route_entry entry[0];
3087 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3089 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3091 struct IO_APIC_route_entry *entry;
3092 struct sysfs_ioapic_data *data;
3095 data = container_of(dev, struct sysfs_ioapic_data, dev);
3096 entry = data->entry;
3097 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3098 *entry = ioapic_read_entry(dev->id, i);
3103 static int ioapic_resume(struct sys_device *dev)
3105 struct IO_APIC_route_entry *entry;
3106 struct sysfs_ioapic_data *data;
3107 unsigned long flags;
3108 union IO_APIC_reg_00 reg_00;
3111 data = container_of(dev, struct sysfs_ioapic_data, dev);
3112 entry = data->entry;
3114 spin_lock_irqsave(&ioapic_lock, flags);
3115 reg_00.raw = io_apic_read(dev->id, 0);
3116 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3117 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3118 io_apic_write(dev->id, 0, reg_00.raw);
3120 spin_unlock_irqrestore(&ioapic_lock, flags);
3121 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3122 ioapic_write_entry(dev->id, i, entry[i]);
3127 static struct sysdev_class ioapic_sysdev_class = {
3129 .suspend = ioapic_suspend,
3130 .resume = ioapic_resume,
3133 static int __init ioapic_init_sysfs(void)
3135 struct sys_device * dev;
3138 error = sysdev_class_register(&ioapic_sysdev_class);
3142 for (i = 0; i < nr_ioapics; i++ ) {
3143 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3144 * sizeof(struct IO_APIC_route_entry);
3145 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3146 if (!mp_ioapic_data[i]) {
3147 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3150 dev = &mp_ioapic_data[i]->dev;
3152 dev->cls = &ioapic_sysdev_class;
3153 error = sysdev_register(dev);
3155 kfree(mp_ioapic_data[i]);
3156 mp_ioapic_data[i] = NULL;
3157 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3165 device_initcall(ioapic_init_sysfs);
3167 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3169 * Dynamic irq allocate and deallocation
3171 unsigned int create_irq_nr(unsigned int irq_want, int node)
3173 /* Allocate an unused irq */
3176 unsigned long flags;
3177 struct irq_cfg *cfg_new = NULL;
3178 struct irq_desc *desc_new = NULL;
3181 if (irq_want < nr_irqs_gsi)
3182 irq_want = nr_irqs_gsi;
3184 spin_lock_irqsave(&vector_lock, flags);
3185 for (new = irq_want; new < nr_irqs; new++) {
3186 desc_new = irq_to_desc_alloc_node(new, node);
3188 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3191 cfg_new = desc_new->chip_data;
3193 if (cfg_new->vector != 0)
3196 desc_new = move_irq_desc(desc_new, node);
3198 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3202 spin_unlock_irqrestore(&vector_lock, flags);
3205 dynamic_irq_init(irq);
3206 /* restore it, in case dynamic_irq_init clear it */
3208 desc_new->chip_data = cfg_new;
3213 int create_irq(void)
3215 int node = cpu_to_node(boot_cpu_id);
3216 unsigned int irq_want;
3219 irq_want = nr_irqs_gsi;
3220 irq = create_irq_nr(irq_want, node);
3228 void destroy_irq(unsigned int irq)
3230 unsigned long flags;
3231 struct irq_cfg *cfg;
3232 struct irq_desc *desc;
3234 /* store it, in case dynamic_irq_cleanup clear it */
3235 desc = irq_to_desc(irq);
3236 cfg = desc->chip_data;
3237 dynamic_irq_cleanup(irq);
3238 /* connect back irq_cfg */
3240 desc->chip_data = cfg;
3243 spin_lock_irqsave(&vector_lock, flags);
3244 __clear_irq_vector(irq, cfg);
3245 spin_unlock_irqrestore(&vector_lock, flags);
3249 * MSI message composition
3251 #ifdef CONFIG_PCI_MSI
3252 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3254 struct irq_cfg *cfg;
3262 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3266 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3268 if (irq_remapped(irq)) {
3273 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3274 BUG_ON(ir_index == -1);
3276 memset (&irte, 0, sizeof(irte));
3279 irte.dst_mode = apic->irq_dest_mode;
3280 irte.trigger_mode = 0; /* edge */
3281 irte.dlvry_mode = apic->irq_delivery_mode;
3282 irte.vector = cfg->vector;
3283 irte.dest_id = IRTE_DEST(dest);
3285 /* Set source-id of interrupt request */
3286 set_msi_sid(&irte, pdev);
3288 modify_irte(irq, &irte);
3290 msg->address_hi = MSI_ADDR_BASE_HI;
3291 msg->data = sub_handle;
3292 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3294 MSI_ADDR_IR_INDEX1(ir_index) |
3295 MSI_ADDR_IR_INDEX2(ir_index);
3297 if (x2apic_enabled())
3298 msg->address_hi = MSI_ADDR_BASE_HI |
3299 MSI_ADDR_EXT_DEST_ID(dest);
3301 msg->address_hi = MSI_ADDR_BASE_HI;
3305 ((apic->irq_dest_mode == 0) ?
3306 MSI_ADDR_DEST_MODE_PHYSICAL:
3307 MSI_ADDR_DEST_MODE_LOGICAL) |
3308 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3309 MSI_ADDR_REDIRECTION_CPU:
3310 MSI_ADDR_REDIRECTION_LOWPRI) |
3311 MSI_ADDR_DEST_ID(dest);
3314 MSI_DATA_TRIGGER_EDGE |
3315 MSI_DATA_LEVEL_ASSERT |
3316 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3317 MSI_DATA_DELIVERY_FIXED:
3318 MSI_DATA_DELIVERY_LOWPRI) |
3319 MSI_DATA_VECTOR(cfg->vector);
3325 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3327 struct irq_desc *desc = irq_to_desc(irq);
3328 struct irq_cfg *cfg;
3332 dest = set_desc_affinity(desc, mask);
3333 if (dest == BAD_APICID)
3336 cfg = desc->chip_data;
3338 read_msi_msg_desc(desc, &msg);
3340 msg.data &= ~MSI_DATA_VECTOR_MASK;
3341 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3342 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3343 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3345 write_msi_msg_desc(desc, &msg);
3349 #ifdef CONFIG_INTR_REMAP
3351 * Migrate the MSI irq to another cpumask. This migration is
3352 * done in the process context using interrupt-remapping hardware.
3355 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3357 struct irq_desc *desc = irq_to_desc(irq);
3358 struct irq_cfg *cfg = desc->chip_data;
3362 if (get_irte(irq, &irte))
3365 dest = set_desc_affinity(desc, mask);
3366 if (dest == BAD_APICID)
3369 irte.vector = cfg->vector;
3370 irte.dest_id = IRTE_DEST(dest);
3373 * atomically update the IRTE with the new destination and vector.
3375 modify_irte(irq, &irte);
3378 * After this point, all the interrupts will start arriving
3379 * at the new destination. So, time to cleanup the previous
3380 * vector allocation.
3382 if (cfg->move_in_progress)
3383 send_cleanup_vector(cfg);
3389 #endif /* CONFIG_SMP */
3392 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3393 * which implement the MSI or MSI-X Capability Structure.
3395 static struct irq_chip msi_chip = {
3397 .unmask = unmask_msi_irq,
3398 .mask = mask_msi_irq,
3399 .ack = ack_apic_edge,
3401 .set_affinity = set_msi_irq_affinity,
3403 .retrigger = ioapic_retrigger_irq,
3406 static struct irq_chip msi_ir_chip = {
3407 .name = "IR-PCI-MSI",
3408 .unmask = unmask_msi_irq,
3409 .mask = mask_msi_irq,
3410 #ifdef CONFIG_INTR_REMAP
3411 .ack = ir_ack_apic_edge,
3413 .set_affinity = ir_set_msi_irq_affinity,
3416 .retrigger = ioapic_retrigger_irq,
3420 * Map the PCI dev to the corresponding remapping hardware unit
3421 * and allocate 'nvec' consecutive interrupt-remapping table entries
3424 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3426 struct intel_iommu *iommu;
3429 iommu = map_dev_to_ir(dev);
3432 "Unable to map PCI %s to iommu\n", pci_name(dev));
3436 index = alloc_irte(iommu, irq, nvec);
3439 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3446 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3451 ret = msi_compose_msg(dev, irq, &msg);
3455 set_irq_msi(irq, msidesc);
3456 write_msi_msg(irq, &msg);
3458 if (irq_remapped(irq)) {
3459 struct irq_desc *desc = irq_to_desc(irq);
3461 * irq migration in process context
3463 desc->status |= IRQ_MOVE_PCNTXT;
3464 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3466 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3468 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3473 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3476 int ret, sub_handle;
3477 struct msi_desc *msidesc;
3478 unsigned int irq_want;
3479 struct intel_iommu *iommu = NULL;
3483 /* x86 doesn't support multiple MSI yet */
3484 if (type == PCI_CAP_ID_MSI && nvec > 1)
3487 node = dev_to_node(&dev->dev);
3488 irq_want = nr_irqs_gsi;
3490 list_for_each_entry(msidesc, &dev->msi_list, list) {
3491 irq = create_irq_nr(irq_want, node);
3495 if (!intr_remapping_enabled)
3500 * allocate the consecutive block of IRTE's
3503 index = msi_alloc_irte(dev, irq, nvec);
3509 iommu = map_dev_to_ir(dev);
3515 * setup the mapping between the irq and the IRTE
3516 * base index, the sub_handle pointing to the
3517 * appropriate interrupt remap table entry.
3519 set_irte_irq(irq, iommu, index, sub_handle);
3522 ret = setup_msi_irq(dev, msidesc, irq);
3534 void arch_teardown_msi_irq(unsigned int irq)
3539 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3541 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3543 struct irq_desc *desc = irq_to_desc(irq);
3544 struct irq_cfg *cfg;
3548 dest = set_desc_affinity(desc, mask);
3549 if (dest == BAD_APICID)
3552 cfg = desc->chip_data;
3554 dmar_msi_read(irq, &msg);
3556 msg.data &= ~MSI_DATA_VECTOR_MASK;
3557 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3558 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3559 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3561 dmar_msi_write(irq, &msg);
3566 #endif /* CONFIG_SMP */
3568 static struct irq_chip dmar_msi_type = {
3570 .unmask = dmar_msi_unmask,
3571 .mask = dmar_msi_mask,
3572 .ack = ack_apic_edge,
3574 .set_affinity = dmar_msi_set_affinity,
3576 .retrigger = ioapic_retrigger_irq,
3579 int arch_setup_dmar_msi(unsigned int irq)
3584 ret = msi_compose_msg(NULL, irq, &msg);
3587 dmar_msi_write(irq, &msg);
3588 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3594 #ifdef CONFIG_HPET_TIMER
3597 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3599 struct irq_desc *desc = irq_to_desc(irq);
3600 struct irq_cfg *cfg;
3604 dest = set_desc_affinity(desc, mask);
3605 if (dest == BAD_APICID)
3608 cfg = desc->chip_data;
3610 hpet_msi_read(irq, &msg);
3612 msg.data &= ~MSI_DATA_VECTOR_MASK;
3613 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3614 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3615 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3617 hpet_msi_write(irq, &msg);
3622 #endif /* CONFIG_SMP */
3624 static struct irq_chip hpet_msi_type = {
3626 .unmask = hpet_msi_unmask,
3627 .mask = hpet_msi_mask,
3628 .ack = ack_apic_edge,
3630 .set_affinity = hpet_msi_set_affinity,
3632 .retrigger = ioapic_retrigger_irq,
3635 int arch_setup_hpet_msi(unsigned int irq)
3639 struct irq_desc *desc = irq_to_desc(irq);
3641 ret = msi_compose_msg(NULL, irq, &msg);
3645 hpet_msi_write(irq, &msg);
3646 desc->status |= IRQ_MOVE_PCNTXT;
3647 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3654 #endif /* CONFIG_PCI_MSI */
3656 * Hypertransport interrupt support
3658 #ifdef CONFIG_HT_IRQ
3662 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3664 struct ht_irq_msg msg;
3665 fetch_ht_irq_msg(irq, &msg);
3667 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3668 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3670 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3671 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3673 write_ht_irq_msg(irq, &msg);
3676 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3678 struct irq_desc *desc = irq_to_desc(irq);
3679 struct irq_cfg *cfg;
3682 dest = set_desc_affinity(desc, mask);
3683 if (dest == BAD_APICID)
3686 cfg = desc->chip_data;
3688 target_ht_irq(irq, dest, cfg->vector);
3695 static struct irq_chip ht_irq_chip = {
3697 .mask = mask_ht_irq,
3698 .unmask = unmask_ht_irq,
3699 .ack = ack_apic_edge,
3701 .set_affinity = set_ht_irq_affinity,
3703 .retrigger = ioapic_retrigger_irq,
3706 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3708 struct irq_cfg *cfg;
3715 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3717 struct ht_irq_msg msg;
3720 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3721 apic->target_cpus());
3723 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3727 HT_IRQ_LOW_DEST_ID(dest) |
3728 HT_IRQ_LOW_VECTOR(cfg->vector) |
3729 ((apic->irq_dest_mode == 0) ?
3730 HT_IRQ_LOW_DM_PHYSICAL :
3731 HT_IRQ_LOW_DM_LOGICAL) |
3732 HT_IRQ_LOW_RQEOI_EDGE |
3733 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3734 HT_IRQ_LOW_MT_FIXED :
3735 HT_IRQ_LOW_MT_ARBITRATED) |
3736 HT_IRQ_LOW_IRQ_MASKED;
3738 write_ht_irq_msg(irq, &msg);
3740 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3741 handle_edge_irq, "edge");
3743 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3747 #endif /* CONFIG_HT_IRQ */
3749 #ifdef CONFIG_X86_UV
3751 * Re-target the irq to the specified CPU and enable the specified MMR located
3752 * on the specified blade to allow the sending of MSIs to the specified CPU.
3754 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3755 unsigned long mmr_offset)
3757 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3758 struct irq_cfg *cfg;
3760 unsigned long mmr_value;
3761 struct uv_IO_APIC_route_entry *entry;
3762 unsigned long flags;
3765 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3769 err = assign_irq_vector(irq, cfg, eligible_cpu);
3773 spin_lock_irqsave(&vector_lock, flags);
3774 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3776 spin_unlock_irqrestore(&vector_lock, flags);
3779 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3780 entry->vector = cfg->vector;
3781 entry->delivery_mode = apic->irq_delivery_mode;
3782 entry->dest_mode = apic->irq_dest_mode;
3783 entry->polarity = 0;
3786 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3788 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3789 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3795 * Disable the specified MMR located on the specified blade so that MSIs are
3796 * longer allowed to be sent.
3798 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3800 unsigned long mmr_value;
3801 struct uv_IO_APIC_route_entry *entry;
3804 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3807 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3810 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3811 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3813 #endif /* CONFIG_X86_64 */
3815 int __init io_apic_get_redir_entries (int ioapic)
3817 union IO_APIC_reg_01 reg_01;
3818 unsigned long flags;
3820 spin_lock_irqsave(&ioapic_lock, flags);
3821 reg_01.raw = io_apic_read(ioapic, 1);
3822 spin_unlock_irqrestore(&ioapic_lock, flags);
3824 return reg_01.bits.entries;
3827 void __init probe_nr_irqs_gsi(void)
3831 nr = acpi_probe_gsi();
3832 if (nr > nr_irqs_gsi) {
3835 /* for acpi=off or acpi is not compiled in */
3839 for (idx = 0; idx < nr_ioapics; idx++)
3840 nr += io_apic_get_redir_entries(idx) + 1;
3842 if (nr > nr_irqs_gsi)
3846 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3849 #ifdef CONFIG_SPARSE_IRQ
3850 int __init arch_probe_nr_irqs(void)
3854 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3855 nr_irqs = NR_VECTORS * nr_cpu_ids;
3857 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3858 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3860 * for MSI and HT dyn irq
3862 nr += nr_irqs_gsi * 16;
3871 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3872 struct io_apic_irq_attr *irq_attr)
3874 struct irq_desc *desc;
3875 struct irq_cfg *cfg;
3878 int trigger, polarity;
3880 ioapic = irq_attr->ioapic;
3881 if (!IO_APIC_IRQ(irq)) {
3882 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3888 node = dev_to_node(dev);
3890 node = cpu_to_node(boot_cpu_id);
3892 desc = irq_to_desc_alloc_node(irq, node);
3894 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3898 pin = irq_attr->ioapic_pin;
3899 trigger = irq_attr->trigger;
3900 polarity = irq_attr->polarity;
3903 * IRQs < 16 are already in the irq_2_pin[] map
3905 if (irq >= NR_IRQS_LEGACY) {
3906 cfg = desc->chip_data;
3907 add_pin_to_irq_node(cfg, node, ioapic, pin);
3910 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3915 int io_apic_set_pci_routing(struct device *dev, int irq,
3916 struct io_apic_irq_attr *irq_attr)
3920 * Avoid pin reprogramming. PRTs typically include entries
3921 * with redundant pin->gsi mappings (but unique PCI devices);
3922 * we only program the IOAPIC on the first.
3924 ioapic = irq_attr->ioapic;
3925 pin = irq_attr->ioapic_pin;
3926 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3927 pr_debug("Pin %d-%d already programmed\n",
3928 mp_ioapics[ioapic].apicid, pin);
3931 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3933 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3936 /* --------------------------------------------------------------------------
3937 ACPI-based IOAPIC Configuration
3938 -------------------------------------------------------------------------- */
3942 #ifdef CONFIG_X86_32
3943 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3945 union IO_APIC_reg_00 reg_00;
3946 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3948 unsigned long flags;
3952 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3953 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3954 * supports up to 16 on one shared APIC bus.
3956 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3957 * advantage of new APIC bus architecture.
3960 if (physids_empty(apic_id_map))
3961 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3963 spin_lock_irqsave(&ioapic_lock, flags);
3964 reg_00.raw = io_apic_read(ioapic, 0);
3965 spin_unlock_irqrestore(&ioapic_lock, flags);
3967 if (apic_id >= get_physical_broadcast()) {
3968 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3969 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3970 apic_id = reg_00.bits.ID;
3974 * Every APIC in a system must have a unique ID or we get lots of nice
3975 * 'stuck on smp_invalidate_needed IPI wait' messages.
3977 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3979 for (i = 0; i < get_physical_broadcast(); i++) {
3980 if (!apic->check_apicid_used(apic_id_map, i))
3984 if (i == get_physical_broadcast())
3985 panic("Max apic_id exceeded!\n");
3987 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3988 "trying %d\n", ioapic, apic_id, i);
3993 tmp = apic->apicid_to_cpu_present(apic_id);
3994 physids_or(apic_id_map, apic_id_map, tmp);
3996 if (reg_00.bits.ID != apic_id) {
3997 reg_00.bits.ID = apic_id;
3999 spin_lock_irqsave(&ioapic_lock, flags);
4000 io_apic_write(ioapic, 0, reg_00.raw);
4001 reg_00.raw = io_apic_read(ioapic, 0);
4002 spin_unlock_irqrestore(&ioapic_lock, flags);
4005 if (reg_00.bits.ID != apic_id) {
4006 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4011 apic_printk(APIC_VERBOSE, KERN_INFO
4012 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4018 int __init io_apic_get_version(int ioapic)
4020 union IO_APIC_reg_01 reg_01;
4021 unsigned long flags;
4023 spin_lock_irqsave(&ioapic_lock, flags);
4024 reg_01.raw = io_apic_read(ioapic, 1);
4025 spin_unlock_irqrestore(&ioapic_lock, flags);
4027 return reg_01.bits.version;
4030 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4034 if (skip_ioapic_setup)
4037 for (i = 0; i < mp_irq_entries; i++)
4038 if (mp_irqs[i].irqtype == mp_INT &&
4039 mp_irqs[i].srcbusirq == bus_irq)
4041 if (i >= mp_irq_entries)
4044 *trigger = irq_trigger(i);
4045 *polarity = irq_polarity(i);
4049 #endif /* CONFIG_ACPI */
4052 * This function currently is only a helper for the i386 smp boot process where
4053 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4054 * so mask in all cases should simply be apic->target_cpus()
4057 void __init setup_ioapic_dest(void)
4059 int pin, ioapic = 0, irq, irq_entry;
4060 struct irq_desc *desc;
4061 const struct cpumask *mask;
4063 if (skip_ioapic_setup == 1)
4067 if (!acpi_disabled && acpi_ioapic) {
4068 ioapic = mp_find_ioapic(0);
4074 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4075 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4076 if (irq_entry == -1)
4078 irq = pin_2_irq(irq_entry, ioapic, pin);
4080 desc = irq_to_desc(irq);
4083 * Honour affinities which have been set in early boot
4086 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4087 mask = desc->affinity;
4089 mask = apic->target_cpus();
4091 if (intr_remapping_enabled)
4092 set_ir_ioapic_affinity_irq_desc(desc, mask);
4094 set_ioapic_affinity_irq_desc(desc, mask);
4100 #define IOAPIC_RESOURCE_NAME_SIZE 11
4102 static struct resource *ioapic_resources;
4104 static struct resource * __init ioapic_setup_resources(void)
4107 struct resource *res;
4111 if (nr_ioapics <= 0)
4114 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4117 mem = alloc_bootmem(n);
4121 mem += sizeof(struct resource) * nr_ioapics;
4123 for (i = 0; i < nr_ioapics; i++) {
4125 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4126 sprintf(mem, "IOAPIC %u", i);
4127 mem += IOAPIC_RESOURCE_NAME_SIZE;
4131 ioapic_resources = res;
4136 void __init ioapic_init_mappings(void)
4138 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4139 struct resource *ioapic_res;
4142 ioapic_res = ioapic_setup_resources();
4143 for (i = 0; i < nr_ioapics; i++) {
4144 if (smp_found_config) {
4145 ioapic_phys = mp_ioapics[i].apicaddr;
4146 #ifdef CONFIG_X86_32
4149 "WARNING: bogus zero IO-APIC "
4150 "address found in MPTABLE, "
4151 "disabling IO/APIC support!\n");
4152 smp_found_config = 0;
4153 skip_ioapic_setup = 1;
4154 goto fake_ioapic_page;
4158 #ifdef CONFIG_X86_32
4161 ioapic_phys = (unsigned long)
4162 alloc_bootmem_pages(PAGE_SIZE);
4163 ioapic_phys = __pa(ioapic_phys);
4165 set_fixmap_nocache(idx, ioapic_phys);
4166 apic_printk(APIC_VERBOSE,
4167 "mapped IOAPIC to %08lx (%08lx)\n",
4168 __fix_to_virt(idx), ioapic_phys);
4171 if (ioapic_res != NULL) {
4172 ioapic_res->start = ioapic_phys;
4173 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4179 static int __init ioapic_insert_resources(void)
4182 struct resource *r = ioapic_resources;
4185 if (nr_ioapics > 0) {
4187 "IO APIC resources couldn't be allocated.\n");
4193 for (i = 0; i < nr_ioapics; i++) {
4194 insert_resource(&iomem_resource, r);
4201 /* Insert the IO APIC resources after PCI initialization has occured to handle
4202 * IO APICS that are mapped in on a BAR in PCI space. */
4203 late_initcall(ioapic_insert_resources);